1/*- 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the acknowledgement as bellow: 16 * 17 * This product includes software developed by K. Kobayashi and H. Shimokawa 18 * 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD$ 35 * 36 */ 37 38#define STATE_CLEAR 0x0000 39#define STATE_SET 0x0004 40#define NODE_IDS 0x0008 41#define RESET_START 0x000c 42#define SPLIT_TIMEOUT_HI 0x0018 43#define SPLIT_TIMEOUT_LO 0x001c 44#define CYCLE_TIME 0x0200 45#define BUS_TIME 0x0204 46#define BUSY_TIMEOUT 0x0210 47#define PRIORITY_BUDGET 0x0218 48#define BUS_MGR_ID 0x021c 49#define BANDWIDTH_AV 0x0220 50#define CHANNELS_AV_HI 0x0224 51#define CHANNELS_AV_LO 0x0228 52#define IP_CHANNELS 0x0234 53 54#define CONF_ROM 0x0400 55 56#define TOPO_MAP 0x1000 57#define SPED_MAP 0x2000 58 59#define CSRTYPE_SHIFT 6 60#define CSRTYPE_MASK (3 << CSRTYPE_SHIFT) 61#define CSRTYPE_I (0 << CSRTYPE_SHIFT) /* Immediate */ 62#define CSRTYPE_C (1 << CSRTYPE_SHIFT) /* CSR offset */ 63#define CSRTYPE_L (2 << CSRTYPE_SHIFT) /* Leaf */ 64#define CSRTYPE_D (3 << CSRTYPE_SHIFT) /* Directory */ 65 66/* 67 * CSR keys 68 * 00 - 2F: defined by CSR architecture standards. 69 * 30 - 37: defined by BUS starndards 70 * 38 - 3F: defined by Vendor/Specifier 71 */ 72#define CSRKEY_MASK 0x3f 73#define CSRKEY_DESC 0x01 /* Descriptor */ 74#define CSRKEY_BDINFO 0x02 /* Bus_Dependent_Info */ 75#define CSRKEY_VENDOR 0x03 /* Vendor */ 76#define CSRKEY_HW 0x04 /* Hardware_Version */ 77#define CSRKEY_MODULE 0x07 /* Module */ 78#define CSRKEY_NCAP 0x0c /* Node_Capabilities */ 79#define CSRKEY_EUI64 0x0d /* EUI_64 */ 80#define CSRKEY_UNIT 0x11 /* Unit */ 81#define CSRKEY_SPEC 0x12 /* Specifier_ID */ 82#define CSRKEY_VER 0x13 /* Version */ 83#define CSRKEY_DINFO 0x14 /* Dependent_Info */ 84#define CSRKEY_ULOC 0x15 /* Unit_Location */ 85#define CSRKEY_MODEL 0x17 /* Model */ 86#define CSRKEY_INST 0x18 /* Instance */ 87#define CSRKEY_KEYW 0x19 /* Keyword */ 88#define CSRKEY_FEAT 0x1a /* Feature */ 89#define CSRKEY_EROM 0x1b /* Extended_ROM */ 90#define CSRKEY_EKSID 0x1c /* Extended_Key_Specifier_ID */ 91#define CSRKEY_EKEY 0x1d /* Extended_Key */ 92#define CSRKEY_EDATA 0x1e /* Extended_Data */ 93#define CSRKEY_MDESC 0x1f /* Modifiable_Descriptor */ 94#define CSRKEY_DID 0x20 /* Directory_ID */ 95#define CSRKEY_REV 0x21 /* Revision */ 96 97#define CSRKEY_FIRM_VER 0x3c /* Firmware version */ 98#define CSRKEY_UNIT_CH 0x3a /* Unit characteristics */ 99#define CSRKEY_COM_SPEC 0x38 /* Command set revision */ 100#define CSRKEY_COM_SET 0x39 /* Command set */ 101 102#define CROM_UDIR (CSRTYPE_D | CSRKEY_UNIT) /* 0x81 Unit directory */ 103#define CROM_TEXTLEAF (CSRTYPE_L | CSRKEY_DESC) /* 0x81 Text leaf */ 104#define CROM_LUN (CSRTYPE_I | CSRKEY_DINFO) /* 0x14 Logical unit num. */ 105#define CROM_MGM (CSRTYPE_C | CSRKEY_DINFO) /* 0x54 Management agent */ 106 107#define CSRVAL_VENDOR_PRIVATE 0xacde48 108#define CSRVAL_1394TA 0x00a02d 109#define CSRVAL_ANSIT10 0x00609e 110#define CSRVAL_IETF 0x00005e 111 112#define CSR_PROTAVC 0x010001 113#define CSR_PROTCAL 0x010002 114#define CSR_PROTEHS 0x010004 115#define CSR_PROTHAVI 0x010008 116#define CSR_PROTCAM104 0x000100 117#define CSR_PROTCAM120 0x000101 118#define CSR_PROTCAM130 0x000102 119#define CSR_PROTDPP 0x0a6be2 120#define CSR_PROTIICP 0x4b661f 121 122#define CSRVAL_T10SBP2 0x010483 123#define CSRVAL_SCSI 0x0104d8 124 125struct csrreg { 126#if BYTE_ORDER == BIG_ENDIAN 127 uint32_t key:8, 128 val:24; 129#else 130 uint32_t val:24, 131 key:8; 132#endif 133}; 134struct csrhdr { 135#if BYTE_ORDER == BIG_ENDIAN 136 uint32_t info_len:8, 137 crc_len:8, 138 crc:16; 139#else 140 uint32_t crc:16, 141 crc_len:8, 142 info_len:8; 143#endif 144}; 145struct csrdirectory { 146 BIT16x2(crc_len, crc); 147 struct csrreg entry[0]; 148}; 149struct csrtext { 150 BIT16x2(crc_len, crc); 151#if BYTE_ORDER == BIG_ENDIAN 152 uint32_t spec_type:8, 153 spec_id:24; 154#else 155 uint32_t spec_id:24, 156 spec_type:8; 157#endif 158 uint32_t lang_id; 159 uint32_t text[0]; 160}; 161 162struct bus_info { 163#define CSR_BUS_NAME_IEEE1394 0x31333934 164 uint32_t bus_name; 165#if BYTE_ORDER == BIG_ENDIAN 166 uint32_t irmc:1, /* iso. resource manager capable */ 167 cmc:1, /* cycle master capable */ 168 isc:1, /* iso. operation support */ 169 bmc:1, /* bus manager capable */ 170 pmc:1, /* power manager capable */ 171 :3, 172 cyc_clk_acc:8, /* 0 <= ppm <= 100 */ 173 max_rec:4, /* (2 << max_rec) bytes */ 174 :2, 175 max_rom:2, 176 generation:4, 177 :1, 178 link_spd:3; 179#else 180 uint32_t link_spd:3, 181 :1, 182 generation:4, 183 max_rom:2, 184 :2, 185 max_rec:4, /* (2 << max_rec) bytes */ 186 cyc_clk_acc:8, /* 0 <= ppm <= 100 */ 187 :3, 188 pmc:1, /* power manager capable */ 189 bmc:1, /* bus manager capable */ 190 isc:1, /* iso. operation support */ 191 cmc:1, /* cycle master capable */ 192 irmc:1; /* iso. resource manager capable */ 193#endif 194 struct fw_eui64 eui64; 195}; 196/* max_rom */ 197#define MAXROM_4 0 198#define MAXROM_64 1 199#define MAXROM_1024 2 200 201#define CROM_MAX_DEPTH 10 202struct crom_ptr { 203 struct csrdirectory *dir; 204 int index; 205}; 206 207struct crom_context { 208 int depth; 209 struct crom_ptr stack[CROM_MAX_DEPTH]; 210}; 211 212void crom_init_context(struct crom_context *, uint32_t *); 213struct csrreg *crom_get(struct crom_context *); 214void crom_next(struct crom_context *); 215void crom_parse_text(struct crom_context *, char *, int); 216uint16_t crom_crc(uint32_t *r, int); 217struct csrreg *crom_search_key(struct crom_context *, uint8_t); 218int crom_has_specver(uint32_t *, uint32_t, uint32_t); 219 220#if !defined(_KERNEL) && !defined(_BOOT) 221char *crom_desc(struct crom_context *, char *, int); 222#endif 223 224/* For CROM build */ 225#if defined(_KERNEL) || defined(_BOOT) || defined(TEST) 226#define CROM_MAX_CHUNK_LEN 20 227struct crom_src { 228 struct csrhdr hdr; 229 struct bus_info businfo; 230 STAILQ_HEAD(, crom_chunk) chunk_list; 231}; 232 233struct crom_chunk { 234 STAILQ_ENTRY(crom_chunk) link; 235 struct crom_chunk *ref_chunk; 236 int ref_index; 237 int offset; 238 struct { 239 BIT16x2(crc_len, crc); 240 uint32_t buf[CROM_MAX_CHUNK_LEN]; 241 } data; 242}; 243 244extern int crom_add_quad(struct crom_chunk *, uint32_t); 245extern int crom_add_entry(struct crom_chunk *, int, int); 246extern int crom_add_chunk(struct crom_src *src, struct crom_chunk *, 247 struct crom_chunk *, int); 248extern int crom_add_simple_text(struct crom_src *src, struct crom_chunk *, 249 struct crom_chunk *, char *); 250extern int crom_load(struct crom_src *, uint32_t *, int); 251#endif 252