fwohcireg.h revision 108662
1116742Ssam/* 2116904Ssam * Copyright (c) 1998-2001 Katsushi Kobayashi and Hidetoshi Shimokawa 3186904Ssam * All rights reserved. 4116742Ssam * 5116742Ssam * Redistribution and use in source and binary forms, with or without 6116742Ssam * modification, are permitted provided that the following conditions 7116742Ssam * are met: 8116742Ssam * 1. Redistributions of source code must retain the above copyright 9116742Ssam * notice, this list of conditions and the following disclaimer. 10116742Ssam * 2. Redistributions in binary form must reproduce the above copyright 11116742Ssam * notice, this list of conditions and the following disclaimer in the 12116742Ssam * documentation and/or other materials provided with the distribution. 13116742Ssam * 3. All advertising materials mentioning features or use of this software 14116742Ssam * must display the acknowledgement as bellow: 15116904Ssam * 16116904Ssam * This product includes software developed by K. Kobayashi and H. Shimokawa 17116904Ssam * 18116904Ssam * 4. The name of the author may not be used to endorse or promote products 19116904Ssam * derived from this software without specific prior written permission. 20116904Ssam * 21116904Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22116904Ssam * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23116904Ssam * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24116904Ssam * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25116904Ssam * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26116742Ssam * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27116742Ssam * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28116742Ssam * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29116742Ssam * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30116742Ssam * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31116742Ssam * POSSIBILITY OF SUCH DAMAGE. 32116742Ssam * 33116742Ssam * $FreeBSD: head/sys/dev/firewire/fwohcireg.h 108662 2003-01-04 16:03:50Z simokawa $ 34116742Ssam * 35116742Ssam */ 36116742Ssam#define PCI_CBMEM 0x10 37116742Ssam 38116742Ssam#define FW_VENDORID_NEC (0x1033 << 16) 39191756Ssam#define FW_VENDORID_TI (0x104c << 16) 40191756Ssam#define FW_VENDORID_SONY (0x104d << 16) 41116742Ssam#define FW_VENDORID_VIA (0x1106 << 16) 42116742Ssam#define FW_VENDORID_RICOH (0x1180 << 16) 43170530Ssam#define FW_VENDORID_APPLE (0x106b << 16) 44170530Ssam#define FW_VENDORID_LUCENT (0x11c1 << 16) 45170530Ssam 46170530Ssam#define FW_DEVICE_UPD861 0x0063 47170530Ssam#define FW_DEVICE_TITSB22 0x8009 48138568Ssam#define FW_DEVICE_TITSB23 0x8019 49116742Ssam#define FW_DEVICE_TITSB26 0x8020 50127903Ssam#define FW_DEVICE_TITSB43 0x8021 51127903Ssam#define FW_DEVICE_TITSB43A 0x8023 52178952Ssam#define FW_DEVICE_TIPCI4450 0x8011 53178952Ssam#define FW_DEVICE_TIPCI4410A 0x8017 54178952Ssam#define FW_DEVICE_CX3022 0x8039 55178952Ssam#define FW_DEVICE_VT6306 0x3044 56178952Ssam#define FW_DEVICE_R5C552 0x0552 57127903Ssam#define FW_DEVICE_PANGEA 0x0030 58116742Ssam#define FW_DEVICE_UNINORTH 0x0031 59116742Ssam#define FW_DEVICE_FW322 0x5811 60116742Ssam 61116742Ssam#define PCI_INTERFACE_OHCI 0x10 62170530Ssam 63170530Ssam#define FW_OHCI_BASE_REG 0x10 64170530Ssam 65170530Ssam#define OHCI_DMA_ITCH 0x20 66170530Ssam#define OHCI_DMA_IRCH 0x20 67170530Ssam 68116742Ssam#define OHCI_MAX_DMA_CH (0x4 + OHCI_DMA_ITCH + OHCI_DMA_IRCH) 69116742Ssam 70138568Ssam 71116742Ssamtypedef volatile u_int32_t fwohcireg_t; 72127903Ssam 73170530Ssamstruct fwohcidb { 74170530Ssam union { 75170530Ssam struct { 76170530Ssam volatile u_int32_t cmd; 77170530Ssam volatile u_int32_t addr; 78170530Ssam volatile u_int32_t depend; 79170530Ssam volatile u_int32_t count:16, 80127903Ssam status:16; 81127903Ssam } desc; 82138568Ssam volatile u_int32_t immed[4]; 83127903Ssam } db; 84127903Ssam#define OHCI_OUTPUT_MORE (0 << 28) 85170530Ssam#define OHCI_OUTPUT_LAST (1 << 28) 86127903Ssam#define OHCI_INPUT_MORE (2 << 28) 87127903Ssam#define OHCI_INPUT_LAST (3 << 28) 88116742Ssam#define OHCI_STORE_QUAD (4 << 28) 89170530Ssam#define OHCI_LOAD_QUAD (5 << 28) 90170530Ssam#define OHCI_NOP (6 << 28) 91170530Ssam#define OHCI_STOP (7 << 28) 92170530Ssam#define OHCI_STORE (8 << 28) 93170530Ssam#define OHCI_CMD_MASK (0xf << 28) 94170530Ssam 95170530Ssam#define OHCI_UPDATE (1 << 27) 96138568Ssam 97116742Ssam#define OHCI_KEY_ST0 (0 << 24) 98127903Ssam#define OHCI_KEY_ST1 (1 << 24) 99127903Ssam#define OHCI_KEY_ST2 (2 << 24) 100170530Ssam#define OHCI_KEY_ST3 (3 << 24) 101170530Ssam#define OHCI_KEY_REGS (5 << 24) 102170530Ssam#define OHCI_KEY_SYS (6 << 24) 103170530Ssam#define OHCI_KEY_DEVICE (7 << 24) 104170530Ssam#define OHCI_KEY_MASK (7 << 24) 105170530Ssam 106170530Ssam#define OHCI_INTERRUPT_NEVER (0 << 20) 107170530Ssam#define OHCI_INTERRUPT_TRUE (1 << 20) 108138568Ssam#define OHCI_INTERRUPT_FALSE (2 << 20) 109127903Ssam#define OHCI_INTERRUPT_ALWAYS (3 << 20) 110116742Ssam 111116742Ssam#define OHCI_BRANCH_NEVER (0 << 18) 112116742Ssam#define OHCI_BRANCH_TRUE (1 << 18) 113116742Ssam#define OHCI_BRANCH_FALSE (2 << 18) 114116742Ssam#define OHCI_BRANCH_ALWAYS (3 << 18) 115116742Ssam#define OHCI_BRANCH_MASK (3 << 18) 116116742Ssam 117116742Ssam#define OHCI_WAIT_NEVER (0 << 16) 118116742Ssam#define OHCI_WAIT_TRUE (1 << 16) 119116742Ssam#define OHCI_WAIT_FALSE (2 << 16) 120116742Ssam#define OHCI_WAIT_ALWAYS (3 << 16) 121116742Ssam}; 122116742Ssam 123116742Ssam#define OHCI_SPD_S100 0x4 124116742Ssam#define OHCI_SPD_S200 0x1 125116742Ssam#define OHCI_SPD_S400 0x2 126116742Ssam 127116742Ssam 128116742Ssam#define FWOHCIEV_NOSTAT 0 129116742Ssam#define FWOHCIEV_LONGP 2 130116742Ssam#define FWOHCIEV_MISSACK 3 131116742Ssam#define FWOHCIEV_UNDRRUN 4 132116742Ssam#define FWOHCIEV_OVRRUN 5 133170530Ssam#define FWOHCIEV_DESCERR 6 134218927Sbschmidt#define FWOHCIEV_DTRDERR 7 135116742Ssam#define FWOHCIEV_DTWRERR 8 136170530Ssam#define FWOHCIEV_BUSRST 9 137192328Ssam#define FWOHCIEV_TIMEOUT 0xa 138116742Ssam#define FWOHCIEV_TCODERR 0xb 139116742Ssam#define FWOHCIEV_UNKNOWN 0xe 140116742Ssam#define FWOHCIEV_FLUSHED 0xf 141116742Ssam#define FWOHCIEV_ACKCOMPL 0x11 142116742Ssam#define FWOHCIEV_ACKPEND 0x12 143116742Ssam#define FWOHCIEV_ACKBSX 0x14 144116742Ssam#define FWOHCIEV_ACKBSA 0x15 145116742Ssam#define FWOHCIEV_ACKBSB 0x16 146116742Ssam#define FWOHCIEV_ACKTARD 0x1b 147116742Ssam#define FWOHCIEV_ACKDERR 0x1d 148116742Ssam#define FWOHCIEV_ACKTERR 0x1e 149116742Ssam 150116742Ssam#define FWOHCIEV_MASK 0x1f 151116742Ssam 152116742Ssamstruct ohci_registers { 153127903Ssam fwohcireg_t ver; /* Version No. 0x0 */ 154138568Ssam fwohcireg_t guid; /* GUID_ROM No. 0x4 */ 155116742Ssam fwohcireg_t retry; /* AT retries 0x8 */ 156116742Ssam#define FWOHCI_RETRY 0x8 157116742Ssam fwohcireg_t csr_data; /* CSR data 0xc */ 158116742Ssam fwohcireg_t csr_cmp; /* CSR compare 0x10 */ 159116742Ssam fwohcireg_t csr_cntl; /* CSR compare 0x14 */ 160116742Ssam fwohcireg_t rom_hdr; /* config ROM ptr. 0x18 */ 161116742Ssam fwohcireg_t bus_id; /* BUS_ID 0x1c */ 162193840Ssam fwohcireg_t bus_opt; /* BUS option 0x20 */ 163193840Ssam#define FWOHCIGUID_H 0x24 164193840Ssam#define FWOHCIGUID_L 0x28 165116742Ssam fwohcireg_t guid_hi; /* GUID hi 0x24 */ 166116742Ssam fwohcireg_t guid_lo; /* GUID lo 0x28 */ 167116742Ssam fwohcireg_t dummy0[2]; /* dummy 0x2c-0x30 */ 168116742Ssam fwohcireg_t config_rom; /* config ROM map 0x34 */ 169116742Ssam fwohcireg_t post_wr_lo; /* post write addr lo 0x38 */ 170116742Ssam fwohcireg_t post_wr_hi; /* post write addr hi 0x3c */ 171116742Ssam fwohcireg_t vender; /* vender ID 0x40 */ 172116742Ssam fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */ 173116742Ssam fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */ 174116742Ssam fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */ 175116742Ssam#define OHCI_HCC_BIBIV (1 << 31) /* BIBimage Valid */ 176170530Ssam#define OHCI_HCC_BIGEND (1 << 30) /* noByteSwapData */ 177116742Ssam#define OHCI_HCC_PRPHY (1 << 23) /* programPhyEnable */ 178170530Ssam#define OHCI_HCC_PHYEN (1 << 22) /* aPhyEnhanceEnable */ 179170530Ssam#define OHCI_HCC_LPS (1 << 19) /* LPS */ 180170530Ssam#define OHCI_HCC_POSTWR (1 << 18) /* postedWriteEnable */ 181170530Ssam#define OHCI_HCC_LINKEN (1 << 17) /* linkEnable */ 182170530Ssam#define OHCI_HCC_RESET (1 << 16) /* softReset */ 183170530Ssam fwohcireg_t dummy2[2]; /* dummy 0x58-0x5c */ 184173273Ssam fwohcireg_t dummy3[1]; /* dummy 0x60 */ 185173273Ssam fwohcireg_t sid_buf; /* self id buffer 0x64 */ 186173273Ssam fwohcireg_t sid_cnt; /* self id count 0x68 */ 187173273Ssam fwohcireg_t dummy4[1]; /* dummy 0x6c */ 188116742Ssam fwohcireg_t ir_mask_hi_set; /* ir mask hi set 0x70 */ 189195618Srpaulo fwohcireg_t ir_mask_hi_clr; /* ir mask hi set 0x74 */ 190116742Ssam fwohcireg_t ir_mask_lo_set; /* ir mask hi set 0x78 */ 191127903Ssam fwohcireg_t ir_mask_lo_clr; /* ir mask hi set 0x7c */ 192127903Ssam#define FWOHCI_INTSTAT 0x80 193170530Ssam#define FWOHCI_INTSTATCLR 0x84 194170530Ssam#define FWOHCI_INTMASK 0x88 195138568Ssam#define FWOHCI_INTMASKCLR 0x8c 196138568Ssam fwohcireg_t int_stat; /* 0x80 */ 197170530Ssam fwohcireg_t int_clear; /* 0x84 */ 198170530Ssam fwohcireg_t int_mask; /* 0x88 */ 199183243Ssam fwohcireg_t int_mask_clear; /* 0x8c */ 200183243Ssam fwohcireg_t it_int_stat; /* 0x90 */ 201138568Ssam fwohcireg_t it_int_clear; /* 0x94 */ 202127903Ssam fwohcireg_t it_int_mask; /* 0x98 */ 203138568Ssam fwohcireg_t it_mask_clear; /* 0x9c */ 204138568Ssam fwohcireg_t ir_int_stat; /* 0xa0 */ 205138568Ssam fwohcireg_t ir_int_clear; /* 0xa4 */ 206138568Ssam fwohcireg_t ir_int_mask; /* 0xa8 */ 207138568Ssam fwohcireg_t ir_mask_clear; /* 0xac */ 208138568Ssam fwohcireg_t dummy5[11]; /* dummy 0xb0-d8 */ 209116742Ssam fwohcireg_t fairness; /* fairness control 0xdc */ 210138568Ssam fwohcireg_t link_cntl; /* Chip control 0xe0*/ 211138568Ssam fwohcireg_t link_cntl_clr; /* Chip control clear 0xe4*/ 212138568Ssam#define FWOHCI_NODEID 0xe8 213170530Ssam fwohcireg_t node; /* Node ID 0xe8 */ 214170530Ssam#define OHCI_NODE_VALID (1 << 31) 215170530Ssam#define OHCI_NODE_ROOT (1 << 30) 216170530Ssam 217170530Ssam#define OHCI_ASYSRCBUS 1 218170530Ssam 219170530Ssam fwohcireg_t phy_access; /* PHY cntl 0xec */ 220138568Ssam#define PHYDEV_RDDONE (1<<31) 221138568Ssam#define PHYDEV_RDCMD (1<<15) 222138568Ssam#define PHYDEV_WRCMD (1<<14) 223138568Ssam#define PHYDEV_REGADDR 8 224138568Ssam#define PHYDEV_WRDATA 0 225138568Ssam#define PHYDEV_RDADDR 24 226170530Ssam#define PHYDEV_RDDATA 16 227170530Ssam 228170530Ssam fwohcireg_t cycle_timer; /* Cycle Timer 0xf0 */ 229170530Ssam fwohcireg_t dummy6[3]; /* dummy 0xf4-fc */ 230170530Ssam fwohcireg_t areq_hi; /* Async req. filter hi 0x100 */ 231170530Ssam fwohcireg_t areq_hi_clr; /* Async req. filter hi 0x104 */ 232170530Ssam fwohcireg_t areq_lo; /* Async req. filter lo 0x108 */ 233170530Ssam fwohcireg_t areq_lo_clr; /* Async req. filter lo 0x10c */ 234170530Ssam fwohcireg_t preq_hi; /* Async req. filter hi 0x110 */ 235170530Ssam fwohcireg_t preq_hi_clr; /* Async req. filter hi 0x114 */ 236170530Ssam fwohcireg_t preq_lo; /* Async req. filter lo 0x118 */ 237170530Ssam fwohcireg_t preq_lo_clr; /* Async req. filter lo 0x11c */ 238170530Ssam 239170530Ssam fwohcireg_t pys_upper; /* Physical Upper bound 0x120 */ 240170530Ssam 241170530Ssam fwohcireg_t dummy7[23]; /* dummy 0x124-0x17c */ 242170530Ssam 243170530Ssam struct ohci_dma{ 244170530Ssam fwohcireg_t cntl; 245170530Ssam 246170530Ssam#define OHCI_CNTL_CYCMATCH_S (0x1 << 31) 247170530Ssam 248138568Ssam#define OHCI_CNTL_BUFFIL (0x1 << 31) 249138568Ssam#define OHCI_CNTL_ISOHDR (0x1 << 30) 250138568Ssam#define OHCI_CNTL_CYCMATCH_R (0x1 << 29) 251138568Ssam#define OHCI_CNTL_MULTICH (0x1 << 28) 252138568Ssam 253138568Ssam#define OHCI_CNTL_DMA_RUN (0x1 << 15) 254170530Ssam#define OHCI_CNTL_DMA_WAKE (0x1 << 12) 255170530Ssam#define OHCI_CNTL_DMA_DEAD (0x1 << 11) 256170530Ssam#define OHCI_CNTL_DMA_ACTIVE (0x1 << 10) 257138568Ssam#define OHCI_CNTL_DMA_BT (0x1 << 8) 258138568Ssam#define OHCI_CNTL_DMA_BAD (0x1 << 7) 259138568Ssam#define OHCI_CNTL_DMA_STAT (0xff) 260170530Ssam 261138568Ssam fwohcireg_t cntl_clr; 262138568Ssam fwohcireg_t dummy0; 263138568Ssam fwohcireg_t cmd; 264138568Ssam fwohcireg_t match; 265138568Ssam fwohcireg_t dummy1; 266138568Ssam fwohcireg_t dummy2; 267138568Ssam fwohcireg_t dummy3; 268138568Ssam }; 269138568Ssam /* 0x180, 0x184, 0x188, 0x18c */ 270138568Ssam /* 0x190, 0x194, 0x198, 0x19c */ 271138568Ssam /* 0x1a0, 0x1a4, 0x1a8, 0x1ac */ 272138568Ssam /* 0x1b0, 0x1b4, 0x1b8, 0x1bc */ 273138568Ssam /* 0x1c0, 0x1c4, 0x1c8, 0x1cc */ 274138568Ssam /* 0x1d0, 0x1d4, 0x1d8, 0x1dc */ 275138568Ssam /* 0x1e0, 0x1e4, 0x1e8, 0x1ec */ 276138568Ssam /* 0x1f0, 0x1f4, 0x1f8, 0x1fc */ 277138568Ssam struct ohci_dma dma_ch[0x4]; 278138568Ssam 279138568Ssam /* 0x200, 0x204, 0x208, 0x20c */ 280173863Ssam /* 0x210, 0x204, 0x208, 0x20c */ 281138568Ssam struct ohci_itdma{ 282138568Ssam fwohcireg_t cntl; 283138568Ssam fwohcireg_t cntl_clr; 284138568Ssam fwohcireg_t dummy0; 285138568Ssam fwohcireg_t cmd; 286138568Ssam }; 287138568Ssam struct ohci_itdma dma_itch[0x20]; 288138568Ssam 289170530Ssam /* 0x400, 0x404, 0x408, 0x40c */ 290170530Ssam /* 0x410, 0x404, 0x408, 0x40c */ 291170530Ssam 292170530Ssam struct ohci_dma dma_irch[0x20]; 293172055Ssam}; 294170530Ssam 295170530Ssamstruct fwohcidb_tr{ 296138568Ssam STAILQ_ENTRY(fwohcidb_tr) link; 297170530Ssam struct fw_xfer *xfer; 298138568Ssam volatile struct fwohcidb *db; 299138568Ssam caddr_t buf; 300138568Ssam caddr_t dummy; 301138568Ssam int dbcnt; 302138568Ssam}; 303138568Ssam 304138568Ssam/* 305170530Ssam * OHCI info structure. 306170530Ssam */ 307170530Ssamstruct fwohci_txpkthdr{ 308170530Ssam union{ 309138568Ssam u_int32_t ld[4]; 310138568Ssam struct { 311138568Ssam u_int32_t res3:4, 312138568Ssam tcode:4, 313138568Ssam res2:8, 314170530Ssam spd:3, 315170530Ssam res1:13; 316170530Ssam }common; 317170530Ssam struct { 318170530Ssam u_int32_t res3:4, 319170530Ssam tcode:4, 320170530Ssam tlrt:8, 321170530Ssam spd:3, 322170530Ssam res2:4, 323193542Ssam srcbus:1, 324193542Ssam res1:8; 325193542Ssam u_int32_t res4:16, 326170530Ssam dst:16; 327172055Ssam }asycomm; 328193542Ssam struct { 329170530Ssam u_int32_t sy:4, 330170530Ssam tcode:4, 331170530Ssam chtag:8, 332170530Ssam spd:3, 333170530Ssam res1:13; 334170530Ssam u_int32_t res2:16, 335170530Ssam len:16; 336170530Ssam }stream; 337170530Ssam }mode; 338170530Ssam}; 339170530Ssamstruct fwohci_trailer{ 340170530Ssam u_int32_t time:16, 341170530Ssam stat:16; 342172055Ssam}; 343170530Ssam 344170530Ssam#define OHCI_CNTL_CYCSRC (0x1 << 22) 345173618Ssam#define OHCI_CNTL_CYCMTR (0x1 << 21) 346170530Ssam#define OHCI_CNTL_CYCTIMER (0x1 << 20) 347170530Ssam#define OHCI_CNTL_PHYPKT (0x1 << 10) 348173618Ssam#define OHCI_CNTL_SID (0x1 << 9) 349173618Ssam 350173618Ssam#define OHCI_INT_DMA_ATRQ (0x1 << 0) 351173618Ssam#define OHCI_INT_DMA_ATRS (0x1 << 1) 352173618Ssam#define OHCI_INT_DMA_ARRQ (0x1 << 2) 353173618Ssam#define OHCI_INT_DMA_ARRS (0x1 << 3) 354173618Ssam#define OHCI_INT_DMA_PRRQ (0x1 << 4) 355170530Ssam#define OHCI_INT_DMA_PRRS (0x1 << 5) 356170530Ssam#define OHCI_INT_DMA_IT (0x1 << 6) 357170530Ssam#define OHCI_INT_DMA_IR (0x1 << 7) 358170530Ssam#define OHCI_INT_PW_ERR (0x1 << 8) 359170530Ssam#define OHCI_INT_LR_ERR (0x1 << 9) 360170530Ssam 361170530Ssam#define OHCI_INT_PHY_SID (0x1 << 16) 362170530Ssam#define OHCI_INT_PHY_BUS_R (0x1 << 17) 363170530Ssam 364170530Ssam#define OHCI_INT_REG_FAIL (0x1 << 18) 365170530Ssam 366170530Ssam#define OHCI_INT_PHY_INT (0x1 << 19) 367170530Ssam#define OHCI_INT_CYC_START (0x1 << 20) 368170530Ssam#define OHCI_INT_CYC_64SECOND (0x1 << 21) 369170530Ssam#define OHCI_INT_CYC_LOST (0x1 << 22) 370170530Ssam#define OHCI_INT_CYC_ERR (0x1 << 23) 371170530Ssam 372170530Ssam#define OHCI_INT_ERR (0x1 << 24) 373170530Ssam#define OHCI_INT_CYC_LONG (0x1 << 25) 374170530Ssam#define OHCI_INT_PHY_REG (0x1 << 26) 375170530Ssam 376170530Ssam#define OHCI_INT_EN (0x1 << 31) 377170530Ssam 378170530Ssam#define IP_CHANNELS 0x0234 379170530Ssam#define FWOHCI_MAXREC 2048 380170530Ssam 381170530Ssam#define OHCI_ISORA 0x02 382170530Ssam#define OHCI_ISORB 0x04 383170530Ssam 384170530Ssam#define FWOHCITCODE_PHY 0xe 385170530Ssam