fwohcireg.h revision 108662
1292915Sdim/* 2292915Sdim * Copyright (c) 1998-2001 Katsushi Kobayashi and Hidetoshi Shimokawa 3353358Sdim * All rights reserved. 4353358Sdim * 5353358Sdim * Redistribution and use in source and binary forms, with or without 6292915Sdim * modification, are permitted provided that the following conditions 7292915Sdim * are met: 8292915Sdim * 1. Redistributions of source code must retain the above copyright 9292915Sdim * notice, this list of conditions and the following disclaimer. 10341825Sdim * 2. Redistributions in binary form must reproduce the above copyright 11292915Sdim * notice, this list of conditions and the following disclaimer in the 12292915Sdim * documentation and/or other materials provided with the distribution. 13292915Sdim * 3. All advertising materials mentioning features or use of this software 14292915Sdim * must display the acknowledgement as bellow: 15292915Sdim * 16292915Sdim * This product includes software developed by K. Kobayashi and H. Shimokawa 17341825Sdim * 18292915Sdim * 4. The name of the author may not be used to endorse or promote products 19292915Sdim * derived from this software without specific prior written permission. 20321369Sdim * 21321369Sdim * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22321369Sdim * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23321369Sdim * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24321369Sdim * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/firewire/fwohcireg.h 108662 2003-01-04 16:03:50Z simokawa $ 34 * 35 */ 36#define PCI_CBMEM 0x10 37 38#define FW_VENDORID_NEC (0x1033 << 16) 39#define FW_VENDORID_TI (0x104c << 16) 40#define FW_VENDORID_SONY (0x104d << 16) 41#define FW_VENDORID_VIA (0x1106 << 16) 42#define FW_VENDORID_RICOH (0x1180 << 16) 43#define FW_VENDORID_APPLE (0x106b << 16) 44#define FW_VENDORID_LUCENT (0x11c1 << 16) 45 46#define FW_DEVICE_UPD861 0x0063 47#define FW_DEVICE_TITSB22 0x8009 48#define FW_DEVICE_TITSB23 0x8019 49#define FW_DEVICE_TITSB26 0x8020 50#define FW_DEVICE_TITSB43 0x8021 51#define FW_DEVICE_TITSB43A 0x8023 52#define FW_DEVICE_TIPCI4450 0x8011 53#define FW_DEVICE_TIPCI4410A 0x8017 54#define FW_DEVICE_CX3022 0x8039 55#define FW_DEVICE_VT6306 0x3044 56#define FW_DEVICE_R5C552 0x0552 57#define FW_DEVICE_PANGEA 0x0030 58#define FW_DEVICE_UNINORTH 0x0031 59#define FW_DEVICE_FW322 0x5811 60 61#define PCI_INTERFACE_OHCI 0x10 62 63#define FW_OHCI_BASE_REG 0x10 64 65#define OHCI_DMA_ITCH 0x20 66#define OHCI_DMA_IRCH 0x20 67 68#define OHCI_MAX_DMA_CH (0x4 + OHCI_DMA_ITCH + OHCI_DMA_IRCH) 69 70 71typedef volatile u_int32_t fwohcireg_t; 72 73struct fwohcidb { 74 union { 75 struct { 76 volatile u_int32_t cmd; 77 volatile u_int32_t addr; 78 volatile u_int32_t depend; 79 volatile u_int32_t count:16, 80 status:16; 81 } desc; 82 volatile u_int32_t immed[4]; 83 } db; 84#define OHCI_OUTPUT_MORE (0 << 28) 85#define OHCI_OUTPUT_LAST (1 << 28) 86#define OHCI_INPUT_MORE (2 << 28) 87#define OHCI_INPUT_LAST (3 << 28) 88#define OHCI_STORE_QUAD (4 << 28) 89#define OHCI_LOAD_QUAD (5 << 28) 90#define OHCI_NOP (6 << 28) 91#define OHCI_STOP (7 << 28) 92#define OHCI_STORE (8 << 28) 93#define OHCI_CMD_MASK (0xf << 28) 94 95#define OHCI_UPDATE (1 << 27) 96 97#define OHCI_KEY_ST0 (0 << 24) 98#define OHCI_KEY_ST1 (1 << 24) 99#define OHCI_KEY_ST2 (2 << 24) 100#define OHCI_KEY_ST3 (3 << 24) 101#define OHCI_KEY_REGS (5 << 24) 102#define OHCI_KEY_SYS (6 << 24) 103#define OHCI_KEY_DEVICE (7 << 24) 104#define OHCI_KEY_MASK (7 << 24) 105 106#define OHCI_INTERRUPT_NEVER (0 << 20) 107#define OHCI_INTERRUPT_TRUE (1 << 20) 108#define OHCI_INTERRUPT_FALSE (2 << 20) 109#define OHCI_INTERRUPT_ALWAYS (3 << 20) 110 111#define OHCI_BRANCH_NEVER (0 << 18) 112#define OHCI_BRANCH_TRUE (1 << 18) 113#define OHCI_BRANCH_FALSE (2 << 18) 114#define OHCI_BRANCH_ALWAYS (3 << 18) 115#define OHCI_BRANCH_MASK (3 << 18) 116 117#define OHCI_WAIT_NEVER (0 << 16) 118#define OHCI_WAIT_TRUE (1 << 16) 119#define OHCI_WAIT_FALSE (2 << 16) 120#define OHCI_WAIT_ALWAYS (3 << 16) 121}; 122 123#define OHCI_SPD_S100 0x4 124#define OHCI_SPD_S200 0x1 125#define OHCI_SPD_S400 0x2 126 127 128#define FWOHCIEV_NOSTAT 0 129#define FWOHCIEV_LONGP 2 130#define FWOHCIEV_MISSACK 3 131#define FWOHCIEV_UNDRRUN 4 132#define FWOHCIEV_OVRRUN 5 133#define FWOHCIEV_DESCERR 6 134#define FWOHCIEV_DTRDERR 7 135#define FWOHCIEV_DTWRERR 8 136#define FWOHCIEV_BUSRST 9 137#define FWOHCIEV_TIMEOUT 0xa 138#define FWOHCIEV_TCODERR 0xb 139#define FWOHCIEV_UNKNOWN 0xe 140#define FWOHCIEV_FLUSHED 0xf 141#define FWOHCIEV_ACKCOMPL 0x11 142#define FWOHCIEV_ACKPEND 0x12 143#define FWOHCIEV_ACKBSX 0x14 144#define FWOHCIEV_ACKBSA 0x15 145#define FWOHCIEV_ACKBSB 0x16 146#define FWOHCIEV_ACKTARD 0x1b 147#define FWOHCIEV_ACKDERR 0x1d 148#define FWOHCIEV_ACKTERR 0x1e 149 150#define FWOHCIEV_MASK 0x1f 151 152struct ohci_registers { 153 fwohcireg_t ver; /* Version No. 0x0 */ 154 fwohcireg_t guid; /* GUID_ROM No. 0x4 */ 155 fwohcireg_t retry; /* AT retries 0x8 */ 156#define FWOHCI_RETRY 0x8 157 fwohcireg_t csr_data; /* CSR data 0xc */ 158 fwohcireg_t csr_cmp; /* CSR compare 0x10 */ 159 fwohcireg_t csr_cntl; /* CSR compare 0x14 */ 160 fwohcireg_t rom_hdr; /* config ROM ptr. 0x18 */ 161 fwohcireg_t bus_id; /* BUS_ID 0x1c */ 162 fwohcireg_t bus_opt; /* BUS option 0x20 */ 163#define FWOHCIGUID_H 0x24 164#define FWOHCIGUID_L 0x28 165 fwohcireg_t guid_hi; /* GUID hi 0x24 */ 166 fwohcireg_t guid_lo; /* GUID lo 0x28 */ 167 fwohcireg_t dummy0[2]; /* dummy 0x2c-0x30 */ 168 fwohcireg_t config_rom; /* config ROM map 0x34 */ 169 fwohcireg_t post_wr_lo; /* post write addr lo 0x38 */ 170 fwohcireg_t post_wr_hi; /* post write addr hi 0x3c */ 171 fwohcireg_t vender; /* vender ID 0x40 */ 172 fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */ 173 fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */ 174 fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */ 175#define OHCI_HCC_BIBIV (1 << 31) /* BIBimage Valid */ 176#define OHCI_HCC_BIGEND (1 << 30) /* noByteSwapData */ 177#define OHCI_HCC_PRPHY (1 << 23) /* programPhyEnable */ 178#define OHCI_HCC_PHYEN (1 << 22) /* aPhyEnhanceEnable */ 179#define OHCI_HCC_LPS (1 << 19) /* LPS */ 180#define OHCI_HCC_POSTWR (1 << 18) /* postedWriteEnable */ 181#define OHCI_HCC_LINKEN (1 << 17) /* linkEnable */ 182#define OHCI_HCC_RESET (1 << 16) /* softReset */ 183 fwohcireg_t dummy2[2]; /* dummy 0x58-0x5c */ 184 fwohcireg_t dummy3[1]; /* dummy 0x60 */ 185 fwohcireg_t sid_buf; /* self id buffer 0x64 */ 186 fwohcireg_t sid_cnt; /* self id count 0x68 */ 187 fwohcireg_t dummy4[1]; /* dummy 0x6c */ 188 fwohcireg_t ir_mask_hi_set; /* ir mask hi set 0x70 */ 189 fwohcireg_t ir_mask_hi_clr; /* ir mask hi set 0x74 */ 190 fwohcireg_t ir_mask_lo_set; /* ir mask hi set 0x78 */ 191 fwohcireg_t ir_mask_lo_clr; /* ir mask hi set 0x7c */ 192#define FWOHCI_INTSTAT 0x80 193#define FWOHCI_INTSTATCLR 0x84 194#define FWOHCI_INTMASK 0x88 195#define FWOHCI_INTMASKCLR 0x8c 196 fwohcireg_t int_stat; /* 0x80 */ 197 fwohcireg_t int_clear; /* 0x84 */ 198 fwohcireg_t int_mask; /* 0x88 */ 199 fwohcireg_t int_mask_clear; /* 0x8c */ 200 fwohcireg_t it_int_stat; /* 0x90 */ 201 fwohcireg_t it_int_clear; /* 0x94 */ 202 fwohcireg_t it_int_mask; /* 0x98 */ 203 fwohcireg_t it_mask_clear; /* 0x9c */ 204 fwohcireg_t ir_int_stat; /* 0xa0 */ 205 fwohcireg_t ir_int_clear; /* 0xa4 */ 206 fwohcireg_t ir_int_mask; /* 0xa8 */ 207 fwohcireg_t ir_mask_clear; /* 0xac */ 208 fwohcireg_t dummy5[11]; /* dummy 0xb0-d8 */ 209 fwohcireg_t fairness; /* fairness control 0xdc */ 210 fwohcireg_t link_cntl; /* Chip control 0xe0*/ 211 fwohcireg_t link_cntl_clr; /* Chip control clear 0xe4*/ 212#define FWOHCI_NODEID 0xe8 213 fwohcireg_t node; /* Node ID 0xe8 */ 214#define OHCI_NODE_VALID (1 << 31) 215#define OHCI_NODE_ROOT (1 << 30) 216 217#define OHCI_ASYSRCBUS 1 218 219 fwohcireg_t phy_access; /* PHY cntl 0xec */ 220#define PHYDEV_RDDONE (1<<31) 221#define PHYDEV_RDCMD (1<<15) 222#define PHYDEV_WRCMD (1<<14) 223#define PHYDEV_REGADDR 8 224#define PHYDEV_WRDATA 0 225#define PHYDEV_RDADDR 24 226#define PHYDEV_RDDATA 16 227 228 fwohcireg_t cycle_timer; /* Cycle Timer 0xf0 */ 229 fwohcireg_t dummy6[3]; /* dummy 0xf4-fc */ 230 fwohcireg_t areq_hi; /* Async req. filter hi 0x100 */ 231 fwohcireg_t areq_hi_clr; /* Async req. filter hi 0x104 */ 232 fwohcireg_t areq_lo; /* Async req. filter lo 0x108 */ 233 fwohcireg_t areq_lo_clr; /* Async req. filter lo 0x10c */ 234 fwohcireg_t preq_hi; /* Async req. filter hi 0x110 */ 235 fwohcireg_t preq_hi_clr; /* Async req. filter hi 0x114 */ 236 fwohcireg_t preq_lo; /* Async req. filter lo 0x118 */ 237 fwohcireg_t preq_lo_clr; /* Async req. filter lo 0x11c */ 238 239 fwohcireg_t pys_upper; /* Physical Upper bound 0x120 */ 240 241 fwohcireg_t dummy7[23]; /* dummy 0x124-0x17c */ 242 243 struct ohci_dma{ 244 fwohcireg_t cntl; 245 246#define OHCI_CNTL_CYCMATCH_S (0x1 << 31) 247 248#define OHCI_CNTL_BUFFIL (0x1 << 31) 249#define OHCI_CNTL_ISOHDR (0x1 << 30) 250#define OHCI_CNTL_CYCMATCH_R (0x1 << 29) 251#define OHCI_CNTL_MULTICH (0x1 << 28) 252 253#define OHCI_CNTL_DMA_RUN (0x1 << 15) 254#define OHCI_CNTL_DMA_WAKE (0x1 << 12) 255#define OHCI_CNTL_DMA_DEAD (0x1 << 11) 256#define OHCI_CNTL_DMA_ACTIVE (0x1 << 10) 257#define OHCI_CNTL_DMA_BT (0x1 << 8) 258#define OHCI_CNTL_DMA_BAD (0x1 << 7) 259#define OHCI_CNTL_DMA_STAT (0xff) 260 261 fwohcireg_t cntl_clr; 262 fwohcireg_t dummy0; 263 fwohcireg_t cmd; 264 fwohcireg_t match; 265 fwohcireg_t dummy1; 266 fwohcireg_t dummy2; 267 fwohcireg_t dummy3; 268 }; 269 /* 0x180, 0x184, 0x188, 0x18c */ 270 /* 0x190, 0x194, 0x198, 0x19c */ 271 /* 0x1a0, 0x1a4, 0x1a8, 0x1ac */ 272 /* 0x1b0, 0x1b4, 0x1b8, 0x1bc */ 273 /* 0x1c0, 0x1c4, 0x1c8, 0x1cc */ 274 /* 0x1d0, 0x1d4, 0x1d8, 0x1dc */ 275 /* 0x1e0, 0x1e4, 0x1e8, 0x1ec */ 276 /* 0x1f0, 0x1f4, 0x1f8, 0x1fc */ 277 struct ohci_dma dma_ch[0x4]; 278 279 /* 0x200, 0x204, 0x208, 0x20c */ 280 /* 0x210, 0x204, 0x208, 0x20c */ 281 struct ohci_itdma{ 282 fwohcireg_t cntl; 283 fwohcireg_t cntl_clr; 284 fwohcireg_t dummy0; 285 fwohcireg_t cmd; 286 }; 287 struct ohci_itdma dma_itch[0x20]; 288 289 /* 0x400, 0x404, 0x408, 0x40c */ 290 /* 0x410, 0x404, 0x408, 0x40c */ 291 292 struct ohci_dma dma_irch[0x20]; 293}; 294 295struct fwohcidb_tr{ 296 STAILQ_ENTRY(fwohcidb_tr) link; 297 struct fw_xfer *xfer; 298 volatile struct fwohcidb *db; 299 caddr_t buf; 300 caddr_t dummy; 301 int dbcnt; 302}; 303 304/* 305 * OHCI info structure. 306 */ 307struct fwohci_txpkthdr{ 308 union{ 309 u_int32_t ld[4]; 310 struct { 311 u_int32_t res3:4, 312 tcode:4, 313 res2:8, 314 spd:3, 315 res1:13; 316 }common; 317 struct { 318 u_int32_t res3:4, 319 tcode:4, 320 tlrt:8, 321 spd:3, 322 res2:4, 323 srcbus:1, 324 res1:8; 325 u_int32_t res4:16, 326 dst:16; 327 }asycomm; 328 struct { 329 u_int32_t sy:4, 330 tcode:4, 331 chtag:8, 332 spd:3, 333 res1:13; 334 u_int32_t res2:16, 335 len:16; 336 }stream; 337 }mode; 338}; 339struct fwohci_trailer{ 340 u_int32_t time:16, 341 stat:16; 342}; 343 344#define OHCI_CNTL_CYCSRC (0x1 << 22) 345#define OHCI_CNTL_CYCMTR (0x1 << 21) 346#define OHCI_CNTL_CYCTIMER (0x1 << 20) 347#define OHCI_CNTL_PHYPKT (0x1 << 10) 348#define OHCI_CNTL_SID (0x1 << 9) 349 350#define OHCI_INT_DMA_ATRQ (0x1 << 0) 351#define OHCI_INT_DMA_ATRS (0x1 << 1) 352#define OHCI_INT_DMA_ARRQ (0x1 << 2) 353#define OHCI_INT_DMA_ARRS (0x1 << 3) 354#define OHCI_INT_DMA_PRRQ (0x1 << 4) 355#define OHCI_INT_DMA_PRRS (0x1 << 5) 356#define OHCI_INT_DMA_IT (0x1 << 6) 357#define OHCI_INT_DMA_IR (0x1 << 7) 358#define OHCI_INT_PW_ERR (0x1 << 8) 359#define OHCI_INT_LR_ERR (0x1 << 9) 360 361#define OHCI_INT_PHY_SID (0x1 << 16) 362#define OHCI_INT_PHY_BUS_R (0x1 << 17) 363 364#define OHCI_INT_REG_FAIL (0x1 << 18) 365 366#define OHCI_INT_PHY_INT (0x1 << 19) 367#define OHCI_INT_CYC_START (0x1 << 20) 368#define OHCI_INT_CYC_64SECOND (0x1 << 21) 369#define OHCI_INT_CYC_LOST (0x1 << 22) 370#define OHCI_INT_CYC_ERR (0x1 << 23) 371 372#define OHCI_INT_ERR (0x1 << 24) 373#define OHCI_INT_CYC_LONG (0x1 << 25) 374#define OHCI_INT_PHY_REG (0x1 << 26) 375 376#define OHCI_INT_EN (0x1 << 31) 377 378#define IP_CHANNELS 0x0234 379#define FWOHCI_MAXREC 2048 380 381#define OHCI_ISORA 0x02 382#define OHCI_ISORB 0x04 383 384#define FWOHCITCODE_PHY 0xe 385