fwohci.c revision 167685
1139749Simp/*- 2113584Ssimokawa * Copyright (c) 2003 Hidetoshi Shimokawa 3103285Sikob * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4103285Sikob * All rights reserved. 5103285Sikob * 6103285Sikob * Redistribution and use in source and binary forms, with or without 7103285Sikob * modification, are permitted provided that the following conditions 8103285Sikob * are met: 9103285Sikob * 1. Redistributions of source code must retain the above copyright 10103285Sikob * notice, this list of conditions and the following disclaimer. 11103285Sikob * 2. Redistributions in binary form must reproduce the above copyright 12103285Sikob * notice, this list of conditions and the following disclaimer in the 13103285Sikob * documentation and/or other materials provided with the distribution. 14103285Sikob * 3. All advertising materials mentioning features or use of this software 15103285Sikob * must display the acknowledgement as bellow: 16103285Sikob * 17106802Ssimokawa * This product includes software developed by K. Kobayashi and H. Shimokawa 18103285Sikob * 19103285Sikob * 4. The name of the author may not be used to endorse or promote products 20103285Sikob * derived from this software without specific prior written permission. 21103285Sikob * 22103285Sikob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23103285Sikob * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24103285Sikob * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25103285Sikob * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26103285Sikob * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27103285Sikob * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28103285Sikob * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29103285Sikob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30103285Sikob * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31103285Sikob * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32103285Sikob * POSSIBILITY OF SUCH DAMAGE. 33103285Sikob * 34103285Sikob * $FreeBSD: head/sys/dev/firewire/fwohci.c 167685 2007-03-19 03:35:45Z simokawa $ 35103285Sikob * 36103285Sikob */ 37106802Ssimokawa 38103285Sikob#define ATRQ_CH 0 39103285Sikob#define ATRS_CH 1 40103285Sikob#define ARRQ_CH 2 41103285Sikob#define ARRS_CH 3 42103285Sikob#define ITX_CH 4 43103285Sikob#define IRX_CH 0x24 44103285Sikob 45103285Sikob#include <sys/param.h> 46103285Sikob#include <sys/systm.h> 47103285Sikob#include <sys/mbuf.h> 48103285Sikob#include <sys/malloc.h> 49103285Sikob#include <sys/sockio.h> 50103285Sikob#include <sys/bus.h> 51103285Sikob#include <sys/kernel.h> 52103285Sikob#include <sys/conf.h> 53113584Ssimokawa#include <sys/endian.h> 54103285Sikob 55103285Sikob#include <machine/bus.h> 56103285Sikob 57127468Ssimokawa#if defined(__DragonFly__) || __FreeBSD_version < 500000 58117067Ssimokawa#include <machine/clock.h> /* for DELAY() */ 59117067Ssimokawa#endif 60117067Ssimokawa 61127468Ssimokawa#ifdef __DragonFly__ 62127468Ssimokawa#include "firewire.h" 63127468Ssimokawa#include "firewirereg.h" 64127468Ssimokawa#include "fwdma.h" 65127468Ssimokawa#include "fwohcireg.h" 66127468Ssimokawa#include "fwohcivar.h" 67127468Ssimokawa#include "firewire_phy.h" 68127468Ssimokawa#else 69103285Sikob#include <dev/firewire/firewire.h> 70103285Sikob#include <dev/firewire/firewirereg.h> 71113584Ssimokawa#include <dev/firewire/fwdma.h> 72103285Sikob#include <dev/firewire/fwohcireg.h> 73103285Sikob#include <dev/firewire/fwohcivar.h> 74103285Sikob#include <dev/firewire/firewire_phy.h> 75127468Ssimokawa#endif 76103285Sikob 77103285Sikob#undef OHCI_DEBUG 78106802Ssimokawa 79103285Sikobstatic char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 80103285Sikob "STOR","LOAD","NOP ","STOP",}; 81113584Ssimokawa 82103285Sikobstatic char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 83103285Sikob "UNDEF","REG","SYS","DEV"}; 84113584Ssimokawastatic char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 85103285Sikobchar fwohcicode[32][0x20]={ 86103285Sikob "No stat","Undef","long","miss Ack err", 87103285Sikob "underrun","overrun","desc err", "data read err", 88103285Sikob "data write err","bus reset","timeout","tcode err", 89103285Sikob "Undef","Undef","unknown event","flushed", 90103285Sikob "Undef","ack complete","ack pend","Undef", 91103285Sikob "ack busy_X","ack busy_A","ack busy_B","Undef", 92103285Sikob "Undef","Undef","Undef","ack tardy", 93103285Sikob "Undef","ack data_err","ack type_err",""}; 94113584Ssimokawa 95116376Ssimokawa#define MAX_SPEED 3 96124378Ssimokawaextern char *linkspeed[]; 97129585Sdfruint32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 98103285Sikob 99103285Sikobstatic struct tcode_info tinfo[] = { 100103285Sikob/* hdr_len block flag*/ 101103285Sikob/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 102103285Sikob/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 103103285Sikob/* 2 WRES */ {12, FWTI_RES}, 104103285Sikob/* 3 XXX */ { 0, 0}, 105103285Sikob/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 106103285Sikob/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 107103285Sikob/* 6 RRESQ */ {16, FWTI_RES}, 108103285Sikob/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 109103285Sikob/* 8 CYCS */ { 0, 0}, 110103285Sikob/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 111103285Sikob/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 112103285Sikob/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 113103285Sikob/* c XXX */ { 0, 0}, 114103285Sikob/* d XXX */ { 0, 0}, 115103285Sikob/* e PHY */ {12, FWTI_REQ}, 116103285Sikob/* f XXX */ { 0, 0} 117103285Sikob}; 118103285Sikob 119103285Sikob#define OHCI_WRITE_SIGMASK 0xffff0000 120103285Sikob#define OHCI_READ_SIGMASK 0xffff0000 121103285Sikob 122103285Sikob#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 123103285Sikob#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 124103285Sikob 125124169Ssimokawastatic void fwohci_ibr (struct firewire_comm *); 126124169Ssimokawastatic void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); 127124169Ssimokawastatic void fwohci_db_free (struct fwohci_dbch *); 128124169Ssimokawastatic void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); 129124169Ssimokawastatic void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); 130124169Ssimokawastatic void fwohci_start_atq (struct firewire_comm *); 131124169Ssimokawastatic void fwohci_start_ats (struct firewire_comm *); 132124169Ssimokawastatic void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); 133129585Sdfrstatic uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t); 134129585Sdfrstatic uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t); 135124169Ssimokawastatic int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); 136124169Ssimokawastatic int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); 137124169Ssimokawastatic int fwohci_irx_enable (struct firewire_comm *, int); 138124169Ssimokawastatic int fwohci_irx_disable (struct firewire_comm *, int); 139113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 140129585Sdfrstatic void fwohci_irx_post (struct firewire_comm *, uint32_t *); 141113584Ssimokawa#endif 142124169Ssimokawastatic int fwohci_itxbuf_enable (struct firewire_comm *, int); 143124169Ssimokawastatic int fwohci_itx_disable (struct firewire_comm *, int); 144124169Ssimokawastatic void fwohci_timeout (void *); 145124169Ssimokawastatic void fwohci_set_intr (struct firewire_comm *, int); 146113584Ssimokawa 147124169Ssimokawastatic int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); 148124169Ssimokawastatic int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); 149129585Sdfrstatic void dump_db (struct fwohci_softc *, uint32_t); 150129585Sdfrstatic void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t); 151129585Sdfrstatic void dump_dma (struct fwohci_softc *, uint32_t); 152129585Sdfrstatic uint32_t fwohci_cyctimer (struct firewire_comm *); 153124169Ssimokawastatic void fwohci_rbuf_update (struct fwohci_softc *, int); 154124169Ssimokawastatic void fwohci_tbuf_update (struct fwohci_softc *, int); 155124169Ssimokawavoid fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); 156113584Ssimokawa#if FWOHCI_TASKQUEUE 157113584Ssimokawastatic void fwohci_complete(void *, int); 158113584Ssimokawa#endif 159103285Sikob 160103285Sikob/* 161103285Sikob * memory allocated for DMA programs 162103285Sikob */ 163103285Sikob#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 164103285Sikob 165103285Sikob#define NDB FWMAXQUEUE 166103285Sikob 167103285Sikob#define OHCI_VERSION 0x00 168112523Ssimokawa#define OHCI_ATRETRY 0x08 169103285Sikob#define OHCI_CROMHDR 0x18 170103285Sikob#define OHCI_BUS_OPT 0x20 171103285Sikob#define OHCI_BUSIRMC (1 << 31) 172103285Sikob#define OHCI_BUSCMC (1 << 30) 173103285Sikob#define OHCI_BUSISC (1 << 29) 174103285Sikob#define OHCI_BUSBMC (1 << 28) 175103285Sikob#define OHCI_BUSPMC (1 << 27) 176103285Sikob#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 177103285Sikob OHCI_BUSBMC | OHCI_BUSPMC 178103285Sikob 179103285Sikob#define OHCI_EUID_HI 0x24 180103285Sikob#define OHCI_EUID_LO 0x28 181103285Sikob 182103285Sikob#define OHCI_CROMPTR 0x34 183103285Sikob#define OHCI_HCCCTL 0x50 184103285Sikob#define OHCI_HCCCTLCLR 0x54 185103285Sikob#define OHCI_AREQHI 0x100 186103285Sikob#define OHCI_AREQHICLR 0x104 187103285Sikob#define OHCI_AREQLO 0x108 188103285Sikob#define OHCI_AREQLOCLR 0x10c 189103285Sikob#define OHCI_PREQHI 0x110 190103285Sikob#define OHCI_PREQHICLR 0x114 191103285Sikob#define OHCI_PREQLO 0x118 192103285Sikob#define OHCI_PREQLOCLR 0x11c 193103285Sikob#define OHCI_PREQUPPER 0x120 194103285Sikob 195103285Sikob#define OHCI_SID_BUF 0x64 196103285Sikob#define OHCI_SID_CNT 0x68 197113584Ssimokawa#define OHCI_SID_ERR (1 << 31) 198103285Sikob#define OHCI_SID_CNT_MASK 0xffc 199103285Sikob 200103285Sikob#define OHCI_IT_STAT 0x90 201103285Sikob#define OHCI_IT_STATCLR 0x94 202103285Sikob#define OHCI_IT_MASK 0x98 203103285Sikob#define OHCI_IT_MASKCLR 0x9c 204103285Sikob 205103285Sikob#define OHCI_IR_STAT 0xa0 206103285Sikob#define OHCI_IR_STATCLR 0xa4 207103285Sikob#define OHCI_IR_MASK 0xa8 208103285Sikob#define OHCI_IR_MASKCLR 0xac 209103285Sikob 210103285Sikob#define OHCI_LNKCTL 0xe0 211103285Sikob#define OHCI_LNKCTLCLR 0xe4 212103285Sikob 213103285Sikob#define OHCI_PHYACCESS 0xec 214103285Sikob#define OHCI_CYCLETIMER 0xf0 215103285Sikob 216103285Sikob#define OHCI_DMACTL(off) (off) 217103285Sikob#define OHCI_DMACTLCLR(off) (off + 4) 218103285Sikob#define OHCI_DMACMD(off) (off + 0xc) 219103285Sikob#define OHCI_DMAMATCH(off) (off + 0x10) 220103285Sikob 221103285Sikob#define OHCI_ATQOFF 0x180 222103285Sikob#define OHCI_ATQCTL OHCI_ATQOFF 223103285Sikob#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 224103285Sikob#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 225103285Sikob#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 226103285Sikob 227103285Sikob#define OHCI_ATSOFF 0x1a0 228103285Sikob#define OHCI_ATSCTL OHCI_ATSOFF 229103285Sikob#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 230103285Sikob#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 231103285Sikob#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 232103285Sikob 233103285Sikob#define OHCI_ARQOFF 0x1c0 234103285Sikob#define OHCI_ARQCTL OHCI_ARQOFF 235103285Sikob#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 236103285Sikob#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 237103285Sikob#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 238103285Sikob 239103285Sikob#define OHCI_ARSOFF 0x1e0 240103285Sikob#define OHCI_ARSCTL OHCI_ARSOFF 241103285Sikob#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 242103285Sikob#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 243103285Sikob#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 244103285Sikob 245103285Sikob#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 246103285Sikob#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 247103285Sikob#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 248103285Sikob#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 249103285Sikob 250103285Sikob#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 251103285Sikob#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 252103285Sikob#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 253103285Sikob#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 254103285Sikob#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 255103285Sikob 256103285Sikobd_ioctl_t fwohci_ioctl; 257103285Sikob 258103285Sikob/* 259103285Sikob * Communication with PHY device 260103285Sikob */ 261129585Sdfrstatic uint32_t 262129585Sdfrfwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data) 263103285Sikob{ 264129585Sdfr uint32_t fun; 265103285Sikob 266103285Sikob addr &= 0xf; 267103285Sikob data &= 0xff; 268103285Sikob 269103285Sikob fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 270103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 271103285Sikob DELAY(100); 272103285Sikob 273103285Sikob return(fwphy_rddata( sc, addr)); 274103285Sikob} 275103285Sikob 276129585Sdfrstatic uint32_t 277103285Sikobfwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 278103285Sikob{ 279103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 280103285Sikob int i; 281129585Sdfr uint32_t bm; 282103285Sikob 283103285Sikob#define OHCI_CSR_DATA 0x0c 284103285Sikob#define OHCI_CSR_COMP 0x10 285103285Sikob#define OHCI_CSR_CONT 0x14 286103285Sikob#define OHCI_BUS_MANAGER_ID 0 287103285Sikob 288103285Sikob OWRITE(sc, OHCI_CSR_DATA, node); 289103285Sikob OWRITE(sc, OHCI_CSR_COMP, 0x3f); 290103285Sikob OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 291103285Sikob for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 292109280Ssimokawa DELAY(10); 293103285Sikob bm = OREAD(sc, OHCI_CSR_DATA); 294107653Ssimokawa if((bm & 0x3f) == 0x3f) 295103285Sikob bm = node; 296132432Ssimokawa if (firewire_debug) 297107653Ssimokawa device_printf(sc->fc.dev, 298107653Ssimokawa "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 299103285Sikob 300103285Sikob return(bm); 301103285Sikob} 302103285Sikob 303129585Sdfrstatic uint32_t 304106790Ssimokawafwphy_rddata(struct fwohci_softc *sc, u_int addr) 305103285Sikob{ 306129585Sdfr uint32_t fun, stat; 307108500Ssimokawa u_int i, retry = 0; 308103285Sikob 309103285Sikob addr &= 0xf; 310108500Ssimokawa#define MAX_RETRY 100 311108500Ssimokawaagain: 312108500Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 313103285Sikob fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 314103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 315108500Ssimokawa for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 316103285Sikob fun = OREAD(sc, OHCI_PHYACCESS); 317103285Sikob if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 318103285Sikob break; 319109280Ssimokawa DELAY(100); 320103285Sikob } 321108500Ssimokawa if(i >= MAX_RETRY) { 322132432Ssimokawa if (firewire_debug) 323109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(1).\n"); 324108527Ssimokawa if (++retry < MAX_RETRY) { 325109280Ssimokawa DELAY(100); 326108527Ssimokawa goto again; 327108527Ssimokawa } 328108500Ssimokawa } 329108500Ssimokawa /* Make sure that SCLK is started */ 330108500Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 331108500Ssimokawa if ((stat & OHCI_INT_REG_FAIL) != 0 || 332108500Ssimokawa ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 333132432Ssimokawa if (firewire_debug) 334109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(2).\n"); 335108500Ssimokawa if (++retry < MAX_RETRY) { 336109280Ssimokawa DELAY(100); 337108500Ssimokawa goto again; 338108500Ssimokawa } 339108500Ssimokawa } 340132432Ssimokawa if (firewire_debug || retry >= MAX_RETRY) 341108500Ssimokawa device_printf(sc->fc.dev, 342119118Ssimokawa "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 343108500Ssimokawa#undef MAX_RETRY 344103285Sikob return((fun >> PHYDEV_RDDATA )& 0xff); 345103285Sikob} 346103285Sikob/* Device specific ioctl. */ 347103285Sikobint 348130585Sphkfwohci_ioctl (struct cdev *dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 349103285Sikob{ 350103285Sikob struct firewire_softc *sc; 351103285Sikob struct fwohci_softc *fc; 352103285Sikob int unit = DEV2UNIT(dev); 353103285Sikob int err = 0; 354103285Sikob struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 355129585Sdfr uint32_t *dmach = (uint32_t *) data; 356103285Sikob 357103285Sikob sc = devclass_get_softc(firewire_devclass, unit); 358103285Sikob if(sc == NULL){ 359103285Sikob return(EINVAL); 360103285Sikob } 361103285Sikob fc = (struct fwohci_softc *)sc->fc; 362103285Sikob 363103285Sikob if (!data) 364103285Sikob return(EINVAL); 365103285Sikob 366103285Sikob switch (cmd) { 367103285Sikob case FWOHCI_WRREG: 368103285Sikob#define OHCI_MAX_REG 0x800 369103285Sikob if(reg->addr <= OHCI_MAX_REG){ 370103285Sikob OWRITE(fc, reg->addr, reg->data); 371103285Sikob reg->data = OREAD(fc, reg->addr); 372103285Sikob }else{ 373103285Sikob err = EINVAL; 374103285Sikob } 375103285Sikob break; 376103285Sikob case FWOHCI_RDREG: 377103285Sikob if(reg->addr <= OHCI_MAX_REG){ 378103285Sikob reg->data = OREAD(fc, reg->addr); 379103285Sikob }else{ 380103285Sikob err = EINVAL; 381103285Sikob } 382103285Sikob break; 383103285Sikob/* Read DMA descriptors for debug */ 384103285Sikob case DUMPDMA: 385103285Sikob if(*dmach <= OHCI_MAX_DMA_CH ){ 386103285Sikob dump_dma(fc, *dmach); 387103285Sikob dump_db(fc, *dmach); 388103285Sikob }else{ 389103285Sikob err = EINVAL; 390103285Sikob } 391103285Sikob break; 392119118Ssimokawa/* Read/Write Phy registers */ 393119118Ssimokawa#define OHCI_MAX_PHY_REG 0xf 394119118Ssimokawa case FWOHCI_RDPHYREG: 395119118Ssimokawa if (reg->addr <= OHCI_MAX_PHY_REG) 396119118Ssimokawa reg->data = fwphy_rddata(fc, reg->addr); 397119118Ssimokawa else 398119118Ssimokawa err = EINVAL; 399119118Ssimokawa break; 400119118Ssimokawa case FWOHCI_WRPHYREG: 401119118Ssimokawa if (reg->addr <= OHCI_MAX_PHY_REG) 402119118Ssimokawa reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 403119118Ssimokawa else 404119118Ssimokawa err = EINVAL; 405119118Ssimokawa break; 406103285Sikob default: 407119118Ssimokawa err = EINVAL; 408103285Sikob break; 409103285Sikob } 410103285Sikob return err; 411103285Sikob} 412106790Ssimokawa 413108530Ssimokawastatic int 414108530Ssimokawafwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 415103285Sikob{ 416129585Sdfr uint32_t reg, reg2; 417108530Ssimokawa int e1394a = 1; 418108530Ssimokawa/* 419108530Ssimokawa * probe PHY parameters 420108530Ssimokawa * 0. to prove PHY version, whether compliance of 1394a. 421108530Ssimokawa * 1. to probe maximum speed supported by the PHY and 422108530Ssimokawa * number of port supported by core-logic. 423108530Ssimokawa * It is not actually available port on your PC . 424108530Ssimokawa */ 425108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 426167685Ssimokawa DELAY(500); 427167685Ssimokawa 428108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 429108530Ssimokawa 430108530Ssimokawa if((reg >> 5) != 7 ){ 431108530Ssimokawa sc->fc.mode &= ~FWPHYASYST; 432108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 433108530Ssimokawa sc->fc.speed = reg & FW_PHY_SPD >> 6; 434108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 435108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 436108530Ssimokawa sc->fc.speed, MAX_SPEED); 437108530Ssimokawa sc->fc.speed = MAX_SPEED; 438108530Ssimokawa } 439108530Ssimokawa device_printf(dev, 440108701Ssimokawa "Phy 1394 only %s, %d ports.\n", 441108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 442108530Ssimokawa }else{ 443108530Ssimokawa reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 444108530Ssimokawa sc->fc.mode |= FWPHYASYST; 445108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 446108530Ssimokawa sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 447108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 448108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 449108530Ssimokawa sc->fc.speed, MAX_SPEED); 450108530Ssimokawa sc->fc.speed = MAX_SPEED; 451108530Ssimokawa } 452108530Ssimokawa device_printf(dev, 453108701Ssimokawa "Phy 1394a available %s, %d ports.\n", 454108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 455108530Ssimokawa 456108530Ssimokawa /* check programPhyEnable */ 457108530Ssimokawa reg2 = fwphy_rddata(sc, 5); 458108530Ssimokawa#if 0 459108530Ssimokawa if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 460108530Ssimokawa#else /* XXX force to enable 1394a */ 461108530Ssimokawa if (e1394a) { 462108530Ssimokawa#endif 463132432Ssimokawa if (firewire_debug) 464108530Ssimokawa device_printf(dev, 465108530Ssimokawa "Enable 1394a Enhancements\n"); 466108530Ssimokawa /* enable EAA EMC */ 467108530Ssimokawa reg2 |= 0x03; 468108530Ssimokawa /* set aPhyEnhanceEnable */ 469108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 470108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 471108530Ssimokawa } else { 472108530Ssimokawa /* for safe */ 473108530Ssimokawa reg2 &= ~0x83; 474108530Ssimokawa } 475108530Ssimokawa reg2 = fwphy_wrdata(sc, 5, reg2); 476108530Ssimokawa } 477108530Ssimokawa 478108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 479108530Ssimokawa if((reg >> 5) == 7 ){ 480108530Ssimokawa reg = fwphy_rddata(sc, 4); 481108530Ssimokawa reg |= 1 << 6; 482108530Ssimokawa fwphy_wrdata(sc, 4, reg); 483108530Ssimokawa reg = fwphy_rddata(sc, 4); 484108530Ssimokawa } 485108530Ssimokawa return 0; 486108530Ssimokawa} 487108530Ssimokawa 488108530Ssimokawa 489108530Ssimokawavoid 490108530Ssimokawafwohci_reset(struct fwohci_softc *sc, device_t dev) 491108530Ssimokawa{ 492108701Ssimokawa int i, max_rec, speed; 493129585Sdfr uint32_t reg, reg2; 494103285Sikob struct fwohcidb_tr *db_tr; 495103285Sikob 496129541Sdfr /* Disable interrupts */ 497108530Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 498108530Ssimokawa 499129541Sdfr /* Now stopping all DMA channels */ 500108530Ssimokawa OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 501108530Ssimokawa OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 502108530Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 503108530Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 504108530Ssimokawa 505108530Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, ~0); 506108530Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 507108530Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 508108530Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 509108530Ssimokawa } 510108530Ssimokawa 511108701Ssimokawa /* FLUSH FIFO and reset Transmitter/Reciever */ 512108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 513132432Ssimokawa if (firewire_debug) 514108530Ssimokawa device_printf(dev, "resetting OHCI..."); 515108530Ssimokawa i = 0; 516108530Ssimokawa while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 517108530Ssimokawa if (i++ > 100) break; 518108530Ssimokawa DELAY(1000); 519108530Ssimokawa } 520132432Ssimokawa if (firewire_debug) 521108530Ssimokawa printf("done (loop=%d)\n", i); 522108530Ssimokawa 523108701Ssimokawa /* Probe phy */ 524108701Ssimokawa fwohci_probe_phy(sc, dev); 525108701Ssimokawa 526108701Ssimokawa /* Probe link */ 527108530Ssimokawa reg = OREAD(sc, OHCI_BUS_OPT); 528108530Ssimokawa reg2 = reg | OHCI_BUSFNC; 529108701Ssimokawa max_rec = (reg & 0x0000f000) >> 12; 530108701Ssimokawa speed = (reg & 0x00000007); 531108701Ssimokawa device_printf(dev, "Link %s, max_rec %d bytes.\n", 532108701Ssimokawa linkspeed[speed], MAXREC(max_rec)); 533108701Ssimokawa /* XXX fix max_rec */ 534108701Ssimokawa sc->fc.maxrec = sc->fc.speed + 8; 535108701Ssimokawa if (max_rec != sc->fc.maxrec) { 536108701Ssimokawa reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 537108701Ssimokawa device_printf(dev, "max_rec %d -> %d\n", 538108701Ssimokawa MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 539108701Ssimokawa } 540132432Ssimokawa if (firewire_debug) 541108530Ssimokawa device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 542108530Ssimokawa OWRITE(sc, OHCI_BUS_OPT, reg2); 543108530Ssimokawa 544108701Ssimokawa /* Initialize registers */ 545108530Ssimokawa OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 546113584Ssimokawa OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 547108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 548108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 549113584Ssimokawa OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 550108530Ssimokawa OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 551108530Ssimokawa 552108701Ssimokawa /* Enable link */ 553108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 554108642Ssimokawa 555108701Ssimokawa /* Force to start async RX DMA */ 556108642Ssimokawa sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 557108642Ssimokawa sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 558108530Ssimokawa fwohci_rx_enable(sc, &sc->arrq); 559108530Ssimokawa fwohci_rx_enable(sc, &sc->arrs); 560108530Ssimokawa 561108701Ssimokawa /* Initialize async TX */ 562108701Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 563108701Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 564116978Ssimokawa 565108701Ssimokawa /* AT Retries */ 566108701Ssimokawa OWRITE(sc, FWOHCI_RETRY, 567108701Ssimokawa /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 568108701Ssimokawa (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 569116978Ssimokawa 570116978Ssimokawa sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 571116978Ssimokawa sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 572116978Ssimokawa sc->atrq.bottom = sc->atrq.top; 573116978Ssimokawa sc->atrs.bottom = sc->atrs.top; 574116978Ssimokawa 575108530Ssimokawa for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 576108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 577108530Ssimokawa db_tr->xfer = NULL; 578108530Ssimokawa } 579108530Ssimokawa for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 580108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 581108530Ssimokawa db_tr->xfer = NULL; 582108530Ssimokawa } 583108530Ssimokawa 584108701Ssimokawa 585129541Sdfr /* Enable interrupts */ 586108530Ssimokawa OWRITE(sc, FWOHCI_INTMASK, 587108530Ssimokawa OHCI_INT_ERR | OHCI_INT_PHY_SID 588108530Ssimokawa | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 589108530Ssimokawa | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 590108530Ssimokawa | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 591108530Ssimokawa fwohci_set_intr(&sc->fc, 1); 592108530Ssimokawa 593108530Ssimokawa} 594108530Ssimokawa 595108530Ssimokawaint 596108530Ssimokawafwohci_init(struct fwohci_softc *sc, device_t dev) 597108530Ssimokawa{ 598121781Ssimokawa int i, mver; 599129585Sdfr uint32_t reg; 600129585Sdfr uint8_t ui[8]; 601108530Ssimokawa 602113584Ssimokawa#if FWOHCI_TASKQUEUE 603113584Ssimokawa TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 604113584Ssimokawa#endif 605113584Ssimokawa 606121781Ssimokawa/* OHCI version */ 607103285Sikob reg = OREAD(sc, OHCI_VERSION); 608121781Ssimokawa mver = (reg >> 16) & 0xff; 609103285Sikob device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 610121781Ssimokawa mver, reg & 0xff, (reg>>24) & 1); 611121781Ssimokawa if (mver < 1 || mver > 9) { 612118416Ssimokawa device_printf(dev, "invalid OHCI version\n"); 613118416Ssimokawa return (ENXIO); 614118416Ssimokawa } 615118416Ssimokawa 616129541Sdfr/* Available Isochronous DMA channel probe */ 617110045Ssimokawa OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 618110045Ssimokawa OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 619110045Ssimokawa reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 620110045Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 621110045Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 622110045Ssimokawa for (i = 0; i < 0x20; i++) 623110045Ssimokawa if ((reg & (1 << i)) == 0) 624110045Ssimokawa break; 625103285Sikob sc->fc.nisodma = i; 626129541Sdfr device_printf(dev, "No. of Isochronous channels is %d.\n", i); 627118820Ssimokawa if (i == 0) 628118820Ssimokawa return (ENXIO); 629103285Sikob 630103285Sikob sc->fc.arq = &sc->arrq.xferq; 631103285Sikob sc->fc.ars = &sc->arrs.xferq; 632103285Sikob sc->fc.atq = &sc->atrq.xferq; 633103285Sikob sc->fc.ats = &sc->atrs.xferq; 634103285Sikob 635113584Ssimokawa sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 636113584Ssimokawa sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 637113584Ssimokawa sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 638113584Ssimokawa sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 639113584Ssimokawa 640103285Sikob sc->arrq.xferq.start = NULL; 641103285Sikob sc->arrs.xferq.start = NULL; 642103285Sikob sc->atrq.xferq.start = fwohci_start_atq; 643103285Sikob sc->atrs.xferq.start = fwohci_start_ats; 644103285Sikob 645113584Ssimokawa sc->arrq.xferq.buf = NULL; 646113584Ssimokawa sc->arrs.xferq.buf = NULL; 647113584Ssimokawa sc->atrq.xferq.buf = NULL; 648113584Ssimokawa sc->atrs.xferq.buf = NULL; 649103285Sikob 650118293Ssimokawa sc->arrq.xferq.dmach = -1; 651118293Ssimokawa sc->arrs.xferq.dmach = -1; 652118293Ssimokawa sc->atrq.xferq.dmach = -1; 653118293Ssimokawa sc->atrs.xferq.dmach = -1; 654118293Ssimokawa 655103285Sikob sc->arrq.ndesc = 1; 656103285Sikob sc->arrs.ndesc = 1; 657110593Ssimokawa sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 658110593Ssimokawa sc->atrs.ndesc = 2; 659103285Sikob 660103285Sikob sc->arrq.ndb = NDB; 661103285Sikob sc->arrs.ndb = NDB / 2; 662103285Sikob sc->atrq.ndb = NDB; 663103285Sikob sc->atrs.ndb = NDB / 2; 664103285Sikob 665103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 666103285Sikob sc->fc.it[i] = &sc->it[i].xferq; 667103285Sikob sc->fc.ir[i] = &sc->ir[i].xferq; 668118293Ssimokawa sc->it[i].xferq.dmach = i; 669118293Ssimokawa sc->ir[i].xferq.dmach = i; 670103285Sikob sc->it[i].ndb = 0; 671103285Sikob sc->ir[i].ndb = 0; 672103285Sikob } 673103285Sikob 674103285Sikob sc->fc.tcode = tinfo; 675113584Ssimokawa sc->fc.dev = dev; 676103285Sikob 677113584Ssimokawa sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 678113584Ssimokawa &sc->crom_dma, BUS_DMA_WAITOK); 679113584Ssimokawa if(sc->fc.config_rom == NULL){ 680113584Ssimokawa device_printf(dev, "config_rom alloc failed."); 681103285Sikob return ENOMEM; 682103285Sikob } 683103285Sikob 684116376Ssimokawa#if 0 685116376Ssimokawa bzero(&sc->fc.config_rom[0], CROMSIZE); 686103285Sikob sc->fc.config_rom[1] = 0x31333934; 687103285Sikob sc->fc.config_rom[2] = 0xf000a002; 688103285Sikob sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 689103285Sikob sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 690103285Sikob sc->fc.config_rom[5] = 0; 691103285Sikob sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 692103285Sikob 693103285Sikob sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 694113584Ssimokawa#endif 695103285Sikob 696103285Sikob 697129541Sdfr/* SID recieve buffer must align 2^11 */ 698103285Sikob#define OHCI_SIDSIZE (1 << 11) 699113584Ssimokawa sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 700113584Ssimokawa &sc->sid_dma, BUS_DMA_WAITOK); 701113584Ssimokawa if (sc->sid_buf == NULL) { 702113584Ssimokawa device_printf(dev, "sid_buf alloc failed."); 703108527Ssimokawa return ENOMEM; 704108527Ssimokawa } 705113584Ssimokawa 706129585Sdfr fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t), 707113584Ssimokawa &sc->dummy_dma, BUS_DMA_WAITOK); 708113584Ssimokawa 709113584Ssimokawa if (sc->dummy_dma.v_addr == NULL) { 710113584Ssimokawa device_printf(dev, "dummy_dma alloc failed."); 711109736Ssimokawa return ENOMEM; 712109736Ssimokawa } 713113584Ssimokawa 714113584Ssimokawa fwohci_db_init(sc, &sc->arrq); 715108527Ssimokawa if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 716108527Ssimokawa return ENOMEM; 717108527Ssimokawa 718113584Ssimokawa fwohci_db_init(sc, &sc->arrs); 719108527Ssimokawa if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 720108527Ssimokawa return ENOMEM; 721103285Sikob 722113584Ssimokawa fwohci_db_init(sc, &sc->atrq); 723108527Ssimokawa if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 724108527Ssimokawa return ENOMEM; 725108527Ssimokawa 726113584Ssimokawa fwohci_db_init(sc, &sc->atrs); 727108527Ssimokawa if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 728108527Ssimokawa return ENOMEM; 729103285Sikob 730109814Ssimokawa sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 731109814Ssimokawa sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 732109814Ssimokawa for( i = 0 ; i < 8 ; i ++) 733109814Ssimokawa ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 734103285Sikob device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 735109814Ssimokawa ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 736109814Ssimokawa 737103285Sikob sc->fc.ioctl = fwohci_ioctl; 738103285Sikob sc->fc.cyctimer = fwohci_cyctimer; 739103285Sikob sc->fc.set_bmr = fwohci_set_bus_manager; 740103285Sikob sc->fc.ibr = fwohci_ibr; 741103285Sikob sc->fc.irx_enable = fwohci_irx_enable; 742103285Sikob sc->fc.irx_disable = fwohci_irx_disable; 743103285Sikob 744103285Sikob sc->fc.itx_enable = fwohci_itxbuf_enable; 745103285Sikob sc->fc.itx_disable = fwohci_itx_disable; 746113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 747103285Sikob sc->fc.irx_post = fwohci_irx_post; 748113584Ssimokawa#else 749113584Ssimokawa sc->fc.irx_post = NULL; 750113584Ssimokawa#endif 751103285Sikob sc->fc.itx_post = NULL; 752103285Sikob sc->fc.timeout = fwohci_timeout; 753103285Sikob sc->fc.poll = fwohci_poll; 754103285Sikob sc->fc.set_intr = fwohci_set_intr; 755106790Ssimokawa 756113584Ssimokawa sc->intmask = sc->irstat = sc->itstat = 0; 757113584Ssimokawa 758108530Ssimokawa fw_init(&sc->fc); 759108530Ssimokawa fwohci_reset(sc, dev); 760103285Sikob 761108530Ssimokawa return 0; 762103285Sikob} 763106790Ssimokawa 764106790Ssimokawavoid 765106790Ssimokawafwohci_timeout(void *arg) 766103285Sikob{ 767103285Sikob struct fwohci_softc *sc; 768103285Sikob 769103285Sikob sc = (struct fwohci_softc *)arg; 770103285Sikob} 771106790Ssimokawa 772129585Sdfruint32_t 773106790Ssimokawafwohci_cyctimer(struct firewire_comm *fc) 774103285Sikob{ 775103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 776103285Sikob return(OREAD(sc, OHCI_CYCLETIMER)); 777103285Sikob} 778103285Sikob 779108527Ssimokawaint 780108527Ssimokawafwohci_detach(struct fwohci_softc *sc, device_t dev) 781108527Ssimokawa{ 782108527Ssimokawa int i; 783108527Ssimokawa 784113584Ssimokawa if (sc->sid_buf != NULL) 785113584Ssimokawa fwdma_free(&sc->fc, &sc->sid_dma); 786113584Ssimokawa if (sc->fc.config_rom != NULL) 787113584Ssimokawa fwdma_free(&sc->fc, &sc->crom_dma); 788108527Ssimokawa 789108527Ssimokawa fwohci_db_free(&sc->arrq); 790108527Ssimokawa fwohci_db_free(&sc->arrs); 791108527Ssimokawa 792108527Ssimokawa fwohci_db_free(&sc->atrq); 793108527Ssimokawa fwohci_db_free(&sc->atrs); 794108527Ssimokawa 795108527Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 796108527Ssimokawa fwohci_db_free(&sc->it[i]); 797108527Ssimokawa fwohci_db_free(&sc->ir[i]); 798108527Ssimokawa } 799108527Ssimokawa 800108527Ssimokawa return 0; 801108527Ssimokawa} 802108527Ssimokawa 803108655Ssimokawa#define LAST_DB(dbtr, db) do { \ 804108655Ssimokawa struct fwohcidb_tr *_dbtr = (dbtr); \ 805108655Ssimokawa int _cnt = _dbtr->dbcnt; \ 806108655Ssimokawa db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 807108655Ssimokawa} while (0) 808108655Ssimokawa 809106790Ssimokawastatic void 810113584Ssimokawafwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 811113584Ssimokawa{ 812113584Ssimokawa struct fwohcidb_tr *db_tr; 813120660Ssimokawa struct fwohcidb *db; 814113584Ssimokawa bus_dma_segment_t *s; 815113584Ssimokawa int i; 816113584Ssimokawa 817113584Ssimokawa db_tr = (struct fwohcidb_tr *)arg; 818113584Ssimokawa db = &db_tr->db[db_tr->dbcnt]; 819113584Ssimokawa if (error) { 820113584Ssimokawa if (firewire_debug || error != EFBIG) 821113584Ssimokawa printf("fwohci_execute_db: error=%d\n", error); 822113584Ssimokawa return; 823113584Ssimokawa } 824113584Ssimokawa for (i = 0; i < nseg; i++) { 825113584Ssimokawa s = &segs[i]; 826113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 827113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 828113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 0); 829113584Ssimokawa db++; 830113584Ssimokawa db_tr->dbcnt++; 831113584Ssimokawa } 832113584Ssimokawa} 833113584Ssimokawa 834113584Ssimokawastatic void 835113584Ssimokawafwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 836113584Ssimokawa bus_size_t size, int error) 837113584Ssimokawa{ 838113584Ssimokawa fwohci_execute_db(arg, segs, nseg, error); 839113584Ssimokawa} 840113584Ssimokawa 841113584Ssimokawastatic void 842106790Ssimokawafwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 843103285Sikob{ 844103285Sikob int i, s; 845120660Ssimokawa int tcode, hdr_len, pl_off; 846103285Sikob int fsegment = -1; 847129585Sdfr uint32_t off; 848103285Sikob struct fw_xfer *xfer; 849103285Sikob struct fw_pkt *fp; 850120660Ssimokawa struct fwohci_txpkthdr *ohcifp; 851103285Sikob struct fwohcidb_tr *db_tr; 852120660Ssimokawa struct fwohcidb *db; 853129585Sdfr uint32_t *ld; 854103285Sikob struct tcode_info *info; 855108655Ssimokawa static int maxdesc=0; 856103285Sikob 857103285Sikob if(&sc->atrq == dbch){ 858103285Sikob off = OHCI_ATQOFF; 859103285Sikob }else if(&sc->atrs == dbch){ 860103285Sikob off = OHCI_ATSOFF; 861103285Sikob }else{ 862103285Sikob return; 863103285Sikob } 864103285Sikob 865103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) 866103285Sikob return; 867103285Sikob 868103285Sikob s = splfw(); 869103285Sikob db_tr = dbch->top; 870103285Sikobtxloop: 871103285Sikob xfer = STAILQ_FIRST(&dbch->xferq.q); 872103285Sikob if(xfer == NULL){ 873103285Sikob goto kick; 874103285Sikob } 875103285Sikob if(dbch->xferq.queued == 0 ){ 876103285Sikob device_printf(sc->fc.dev, "TX queue empty\n"); 877103285Sikob } 878103285Sikob STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 879103285Sikob db_tr->xfer = xfer; 880103285Sikob xfer->state = FWXF_START; 881103285Sikob 882120660Ssimokawa fp = &xfer->send.hdr; 883103285Sikob tcode = fp->mode.common.tcode; 884103285Sikob 885120660Ssimokawa ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 886103285Sikob info = &tinfo[tcode]; 887113584Ssimokawa hdr_len = pl_off = info->hdr_len; 888119155Ssimokawa 889119155Ssimokawa ld = &ohcifp->mode.ld[0]; 890119155Ssimokawa ld[0] = ld[1] = ld[2] = ld[3] = 0; 891119155Ssimokawa for( i = 0 ; i < pl_off ; i+= 4) 892119155Ssimokawa ld[i/4] = fp->mode.ld[i/4]; 893119155Ssimokawa 894120660Ssimokawa ohcifp->mode.common.spd = xfer->send.spd & 0x7; 895103285Sikob if (tcode == FWTCODE_STREAM ){ 896103285Sikob hdr_len = 8; 897113584Ssimokawa ohcifp->mode.stream.len = fp->mode.stream.len; 898103285Sikob } else if (tcode == FWTCODE_PHY) { 899103285Sikob hdr_len = 12; 900119155Ssimokawa ld[1] = fp->mode.ld[1]; 901119155Ssimokawa ld[2] = fp->mode.ld[2]; 902103285Sikob ohcifp->mode.common.spd = 0; 903103285Sikob ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 904103285Sikob } else { 905113584Ssimokawa ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 906103285Sikob ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 907103285Sikob ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 908103285Sikob } 909103285Sikob db = &db_tr->db[0]; 910113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.cmd, 911113584Ssimokawa OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 912119155Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 913113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 0); 914103285Sikob/* Specify bound timer of asy. responce */ 915103285Sikob if(&sc->atrs == dbch){ 916113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 917113584Ssimokawa (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 918103285Sikob } 919113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 920113584Ssimokawa if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 921113584Ssimokawa hdr_len = 12; 922113584Ssimokawa for (i = 0; i < hdr_len/4; i ++) 923119155Ssimokawa FWOHCI_DMA_WRITE(ld[i], ld[i]); 924113584Ssimokawa#endif 925103285Sikob 926111942Ssimokawaagain: 927103285Sikob db_tr->dbcnt = 2; 928103285Sikob db = &db_tr->db[db_tr->dbcnt]; 929120660Ssimokawa if (xfer->send.pay_len > 0) { 930113584Ssimokawa int err; 931113584Ssimokawa /* handle payload */ 932103285Sikob if (xfer->mbuf == NULL) { 933113584Ssimokawa err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 934120660Ssimokawa &xfer->send.payload[0], xfer->send.pay_len, 935113584Ssimokawa fwohci_execute_db, db_tr, 936113584Ssimokawa /*flags*/0); 937103285Sikob } else { 938111942Ssimokawa /* XXX we can handle only 6 (=8-2) mbuf chains */ 939113584Ssimokawa err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 940113584Ssimokawa xfer->mbuf, 941113584Ssimokawa fwohci_execute_db2, db_tr, 942113584Ssimokawa /* flags */0); 943113584Ssimokawa if (err == EFBIG) { 944113584Ssimokawa struct mbuf *m0; 945113584Ssimokawa 946113584Ssimokawa if (firewire_debug) 947113584Ssimokawa device_printf(sc->fc.dev, "EFBIG.\n"); 948113584Ssimokawa m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 949113584Ssimokawa if (m0 != NULL) { 950111942Ssimokawa m_copydata(xfer->mbuf, 0, 951111942Ssimokawa xfer->mbuf->m_pkthdr.len, 952113584Ssimokawa mtod(m0, caddr_t)); 953113584Ssimokawa m0->m_len = m0->m_pkthdr.len = 954111942Ssimokawa xfer->mbuf->m_pkthdr.len; 955111942Ssimokawa m_freem(xfer->mbuf); 956113584Ssimokawa xfer->mbuf = m0; 957111942Ssimokawa goto again; 958111942Ssimokawa } 959111942Ssimokawa device_printf(sc->fc.dev, "m_getcl failed.\n"); 960111942Ssimokawa } 961103285Sikob } 962113584Ssimokawa if (err) 963113584Ssimokawa printf("dmamap_load: err=%d\n", err); 964113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 965113584Ssimokawa BUS_DMASYNC_PREWRITE); 966113584Ssimokawa#if 0 /* OHCI_OUTPUT_MODE == 0 */ 967113584Ssimokawa for (i = 2; i < db_tr->dbcnt; i++) 968113584Ssimokawa FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 969113584Ssimokawa OHCI_OUTPUT_MORE); 970113584Ssimokawa#endif 971103285Sikob } 972108655Ssimokawa if (maxdesc < db_tr->dbcnt) { 973108655Ssimokawa maxdesc = db_tr->dbcnt; 974132432Ssimokawa if (firewire_debug) 975108655Ssimokawa device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 976108655Ssimokawa } 977103285Sikob /* last db */ 978103285Sikob LAST_DB(db_tr, db); 979113584Ssimokawa FWOHCI_DMA_SET(db->db.desc.cmd, 980113584Ssimokawa OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 981113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.depend, 982113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr); 983103285Sikob 984103285Sikob if(fsegment == -1 ) 985103285Sikob fsegment = db_tr->dbcnt; 986103285Sikob if (dbch->pdb_tr != NULL) { 987103285Sikob LAST_DB(dbch->pdb_tr, db); 988113584Ssimokawa FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 989103285Sikob } 990103285Sikob dbch->pdb_tr = db_tr; 991103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 992103285Sikob if(db_tr != dbch->bottom){ 993103285Sikob goto txloop; 994103285Sikob } else { 995107653Ssimokawa device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 996103285Sikob dbch->flags |= FWOHCI_DBCH_FULL; 997103285Sikob } 998103285Sikobkick: 999103285Sikob /* kick asy q */ 1000113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1001113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1002103285Sikob 1003103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) { 1004103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 1005103285Sikob } else { 1006132432Ssimokawa if (firewire_debug) 1007107653Ssimokawa device_printf(sc->fc.dev, "start AT DMA status=%x\n", 1008103285Sikob OREAD(sc, OHCI_DMACTL(off))); 1009113584Ssimokawa OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1010103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1011103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1012103285Sikob } 1013106790Ssimokawa 1014103285Sikob dbch->top = db_tr; 1015103285Sikob splx(s); 1016103285Sikob return; 1017103285Sikob} 1018106790Ssimokawa 1019106790Ssimokawastatic void 1020106790Ssimokawafwohci_start_atq(struct firewire_comm *fc) 1021103285Sikob{ 1022103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1023103285Sikob fwohci_start( sc, &(sc->atrq)); 1024103285Sikob return; 1025103285Sikob} 1026106790Ssimokawa 1027106790Ssimokawastatic void 1028106790Ssimokawafwohci_start_ats(struct firewire_comm *fc) 1029103285Sikob{ 1030103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1031103285Sikob fwohci_start( sc, &(sc->atrs)); 1032103285Sikob return; 1033103285Sikob} 1034106790Ssimokawa 1035106790Ssimokawavoid 1036106790Ssimokawafwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1037103285Sikob{ 1038113584Ssimokawa int s, ch, err = 0; 1039103285Sikob struct fwohcidb_tr *tr; 1040120660Ssimokawa struct fwohcidb *db; 1041103285Sikob struct fw_xfer *xfer; 1042129585Sdfr uint32_t off; 1043113584Ssimokawa u_int stat, status; 1044103285Sikob int packets; 1045103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1046113584Ssimokawa 1047103285Sikob if(&sc->atrq == dbch){ 1048103285Sikob off = OHCI_ATQOFF; 1049113584Ssimokawa ch = ATRQ_CH; 1050103285Sikob }else if(&sc->atrs == dbch){ 1051103285Sikob off = OHCI_ATSOFF; 1052113584Ssimokawa ch = ATRS_CH; 1053103285Sikob }else{ 1054103285Sikob return; 1055103285Sikob } 1056103285Sikob s = splfw(); 1057103285Sikob tr = dbch->bottom; 1058103285Sikob packets = 0; 1059113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 1060113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 1061103285Sikob while(dbch->xferq.queued > 0){ 1062103285Sikob LAST_DB(tr, db); 1063113584Ssimokawa status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1064113584Ssimokawa if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1065103285Sikob if (fc->status != FWBUSRESET) 1066103285Sikob /* maybe out of order?? */ 1067103285Sikob goto out; 1068103285Sikob } 1069113584Ssimokawa bus_dmamap_sync(dbch->dmat, tr->dma_map, 1070113584Ssimokawa BUS_DMASYNC_POSTWRITE); 1071113584Ssimokawa bus_dmamap_unload(dbch->dmat, tr->dma_map); 1072119155Ssimokawa#if 1 1073167629Ssimokawa if (firewire_debug > 1) 1074119155Ssimokawa dump_db(sc, ch); 1075103285Sikob#endif 1076113584Ssimokawa if(status & OHCI_CNTL_DMA_DEAD) { 1077113584Ssimokawa /* Stop DMA */ 1078103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1079103285Sikob device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1080103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1081103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1082103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1083103285Sikob } 1084113584Ssimokawa stat = status & FWOHCIEV_MASK; 1085103285Sikob switch(stat){ 1086110577Ssimokawa case FWOHCIEV_ACKPEND: 1087103285Sikob case FWOHCIEV_ACKCOMPL: 1088103285Sikob err = 0; 1089103285Sikob break; 1090103285Sikob case FWOHCIEV_ACKBSA: 1091103285Sikob case FWOHCIEV_ACKBSB: 1092110577Ssimokawa case FWOHCIEV_ACKBSX: 1093103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1094103285Sikob err = EBUSY; 1095103285Sikob break; 1096103285Sikob case FWOHCIEV_FLUSHED: 1097103285Sikob case FWOHCIEV_ACKTARD: 1098103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1099103285Sikob err = EAGAIN; 1100103285Sikob break; 1101103285Sikob case FWOHCIEV_MISSACK: 1102103285Sikob case FWOHCIEV_UNDRRUN: 1103103285Sikob case FWOHCIEV_OVRRUN: 1104103285Sikob case FWOHCIEV_DESCERR: 1105103285Sikob case FWOHCIEV_DTRDERR: 1106103285Sikob case FWOHCIEV_TIMEOUT: 1107103285Sikob case FWOHCIEV_TCODERR: 1108103285Sikob case FWOHCIEV_UNKNOWN: 1109103285Sikob case FWOHCIEV_ACKDERR: 1110103285Sikob case FWOHCIEV_ACKTERR: 1111103285Sikob default: 1112103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", 1113103285Sikob stat, fwohcicode[stat]); 1114103285Sikob err = EINVAL; 1115103285Sikob break; 1116103285Sikob } 1117110577Ssimokawa if (tr->xfer != NULL) { 1118103285Sikob xfer = tr->xfer; 1119113584Ssimokawa if (xfer->state == FWXF_RCVD) { 1120119289Ssimokawa#if 0 1121113584Ssimokawa if (firewire_debug) 1122113584Ssimokawa printf("already rcvd\n"); 1123119289Ssimokawa#endif 1124113584Ssimokawa fw_xfer_done(xfer); 1125113584Ssimokawa } else { 1126114218Ssimokawa xfer->state = FWXF_SENT; 1127114218Ssimokawa if (err == EBUSY && fc->status != FWBUSRESET) { 1128114218Ssimokawa xfer->state = FWXF_BUSY; 1129114218Ssimokawa xfer->resp = err; 1130167630Ssimokawa xfer->recv.pay_len = 0; 1131167630Ssimokawa fw_xfer_done(xfer); 1132114218Ssimokawa } else if (stat != FWOHCIEV_ACKPEND) { 1133114218Ssimokawa if (stat != FWOHCIEV_ACKCOMPL) 1134114218Ssimokawa xfer->state = FWXF_SENTERR; 1135114218Ssimokawa xfer->resp = err; 1136120660Ssimokawa xfer->recv.pay_len = 0; 1137113584Ssimokawa fw_xfer_done(xfer); 1138114218Ssimokawa } 1139103285Sikob } 1140110577Ssimokawa /* 1141110577Ssimokawa * The watchdog timer takes care of split 1142110577Ssimokawa * transcation timeout for ACKPEND case. 1143110577Ssimokawa */ 1144113584Ssimokawa } else { 1145113584Ssimokawa printf("this shouldn't happen\n"); 1146103285Sikob } 1147110269Ssimokawa dbch->xferq.queued --; 1148103285Sikob tr->xfer = NULL; 1149103285Sikob 1150103285Sikob packets ++; 1151103285Sikob tr = STAILQ_NEXT(tr, link); 1152103285Sikob dbch->bottom = tr; 1153111956Ssimokawa if (dbch->bottom == dbch->top) { 1154111956Ssimokawa /* we reaches the end of context program */ 1155111956Ssimokawa if (firewire_debug && dbch->xferq.queued > 0) 1156111956Ssimokawa printf("queued > 0\n"); 1157111956Ssimokawa break; 1158111956Ssimokawa } 1159103285Sikob } 1160103285Sikobout: 1161103285Sikob if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1162103285Sikob printf("make free slot\n"); 1163103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1164103285Sikob fwohci_start(sc, dbch); 1165103285Sikob } 1166103285Sikob splx(s); 1167103285Sikob} 1168106790Ssimokawa 1169106790Ssimokawastatic void 1170106790Ssimokawafwohci_db_free(struct fwohci_dbch *dbch) 1171103285Sikob{ 1172103285Sikob struct fwohcidb_tr *db_tr; 1173113584Ssimokawa int idb; 1174103285Sikob 1175108527Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1176108527Ssimokawa return; 1177108527Ssimokawa 1178113584Ssimokawa for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1179103285Sikob db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1180113584Ssimokawa if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1181113584Ssimokawa db_tr->buf != NULL) { 1182113584Ssimokawa fwdma_free_size(dbch->dmat, db_tr->dma_map, 1183113584Ssimokawa db_tr->buf, dbch->xferq.psize); 1184113584Ssimokawa db_tr->buf = NULL; 1185113584Ssimokawa } else if (db_tr->dma_map != NULL) 1186113584Ssimokawa bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1187103285Sikob } 1188103285Sikob dbch->ndb = 0; 1189103285Sikob db_tr = STAILQ_FIRST(&dbch->db_trq); 1190113584Ssimokawa fwdma_free_multiseg(dbch->am); 1191110195Ssimokawa free(db_tr, M_FW); 1192103285Sikob STAILQ_INIT(&dbch->db_trq); 1193108527Ssimokawa dbch->flags &= ~FWOHCI_DBCH_INIT; 1194103285Sikob} 1195106790Ssimokawa 1196106790Ssimokawastatic void 1197113584Ssimokawafwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1198103285Sikob{ 1199103285Sikob int idb; 1200103285Sikob struct fwohcidb_tr *db_tr; 1201108642Ssimokawa 1202108642Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1203108642Ssimokawa goto out; 1204108642Ssimokawa 1205113584Ssimokawa /* create dma_tag for buffers */ 1206113584Ssimokawa#define MAX_REQCOUNT 0xffff 1207113584Ssimokawa if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1208113584Ssimokawa /*alignment*/ 1, /*boundary*/ 0, 1209113584Ssimokawa /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1210113584Ssimokawa /*highaddr*/ BUS_SPACE_MAXADDR, 1211113584Ssimokawa /*filter*/NULL, /*filterarg*/NULL, 1212113584Ssimokawa /*maxsize*/ dbch->xferq.psize, 1213113584Ssimokawa /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1214113584Ssimokawa /*maxsegsz*/ MAX_REQCOUNT, 1215117126Sscottl /*flags*/ 0, 1216127468Ssimokawa#if defined(__FreeBSD__) && __FreeBSD_version >= 501102 1217117126Sscottl /*lockfunc*/busdma_lock_mutex, 1218117228Ssimokawa /*lockarg*/&Giant, 1219117228Ssimokawa#endif 1220117228Ssimokawa &dbch->dmat)) 1221113584Ssimokawa return; 1222113584Ssimokawa 1223103285Sikob /* allocate DB entries and attach one to each DMA channels */ 1224103285Sikob /* DB entry must start at 16 bytes bounary. */ 1225103285Sikob STAILQ_INIT(&dbch->db_trq); 1226103285Sikob db_tr = (struct fwohcidb_tr *) 1227103285Sikob malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1228113584Ssimokawa M_FW, M_WAITOK | M_ZERO); 1229103285Sikob if(db_tr == NULL){ 1230109379Ssimokawa printf("fwohci_db_init: malloc(1) failed\n"); 1231103285Sikob return; 1232103285Sikob } 1233109379Ssimokawa 1234113584Ssimokawa#define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1235113584Ssimokawa dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1236113584Ssimokawa DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1237113584Ssimokawa if (dbch->am == NULL) { 1238113584Ssimokawa printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1239124836Ssimokawa free(db_tr, M_FW); 1240103285Sikob return; 1241103285Sikob } 1242103285Sikob /* Attach DB to DMA ch. */ 1243103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb++){ 1244103285Sikob db_tr->dbcnt = 0; 1245113584Ssimokawa db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1246113584Ssimokawa db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1247113584Ssimokawa /* create dmamap for buffers */ 1248113584Ssimokawa /* XXX do we need 4bytes alignment tag? */ 1249113584Ssimokawa /* XXX don't alloc dma_map for AR */ 1250113584Ssimokawa if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1251113584Ssimokawa printf("bus_dmamap_create failed\n"); 1252113584Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1253113584Ssimokawa fwohci_db_free(dbch); 1254113584Ssimokawa return; 1255113584Ssimokawa } 1256103285Sikob STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1257113584Ssimokawa if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1258108530Ssimokawa if (idb % dbch->xferq.bnpacket == 0) 1259108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1260108530Ssimokawa ].start = (caddr_t)db_tr; 1261108530Ssimokawa if ((idb + 1) % dbch->xferq.bnpacket == 0) 1262108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1263108530Ssimokawa ].end = (caddr_t)db_tr; 1264103285Sikob } 1265103285Sikob db_tr++; 1266103285Sikob } 1267103285Sikob STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1268103285Sikob = STAILQ_FIRST(&dbch->db_trq); 1269108642Ssimokawaout: 1270108642Ssimokawa dbch->xferq.queued = 0; 1271108642Ssimokawa dbch->pdb_tr = NULL; 1272103285Sikob dbch->top = STAILQ_FIRST(&dbch->db_trq); 1273103285Sikob dbch->bottom = dbch->top; 1274108527Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; 1275103285Sikob} 1276106790Ssimokawa 1277106790Ssimokawastatic int 1278106790Ssimokawafwohci_itx_disable(struct firewire_comm *fc, int dmach) 1279103285Sikob{ 1280103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1281109890Ssimokawa 1282113584Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 1283113584Ssimokawa OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1284103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1285103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1286109890Ssimokawa /* XXX we cannot free buffers until the DMA really stops */ 1287167086Sjhb pause("fwitxd", hz); 1288103285Sikob fwohci_db_free(&sc->it[dmach]); 1289103285Sikob sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1290103285Sikob return 0; 1291103285Sikob} 1292106790Ssimokawa 1293106790Ssimokawastatic int 1294106790Ssimokawafwohci_irx_disable(struct firewire_comm *fc, int dmach) 1295103285Sikob{ 1296103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1297103285Sikob 1298103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1299103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1300103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1301109890Ssimokawa /* XXX we cannot free buffers until the DMA really stops */ 1302167086Sjhb pause("fwirxd", hz); 1303103285Sikob fwohci_db_free(&sc->ir[dmach]); 1304103285Sikob sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1305103285Sikob return 0; 1306103285Sikob} 1307106790Ssimokawa 1308113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 1309106790Ssimokawastatic void 1310129585Sdfrfwohci_irx_post (struct firewire_comm *fc , uint32_t *qld) 1311103285Sikob{ 1312113584Ssimokawa qld[0] = FWOHCI_DMA_READ(qld[0]); 1313103285Sikob return; 1314103285Sikob} 1315103285Sikob#endif 1316103285Sikob 1317106790Ssimokawastatic int 1318106790Ssimokawafwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1319103285Sikob{ 1320103285Sikob int err = 0; 1321113584Ssimokawa int idb, z, i, dmach = 0, ldesc; 1322129585Sdfr uint32_t off = 0; 1323103285Sikob struct fwohcidb_tr *db_tr; 1324120660Ssimokawa struct fwohcidb *db; 1325103285Sikob 1326103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1327103285Sikob err = EINVAL; 1328103285Sikob return err; 1329103285Sikob } 1330103285Sikob z = dbch->ndesc; 1331103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1332103285Sikob if( &sc->it[dmach] == dbch){ 1333103285Sikob off = OHCI_ITOFF(dmach); 1334103285Sikob break; 1335103285Sikob } 1336103285Sikob } 1337123740Speter if(off == 0){ 1338103285Sikob err = EINVAL; 1339103285Sikob return err; 1340103285Sikob } 1341103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1342103285Sikob return err; 1343103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1344103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1345103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1346103285Sikob } 1347103285Sikob db_tr = dbch->top; 1348113584Ssimokawa for (idb = 0; idb < dbch->ndb; idb ++) { 1349113584Ssimokawa fwohci_add_tx_buf(dbch, db_tr, idb); 1350103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1351103285Sikob break; 1352103285Sikob } 1353109892Ssimokawa db = db_tr->db; 1354113584Ssimokawa ldesc = db_tr->dbcnt - 1; 1355113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1356113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr | z); 1357113584Ssimokawa db[ldesc].db.desc.depend = db[0].db.desc.depend; 1358103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1359103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1360113584Ssimokawa FWOHCI_DMA_SET( 1361113584Ssimokawa db[ldesc].db.desc.cmd, 1362113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1363109280Ssimokawa /* OHCI 1.1 and above */ 1364113584Ssimokawa FWOHCI_DMA_SET( 1365113584Ssimokawa db[0].db.desc.cmd, 1366113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1367103285Sikob } 1368103285Sikob } 1369103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1370103285Sikob } 1371113584Ssimokawa FWOHCI_DMA_CLEAR( 1372113584Ssimokawa dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1373103285Sikob return err; 1374103285Sikob} 1375106790Ssimokawa 1376106790Ssimokawastatic int 1377106790Ssimokawafwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1378103285Sikob{ 1379103285Sikob int err = 0; 1380109892Ssimokawa int idb, z, i, dmach = 0, ldesc; 1381129585Sdfr uint32_t off = 0; 1382103285Sikob struct fwohcidb_tr *db_tr; 1383120660Ssimokawa struct fwohcidb *db; 1384103285Sikob 1385103285Sikob z = dbch->ndesc; 1386103285Sikob if(&sc->arrq == dbch){ 1387103285Sikob off = OHCI_ARQOFF; 1388103285Sikob }else if(&sc->arrs == dbch){ 1389103285Sikob off = OHCI_ARSOFF; 1390103285Sikob }else{ 1391103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1392103285Sikob if( &sc->ir[dmach] == dbch){ 1393103285Sikob off = OHCI_IROFF(dmach); 1394103285Sikob break; 1395103285Sikob } 1396103285Sikob } 1397103285Sikob } 1398123740Speter if(off == 0){ 1399103285Sikob err = EINVAL; 1400103285Sikob return err; 1401103285Sikob } 1402103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1403103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1404103285Sikob return err; 1405103285Sikob }else{ 1406103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1407103285Sikob err = EBUSY; 1408103285Sikob return err; 1409103285Sikob } 1410103285Sikob } 1411103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1412108642Ssimokawa dbch->top = STAILQ_FIRST(&dbch->db_trq); 1413103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1414103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1415103285Sikob } 1416103285Sikob db_tr = dbch->top; 1417113584Ssimokawa for (idb = 0; idb < dbch->ndb; idb ++) { 1418113584Ssimokawa fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1419113584Ssimokawa if (STAILQ_NEXT(db_tr, link) == NULL) 1420103285Sikob break; 1421109892Ssimokawa db = db_tr->db; 1422109892Ssimokawa ldesc = db_tr->dbcnt - 1; 1423113584Ssimokawa FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1424113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr | z); 1425103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1426103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1427113584Ssimokawa FWOHCI_DMA_SET( 1428113584Ssimokawa db[ldesc].db.desc.cmd, 1429113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1430113584Ssimokawa FWOHCI_DMA_CLEAR( 1431113584Ssimokawa db[ldesc].db.desc.depend, 1432113584Ssimokawa 0xf); 1433103285Sikob } 1434103285Sikob } 1435103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1436103285Sikob } 1437113584Ssimokawa FWOHCI_DMA_CLEAR( 1438113584Ssimokawa dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1439103285Sikob dbch->buf_offset = 0; 1440113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1441113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1442103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1443103285Sikob return err; 1444103285Sikob }else{ 1445113584Ssimokawa OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1446103285Sikob } 1447103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1448103285Sikob return err; 1449103285Sikob} 1450106790Ssimokawa 1451106790Ssimokawastatic int 1452113584Ssimokawafwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1453109890Ssimokawa{ 1454109890Ssimokawa int sec, cycle, cycle_match; 1455109890Ssimokawa 1456109890Ssimokawa cycle = cycle_now & 0x1fff; 1457109890Ssimokawa sec = cycle_now >> 13; 1458109890Ssimokawa#define CYCLE_MOD 0x10 1459113584Ssimokawa#if 1 1460109890Ssimokawa#define CYCLE_DELAY 8 /* min delay to start DMA */ 1461113584Ssimokawa#else 1462113584Ssimokawa#define CYCLE_DELAY 7000 /* min delay to start DMA */ 1463113584Ssimokawa#endif 1464109890Ssimokawa cycle = cycle + CYCLE_DELAY; 1465109890Ssimokawa if (cycle >= 8000) { 1466109890Ssimokawa sec ++; 1467109890Ssimokawa cycle -= 8000; 1468109890Ssimokawa } 1469113584Ssimokawa cycle = roundup2(cycle, CYCLE_MOD); 1470109890Ssimokawa if (cycle >= 8000) { 1471109890Ssimokawa sec ++; 1472109890Ssimokawa if (cycle == 8000) 1473109890Ssimokawa cycle = 0; 1474109890Ssimokawa else 1475109890Ssimokawa cycle = CYCLE_MOD; 1476109890Ssimokawa } 1477109890Ssimokawa cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1478109890Ssimokawa 1479109890Ssimokawa return(cycle_match); 1480109890Ssimokawa} 1481109890Ssimokawa 1482109890Ssimokawastatic int 1483106790Ssimokawafwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1484103285Sikob{ 1485103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1486103285Sikob int err = 0; 1487103285Sikob unsigned short tag, ich; 1488103285Sikob struct fwohci_dbch *dbch; 1489109890Ssimokawa int cycle_match, cycle_now, s, ldesc; 1490129585Sdfr uint32_t stat; 1491109890Ssimokawa struct fw_bulkxfer *first, *chunk, *prev; 1492109890Ssimokawa struct fw_xferq *it; 1493103285Sikob 1494103285Sikob dbch = &sc->it[dmach]; 1495109890Ssimokawa it = &dbch->xferq; 1496109890Ssimokawa 1497109890Ssimokawa tag = (it->flag >> 6) & 3; 1498109890Ssimokawa ich = it->flag & 0x3f; 1499109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1500109890Ssimokawa dbch->ndb = it->bnpacket * it->bnchunk; 1501103285Sikob dbch->ndesc = 3; 1502113584Ssimokawa fwohci_db_init(sc, dbch); 1503109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1504109179Ssimokawa return ENOMEM; 1505103285Sikob err = fwohci_tx_enable(sc, dbch); 1506103285Sikob } 1507103285Sikob if(err) 1508103285Sikob return err; 1509109890Ssimokawa 1510109892Ssimokawa ldesc = dbch->ndesc - 1; 1511109890Ssimokawa s = splfw(); 1512109890Ssimokawa prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1513109890Ssimokawa while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1514120660Ssimokawa struct fwohcidb *db; 1515109890Ssimokawa 1516113584Ssimokawa fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1517113584Ssimokawa BUS_DMASYNC_PREWRITE); 1518109890Ssimokawa fwohci_txbufdb(sc, dmach, chunk); 1519109890Ssimokawa if (prev != NULL) { 1520109890Ssimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 1521113584Ssimokawa#if 0 /* XXX necessary? */ 1522113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1523113584Ssimokawa OHCI_BRANCH_ALWAYS); 1524113584Ssimokawa#endif 1525109892Ssimokawa#if 0 /* if bulkxfer->npacket changes */ 1526109890Ssimokawa db[ldesc].db.desc.depend = db[0].db.desc.depend = 1527113584Ssimokawa ((struct fwohcidb_tr *) 1528113584Ssimokawa (chunk->start))->bus_addr | dbch->ndesc; 1529109892Ssimokawa#else 1530113584Ssimokawa FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1531113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1532109892Ssimokawa#endif 1533103285Sikob } 1534109890Ssimokawa STAILQ_REMOVE_HEAD(&it->stvalid, link); 1535109890Ssimokawa STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1536109890Ssimokawa prev = chunk; 1537109403Ssimokawa } 1538113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1539113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1540109890Ssimokawa splx(s); 1541109890Ssimokawa stat = OREAD(sc, OHCI_ITCTL(dmach)); 1542113584Ssimokawa if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1543113584Ssimokawa printf("stat 0x%x\n", stat); 1544113584Ssimokawa 1545109890Ssimokawa if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1546109890Ssimokawa return 0; 1547109890Ssimokawa 1548113584Ssimokawa#if 0 1549109890Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1550113584Ssimokawa#endif 1551109403Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1552109403Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1553109403Ssimokawa OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1554113584Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1555109890Ssimokawa 1556109890Ssimokawa first = STAILQ_FIRST(&it->stdma); 1557113584Ssimokawa OWRITE(sc, OHCI_ITCMD(dmach), 1558113584Ssimokawa ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1559167629Ssimokawa if (firewire_debug > 1) { 1560109890Ssimokawa printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1561113584Ssimokawa#if 1 1562113584Ssimokawa dump_dma(sc, ITX_CH + dmach); 1563113584Ssimokawa#endif 1564113584Ssimokawa } 1565109403Ssimokawa if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1566109890Ssimokawa#if 1 1567109890Ssimokawa /* Don't start until all chunks are buffered */ 1568109890Ssimokawa if (STAILQ_FIRST(&it->stfree) != NULL) 1569109890Ssimokawa goto out; 1570109890Ssimokawa#endif 1571113584Ssimokawa#if 1 1572109890Ssimokawa /* Clear cycle match counter bits */ 1573109890Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1574109890Ssimokawa 1575109356Ssimokawa /* 2bit second + 13bit cycle */ 1576109356Ssimokawa cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1577113584Ssimokawa cycle_match = fwohci_next_cycle(fc, cycle_now); 1578109890Ssimokawa 1579109356Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), 1580109356Ssimokawa OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1581109356Ssimokawa | OHCI_CNTL_DMA_RUN); 1582113584Ssimokawa#else 1583113584Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1584113584Ssimokawa#endif 1585167629Ssimokawa if (firewire_debug > 1) { 1586109403Ssimokawa printf("cycle_match: 0x%04x->0x%04x\n", 1587109403Ssimokawa cycle_now, cycle_match); 1588113584Ssimokawa dump_dma(sc, ITX_CH + dmach); 1589113584Ssimokawa dump_db(sc, ITX_CH + dmach); 1590113584Ssimokawa } 1591109403Ssimokawa } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1592109890Ssimokawa device_printf(sc->fc.dev, 1593109890Ssimokawa "IT DMA underrun (0x%08x)\n", stat); 1594113584Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1595103285Sikob } 1596109890Ssimokawaout: 1597103285Sikob return err; 1598103285Sikob} 1599106790Ssimokawa 1600106790Ssimokawastatic int 1601113584Ssimokawafwohci_irx_enable(struct firewire_comm *fc, int dmach) 1602103285Sikob{ 1603103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1604109890Ssimokawa int err = 0, s, ldesc; 1605103285Sikob unsigned short tag, ich; 1606129585Sdfr uint32_t stat; 1607109890Ssimokawa struct fwohci_dbch *dbch; 1608113584Ssimokawa struct fwohcidb_tr *db_tr; 1609109890Ssimokawa struct fw_bulkxfer *first, *prev, *chunk; 1610109890Ssimokawa struct fw_xferq *ir; 1611103285Sikob 1612109890Ssimokawa dbch = &sc->ir[dmach]; 1613109890Ssimokawa ir = &dbch->xferq; 1614109890Ssimokawa 1615109890Ssimokawa if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1616109890Ssimokawa tag = (ir->flag >> 6) & 3; 1617109890Ssimokawa ich = ir->flag & 0x3f; 1618108995Ssimokawa OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1619108995Ssimokawa 1620109890Ssimokawa ir->queued = 0; 1621109890Ssimokawa dbch->ndb = ir->bnpacket * ir->bnchunk; 1622109890Ssimokawa dbch->ndesc = 2; 1623113584Ssimokawa fwohci_db_init(sc, dbch); 1624109890Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1625109179Ssimokawa return ENOMEM; 1626109890Ssimokawa err = fwohci_rx_enable(sc, dbch); 1627103285Sikob } 1628103285Sikob if(err) 1629103285Sikob return err; 1630103285Sikob 1631109890Ssimokawa first = STAILQ_FIRST(&ir->stfree); 1632109890Ssimokawa if (first == NULL) { 1633109890Ssimokawa device_printf(fc->dev, "IR DMA no free chunk\n"); 1634109890Ssimokawa return 0; 1635109890Ssimokawa } 1636109890Ssimokawa 1637111892Ssimokawa ldesc = dbch->ndesc - 1; 1638111892Ssimokawa s = splfw(); 1639109890Ssimokawa prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1640109890Ssimokawa while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1641120660Ssimokawa struct fwohcidb *db; 1642109890Ssimokawa 1643111942Ssimokawa#if 1 /* XXX for if_fwe */ 1644113584Ssimokawa if (chunk->mbuf != NULL) { 1645113584Ssimokawa db_tr = (struct fwohcidb_tr *)(chunk->start); 1646113584Ssimokawa db_tr->dbcnt = 1; 1647113584Ssimokawa err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 1648113584Ssimokawa chunk->mbuf, fwohci_execute_db2, db_tr, 1649113584Ssimokawa /* flags */0); 1650113584Ssimokawa FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1651113584Ssimokawa OHCI_UPDATE | OHCI_INPUT_LAST | 1652113584Ssimokawa OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1653113584Ssimokawa } 1654111942Ssimokawa#endif 1655109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 1656113584Ssimokawa FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1657113584Ssimokawa FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1658109890Ssimokawa if (prev != NULL) { 1659109890Ssimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 1660113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1661103285Sikob } 1662109890Ssimokawa STAILQ_REMOVE_HEAD(&ir->stfree, link); 1663109890Ssimokawa STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1664109890Ssimokawa prev = chunk; 1665103285Sikob } 1666113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1667113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1668109890Ssimokawa splx(s); 1669109890Ssimokawa stat = OREAD(sc, OHCI_IRCTL(dmach)); 1670109890Ssimokawa if (stat & OHCI_CNTL_DMA_ACTIVE) 1671109890Ssimokawa return 0; 1672109890Ssimokawa if (stat & OHCI_CNTL_DMA_RUN) { 1673109890Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1674109890Ssimokawa device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1675109890Ssimokawa } 1676109890Ssimokawa 1677113584Ssimokawa if (firewire_debug) 1678113584Ssimokawa printf("start IR DMA 0x%x\n", stat); 1679109890Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1680109890Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1681109890Ssimokawa OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1682109890Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1683109890Ssimokawa OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1684109890Ssimokawa OWRITE(sc, OHCI_IRCMD(dmach), 1685113584Ssimokawa ((struct fwohcidb_tr *)(first->start))->bus_addr 1686109890Ssimokawa | dbch->ndesc); 1687109890Ssimokawa OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1688109890Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1689113584Ssimokawa#if 0 1690113584Ssimokawa dump_db(sc, IRX_CH + dmach); 1691113584Ssimokawa#endif 1692103285Sikob return err; 1693103285Sikob} 1694106790Ssimokawa 1695106790Ssimokawaint 1696110145Ssimokawafwohci_stop(struct fwohci_softc *sc, device_t dev) 1697103285Sikob{ 1698103285Sikob u_int i; 1699103285Sikob 1700103285Sikob/* Now stopping all DMA channel */ 1701103285Sikob OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1702103285Sikob OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1703103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1704103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1705103285Sikob 1706103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1707103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1708103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1709103285Sikob } 1710103285Sikob 1711103285Sikob/* FLUSH FIFO and reset Transmitter/Reciever */ 1712103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1713103285Sikob 1714103285Sikob/* Stop interrupt */ 1715103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, 1716103285Sikob OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1717103285Sikob | OHCI_INT_PHY_INT 1718103285Sikob | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1719103285Sikob | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1720103285Sikob | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1721103285Sikob | OHCI_INT_PHY_BUS_R); 1722116978Ssimokawa 1723118416Ssimokawa if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1724118416Ssimokawa fw_drain_txq(&sc->fc); 1725116978Ssimokawa 1726108642Ssimokawa/* XXX Link down? Bus reset? */ 1727103285Sikob return 0; 1728103285Sikob} 1729103285Sikob 1730108642Ssimokawaint 1731108642Ssimokawafwohci_resume(struct fwohci_softc *sc, device_t dev) 1732108642Ssimokawa{ 1733108642Ssimokawa int i; 1734116978Ssimokawa struct fw_xferq *ir; 1735116978Ssimokawa struct fw_bulkxfer *chunk; 1736108642Ssimokawa 1737108642Ssimokawa fwohci_reset(sc, dev); 1738129541Sdfr /* XXX resume isochronous receive automatically. (how about TX?) */ 1739108642Ssimokawa for(i = 0; i < sc->fc.nisodma; i ++) { 1740116978Ssimokawa ir = &sc->ir[i].xferq; 1741116978Ssimokawa if((ir->flag & FWXFERQ_RUNNING) != 0) { 1742108642Ssimokawa device_printf(sc->fc.dev, 1743108642Ssimokawa "resume iso receive ch: %d\n", i); 1744116978Ssimokawa ir->flag &= ~FWXFERQ_RUNNING; 1745116978Ssimokawa /* requeue stdma to stfree */ 1746116978Ssimokawa while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1747116978Ssimokawa STAILQ_REMOVE_HEAD(&ir->stdma, link); 1748116978Ssimokawa STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1749116978Ssimokawa } 1750108642Ssimokawa sc->fc.irx_enable(&sc->fc, i); 1751108642Ssimokawa } 1752108642Ssimokawa } 1753108642Ssimokawa 1754108642Ssimokawa bus_generic_resume(dev); 1755108642Ssimokawa sc->fc.ibr(&sc->fc); 1756108642Ssimokawa return 0; 1757108642Ssimokawa} 1758108642Ssimokawa 1759103285Sikob#define ACK_ALL 1760103285Sikobstatic void 1761129585Sdfrfwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count) 1762103285Sikob{ 1763129585Sdfr uint32_t irstat, itstat; 1764103285Sikob u_int i; 1765103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1766103285Sikob 1767103285Sikob#ifdef OHCI_DEBUG 1768103285Sikob if(stat & OREAD(sc, FWOHCI_INTMASK)) 1769103285Sikob device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1770103285Sikob stat & OHCI_INT_EN ? "DMA_EN ":"", 1771103285Sikob stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1772103285Sikob stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1773103285Sikob stat & OHCI_INT_ERR ? "INT_ERR ":"", 1774103285Sikob stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1775103285Sikob stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1776103285Sikob stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1777103285Sikob stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1778103285Sikob stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1779103285Sikob stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1780103285Sikob stat & OHCI_INT_PHY_SID ? "SID ":"", 1781103285Sikob stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1782103285Sikob stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1783103285Sikob stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1784103285Sikob stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1785103285Sikob stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1786103285Sikob stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1787103285Sikob stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1788103285Sikob stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1789103285Sikob stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1790103285Sikob stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1791103285Sikob stat, OREAD(sc, FWOHCI_INTMASK) 1792103285Sikob ); 1793103285Sikob#endif 1794103285Sikob/* Bus reset */ 1795103285Sikob if(stat & OHCI_INT_PHY_BUS_R ){ 1796111074Ssimokawa if (fc->status == FWBUSRESET) 1797111074Ssimokawa goto busresetout; 1798111074Ssimokawa /* Disable bus reset interrupt until sid recv. */ 1799111074Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1800111074Ssimokawa 1801103285Sikob device_printf(fc->dev, "BUS reset\n"); 1802103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1803103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1804103285Sikob 1805103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1806103285Sikob sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1807103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1808103285Sikob sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1809103285Sikob 1810103285Sikob#ifndef ACK_ALL 1811103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1812103285Sikob#endif 1813110798Ssimokawa fw_busreset(fc); 1814116376Ssimokawa OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1815116376Ssimokawa OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1816103285Sikob } 1817111074Ssimokawabusresetout: 1818103285Sikob if((stat & OHCI_INT_DMA_IR )){ 1819103285Sikob#ifndef ACK_ALL 1820103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1821103285Sikob#endif 1822127468Ssimokawa#if defined(__DragonFly__) || __FreeBSD_version < 500000 1823113584Ssimokawa irstat = sc->irstat; 1824113584Ssimokawa sc->irstat = 0; 1825127468Ssimokawa#else 1826127468Ssimokawa irstat = atomic_readandclear_int(&sc->irstat); 1827113584Ssimokawa#endif 1828103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1829109644Ssimokawa struct fwohci_dbch *dbch; 1830109644Ssimokawa 1831103285Sikob if((irstat & (1 << i)) != 0){ 1832109644Ssimokawa dbch = &sc->ir[i]; 1833109644Ssimokawa if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1834109644Ssimokawa device_printf(sc->fc.dev, 1835109644Ssimokawa "dma(%d) not active\n", i); 1836109644Ssimokawa continue; 1837109644Ssimokawa } 1838113584Ssimokawa fwohci_rbuf_update(sc, i); 1839103285Sikob } 1840103285Sikob } 1841103285Sikob } 1842103285Sikob if((stat & OHCI_INT_DMA_IT )){ 1843103285Sikob#ifndef ACK_ALL 1844103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1845103285Sikob#endif 1846127468Ssimokawa#if defined(__DragonFly__) || __FreeBSD_version < 500000 1847113584Ssimokawa itstat = sc->itstat; 1848113584Ssimokawa sc->itstat = 0; 1849127468Ssimokawa#else 1850127468Ssimokawa itstat = atomic_readandclear_int(&sc->itstat); 1851113584Ssimokawa#endif 1852103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1853103285Sikob if((itstat & (1 << i)) != 0){ 1854103285Sikob fwohci_tbuf_update(sc, i); 1855103285Sikob } 1856103285Sikob } 1857103285Sikob } 1858103285Sikob if((stat & OHCI_INT_DMA_PRRS )){ 1859103285Sikob#ifndef ACK_ALL 1860103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1861103285Sikob#endif 1862103285Sikob#if 0 1863103285Sikob dump_dma(sc, ARRS_CH); 1864103285Sikob dump_db(sc, ARRS_CH); 1865103285Sikob#endif 1866106789Ssimokawa fwohci_arcv(sc, &sc->arrs, count); 1867103285Sikob } 1868103285Sikob if((stat & OHCI_INT_DMA_PRRQ )){ 1869103285Sikob#ifndef ACK_ALL 1870103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1871103285Sikob#endif 1872103285Sikob#if 0 1873103285Sikob dump_dma(sc, ARRQ_CH); 1874103285Sikob dump_db(sc, ARRQ_CH); 1875103285Sikob#endif 1876106789Ssimokawa fwohci_arcv(sc, &sc->arrq, count); 1877103285Sikob } 1878167628Ssimokawa if (stat & OHCI_INT_CYC_LOST) { 1879167628Ssimokawa if (sc->cycle_lost >= 0) 1880167628Ssimokawa sc->cycle_lost ++; 1881167628Ssimokawa if (sc->cycle_lost > 10) { 1882167628Ssimokawa sc->cycle_lost = -1; 1883167628Ssimokawa#if 0 1884167628Ssimokawa OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER); 1885167628Ssimokawa#endif 1886167628Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1887167628Ssimokawa device_printf(fc->dev, "too many cycle lost, " 1888167628Ssimokawa "no cycle master presents?\n"); 1889167628Ssimokawa } 1890167628Ssimokawa } 1891103285Sikob if(stat & OHCI_INT_PHY_SID){ 1892129585Sdfr uint32_t *buf, node_id; 1893103285Sikob int plen; 1894103285Sikob 1895103285Sikob#ifndef ACK_ALL 1896103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1897103285Sikob#endif 1898111074Ssimokawa /* Enable bus reset interrupt */ 1899111074Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1900111787Ssimokawa /* Allow async. request to us */ 1901111787Ssimokawa OWRITE(sc, OHCI_AREQHI, 1 << 31); 1902111787Ssimokawa /* XXX insecure ?? */ 1903111787Ssimokawa OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1904111787Ssimokawa OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1905111787Ssimokawa OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1906112523Ssimokawa /* Set ATRetries register */ 1907112523Ssimokawa OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1908103285Sikob/* 1909103285Sikob** Checking whether the node is root or not. If root, turn on 1910103285Sikob** cycle master. 1911103285Sikob*/ 1912113584Ssimokawa node_id = OREAD(sc, FWOHCI_NODEID); 1913113584Ssimokawa plen = OREAD(sc, OHCI_SID_CNT); 1914113584Ssimokawa 1915113584Ssimokawa device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 1916113584Ssimokawa node_id, (plen >> 16) & 0xff); 1917113584Ssimokawa if (!(node_id & OHCI_NODE_VALID)) { 1918103285Sikob printf("Bus reset failure\n"); 1919103285Sikob goto sidout; 1920103285Sikob } 1921167628Ssimokawa 1922167628Ssimokawa /* cycle timer */ 1923167628Ssimokawa sc->cycle_lost = 0; 1924167628Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST); 1925113584Ssimokawa if (node_id & OHCI_NODE_ROOT) { 1926103285Sikob printf("CYCLEMASTER mode\n"); 1927103285Sikob OWRITE(sc, OHCI_LNKCTL, 1928103285Sikob OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1929113584Ssimokawa } else { 1930103285Sikob printf("non CYCLEMASTER mode\n"); 1931103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1932103285Sikob OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1933103285Sikob } 1934167628Ssimokawa 1935113584Ssimokawa fc->nodeid = node_id & 0x3f; 1936103285Sikob 1937113584Ssimokawa if (plen & OHCI_SID_ERR) { 1938113584Ssimokawa device_printf(fc->dev, "SID Error\n"); 1939113584Ssimokawa goto sidout; 1940113584Ssimokawa } 1941113584Ssimokawa plen &= OHCI_SID_CNT_MASK; 1942109736Ssimokawa if (plen < 4 || plen > OHCI_SIDSIZE) { 1943109736Ssimokawa device_printf(fc->dev, "invalid SID len = %d\n", plen); 1944109736Ssimokawa goto sidout; 1945109736Ssimokawa } 1946103285Sikob plen -= 4; /* chop control info */ 1947129585Sdfr buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1948113584Ssimokawa if (buf == NULL) { 1949113584Ssimokawa device_printf(fc->dev, "malloc failed\n"); 1950113584Ssimokawa goto sidout; 1951113584Ssimokawa } 1952113584Ssimokawa for (i = 0; i < plen / 4; i ++) 1953113584Ssimokawa buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 1954127468Ssimokawa#if 1 /* XXX needed?? */ 1955110269Ssimokawa /* pending all pre-bus_reset packets */ 1956110269Ssimokawa fwohci_txd(sc, &sc->atrq); 1957110269Ssimokawa fwohci_txd(sc, &sc->atrs); 1958110269Ssimokawa fwohci_arcv(sc, &sc->arrs, -1); 1959110269Ssimokawa fwohci_arcv(sc, &sc->arrq, -1); 1960110798Ssimokawa fw_drain_txq(fc); 1961110269Ssimokawa#endif 1962113584Ssimokawa fw_sidrcv(fc, buf, plen); 1963113584Ssimokawa free(buf, M_FW); 1964103285Sikob } 1965103285Sikobsidout: 1966103285Sikob if((stat & OHCI_INT_DMA_ATRQ )){ 1967103285Sikob#ifndef ACK_ALL 1968103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1969103285Sikob#endif 1970103285Sikob fwohci_txd(sc, &(sc->atrq)); 1971103285Sikob } 1972103285Sikob if((stat & OHCI_INT_DMA_ATRS )){ 1973103285Sikob#ifndef ACK_ALL 1974103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1975103285Sikob#endif 1976103285Sikob fwohci_txd(sc, &(sc->atrs)); 1977103285Sikob } 1978103285Sikob if((stat & OHCI_INT_PW_ERR )){ 1979103285Sikob#ifndef ACK_ALL 1980103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1981103285Sikob#endif 1982103285Sikob device_printf(fc->dev, "posted write error\n"); 1983103285Sikob } 1984103285Sikob if((stat & OHCI_INT_ERR )){ 1985103285Sikob#ifndef ACK_ALL 1986103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1987103285Sikob#endif 1988103285Sikob device_printf(fc->dev, "unrecoverable error\n"); 1989103285Sikob } 1990103285Sikob if((stat & OHCI_INT_PHY_INT)) { 1991103285Sikob#ifndef ACK_ALL 1992103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1993103285Sikob#endif 1994103285Sikob device_printf(fc->dev, "phy int\n"); 1995103285Sikob } 1996103285Sikob 1997103285Sikob return; 1998103285Sikob} 1999103285Sikob 2000113584Ssimokawa#if FWOHCI_TASKQUEUE 2001113584Ssimokawastatic void 2002113584Ssimokawafwohci_complete(void *arg, int pending) 2003113584Ssimokawa{ 2004113584Ssimokawa struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2005129585Sdfr uint32_t stat; 2006113584Ssimokawa 2007113584Ssimokawaagain: 2008113584Ssimokawa stat = atomic_readandclear_int(&sc->intstat); 2009113584Ssimokawa if (stat) 2010113584Ssimokawa fwohci_intr_body(sc, stat, -1); 2011113584Ssimokawa else 2012113584Ssimokawa return; 2013113584Ssimokawa goto again; 2014113584Ssimokawa} 2015113584Ssimokawa#endif 2016113584Ssimokawa 2017129585Sdfrstatic uint32_t 2018113584Ssimokawafwochi_check_stat(struct fwohci_softc *sc) 2019113584Ssimokawa{ 2020129585Sdfr uint32_t stat, irstat, itstat; 2021113584Ssimokawa 2022113584Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 2023113584Ssimokawa if (stat == 0xffffffff) { 2024113584Ssimokawa device_printf(sc->fc.dev, 2025113584Ssimokawa "device physically ejected?\n"); 2026113584Ssimokawa return(stat); 2027113584Ssimokawa } 2028113584Ssimokawa#ifdef ACK_ALL 2029113584Ssimokawa if (stat) 2030113584Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2031113584Ssimokawa#endif 2032113584Ssimokawa if (stat & OHCI_INT_DMA_IR) { 2033113584Ssimokawa irstat = OREAD(sc, OHCI_IR_STAT); 2034113584Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, irstat); 2035113584Ssimokawa atomic_set_int(&sc->irstat, irstat); 2036113584Ssimokawa } 2037113584Ssimokawa if (stat & OHCI_INT_DMA_IT) { 2038113584Ssimokawa itstat = OREAD(sc, OHCI_IT_STAT); 2039113584Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, itstat); 2040113584Ssimokawa atomic_set_int(&sc->itstat, itstat); 2041113584Ssimokawa } 2042113584Ssimokawa return(stat); 2043113584Ssimokawa} 2044113584Ssimokawa 2045103285Sikobvoid 2046103285Sikobfwohci_intr(void *arg) 2047103285Sikob{ 2048103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2049129585Sdfr uint32_t stat; 2050113584Ssimokawa#if !FWOHCI_TASKQUEUE 2051129585Sdfr uint32_t bus_reset = 0; 2052113584Ssimokawa#endif 2053103285Sikob 2054103285Sikob if (!(sc->intmask & OHCI_INT_EN)) { 2055103285Sikob /* polling mode */ 2056103285Sikob return; 2057103285Sikob } 2058103285Sikob 2059113584Ssimokawa#if !FWOHCI_TASKQUEUE 2060113584Ssimokawaagain: 2061103285Sikob#endif 2062113584Ssimokawa stat = fwochi_check_stat(sc); 2063113584Ssimokawa if (stat == 0 || stat == 0xffffffff) 2064113584Ssimokawa return; 2065113584Ssimokawa#if FWOHCI_TASKQUEUE 2066113584Ssimokawa atomic_set_int(&sc->intstat, stat); 2067113584Ssimokawa /* XXX mask bus reset intr. during bus reset phase */ 2068113584Ssimokawa if (stat) 2069113584Ssimokawa taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete); 2070113584Ssimokawa#else 2071113584Ssimokawa /* We cannot clear bus reset event during bus reset phase */ 2072113584Ssimokawa if ((stat & ~bus_reset) == 0) 2073113584Ssimokawa return; 2074113584Ssimokawa bus_reset = stat & OHCI_INT_PHY_BUS_R; 2075113584Ssimokawa fwohci_intr_body(sc, stat, -1); 2076113584Ssimokawa goto again; 2077113584Ssimokawa#endif 2078103285Sikob} 2079103285Sikob 2080116897Ssimokawavoid 2081103285Sikobfwohci_poll(struct firewire_comm *fc, int quick, int count) 2082103285Sikob{ 2083103285Sikob int s; 2084129585Sdfr uint32_t stat; 2085103285Sikob struct fwohci_softc *sc; 2086103285Sikob 2087103285Sikob 2088103285Sikob sc = (struct fwohci_softc *)fc; 2089103285Sikob stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2090103285Sikob OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2091103285Sikob OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2092103285Sikob#if 0 2093103285Sikob if (!quick) { 2094103285Sikob#else 2095103285Sikob if (1) { 2096103285Sikob#endif 2097113584Ssimokawa stat = fwochi_check_stat(sc); 2098113584Ssimokawa if (stat == 0 || stat == 0xffffffff) 2099103285Sikob return; 2100103285Sikob } 2101103285Sikob s = splfw(); 2102106789Ssimokawa fwohci_intr_body(sc, stat, count); 2103103285Sikob splx(s); 2104103285Sikob} 2105103285Sikob 2106103285Sikobstatic void 2107103285Sikobfwohci_set_intr(struct firewire_comm *fc, int enable) 2108103285Sikob{ 2109103285Sikob struct fwohci_softc *sc; 2110103285Sikob 2111103285Sikob sc = (struct fwohci_softc *)fc; 2112132432Ssimokawa if (firewire_debug) 2113108642Ssimokawa device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2114103285Sikob if (enable) { 2115103285Sikob sc->intmask |= OHCI_INT_EN; 2116103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2117103285Sikob } else { 2118103285Sikob sc->intmask &= ~OHCI_INT_EN; 2119103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2120103285Sikob } 2121103285Sikob} 2122103285Sikob 2123106790Ssimokawastatic void 2124106790Ssimokawafwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2125103285Sikob{ 2126103285Sikob struct firewire_comm *fc = &sc->fc; 2127120660Ssimokawa struct fwohcidb *db; 2128109890Ssimokawa struct fw_bulkxfer *chunk; 2129109890Ssimokawa struct fw_xferq *it; 2130129585Sdfr uint32_t stat, count; 2131113584Ssimokawa int s, w=0, ldesc; 2132103285Sikob 2133109890Ssimokawa it = fc->it[dmach]; 2134113584Ssimokawa ldesc = sc->it[dmach].ndesc - 1; 2135109890Ssimokawa s = splfw(); /* unnecessary ? */ 2136113584Ssimokawa fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2137119155Ssimokawa if (firewire_debug) 2138119155Ssimokawa dump_db(sc, ITX_CH + dmach); 2139109890Ssimokawa while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2140109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 2141113584Ssimokawa stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2142113584Ssimokawa >> OHCI_STATUS_SHIFT; 2143109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->start))->db; 2144119155Ssimokawa /* timestamp */ 2145113584Ssimokawa count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2146113584Ssimokawa & OHCI_COUNT_MASK; 2147109890Ssimokawa if (stat == 0) 2148109890Ssimokawa break; 2149109890Ssimokawa STAILQ_REMOVE_HEAD(&it->stdma, link); 2150109890Ssimokawa switch (stat & FWOHCIEV_MASK){ 2151109890Ssimokawa case FWOHCIEV_ACKCOMPL: 2152109890Ssimokawa#if 0 2153109890Ssimokawa device_printf(fc->dev, "0x%08x\n", count); 2154109179Ssimokawa#endif 2155109890Ssimokawa break; 2156109890Ssimokawa default: 2157109423Ssimokawa device_printf(fc->dev, 2158113584Ssimokawa "Isochronous transmit err %02x(%s)\n", 2159113584Ssimokawa stat, fwohcicode[stat & 0x1f]); 2160109890Ssimokawa } 2161109890Ssimokawa STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2162109890Ssimokawa w++; 2163109403Ssimokawa } 2164109890Ssimokawa splx(s); 2165109890Ssimokawa if (w) 2166109890Ssimokawa wakeup(it); 2167103285Sikob} 2168106790Ssimokawa 2169106790Ssimokawastatic void 2170106790Ssimokawafwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2171103285Sikob{ 2172109179Ssimokawa struct firewire_comm *fc = &sc->fc; 2173120660Ssimokawa struct fwohcidb_tr *db_tr; 2174109890Ssimokawa struct fw_bulkxfer *chunk; 2175109890Ssimokawa struct fw_xferq *ir; 2176129585Sdfr uint32_t stat; 2177113584Ssimokawa int s, w=0, ldesc; 2178109179Ssimokawa 2179109890Ssimokawa ir = fc->ir[dmach]; 2180113584Ssimokawa ldesc = sc->ir[dmach].ndesc - 1; 2181113584Ssimokawa#if 0 2182113584Ssimokawa dump_db(sc, dmach); 2183113584Ssimokawa#endif 2184109890Ssimokawa s = splfw(); 2185113584Ssimokawa fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2186109890Ssimokawa while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2187113584Ssimokawa db_tr = (struct fwohcidb_tr *)chunk->end; 2188113584Ssimokawa stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2189113584Ssimokawa >> OHCI_STATUS_SHIFT; 2190109890Ssimokawa if (stat == 0) 2191109890Ssimokawa break; 2192113584Ssimokawa 2193113584Ssimokawa if (chunk->mbuf != NULL) { 2194113584Ssimokawa bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2195113584Ssimokawa BUS_DMASYNC_POSTREAD); 2196113584Ssimokawa bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 2197113584Ssimokawa } else if (ir->buf != NULL) { 2198113584Ssimokawa fwdma_sync_multiseg(ir->buf, chunk->poffset, 2199113584Ssimokawa ir->bnpacket, BUS_DMASYNC_POSTREAD); 2200113584Ssimokawa } else { 2201113584Ssimokawa /* XXX */ 2202113584Ssimokawa printf("fwohci_rbuf_update: this shouldn't happend\n"); 2203113584Ssimokawa } 2204113584Ssimokawa 2205109890Ssimokawa STAILQ_REMOVE_HEAD(&ir->stdma, link); 2206109890Ssimokawa STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2207109890Ssimokawa switch (stat & FWOHCIEV_MASK) { 2208109890Ssimokawa case FWOHCIEV_ACKCOMPL: 2209111942Ssimokawa chunk->resp = 0; 2210109890Ssimokawa break; 2211109890Ssimokawa default: 2212111942Ssimokawa chunk->resp = EINVAL; 2213109890Ssimokawa device_printf(fc->dev, 2214113584Ssimokawa "Isochronous receive err %02x(%s)\n", 2215113584Ssimokawa stat, fwohcicode[stat & 0x1f]); 2216109890Ssimokawa } 2217109890Ssimokawa w++; 2218103285Sikob } 2219109890Ssimokawa splx(s); 2220111942Ssimokawa if (w) { 2221111942Ssimokawa if (ir->flag & FWXFERQ_HANDLER) 2222111942Ssimokawa ir->hand(ir); 2223111942Ssimokawa else 2224111942Ssimokawa wakeup(ir); 2225111942Ssimokawa } 2226103285Sikob} 2227106790Ssimokawa 2228106790Ssimokawavoid 2229129585Sdfrdump_dma(struct fwohci_softc *sc, uint32_t ch) 2230106790Ssimokawa{ 2231129585Sdfr uint32_t off, cntl, stat, cmd, match; 2232103285Sikob 2233103285Sikob if(ch == 0){ 2234103285Sikob off = OHCI_ATQOFF; 2235103285Sikob }else if(ch == 1){ 2236103285Sikob off = OHCI_ATSOFF; 2237103285Sikob }else if(ch == 2){ 2238103285Sikob off = OHCI_ARQOFF; 2239103285Sikob }else if(ch == 3){ 2240103285Sikob off = OHCI_ARSOFF; 2241103285Sikob }else if(ch < IRX_CH){ 2242103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2243103285Sikob }else{ 2244103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2245103285Sikob } 2246103285Sikob cntl = stat = OREAD(sc, off); 2247103285Sikob cmd = OREAD(sc, off + 0xc); 2248103285Sikob match = OREAD(sc, off + 0x10); 2249103285Sikob 2250113584Ssimokawa device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2251103285Sikob ch, 2252103285Sikob cntl, 2253103285Sikob cmd, 2254103285Sikob match); 2255103285Sikob stat &= 0xffff ; 2256113584Ssimokawa if (stat) { 2257103285Sikob device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2258103285Sikob ch, 2259103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2260103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2261103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2262103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2263103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2264103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2265103285Sikob fwohcicode[stat & 0x1f], 2266103285Sikob stat & 0x1f 2267103285Sikob ); 2268103285Sikob }else{ 2269103285Sikob device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2270103285Sikob } 2271103285Sikob} 2272106790Ssimokawa 2273106790Ssimokawavoid 2274129585Sdfrdump_db(struct fwohci_softc *sc, uint32_t ch) 2275106790Ssimokawa{ 2276103285Sikob struct fwohci_dbch *dbch; 2277113584Ssimokawa struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2278120660Ssimokawa struct fwohcidb *curr = NULL, *prev, *next = NULL; 2279103285Sikob int idb, jdb; 2280129585Sdfr uint32_t cmd, off; 2281103285Sikob if(ch == 0){ 2282103285Sikob off = OHCI_ATQOFF; 2283103285Sikob dbch = &sc->atrq; 2284103285Sikob }else if(ch == 1){ 2285103285Sikob off = OHCI_ATSOFF; 2286103285Sikob dbch = &sc->atrs; 2287103285Sikob }else if(ch == 2){ 2288103285Sikob off = OHCI_ARQOFF; 2289103285Sikob dbch = &sc->arrq; 2290103285Sikob }else if(ch == 3){ 2291103285Sikob off = OHCI_ARSOFF; 2292103285Sikob dbch = &sc->arrs; 2293103285Sikob }else if(ch < IRX_CH){ 2294103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2295103285Sikob dbch = &sc->it[ch - ITX_CH]; 2296103285Sikob }else { 2297103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2298103285Sikob dbch = &sc->ir[ch - IRX_CH]; 2299103285Sikob } 2300103285Sikob cmd = OREAD(sc, off + 0xc); 2301103285Sikob 2302103285Sikob if( dbch->ndb == 0 ){ 2303103285Sikob device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2304103285Sikob return; 2305103285Sikob } 2306103285Sikob pp = dbch->top; 2307103285Sikob prev = pp->db; 2308103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2309103285Sikob cp = STAILQ_NEXT(pp, link); 2310103285Sikob if(cp == NULL){ 2311103285Sikob curr = NULL; 2312103285Sikob goto outdb; 2313103285Sikob } 2314103285Sikob np = STAILQ_NEXT(cp, link); 2315103285Sikob for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2316113584Ssimokawa if ((cmd & 0xfffffff0) == cp->bus_addr) { 2317103285Sikob curr = cp->db; 2318103285Sikob if(np != NULL){ 2319103285Sikob next = np->db; 2320103285Sikob }else{ 2321103285Sikob next = NULL; 2322103285Sikob } 2323103285Sikob goto outdb; 2324103285Sikob } 2325103285Sikob } 2326103285Sikob pp = STAILQ_NEXT(pp, link); 2327144263Ssam if(pp == NULL){ 2328144263Ssam curr = NULL; 2329144263Ssam goto outdb; 2330144263Ssam } 2331103285Sikob prev = pp->db; 2332103285Sikob } 2333103285Sikoboutdb: 2334103285Sikob if( curr != NULL){ 2335113584Ssimokawa#if 0 2336103285Sikob printf("Prev DB %d\n", ch); 2337113584Ssimokawa print_db(pp, prev, ch, dbch->ndesc); 2338113584Ssimokawa#endif 2339103285Sikob printf("Current DB %d\n", ch); 2340113584Ssimokawa print_db(cp, curr, ch, dbch->ndesc); 2341113584Ssimokawa#if 0 2342103285Sikob printf("Next DB %d\n", ch); 2343113584Ssimokawa print_db(np, next, ch, dbch->ndesc); 2344113584Ssimokawa#endif 2345103285Sikob }else{ 2346103285Sikob printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2347103285Sikob } 2348103285Sikob return; 2349103285Sikob} 2350106790Ssimokawa 2351106790Ssimokawavoid 2352120660Ssimokawaprint_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2353129585Sdfr uint32_t ch, uint32_t max) 2354106790Ssimokawa{ 2355103285Sikob fwohcireg_t stat; 2356103285Sikob int i, key; 2357129585Sdfr uint32_t cmd, res; 2358103285Sikob 2359103285Sikob if(db == NULL){ 2360103285Sikob printf("No Descriptor is found\n"); 2361103285Sikob return; 2362103285Sikob } 2363103285Sikob 2364103285Sikob printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2365103285Sikob ch, 2366103285Sikob "Current", 2367103285Sikob "OP ", 2368103285Sikob "KEY", 2369103285Sikob "INT", 2370103285Sikob "BR ", 2371103285Sikob "len", 2372103285Sikob "Addr", 2373103285Sikob "Depend", 2374103285Sikob "Stat", 2375103285Sikob "Cnt"); 2376103285Sikob for( i = 0 ; i <= max ; i ++){ 2377113584Ssimokawa cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2378113584Ssimokawa res = FWOHCI_DMA_READ(db[i].db.desc.res); 2379113584Ssimokawa key = cmd & OHCI_KEY_MASK; 2380113584Ssimokawa stat = res >> OHCI_STATUS_SHIFT; 2381127468Ssimokawa#if defined(__DragonFly__) || __FreeBSD_version < 500000 2382127468Ssimokawa printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2383127468Ssimokawa db_tr->bus_addr, 2384127468Ssimokawa#else 2385113972Ssimokawa printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2386114142Ssimokawa (uintmax_t)db_tr->bus_addr, 2387108712Ssimokawa#endif 2388113584Ssimokawa dbcode[(cmd >> 28) & 0xf], 2389113584Ssimokawa dbkey[(cmd >> 24) & 0x7], 2390113584Ssimokawa dbcond[(cmd >> 20) & 0x3], 2391113584Ssimokawa dbcond[(cmd >> 18) & 0x3], 2392113584Ssimokawa cmd & OHCI_COUNT_MASK, 2393113584Ssimokawa FWOHCI_DMA_READ(db[i].db.desc.addr), 2394113584Ssimokawa FWOHCI_DMA_READ(db[i].db.desc.depend), 2395113584Ssimokawa stat, 2396113584Ssimokawa res & OHCI_COUNT_MASK); 2397103285Sikob if(stat & 0xff00){ 2398103285Sikob printf(" %s%s%s%s%s%s %s(%x)\n", 2399103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2400103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2401103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2402103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2403103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2404103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2405103285Sikob fwohcicode[stat & 0x1f], 2406103285Sikob stat & 0x1f 2407103285Sikob ); 2408103285Sikob }else{ 2409103285Sikob printf(" Nostat\n"); 2410103285Sikob } 2411103285Sikob if(key == OHCI_KEY_ST2 ){ 2412103285Sikob printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2413113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2414113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2415113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2416113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2417103285Sikob } 2418103285Sikob if(key == OHCI_KEY_DEVICE){ 2419103285Sikob return; 2420103285Sikob } 2421113584Ssimokawa if((cmd & OHCI_BRANCH_MASK) 2422103285Sikob == OHCI_BRANCH_ALWAYS){ 2423103285Sikob return; 2424103285Sikob } 2425113584Ssimokawa if((cmd & OHCI_CMD_MASK) 2426103285Sikob == OHCI_OUTPUT_LAST){ 2427103285Sikob return; 2428103285Sikob } 2429113584Ssimokawa if((cmd & OHCI_CMD_MASK) 2430103285Sikob == OHCI_INPUT_LAST){ 2431103285Sikob return; 2432103285Sikob } 2433103285Sikob if(key == OHCI_KEY_ST2 ){ 2434103285Sikob i++; 2435103285Sikob } 2436103285Sikob } 2437103285Sikob return; 2438103285Sikob} 2439106790Ssimokawa 2440106790Ssimokawavoid 2441106790Ssimokawafwohci_ibr(struct firewire_comm *fc) 2442103285Sikob{ 2443103285Sikob struct fwohci_softc *sc; 2444129585Sdfr uint32_t fun; 2445103285Sikob 2446110577Ssimokawa device_printf(fc->dev, "Initiate bus reset\n"); 2447103285Sikob sc = (struct fwohci_softc *)fc; 2448108276Ssimokawa 2449108276Ssimokawa /* 2450129611Sdfr * Make sure our cached values from the config rom are 2451129611Sdfr * initialised. 2452129611Sdfr */ 2453129611Sdfr OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 2454129611Sdfr OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 2455129611Sdfr 2456129611Sdfr /* 2457108276Ssimokawa * Set root hold-off bit so that non cyclemaster capable node 2458108276Ssimokawa * shouldn't became the root node. 2459108276Ssimokawa */ 2460103285Sikob#if 1 2461103285Sikob fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2462109280Ssimokawa fun |= FW_PHY_IBR | FW_PHY_RHB; 2463103285Sikob fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2464109280Ssimokawa#else /* Short bus reset */ 2465103285Sikob fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2466109280Ssimokawa fun |= FW_PHY_ISBR | FW_PHY_RHB; 2467103285Sikob fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2468103285Sikob#endif 2469103285Sikob} 2470106790Ssimokawa 2471106790Ssimokawavoid 2472106790Ssimokawafwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2473103285Sikob{ 2474103285Sikob struct fwohcidb_tr *db_tr, *fdb_tr; 2475103285Sikob struct fwohci_dbch *dbch; 2476120660Ssimokawa struct fwohcidb *db; 2477103285Sikob struct fw_pkt *fp; 2478120660Ssimokawa struct fwohci_txpkthdr *ohcifp; 2479103285Sikob unsigned short chtag; 2480103285Sikob int idb; 2481103285Sikob 2482103285Sikob dbch = &sc->it[dmach]; 2483103285Sikob chtag = sc->it[dmach].xferq.flag & 0xff; 2484103285Sikob 2485103285Sikob db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2486103285Sikob fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2487103285Sikob/* 2488113584Ssimokawadevice_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2489103285Sikob*/ 2490113584Ssimokawa for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2491109892Ssimokawa db = db_tr->db; 2492103285Sikob fp = (struct fw_pkt *)db_tr->buf; 2493120660Ssimokawa ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2494113584Ssimokawa ohcifp->mode.ld[0] = fp->mode.ld[0]; 2495119155Ssimokawa ohcifp->mode.common.spd = 0 & 0x7; 2496113584Ssimokawa ohcifp->mode.stream.len = fp->mode.stream.len; 2497103285Sikob ohcifp->mode.stream.chtag = chtag; 2498103285Sikob ohcifp->mode.stream.tcode = 0xa; 2499113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2500113584Ssimokawa FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2501113584Ssimokawa FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2502113584Ssimokawa#endif 2503103285Sikob 2504113584Ssimokawa FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2505113584Ssimokawa FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2506113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2507109892Ssimokawa#if 0 /* if bulkxfer->npackets changes */ 2508113584Ssimokawa db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2509103285Sikob | OHCI_UPDATE 2510109892Ssimokawa | OHCI_BRANCH_ALWAYS; 2511109892Ssimokawa db[0].db.desc.depend = 2512109892Ssimokawa = db[dbch->ndesc - 1].db.desc.depend 2513113584Ssimokawa = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2514109892Ssimokawa#else 2515113584Ssimokawa FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2516113584Ssimokawa FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2517109892Ssimokawa#endif 2518103285Sikob bulkxfer->end = (caddr_t)db_tr; 2519103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2520103285Sikob } 2521109892Ssimokawa db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2522113584Ssimokawa FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2523113584Ssimokawa FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2524109892Ssimokawa#if 0 /* if bulkxfer->npackets changes */ 2525109892Ssimokawa db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2526109280Ssimokawa /* OHCI 1.1 and above */ 2527109892Ssimokawa db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2528109892Ssimokawa#endif 2529109892Ssimokawa/* 2530103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2531103285Sikob fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2532113584Ssimokawadevice_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2533103285Sikob*/ 2534103285Sikob return; 2535103285Sikob} 2536106790Ssimokawa 2537106790Ssimokawastatic int 2538113584Ssimokawafwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2539113584Ssimokawa int poffset) 2540103285Sikob{ 2541120660Ssimokawa struct fwohcidb *db = db_tr->db; 2542113584Ssimokawa struct fw_xferq *it; 2543103285Sikob int err = 0; 2544113584Ssimokawa 2545113584Ssimokawa it = &dbch->xferq; 2546113584Ssimokawa if(it->buf == 0){ 2547103285Sikob err = EINVAL; 2548103285Sikob return err; 2549103285Sikob } 2550113584Ssimokawa db_tr->buf = fwdma_v_addr(it->buf, poffset); 2551103285Sikob db_tr->dbcnt = 3; 2552103285Sikob 2553113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2554113584Ssimokawa OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2555119155Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2556120660Ssimokawa bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2557113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2558129585Sdfr fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t)); 2559113584Ssimokawa 2560113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2561113584Ssimokawa OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2562109892Ssimokawa#if 1 2563113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2564113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2565109892Ssimokawa#endif 2566113584Ssimokawa return 0; 2567103285Sikob} 2568106790Ssimokawa 2569106790Ssimokawaint 2570113584Ssimokawafwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2571113584Ssimokawa int poffset, struct fwdma_alloc *dummy_dma) 2572103285Sikob{ 2573120660Ssimokawa struct fwohcidb *db = db_tr->db; 2574113584Ssimokawa struct fw_xferq *ir; 2575113584Ssimokawa int i, ldesc; 2576113584Ssimokawa bus_addr_t dbuf[2]; 2577103285Sikob int dsiz[2]; 2578103285Sikob 2579113584Ssimokawa ir = &dbch->xferq; 2580113584Ssimokawa if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2581113584Ssimokawa db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2582113584Ssimokawa ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2583113584Ssimokawa if (db_tr->buf == NULL) 2584113584Ssimokawa return(ENOMEM); 2585103285Sikob db_tr->dbcnt = 1; 2586113584Ssimokawa dsiz[0] = ir->psize; 2587113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2588113584Ssimokawa BUS_DMASYNC_PREREAD); 2589113584Ssimokawa } else { 2590113584Ssimokawa db_tr->dbcnt = 0; 2591113584Ssimokawa if (dummy_dma != NULL) { 2592129585Sdfr dsiz[db_tr->dbcnt] = sizeof(uint32_t); 2593113584Ssimokawa dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2594113584Ssimokawa } 2595113584Ssimokawa dsiz[db_tr->dbcnt] = ir->psize; 2596113584Ssimokawa if (ir->buf != NULL) { 2597113584Ssimokawa db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2598113584Ssimokawa dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2599113584Ssimokawa } 2600113584Ssimokawa db_tr->dbcnt++; 2601103285Sikob } 2602103285Sikob for(i = 0 ; i < db_tr->dbcnt ; i++){ 2603113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2604113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2605113584Ssimokawa if (ir->flag & FWXFERQ_STREAM) { 2606113584Ssimokawa FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2607103285Sikob } 2608113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2609103285Sikob } 2610113584Ssimokawa ldesc = db_tr->dbcnt - 1; 2611113584Ssimokawa if (ir->flag & FWXFERQ_STREAM) { 2612113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2613103285Sikob } 2614113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2615113584Ssimokawa return 0; 2616103285Sikob} 2617106790Ssimokawa 2618113584Ssimokawa 2619113584Ssimokawastatic int 2620113584Ssimokawafwohci_arcv_swap(struct fw_pkt *fp, int len) 2621103285Sikob{ 2622113584Ssimokawa struct fw_pkt *fp0; 2623129585Sdfr uint32_t ld0; 2624120660Ssimokawa int slen, hlen; 2625113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2626113584Ssimokawa int i; 2627113584Ssimokawa#endif 2628103285Sikob 2629113584Ssimokawa ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2630113584Ssimokawa#if 0 2631113584Ssimokawa printf("ld0: x%08x\n", ld0); 2632113584Ssimokawa#endif 2633113584Ssimokawa fp0 = (struct fw_pkt *)&ld0; 2634120660Ssimokawa /* determine length to swap */ 2635113584Ssimokawa switch (fp0->mode.common.tcode) { 2636113584Ssimokawa case FWTCODE_RREQQ: 2637113584Ssimokawa case FWTCODE_WRES: 2638113584Ssimokawa case FWTCODE_WREQQ: 2639113584Ssimokawa case FWTCODE_RRESQ: 2640113584Ssimokawa case FWOHCITCODE_PHY: 2641113584Ssimokawa slen = 12; 2642113584Ssimokawa break; 2643113584Ssimokawa case FWTCODE_RREQB: 2644113584Ssimokawa case FWTCODE_WREQB: 2645113584Ssimokawa case FWTCODE_LREQ: 2646113584Ssimokawa case FWTCODE_RRESB: 2647113584Ssimokawa case FWTCODE_LRES: 2648113584Ssimokawa slen = 16; 2649113584Ssimokawa break; 2650113584Ssimokawa default: 2651113584Ssimokawa printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2652113584Ssimokawa return(0); 2653103285Sikob } 2654120660Ssimokawa hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2655120660Ssimokawa if (hlen > len) { 2656113584Ssimokawa if (firewire_debug) 2657113584Ssimokawa printf("splitted header\n"); 2658120660Ssimokawa return(-hlen); 2659103285Sikob } 2660113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2661113584Ssimokawa for(i = 0; i < slen/4; i ++) 2662113584Ssimokawa fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2663113584Ssimokawa#endif 2664120660Ssimokawa return(hlen); 2665103285Sikob} 2666103285Sikob 2667103285Sikobstatic int 2668113584Ssimokawafwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2669103285Sikob{ 2670120660Ssimokawa struct tcode_info *info; 2671113584Ssimokawa int r; 2672103285Sikob 2673120660Ssimokawa info = &tinfo[fp->mode.common.tcode]; 2674129585Sdfr r = info->hdr_len + sizeof(uint32_t); 2675120660Ssimokawa if ((info->flag & FWTI_BLOCK_ASY) != 0) 2676129585Sdfr r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t)); 2677120660Ssimokawa 2678129585Sdfr if (r == sizeof(uint32_t)) 2679120660Ssimokawa /* XXX */ 2680110798Ssimokawa device_printf(sc->fc.dev, "Unknown tcode %d\n", 2681110798Ssimokawa fp->mode.common.tcode); 2682120660Ssimokawa 2683110798Ssimokawa if (r > dbch->xferq.psize) { 2684110798Ssimokawa device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2685110798Ssimokawa /* panic ? */ 2686110798Ssimokawa } 2687120660Ssimokawa 2688110798Ssimokawa return r; 2689103285Sikob} 2690103285Sikob 2691106790Ssimokawastatic void 2692113584Ssimokawafwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr) 2693113584Ssimokawa{ 2694120660Ssimokawa struct fwohcidb *db = &db_tr->db[0]; 2695113584Ssimokawa 2696113584Ssimokawa FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2697113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2698113584Ssimokawa FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2699113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 2700113584Ssimokawa dbch->bottom = db_tr; 2701113584Ssimokawa} 2702113584Ssimokawa 2703113584Ssimokawastatic void 2704106790Ssimokawafwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2705103285Sikob{ 2706103285Sikob struct fwohcidb_tr *db_tr; 2707113584Ssimokawa struct iovec vec[2]; 2708113584Ssimokawa struct fw_pkt pktbuf; 2709113584Ssimokawa int nvec; 2710103285Sikob struct fw_pkt *fp; 2711129585Sdfr uint8_t *ld; 2712129585Sdfr uint32_t stat, off, status; 2713103285Sikob u_int spd; 2714113584Ssimokawa int len, plen, hlen, pcnt, offset; 2715103285Sikob int s; 2716103285Sikob caddr_t buf; 2717103285Sikob int resCount; 2718103285Sikob 2719103285Sikob if(&sc->arrq == dbch){ 2720103285Sikob off = OHCI_ARQOFF; 2721103285Sikob }else if(&sc->arrs == dbch){ 2722103285Sikob off = OHCI_ARSOFF; 2723103285Sikob }else{ 2724103285Sikob return; 2725103285Sikob } 2726103285Sikob 2727103285Sikob s = splfw(); 2728103285Sikob db_tr = dbch->top; 2729103285Sikob pcnt = 0; 2730103285Sikob /* XXX we cannot handle a packet which lies in more than two buf */ 2731113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 2732113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 2733113584Ssimokawa status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2734113584Ssimokawa resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2735113584Ssimokawa#if 0 2736113584Ssimokawa printf("status 0x%04x, resCount 0x%04x\n", status, resCount); 2737113584Ssimokawa#endif 2738113584Ssimokawa while (status & OHCI_CNTL_DMA_ACTIVE) { 2739113584Ssimokawa len = dbch->xferq.psize - resCount; 2740129585Sdfr ld = (uint8_t *)db_tr->buf; 2741113584Ssimokawa if (dbch->pdb_tr == NULL) { 2742113584Ssimokawa len -= dbch->buf_offset; 2743113584Ssimokawa ld += dbch->buf_offset; 2744113584Ssimokawa } 2745113584Ssimokawa if (len > 0) 2746113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2747113584Ssimokawa BUS_DMASYNC_POSTREAD); 2748103285Sikob while (len > 0 ) { 2749106789Ssimokawa if (count >= 0 && count-- == 0) 2750106789Ssimokawa goto out; 2751113584Ssimokawa if(dbch->pdb_tr != NULL){ 2752113584Ssimokawa /* we have a fragment in previous buffer */ 2753113584Ssimokawa int rlen; 2754103285Sikob 2755113584Ssimokawa offset = dbch->buf_offset; 2756113584Ssimokawa if (offset < 0) 2757113584Ssimokawa offset = - offset; 2758113584Ssimokawa buf = dbch->pdb_tr->buf + offset; 2759113584Ssimokawa rlen = dbch->xferq.psize - offset; 2760113584Ssimokawa if (firewire_debug) 2761113584Ssimokawa printf("rlen=%d, offset=%d\n", 2762113584Ssimokawa rlen, dbch->buf_offset); 2763113584Ssimokawa if (dbch->buf_offset < 0) { 2764113584Ssimokawa /* splitted in header, pull up */ 2765113584Ssimokawa char *p; 2766113584Ssimokawa 2767113584Ssimokawa p = (char *)&pktbuf; 2768113584Ssimokawa bcopy(buf, p, rlen); 2769113584Ssimokawa p += rlen; 2770113584Ssimokawa /* this must be too long but harmless */ 2771113584Ssimokawa rlen = sizeof(pktbuf) - rlen; 2772113584Ssimokawa if (rlen < 0) 2773113584Ssimokawa printf("why rlen < 0\n"); 2774113584Ssimokawa bcopy(db_tr->buf, p, rlen); 2775103285Sikob ld += rlen; 2776103285Sikob len -= rlen; 2777113584Ssimokawa hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2778113584Ssimokawa if (hlen < 0) { 2779113584Ssimokawa printf("hlen < 0 shouldn't happen"); 2780113584Ssimokawa } 2781113584Ssimokawa offset = sizeof(pktbuf); 2782113584Ssimokawa vec[0].iov_base = (char *)&pktbuf; 2783113584Ssimokawa vec[0].iov_len = offset; 2784113584Ssimokawa } else { 2785113584Ssimokawa /* splitted in payload */ 2786113584Ssimokawa offset = rlen; 2787113584Ssimokawa vec[0].iov_base = buf; 2788113584Ssimokawa vec[0].iov_len = rlen; 2789103285Sikob } 2790113584Ssimokawa fp=(struct fw_pkt *)vec[0].iov_base; 2791113584Ssimokawa nvec = 1; 2792113584Ssimokawa } else { 2793113584Ssimokawa /* no fragment in previous buffer */ 2794103285Sikob fp=(struct fw_pkt *)ld; 2795113584Ssimokawa hlen = fwohci_arcv_swap(fp, len); 2796113584Ssimokawa if (hlen == 0) 2797113584Ssimokawa /* XXX need reset */ 2798103285Sikob goto out; 2799113584Ssimokawa if (hlen < 0) { 2800113584Ssimokawa dbch->pdb_tr = db_tr; 2801113584Ssimokawa dbch->buf_offset = - dbch->buf_offset; 2802113584Ssimokawa /* sanity check */ 2803113584Ssimokawa if (resCount != 0) 2804124145Ssimokawa printf("resCount = %d !?\n", 2805124145Ssimokawa resCount); 2806124145Ssimokawa /* XXX clear pdb_tr */ 2807113584Ssimokawa goto out; 2808103285Sikob } 2809113584Ssimokawa offset = 0; 2810113584Ssimokawa nvec = 0; 2811113584Ssimokawa } 2812113584Ssimokawa plen = fwohci_get_plen(sc, dbch, fp) - offset; 2813113584Ssimokawa if (plen < 0) { 2814113584Ssimokawa /* minimum header size + trailer 2815113584Ssimokawa = sizeof(fw_pkt) so this shouldn't happens */ 2816120660Ssimokawa printf("plen(%d) is negative! offset=%d\n", 2817120660Ssimokawa plen, offset); 2818124145Ssimokawa /* XXX clear pdb_tr */ 2819113584Ssimokawa goto out; 2820113584Ssimokawa } 2821113584Ssimokawa if (plen > 0) { 2822113584Ssimokawa len -= plen; 2823113584Ssimokawa if (len < 0) { 2824113584Ssimokawa dbch->pdb_tr = db_tr; 2825113584Ssimokawa if (firewire_debug) 2826113584Ssimokawa printf("splitted payload\n"); 2827113584Ssimokawa /* sanity check */ 2828113584Ssimokawa if (resCount != 0) 2829124145Ssimokawa printf("resCount = %d !?\n", 2830124145Ssimokawa resCount); 2831124145Ssimokawa /* XXX clear pdb_tr */ 2832113584Ssimokawa goto out; 2833103285Sikob } 2834113584Ssimokawa vec[nvec].iov_base = ld; 2835113584Ssimokawa vec[nvec].iov_len = plen; 2836113584Ssimokawa nvec ++; 2837103285Sikob ld += plen; 2838103285Sikob } 2839129585Sdfr dbch->buf_offset = ld - (uint8_t *)db_tr->buf; 2840113584Ssimokawa if (nvec == 0) 2841113584Ssimokawa printf("nvec == 0\n"); 2842113584Ssimokawa 2843103285Sikob/* DMA result-code will be written at the tail of packet */ 2844113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2845113584Ssimokawa stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16; 2846113584Ssimokawa#else 2847113584Ssimokawa stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2848113584Ssimokawa#endif 2849110577Ssimokawa#if 0 2850120660Ssimokawa printf("plen: %d, stat %x\n", 2851120660Ssimokawa plen ,stat); 2852103285Sikob#endif 2853113584Ssimokawa spd = (stat >> 5) & 0x3; 2854113584Ssimokawa stat &= 0x1f; 2855113584Ssimokawa switch(stat){ 2856113584Ssimokawa case FWOHCIEV_ACKPEND: 2857113584Ssimokawa#if 0 2858113584Ssimokawa printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2859113584Ssimokawa#endif 2860113584Ssimokawa /* fall through */ 2861113584Ssimokawa case FWOHCIEV_ACKCOMPL: 2862120660Ssimokawa { 2863120660Ssimokawa struct fw_rcv_buf rb; 2864120660Ssimokawa 2865113584Ssimokawa if ((vec[nvec-1].iov_len -= 2866113584Ssimokawa sizeof(struct fwohci_trailer)) == 0) 2867113584Ssimokawa nvec--; 2868120660Ssimokawa rb.fc = &sc->fc; 2869120660Ssimokawa rb.vec = vec; 2870120660Ssimokawa rb.nvec = nvec; 2871120660Ssimokawa rb.spd = spd; 2872120660Ssimokawa fw_rcv(&rb); 2873120660Ssimokawa break; 2874120660Ssimokawa } 2875113584Ssimokawa case FWOHCIEV_BUSRST: 2876113584Ssimokawa if (sc->fc.status != FWBUSRESET) 2877113584Ssimokawa printf("got BUSRST packet!?\n"); 2878113584Ssimokawa break; 2879113584Ssimokawa default: 2880113584Ssimokawa device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2881103285Sikob#if 0 /* XXX */ 2882113584Ssimokawa goto out; 2883103285Sikob#endif 2884113584Ssimokawa break; 2885103285Sikob } 2886103285Sikob pcnt ++; 2887113584Ssimokawa if (dbch->pdb_tr != NULL) { 2888113584Ssimokawa fwohci_arcv_free_buf(dbch, dbch->pdb_tr); 2889113584Ssimokawa dbch->pdb_tr = NULL; 2890113584Ssimokawa } 2891113584Ssimokawa 2892113584Ssimokawa } 2893103285Sikobout: 2894103285Sikob if (resCount == 0) { 2895103285Sikob /* done on this buffer */ 2896113584Ssimokawa if (dbch->pdb_tr == NULL) { 2897113584Ssimokawa fwohci_arcv_free_buf(dbch, db_tr); 2898113584Ssimokawa dbch->buf_offset = 0; 2899113584Ssimokawa } else 2900113584Ssimokawa if (dbch->pdb_tr != db_tr) 2901113584Ssimokawa printf("pdb_tr != db_tr\n"); 2902103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2903113584Ssimokawa status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2904113584Ssimokawa >> OHCI_STATUS_SHIFT; 2905113584Ssimokawa resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2906113584Ssimokawa & OHCI_COUNT_MASK; 2907113584Ssimokawa /* XXX check buffer overrun */ 2908103285Sikob dbch->top = db_tr; 2909103285Sikob } else { 2910103285Sikob dbch->buf_offset = dbch->xferq.psize - resCount; 2911103285Sikob break; 2912103285Sikob } 2913103285Sikob /* XXX make sure DMA is not dead */ 2914103285Sikob } 2915103285Sikob#if 0 2916103285Sikob if (pcnt < 1) 2917103285Sikob printf("fwohci_arcv: no packets\n"); 2918103285Sikob#endif 2919103285Sikob splx(s); 2920103285Sikob} 2921