fwohci.c revision 167685
1/*- 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the acknowledgement as bellow: 16 * 17 * This product includes software developed by K. Kobayashi and H. Shimokawa 18 * 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: head/sys/dev/firewire/fwohci.c 167685 2007-03-19 03:35:45Z simokawa $ 35 * 36 */ 37 38#define ATRQ_CH 0 39#define ATRS_CH 1 40#define ARRQ_CH 2 41#define ARRS_CH 3 42#define ITX_CH 4 43#define IRX_CH 0x24 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/mbuf.h> 48#include <sys/malloc.h> 49#include <sys/sockio.h> 50#include <sys/bus.h> 51#include <sys/kernel.h> 52#include <sys/conf.h> 53#include <sys/endian.h> 54 55#include <machine/bus.h> 56 57#if defined(__DragonFly__) || __FreeBSD_version < 500000 58#include <machine/clock.h> /* for DELAY() */ 59#endif 60 61#ifdef __DragonFly__ 62#include "firewire.h" 63#include "firewirereg.h" 64#include "fwdma.h" 65#include "fwohcireg.h" 66#include "fwohcivar.h" 67#include "firewire_phy.h" 68#else 69#include <dev/firewire/firewire.h> 70#include <dev/firewire/firewirereg.h> 71#include <dev/firewire/fwdma.h> 72#include <dev/firewire/fwohcireg.h> 73#include <dev/firewire/fwohcivar.h> 74#include <dev/firewire/firewire_phy.h> 75#endif 76 77#undef OHCI_DEBUG 78 79static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 80 "STOR","LOAD","NOP ","STOP",}; 81 82static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 83 "UNDEF","REG","SYS","DEV"}; 84static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 85char fwohcicode[32][0x20]={ 86 "No stat","Undef","long","miss Ack err", 87 "underrun","overrun","desc err", "data read err", 88 "data write err","bus reset","timeout","tcode err", 89 "Undef","Undef","unknown event","flushed", 90 "Undef","ack complete","ack pend","Undef", 91 "ack busy_X","ack busy_A","ack busy_B","Undef", 92 "Undef","Undef","Undef","ack tardy", 93 "Undef","ack data_err","ack type_err",""}; 94 95#define MAX_SPEED 3 96extern char *linkspeed[]; 97uint32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 98 99static struct tcode_info tinfo[] = { 100/* hdr_len block flag*/ 101/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 102/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 103/* 2 WRES */ {12, FWTI_RES}, 104/* 3 XXX */ { 0, 0}, 105/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 106/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 107/* 6 RRESQ */ {16, FWTI_RES}, 108/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 109/* 8 CYCS */ { 0, 0}, 110/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 111/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 112/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 113/* c XXX */ { 0, 0}, 114/* d XXX */ { 0, 0}, 115/* e PHY */ {12, FWTI_REQ}, 116/* f XXX */ { 0, 0} 117}; 118 119#define OHCI_WRITE_SIGMASK 0xffff0000 120#define OHCI_READ_SIGMASK 0xffff0000 121 122#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 123#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 124 125static void fwohci_ibr (struct firewire_comm *); 126static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); 127static void fwohci_db_free (struct fwohci_dbch *); 128static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); 129static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); 130static void fwohci_start_atq (struct firewire_comm *); 131static void fwohci_start_ats (struct firewire_comm *); 132static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); 133static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t); 134static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t); 135static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); 136static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); 137static int fwohci_irx_enable (struct firewire_comm *, int); 138static int fwohci_irx_disable (struct firewire_comm *, int); 139#if BYTE_ORDER == BIG_ENDIAN 140static void fwohci_irx_post (struct firewire_comm *, uint32_t *); 141#endif 142static int fwohci_itxbuf_enable (struct firewire_comm *, int); 143static int fwohci_itx_disable (struct firewire_comm *, int); 144static void fwohci_timeout (void *); 145static void fwohci_set_intr (struct firewire_comm *, int); 146 147static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); 148static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); 149static void dump_db (struct fwohci_softc *, uint32_t); 150static void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t); 151static void dump_dma (struct fwohci_softc *, uint32_t); 152static uint32_t fwohci_cyctimer (struct firewire_comm *); 153static void fwohci_rbuf_update (struct fwohci_softc *, int); 154static void fwohci_tbuf_update (struct fwohci_softc *, int); 155void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); 156#if FWOHCI_TASKQUEUE 157static void fwohci_complete(void *, int); 158#endif 159 160/* 161 * memory allocated for DMA programs 162 */ 163#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 164 165#define NDB FWMAXQUEUE 166 167#define OHCI_VERSION 0x00 168#define OHCI_ATRETRY 0x08 169#define OHCI_CROMHDR 0x18 170#define OHCI_BUS_OPT 0x20 171#define OHCI_BUSIRMC (1 << 31) 172#define OHCI_BUSCMC (1 << 30) 173#define OHCI_BUSISC (1 << 29) 174#define OHCI_BUSBMC (1 << 28) 175#define OHCI_BUSPMC (1 << 27) 176#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 177 OHCI_BUSBMC | OHCI_BUSPMC 178 179#define OHCI_EUID_HI 0x24 180#define OHCI_EUID_LO 0x28 181 182#define OHCI_CROMPTR 0x34 183#define OHCI_HCCCTL 0x50 184#define OHCI_HCCCTLCLR 0x54 185#define OHCI_AREQHI 0x100 186#define OHCI_AREQHICLR 0x104 187#define OHCI_AREQLO 0x108 188#define OHCI_AREQLOCLR 0x10c 189#define OHCI_PREQHI 0x110 190#define OHCI_PREQHICLR 0x114 191#define OHCI_PREQLO 0x118 192#define OHCI_PREQLOCLR 0x11c 193#define OHCI_PREQUPPER 0x120 194 195#define OHCI_SID_BUF 0x64 196#define OHCI_SID_CNT 0x68 197#define OHCI_SID_ERR (1 << 31) 198#define OHCI_SID_CNT_MASK 0xffc 199 200#define OHCI_IT_STAT 0x90 201#define OHCI_IT_STATCLR 0x94 202#define OHCI_IT_MASK 0x98 203#define OHCI_IT_MASKCLR 0x9c 204 205#define OHCI_IR_STAT 0xa0 206#define OHCI_IR_STATCLR 0xa4 207#define OHCI_IR_MASK 0xa8 208#define OHCI_IR_MASKCLR 0xac 209 210#define OHCI_LNKCTL 0xe0 211#define OHCI_LNKCTLCLR 0xe4 212 213#define OHCI_PHYACCESS 0xec 214#define OHCI_CYCLETIMER 0xf0 215 216#define OHCI_DMACTL(off) (off) 217#define OHCI_DMACTLCLR(off) (off + 4) 218#define OHCI_DMACMD(off) (off + 0xc) 219#define OHCI_DMAMATCH(off) (off + 0x10) 220 221#define OHCI_ATQOFF 0x180 222#define OHCI_ATQCTL OHCI_ATQOFF 223#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 224#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 225#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 226 227#define OHCI_ATSOFF 0x1a0 228#define OHCI_ATSCTL OHCI_ATSOFF 229#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 230#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 231#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 232 233#define OHCI_ARQOFF 0x1c0 234#define OHCI_ARQCTL OHCI_ARQOFF 235#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 236#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 237#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 238 239#define OHCI_ARSOFF 0x1e0 240#define OHCI_ARSCTL OHCI_ARSOFF 241#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 242#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 243#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 244 245#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 246#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 247#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 248#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 249 250#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 251#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 252#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 253#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 254#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 255 256d_ioctl_t fwohci_ioctl; 257 258/* 259 * Communication with PHY device 260 */ 261static uint32_t 262fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data) 263{ 264 uint32_t fun; 265 266 addr &= 0xf; 267 data &= 0xff; 268 269 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 270 OWRITE(sc, OHCI_PHYACCESS, fun); 271 DELAY(100); 272 273 return(fwphy_rddata( sc, addr)); 274} 275 276static uint32_t 277fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 278{ 279 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 280 int i; 281 uint32_t bm; 282 283#define OHCI_CSR_DATA 0x0c 284#define OHCI_CSR_COMP 0x10 285#define OHCI_CSR_CONT 0x14 286#define OHCI_BUS_MANAGER_ID 0 287 288 OWRITE(sc, OHCI_CSR_DATA, node); 289 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 290 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 291 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 292 DELAY(10); 293 bm = OREAD(sc, OHCI_CSR_DATA); 294 if((bm & 0x3f) == 0x3f) 295 bm = node; 296 if (firewire_debug) 297 device_printf(sc->fc.dev, 298 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 299 300 return(bm); 301} 302 303static uint32_t 304fwphy_rddata(struct fwohci_softc *sc, u_int addr) 305{ 306 uint32_t fun, stat; 307 u_int i, retry = 0; 308 309 addr &= 0xf; 310#define MAX_RETRY 100 311again: 312 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 313 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 314 OWRITE(sc, OHCI_PHYACCESS, fun); 315 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 316 fun = OREAD(sc, OHCI_PHYACCESS); 317 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 318 break; 319 DELAY(100); 320 } 321 if(i >= MAX_RETRY) { 322 if (firewire_debug) 323 device_printf(sc->fc.dev, "phy read failed(1).\n"); 324 if (++retry < MAX_RETRY) { 325 DELAY(100); 326 goto again; 327 } 328 } 329 /* Make sure that SCLK is started */ 330 stat = OREAD(sc, FWOHCI_INTSTAT); 331 if ((stat & OHCI_INT_REG_FAIL) != 0 || 332 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 333 if (firewire_debug) 334 device_printf(sc->fc.dev, "phy read failed(2).\n"); 335 if (++retry < MAX_RETRY) { 336 DELAY(100); 337 goto again; 338 } 339 } 340 if (firewire_debug || retry >= MAX_RETRY) 341 device_printf(sc->fc.dev, 342 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 343#undef MAX_RETRY 344 return((fun >> PHYDEV_RDDATA )& 0xff); 345} 346/* Device specific ioctl. */ 347int 348fwohci_ioctl (struct cdev *dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 349{ 350 struct firewire_softc *sc; 351 struct fwohci_softc *fc; 352 int unit = DEV2UNIT(dev); 353 int err = 0; 354 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 355 uint32_t *dmach = (uint32_t *) data; 356 357 sc = devclass_get_softc(firewire_devclass, unit); 358 if(sc == NULL){ 359 return(EINVAL); 360 } 361 fc = (struct fwohci_softc *)sc->fc; 362 363 if (!data) 364 return(EINVAL); 365 366 switch (cmd) { 367 case FWOHCI_WRREG: 368#define OHCI_MAX_REG 0x800 369 if(reg->addr <= OHCI_MAX_REG){ 370 OWRITE(fc, reg->addr, reg->data); 371 reg->data = OREAD(fc, reg->addr); 372 }else{ 373 err = EINVAL; 374 } 375 break; 376 case FWOHCI_RDREG: 377 if(reg->addr <= OHCI_MAX_REG){ 378 reg->data = OREAD(fc, reg->addr); 379 }else{ 380 err = EINVAL; 381 } 382 break; 383/* Read DMA descriptors for debug */ 384 case DUMPDMA: 385 if(*dmach <= OHCI_MAX_DMA_CH ){ 386 dump_dma(fc, *dmach); 387 dump_db(fc, *dmach); 388 }else{ 389 err = EINVAL; 390 } 391 break; 392/* Read/Write Phy registers */ 393#define OHCI_MAX_PHY_REG 0xf 394 case FWOHCI_RDPHYREG: 395 if (reg->addr <= OHCI_MAX_PHY_REG) 396 reg->data = fwphy_rddata(fc, reg->addr); 397 else 398 err = EINVAL; 399 break; 400 case FWOHCI_WRPHYREG: 401 if (reg->addr <= OHCI_MAX_PHY_REG) 402 reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 403 else 404 err = EINVAL; 405 break; 406 default: 407 err = EINVAL; 408 break; 409 } 410 return err; 411} 412 413static int 414fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 415{ 416 uint32_t reg, reg2; 417 int e1394a = 1; 418/* 419 * probe PHY parameters 420 * 0. to prove PHY version, whether compliance of 1394a. 421 * 1. to probe maximum speed supported by the PHY and 422 * number of port supported by core-logic. 423 * It is not actually available port on your PC . 424 */ 425 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 426 DELAY(500); 427 428 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 429 430 if((reg >> 5) != 7 ){ 431 sc->fc.mode &= ~FWPHYASYST; 432 sc->fc.nport = reg & FW_PHY_NP; 433 sc->fc.speed = reg & FW_PHY_SPD >> 6; 434 if (sc->fc.speed > MAX_SPEED) { 435 device_printf(dev, "invalid speed %d (fixed to %d).\n", 436 sc->fc.speed, MAX_SPEED); 437 sc->fc.speed = MAX_SPEED; 438 } 439 device_printf(dev, 440 "Phy 1394 only %s, %d ports.\n", 441 linkspeed[sc->fc.speed], sc->fc.nport); 442 }else{ 443 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 444 sc->fc.mode |= FWPHYASYST; 445 sc->fc.nport = reg & FW_PHY_NP; 446 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 447 if (sc->fc.speed > MAX_SPEED) { 448 device_printf(dev, "invalid speed %d (fixed to %d).\n", 449 sc->fc.speed, MAX_SPEED); 450 sc->fc.speed = MAX_SPEED; 451 } 452 device_printf(dev, 453 "Phy 1394a available %s, %d ports.\n", 454 linkspeed[sc->fc.speed], sc->fc.nport); 455 456 /* check programPhyEnable */ 457 reg2 = fwphy_rddata(sc, 5); 458#if 0 459 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 460#else /* XXX force to enable 1394a */ 461 if (e1394a) { 462#endif 463 if (firewire_debug) 464 device_printf(dev, 465 "Enable 1394a Enhancements\n"); 466 /* enable EAA EMC */ 467 reg2 |= 0x03; 468 /* set aPhyEnhanceEnable */ 469 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 470 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 471 } else { 472 /* for safe */ 473 reg2 &= ~0x83; 474 } 475 reg2 = fwphy_wrdata(sc, 5, reg2); 476 } 477 478 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 479 if((reg >> 5) == 7 ){ 480 reg = fwphy_rddata(sc, 4); 481 reg |= 1 << 6; 482 fwphy_wrdata(sc, 4, reg); 483 reg = fwphy_rddata(sc, 4); 484 } 485 return 0; 486} 487 488 489void 490fwohci_reset(struct fwohci_softc *sc, device_t dev) 491{ 492 int i, max_rec, speed; 493 uint32_t reg, reg2; 494 struct fwohcidb_tr *db_tr; 495 496 /* Disable interrupts */ 497 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 498 499 /* Now stopping all DMA channels */ 500 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 501 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 502 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 503 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 504 505 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 506 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 507 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 508 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 509 } 510 511 /* FLUSH FIFO and reset Transmitter/Reciever */ 512 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 513 if (firewire_debug) 514 device_printf(dev, "resetting OHCI..."); 515 i = 0; 516 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 517 if (i++ > 100) break; 518 DELAY(1000); 519 } 520 if (firewire_debug) 521 printf("done (loop=%d)\n", i); 522 523 /* Probe phy */ 524 fwohci_probe_phy(sc, dev); 525 526 /* Probe link */ 527 reg = OREAD(sc, OHCI_BUS_OPT); 528 reg2 = reg | OHCI_BUSFNC; 529 max_rec = (reg & 0x0000f000) >> 12; 530 speed = (reg & 0x00000007); 531 device_printf(dev, "Link %s, max_rec %d bytes.\n", 532 linkspeed[speed], MAXREC(max_rec)); 533 /* XXX fix max_rec */ 534 sc->fc.maxrec = sc->fc.speed + 8; 535 if (max_rec != sc->fc.maxrec) { 536 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 537 device_printf(dev, "max_rec %d -> %d\n", 538 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 539 } 540 if (firewire_debug) 541 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 542 OWRITE(sc, OHCI_BUS_OPT, reg2); 543 544 /* Initialize registers */ 545 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 546 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 547 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 548 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 549 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 550 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 551 552 /* Enable link */ 553 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 554 555 /* Force to start async RX DMA */ 556 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 557 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 558 fwohci_rx_enable(sc, &sc->arrq); 559 fwohci_rx_enable(sc, &sc->arrs); 560 561 /* Initialize async TX */ 562 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 563 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 564 565 /* AT Retries */ 566 OWRITE(sc, FWOHCI_RETRY, 567 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 568 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 569 570 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 571 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 572 sc->atrq.bottom = sc->atrq.top; 573 sc->atrs.bottom = sc->atrs.top; 574 575 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 576 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 577 db_tr->xfer = NULL; 578 } 579 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 580 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 581 db_tr->xfer = NULL; 582 } 583 584 585 /* Enable interrupts */ 586 OWRITE(sc, FWOHCI_INTMASK, 587 OHCI_INT_ERR | OHCI_INT_PHY_SID 588 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 589 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 590 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 591 fwohci_set_intr(&sc->fc, 1); 592 593} 594 595int 596fwohci_init(struct fwohci_softc *sc, device_t dev) 597{ 598 int i, mver; 599 uint32_t reg; 600 uint8_t ui[8]; 601 602#if FWOHCI_TASKQUEUE 603 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 604#endif 605 606/* OHCI version */ 607 reg = OREAD(sc, OHCI_VERSION); 608 mver = (reg >> 16) & 0xff; 609 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 610 mver, reg & 0xff, (reg>>24) & 1); 611 if (mver < 1 || mver > 9) { 612 device_printf(dev, "invalid OHCI version\n"); 613 return (ENXIO); 614 } 615 616/* Available Isochronous DMA channel probe */ 617 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 618 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 619 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 620 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 621 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 622 for (i = 0; i < 0x20; i++) 623 if ((reg & (1 << i)) == 0) 624 break; 625 sc->fc.nisodma = i; 626 device_printf(dev, "No. of Isochronous channels is %d.\n", i); 627 if (i == 0) 628 return (ENXIO); 629 630 sc->fc.arq = &sc->arrq.xferq; 631 sc->fc.ars = &sc->arrs.xferq; 632 sc->fc.atq = &sc->atrq.xferq; 633 sc->fc.ats = &sc->atrs.xferq; 634 635 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 636 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 637 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 638 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 639 640 sc->arrq.xferq.start = NULL; 641 sc->arrs.xferq.start = NULL; 642 sc->atrq.xferq.start = fwohci_start_atq; 643 sc->atrs.xferq.start = fwohci_start_ats; 644 645 sc->arrq.xferq.buf = NULL; 646 sc->arrs.xferq.buf = NULL; 647 sc->atrq.xferq.buf = NULL; 648 sc->atrs.xferq.buf = NULL; 649 650 sc->arrq.xferq.dmach = -1; 651 sc->arrs.xferq.dmach = -1; 652 sc->atrq.xferq.dmach = -1; 653 sc->atrs.xferq.dmach = -1; 654 655 sc->arrq.ndesc = 1; 656 sc->arrs.ndesc = 1; 657 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 658 sc->atrs.ndesc = 2; 659 660 sc->arrq.ndb = NDB; 661 sc->arrs.ndb = NDB / 2; 662 sc->atrq.ndb = NDB; 663 sc->atrs.ndb = NDB / 2; 664 665 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 666 sc->fc.it[i] = &sc->it[i].xferq; 667 sc->fc.ir[i] = &sc->ir[i].xferq; 668 sc->it[i].xferq.dmach = i; 669 sc->ir[i].xferq.dmach = i; 670 sc->it[i].ndb = 0; 671 sc->ir[i].ndb = 0; 672 } 673 674 sc->fc.tcode = tinfo; 675 sc->fc.dev = dev; 676 677 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 678 &sc->crom_dma, BUS_DMA_WAITOK); 679 if(sc->fc.config_rom == NULL){ 680 device_printf(dev, "config_rom alloc failed."); 681 return ENOMEM; 682 } 683 684#if 0 685 bzero(&sc->fc.config_rom[0], CROMSIZE); 686 sc->fc.config_rom[1] = 0x31333934; 687 sc->fc.config_rom[2] = 0xf000a002; 688 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 689 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 690 sc->fc.config_rom[5] = 0; 691 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 692 693 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 694#endif 695 696 697/* SID recieve buffer must align 2^11 */ 698#define OHCI_SIDSIZE (1 << 11) 699 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 700 &sc->sid_dma, BUS_DMA_WAITOK); 701 if (sc->sid_buf == NULL) { 702 device_printf(dev, "sid_buf alloc failed."); 703 return ENOMEM; 704 } 705 706 fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t), 707 &sc->dummy_dma, BUS_DMA_WAITOK); 708 709 if (sc->dummy_dma.v_addr == NULL) { 710 device_printf(dev, "dummy_dma alloc failed."); 711 return ENOMEM; 712 } 713 714 fwohci_db_init(sc, &sc->arrq); 715 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 716 return ENOMEM; 717 718 fwohci_db_init(sc, &sc->arrs); 719 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 720 return ENOMEM; 721 722 fwohci_db_init(sc, &sc->atrq); 723 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 724 return ENOMEM; 725 726 fwohci_db_init(sc, &sc->atrs); 727 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 728 return ENOMEM; 729 730 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 731 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 732 for( i = 0 ; i < 8 ; i ++) 733 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 734 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 735 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 736 737 sc->fc.ioctl = fwohci_ioctl; 738 sc->fc.cyctimer = fwohci_cyctimer; 739 sc->fc.set_bmr = fwohci_set_bus_manager; 740 sc->fc.ibr = fwohci_ibr; 741 sc->fc.irx_enable = fwohci_irx_enable; 742 sc->fc.irx_disable = fwohci_irx_disable; 743 744 sc->fc.itx_enable = fwohci_itxbuf_enable; 745 sc->fc.itx_disable = fwohci_itx_disable; 746#if BYTE_ORDER == BIG_ENDIAN 747 sc->fc.irx_post = fwohci_irx_post; 748#else 749 sc->fc.irx_post = NULL; 750#endif 751 sc->fc.itx_post = NULL; 752 sc->fc.timeout = fwohci_timeout; 753 sc->fc.poll = fwohci_poll; 754 sc->fc.set_intr = fwohci_set_intr; 755 756 sc->intmask = sc->irstat = sc->itstat = 0; 757 758 fw_init(&sc->fc); 759 fwohci_reset(sc, dev); 760 761 return 0; 762} 763 764void 765fwohci_timeout(void *arg) 766{ 767 struct fwohci_softc *sc; 768 769 sc = (struct fwohci_softc *)arg; 770} 771 772uint32_t 773fwohci_cyctimer(struct firewire_comm *fc) 774{ 775 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 776 return(OREAD(sc, OHCI_CYCLETIMER)); 777} 778 779int 780fwohci_detach(struct fwohci_softc *sc, device_t dev) 781{ 782 int i; 783 784 if (sc->sid_buf != NULL) 785 fwdma_free(&sc->fc, &sc->sid_dma); 786 if (sc->fc.config_rom != NULL) 787 fwdma_free(&sc->fc, &sc->crom_dma); 788 789 fwohci_db_free(&sc->arrq); 790 fwohci_db_free(&sc->arrs); 791 792 fwohci_db_free(&sc->atrq); 793 fwohci_db_free(&sc->atrs); 794 795 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 796 fwohci_db_free(&sc->it[i]); 797 fwohci_db_free(&sc->ir[i]); 798 } 799 800 return 0; 801} 802 803#define LAST_DB(dbtr, db) do { \ 804 struct fwohcidb_tr *_dbtr = (dbtr); \ 805 int _cnt = _dbtr->dbcnt; \ 806 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 807} while (0) 808 809static void 810fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 811{ 812 struct fwohcidb_tr *db_tr; 813 struct fwohcidb *db; 814 bus_dma_segment_t *s; 815 int i; 816 817 db_tr = (struct fwohcidb_tr *)arg; 818 db = &db_tr->db[db_tr->dbcnt]; 819 if (error) { 820 if (firewire_debug || error != EFBIG) 821 printf("fwohci_execute_db: error=%d\n", error); 822 return; 823 } 824 for (i = 0; i < nseg; i++) { 825 s = &segs[i]; 826 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 827 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 828 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 829 db++; 830 db_tr->dbcnt++; 831 } 832} 833 834static void 835fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 836 bus_size_t size, int error) 837{ 838 fwohci_execute_db(arg, segs, nseg, error); 839} 840 841static void 842fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 843{ 844 int i, s; 845 int tcode, hdr_len, pl_off; 846 int fsegment = -1; 847 uint32_t off; 848 struct fw_xfer *xfer; 849 struct fw_pkt *fp; 850 struct fwohci_txpkthdr *ohcifp; 851 struct fwohcidb_tr *db_tr; 852 struct fwohcidb *db; 853 uint32_t *ld; 854 struct tcode_info *info; 855 static int maxdesc=0; 856 857 if(&sc->atrq == dbch){ 858 off = OHCI_ATQOFF; 859 }else if(&sc->atrs == dbch){ 860 off = OHCI_ATSOFF; 861 }else{ 862 return; 863 } 864 865 if (dbch->flags & FWOHCI_DBCH_FULL) 866 return; 867 868 s = splfw(); 869 db_tr = dbch->top; 870txloop: 871 xfer = STAILQ_FIRST(&dbch->xferq.q); 872 if(xfer == NULL){ 873 goto kick; 874 } 875 if(dbch->xferq.queued == 0 ){ 876 device_printf(sc->fc.dev, "TX queue empty\n"); 877 } 878 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 879 db_tr->xfer = xfer; 880 xfer->state = FWXF_START; 881 882 fp = &xfer->send.hdr; 883 tcode = fp->mode.common.tcode; 884 885 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 886 info = &tinfo[tcode]; 887 hdr_len = pl_off = info->hdr_len; 888 889 ld = &ohcifp->mode.ld[0]; 890 ld[0] = ld[1] = ld[2] = ld[3] = 0; 891 for( i = 0 ; i < pl_off ; i+= 4) 892 ld[i/4] = fp->mode.ld[i/4]; 893 894 ohcifp->mode.common.spd = xfer->send.spd & 0x7; 895 if (tcode == FWTCODE_STREAM ){ 896 hdr_len = 8; 897 ohcifp->mode.stream.len = fp->mode.stream.len; 898 } else if (tcode == FWTCODE_PHY) { 899 hdr_len = 12; 900 ld[1] = fp->mode.ld[1]; 901 ld[2] = fp->mode.ld[2]; 902 ohcifp->mode.common.spd = 0; 903 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 904 } else { 905 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 906 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 907 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 908 } 909 db = &db_tr->db[0]; 910 FWOHCI_DMA_WRITE(db->db.desc.cmd, 911 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 912 FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 913 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 914/* Specify bound timer of asy. responce */ 915 if(&sc->atrs == dbch){ 916 FWOHCI_DMA_WRITE(db->db.desc.res, 917 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 918 } 919#if BYTE_ORDER == BIG_ENDIAN 920 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 921 hdr_len = 12; 922 for (i = 0; i < hdr_len/4; i ++) 923 FWOHCI_DMA_WRITE(ld[i], ld[i]); 924#endif 925 926again: 927 db_tr->dbcnt = 2; 928 db = &db_tr->db[db_tr->dbcnt]; 929 if (xfer->send.pay_len > 0) { 930 int err; 931 /* handle payload */ 932 if (xfer->mbuf == NULL) { 933 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 934 &xfer->send.payload[0], xfer->send.pay_len, 935 fwohci_execute_db, db_tr, 936 /*flags*/0); 937 } else { 938 /* XXX we can handle only 6 (=8-2) mbuf chains */ 939 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 940 xfer->mbuf, 941 fwohci_execute_db2, db_tr, 942 /* flags */0); 943 if (err == EFBIG) { 944 struct mbuf *m0; 945 946 if (firewire_debug) 947 device_printf(sc->fc.dev, "EFBIG.\n"); 948 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 949 if (m0 != NULL) { 950 m_copydata(xfer->mbuf, 0, 951 xfer->mbuf->m_pkthdr.len, 952 mtod(m0, caddr_t)); 953 m0->m_len = m0->m_pkthdr.len = 954 xfer->mbuf->m_pkthdr.len; 955 m_freem(xfer->mbuf); 956 xfer->mbuf = m0; 957 goto again; 958 } 959 device_printf(sc->fc.dev, "m_getcl failed.\n"); 960 } 961 } 962 if (err) 963 printf("dmamap_load: err=%d\n", err); 964 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 965 BUS_DMASYNC_PREWRITE); 966#if 0 /* OHCI_OUTPUT_MODE == 0 */ 967 for (i = 2; i < db_tr->dbcnt; i++) 968 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 969 OHCI_OUTPUT_MORE); 970#endif 971 } 972 if (maxdesc < db_tr->dbcnt) { 973 maxdesc = db_tr->dbcnt; 974 if (firewire_debug) 975 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 976 } 977 /* last db */ 978 LAST_DB(db_tr, db); 979 FWOHCI_DMA_SET(db->db.desc.cmd, 980 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 981 FWOHCI_DMA_WRITE(db->db.desc.depend, 982 STAILQ_NEXT(db_tr, link)->bus_addr); 983 984 if(fsegment == -1 ) 985 fsegment = db_tr->dbcnt; 986 if (dbch->pdb_tr != NULL) { 987 LAST_DB(dbch->pdb_tr, db); 988 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 989 } 990 dbch->pdb_tr = db_tr; 991 db_tr = STAILQ_NEXT(db_tr, link); 992 if(db_tr != dbch->bottom){ 993 goto txloop; 994 } else { 995 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 996 dbch->flags |= FWOHCI_DBCH_FULL; 997 } 998kick: 999 /* kick asy q */ 1000 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1001 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1002 1003 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 1004 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 1005 } else { 1006 if (firewire_debug) 1007 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 1008 OREAD(sc, OHCI_DMACTL(off))); 1009 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1010 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1011 dbch->xferq.flag |= FWXFERQ_RUNNING; 1012 } 1013 1014 dbch->top = db_tr; 1015 splx(s); 1016 return; 1017} 1018 1019static void 1020fwohci_start_atq(struct firewire_comm *fc) 1021{ 1022 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1023 fwohci_start( sc, &(sc->atrq)); 1024 return; 1025} 1026 1027static void 1028fwohci_start_ats(struct firewire_comm *fc) 1029{ 1030 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1031 fwohci_start( sc, &(sc->atrs)); 1032 return; 1033} 1034 1035void 1036fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1037{ 1038 int s, ch, err = 0; 1039 struct fwohcidb_tr *tr; 1040 struct fwohcidb *db; 1041 struct fw_xfer *xfer; 1042 uint32_t off; 1043 u_int stat, status; 1044 int packets; 1045 struct firewire_comm *fc = (struct firewire_comm *)sc; 1046 1047 if(&sc->atrq == dbch){ 1048 off = OHCI_ATQOFF; 1049 ch = ATRQ_CH; 1050 }else if(&sc->atrs == dbch){ 1051 off = OHCI_ATSOFF; 1052 ch = ATRS_CH; 1053 }else{ 1054 return; 1055 } 1056 s = splfw(); 1057 tr = dbch->bottom; 1058 packets = 0; 1059 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 1060 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 1061 while(dbch->xferq.queued > 0){ 1062 LAST_DB(tr, db); 1063 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1064 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1065 if (fc->status != FWBUSRESET) 1066 /* maybe out of order?? */ 1067 goto out; 1068 } 1069 bus_dmamap_sync(dbch->dmat, tr->dma_map, 1070 BUS_DMASYNC_POSTWRITE); 1071 bus_dmamap_unload(dbch->dmat, tr->dma_map); 1072#if 1 1073 if (firewire_debug > 1) 1074 dump_db(sc, ch); 1075#endif 1076 if(status & OHCI_CNTL_DMA_DEAD) { 1077 /* Stop DMA */ 1078 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1079 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1080 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1081 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1082 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1083 } 1084 stat = status & FWOHCIEV_MASK; 1085 switch(stat){ 1086 case FWOHCIEV_ACKPEND: 1087 case FWOHCIEV_ACKCOMPL: 1088 err = 0; 1089 break; 1090 case FWOHCIEV_ACKBSA: 1091 case FWOHCIEV_ACKBSB: 1092 case FWOHCIEV_ACKBSX: 1093 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1094 err = EBUSY; 1095 break; 1096 case FWOHCIEV_FLUSHED: 1097 case FWOHCIEV_ACKTARD: 1098 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1099 err = EAGAIN; 1100 break; 1101 case FWOHCIEV_MISSACK: 1102 case FWOHCIEV_UNDRRUN: 1103 case FWOHCIEV_OVRRUN: 1104 case FWOHCIEV_DESCERR: 1105 case FWOHCIEV_DTRDERR: 1106 case FWOHCIEV_TIMEOUT: 1107 case FWOHCIEV_TCODERR: 1108 case FWOHCIEV_UNKNOWN: 1109 case FWOHCIEV_ACKDERR: 1110 case FWOHCIEV_ACKTERR: 1111 default: 1112 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1113 stat, fwohcicode[stat]); 1114 err = EINVAL; 1115 break; 1116 } 1117 if (tr->xfer != NULL) { 1118 xfer = tr->xfer; 1119 if (xfer->state == FWXF_RCVD) { 1120#if 0 1121 if (firewire_debug) 1122 printf("already rcvd\n"); 1123#endif 1124 fw_xfer_done(xfer); 1125 } else { 1126 xfer->state = FWXF_SENT; 1127 if (err == EBUSY && fc->status != FWBUSRESET) { 1128 xfer->state = FWXF_BUSY; 1129 xfer->resp = err; 1130 xfer->recv.pay_len = 0; 1131 fw_xfer_done(xfer); 1132 } else if (stat != FWOHCIEV_ACKPEND) { 1133 if (stat != FWOHCIEV_ACKCOMPL) 1134 xfer->state = FWXF_SENTERR; 1135 xfer->resp = err; 1136 xfer->recv.pay_len = 0; 1137 fw_xfer_done(xfer); 1138 } 1139 } 1140 /* 1141 * The watchdog timer takes care of split 1142 * transcation timeout for ACKPEND case. 1143 */ 1144 } else { 1145 printf("this shouldn't happen\n"); 1146 } 1147 dbch->xferq.queued --; 1148 tr->xfer = NULL; 1149 1150 packets ++; 1151 tr = STAILQ_NEXT(tr, link); 1152 dbch->bottom = tr; 1153 if (dbch->bottom == dbch->top) { 1154 /* we reaches the end of context program */ 1155 if (firewire_debug && dbch->xferq.queued > 0) 1156 printf("queued > 0\n"); 1157 break; 1158 } 1159 } 1160out: 1161 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1162 printf("make free slot\n"); 1163 dbch->flags &= ~FWOHCI_DBCH_FULL; 1164 fwohci_start(sc, dbch); 1165 } 1166 splx(s); 1167} 1168 1169static void 1170fwohci_db_free(struct fwohci_dbch *dbch) 1171{ 1172 struct fwohcidb_tr *db_tr; 1173 int idb; 1174 1175 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1176 return; 1177 1178 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1179 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1180 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1181 db_tr->buf != NULL) { 1182 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1183 db_tr->buf, dbch->xferq.psize); 1184 db_tr->buf = NULL; 1185 } else if (db_tr->dma_map != NULL) 1186 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1187 } 1188 dbch->ndb = 0; 1189 db_tr = STAILQ_FIRST(&dbch->db_trq); 1190 fwdma_free_multiseg(dbch->am); 1191 free(db_tr, M_FW); 1192 STAILQ_INIT(&dbch->db_trq); 1193 dbch->flags &= ~FWOHCI_DBCH_INIT; 1194} 1195 1196static void 1197fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1198{ 1199 int idb; 1200 struct fwohcidb_tr *db_tr; 1201 1202 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1203 goto out; 1204 1205 /* create dma_tag for buffers */ 1206#define MAX_REQCOUNT 0xffff 1207 if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1208 /*alignment*/ 1, /*boundary*/ 0, 1209 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1210 /*highaddr*/ BUS_SPACE_MAXADDR, 1211 /*filter*/NULL, /*filterarg*/NULL, 1212 /*maxsize*/ dbch->xferq.psize, 1213 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1214 /*maxsegsz*/ MAX_REQCOUNT, 1215 /*flags*/ 0, 1216#if defined(__FreeBSD__) && __FreeBSD_version >= 501102 1217 /*lockfunc*/busdma_lock_mutex, 1218 /*lockarg*/&Giant, 1219#endif 1220 &dbch->dmat)) 1221 return; 1222 1223 /* allocate DB entries and attach one to each DMA channels */ 1224 /* DB entry must start at 16 bytes bounary. */ 1225 STAILQ_INIT(&dbch->db_trq); 1226 db_tr = (struct fwohcidb_tr *) 1227 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1228 M_FW, M_WAITOK | M_ZERO); 1229 if(db_tr == NULL){ 1230 printf("fwohci_db_init: malloc(1) failed\n"); 1231 return; 1232 } 1233 1234#define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1235 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1236 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1237 if (dbch->am == NULL) { 1238 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1239 free(db_tr, M_FW); 1240 return; 1241 } 1242 /* Attach DB to DMA ch. */ 1243 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1244 db_tr->dbcnt = 0; 1245 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1246 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1247 /* create dmamap for buffers */ 1248 /* XXX do we need 4bytes alignment tag? */ 1249 /* XXX don't alloc dma_map for AR */ 1250 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1251 printf("bus_dmamap_create failed\n"); 1252 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1253 fwohci_db_free(dbch); 1254 return; 1255 } 1256 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1257 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1258 if (idb % dbch->xferq.bnpacket == 0) 1259 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1260 ].start = (caddr_t)db_tr; 1261 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1262 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1263 ].end = (caddr_t)db_tr; 1264 } 1265 db_tr++; 1266 } 1267 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1268 = STAILQ_FIRST(&dbch->db_trq); 1269out: 1270 dbch->xferq.queued = 0; 1271 dbch->pdb_tr = NULL; 1272 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1273 dbch->bottom = dbch->top; 1274 dbch->flags = FWOHCI_DBCH_INIT; 1275} 1276 1277static int 1278fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1279{ 1280 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1281 1282 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1283 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1284 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1285 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1286 /* XXX we cannot free buffers until the DMA really stops */ 1287 pause("fwitxd", hz); 1288 fwohci_db_free(&sc->it[dmach]); 1289 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1290 return 0; 1291} 1292 1293static int 1294fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1295{ 1296 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1297 1298 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1299 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1300 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1301 /* XXX we cannot free buffers until the DMA really stops */ 1302 pause("fwirxd", hz); 1303 fwohci_db_free(&sc->ir[dmach]); 1304 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1305 return 0; 1306} 1307 1308#if BYTE_ORDER == BIG_ENDIAN 1309static void 1310fwohci_irx_post (struct firewire_comm *fc , uint32_t *qld) 1311{ 1312 qld[0] = FWOHCI_DMA_READ(qld[0]); 1313 return; 1314} 1315#endif 1316 1317static int 1318fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1319{ 1320 int err = 0; 1321 int idb, z, i, dmach = 0, ldesc; 1322 uint32_t off = 0; 1323 struct fwohcidb_tr *db_tr; 1324 struct fwohcidb *db; 1325 1326 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1327 err = EINVAL; 1328 return err; 1329 } 1330 z = dbch->ndesc; 1331 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1332 if( &sc->it[dmach] == dbch){ 1333 off = OHCI_ITOFF(dmach); 1334 break; 1335 } 1336 } 1337 if(off == 0){ 1338 err = EINVAL; 1339 return err; 1340 } 1341 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1342 return err; 1343 dbch->xferq.flag |= FWXFERQ_RUNNING; 1344 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1345 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1346 } 1347 db_tr = dbch->top; 1348 for (idb = 0; idb < dbch->ndb; idb ++) { 1349 fwohci_add_tx_buf(dbch, db_tr, idb); 1350 if(STAILQ_NEXT(db_tr, link) == NULL){ 1351 break; 1352 } 1353 db = db_tr->db; 1354 ldesc = db_tr->dbcnt - 1; 1355 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1356 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1357 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1358 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1359 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1360 FWOHCI_DMA_SET( 1361 db[ldesc].db.desc.cmd, 1362 OHCI_INTERRUPT_ALWAYS); 1363 /* OHCI 1.1 and above */ 1364 FWOHCI_DMA_SET( 1365 db[0].db.desc.cmd, 1366 OHCI_INTERRUPT_ALWAYS); 1367 } 1368 } 1369 db_tr = STAILQ_NEXT(db_tr, link); 1370 } 1371 FWOHCI_DMA_CLEAR( 1372 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1373 return err; 1374} 1375 1376static int 1377fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1378{ 1379 int err = 0; 1380 int idb, z, i, dmach = 0, ldesc; 1381 uint32_t off = 0; 1382 struct fwohcidb_tr *db_tr; 1383 struct fwohcidb *db; 1384 1385 z = dbch->ndesc; 1386 if(&sc->arrq == dbch){ 1387 off = OHCI_ARQOFF; 1388 }else if(&sc->arrs == dbch){ 1389 off = OHCI_ARSOFF; 1390 }else{ 1391 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1392 if( &sc->ir[dmach] == dbch){ 1393 off = OHCI_IROFF(dmach); 1394 break; 1395 } 1396 } 1397 } 1398 if(off == 0){ 1399 err = EINVAL; 1400 return err; 1401 } 1402 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1403 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1404 return err; 1405 }else{ 1406 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1407 err = EBUSY; 1408 return err; 1409 } 1410 } 1411 dbch->xferq.flag |= FWXFERQ_RUNNING; 1412 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1413 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1414 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1415 } 1416 db_tr = dbch->top; 1417 for (idb = 0; idb < dbch->ndb; idb ++) { 1418 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1419 if (STAILQ_NEXT(db_tr, link) == NULL) 1420 break; 1421 db = db_tr->db; 1422 ldesc = db_tr->dbcnt - 1; 1423 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1424 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1425 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1426 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1427 FWOHCI_DMA_SET( 1428 db[ldesc].db.desc.cmd, 1429 OHCI_INTERRUPT_ALWAYS); 1430 FWOHCI_DMA_CLEAR( 1431 db[ldesc].db.desc.depend, 1432 0xf); 1433 } 1434 } 1435 db_tr = STAILQ_NEXT(db_tr, link); 1436 } 1437 FWOHCI_DMA_CLEAR( 1438 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1439 dbch->buf_offset = 0; 1440 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1441 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1442 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1443 return err; 1444 }else{ 1445 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1446 } 1447 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1448 return err; 1449} 1450 1451static int 1452fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1453{ 1454 int sec, cycle, cycle_match; 1455 1456 cycle = cycle_now & 0x1fff; 1457 sec = cycle_now >> 13; 1458#define CYCLE_MOD 0x10 1459#if 1 1460#define CYCLE_DELAY 8 /* min delay to start DMA */ 1461#else 1462#define CYCLE_DELAY 7000 /* min delay to start DMA */ 1463#endif 1464 cycle = cycle + CYCLE_DELAY; 1465 if (cycle >= 8000) { 1466 sec ++; 1467 cycle -= 8000; 1468 } 1469 cycle = roundup2(cycle, CYCLE_MOD); 1470 if (cycle >= 8000) { 1471 sec ++; 1472 if (cycle == 8000) 1473 cycle = 0; 1474 else 1475 cycle = CYCLE_MOD; 1476 } 1477 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1478 1479 return(cycle_match); 1480} 1481 1482static int 1483fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1484{ 1485 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1486 int err = 0; 1487 unsigned short tag, ich; 1488 struct fwohci_dbch *dbch; 1489 int cycle_match, cycle_now, s, ldesc; 1490 uint32_t stat; 1491 struct fw_bulkxfer *first, *chunk, *prev; 1492 struct fw_xferq *it; 1493 1494 dbch = &sc->it[dmach]; 1495 it = &dbch->xferq; 1496 1497 tag = (it->flag >> 6) & 3; 1498 ich = it->flag & 0x3f; 1499 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1500 dbch->ndb = it->bnpacket * it->bnchunk; 1501 dbch->ndesc = 3; 1502 fwohci_db_init(sc, dbch); 1503 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1504 return ENOMEM; 1505 err = fwohci_tx_enable(sc, dbch); 1506 } 1507 if(err) 1508 return err; 1509 1510 ldesc = dbch->ndesc - 1; 1511 s = splfw(); 1512 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1513 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1514 struct fwohcidb *db; 1515 1516 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1517 BUS_DMASYNC_PREWRITE); 1518 fwohci_txbufdb(sc, dmach, chunk); 1519 if (prev != NULL) { 1520 db = ((struct fwohcidb_tr *)(prev->end))->db; 1521#if 0 /* XXX necessary? */ 1522 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1523 OHCI_BRANCH_ALWAYS); 1524#endif 1525#if 0 /* if bulkxfer->npacket changes */ 1526 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1527 ((struct fwohcidb_tr *) 1528 (chunk->start))->bus_addr | dbch->ndesc; 1529#else 1530 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1531 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1532#endif 1533 } 1534 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1535 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1536 prev = chunk; 1537 } 1538 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1539 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1540 splx(s); 1541 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1542 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1543 printf("stat 0x%x\n", stat); 1544 1545 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1546 return 0; 1547 1548#if 0 1549 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1550#endif 1551 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1552 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1553 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1554 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1555 1556 first = STAILQ_FIRST(&it->stdma); 1557 OWRITE(sc, OHCI_ITCMD(dmach), 1558 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1559 if (firewire_debug > 1) { 1560 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1561#if 1 1562 dump_dma(sc, ITX_CH + dmach); 1563#endif 1564 } 1565 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1566#if 1 1567 /* Don't start until all chunks are buffered */ 1568 if (STAILQ_FIRST(&it->stfree) != NULL) 1569 goto out; 1570#endif 1571#if 1 1572 /* Clear cycle match counter bits */ 1573 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1574 1575 /* 2bit second + 13bit cycle */ 1576 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1577 cycle_match = fwohci_next_cycle(fc, cycle_now); 1578 1579 OWRITE(sc, OHCI_ITCTL(dmach), 1580 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1581 | OHCI_CNTL_DMA_RUN); 1582#else 1583 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1584#endif 1585 if (firewire_debug > 1) { 1586 printf("cycle_match: 0x%04x->0x%04x\n", 1587 cycle_now, cycle_match); 1588 dump_dma(sc, ITX_CH + dmach); 1589 dump_db(sc, ITX_CH + dmach); 1590 } 1591 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1592 device_printf(sc->fc.dev, 1593 "IT DMA underrun (0x%08x)\n", stat); 1594 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1595 } 1596out: 1597 return err; 1598} 1599 1600static int 1601fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1602{ 1603 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1604 int err = 0, s, ldesc; 1605 unsigned short tag, ich; 1606 uint32_t stat; 1607 struct fwohci_dbch *dbch; 1608 struct fwohcidb_tr *db_tr; 1609 struct fw_bulkxfer *first, *prev, *chunk; 1610 struct fw_xferq *ir; 1611 1612 dbch = &sc->ir[dmach]; 1613 ir = &dbch->xferq; 1614 1615 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1616 tag = (ir->flag >> 6) & 3; 1617 ich = ir->flag & 0x3f; 1618 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1619 1620 ir->queued = 0; 1621 dbch->ndb = ir->bnpacket * ir->bnchunk; 1622 dbch->ndesc = 2; 1623 fwohci_db_init(sc, dbch); 1624 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1625 return ENOMEM; 1626 err = fwohci_rx_enable(sc, dbch); 1627 } 1628 if(err) 1629 return err; 1630 1631 first = STAILQ_FIRST(&ir->stfree); 1632 if (first == NULL) { 1633 device_printf(fc->dev, "IR DMA no free chunk\n"); 1634 return 0; 1635 } 1636 1637 ldesc = dbch->ndesc - 1; 1638 s = splfw(); 1639 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1640 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1641 struct fwohcidb *db; 1642 1643#if 1 /* XXX for if_fwe */ 1644 if (chunk->mbuf != NULL) { 1645 db_tr = (struct fwohcidb_tr *)(chunk->start); 1646 db_tr->dbcnt = 1; 1647 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 1648 chunk->mbuf, fwohci_execute_db2, db_tr, 1649 /* flags */0); 1650 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1651 OHCI_UPDATE | OHCI_INPUT_LAST | 1652 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1653 } 1654#endif 1655 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1656 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1657 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1658 if (prev != NULL) { 1659 db = ((struct fwohcidb_tr *)(prev->end))->db; 1660 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1661 } 1662 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1663 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1664 prev = chunk; 1665 } 1666 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1667 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1668 splx(s); 1669 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1670 if (stat & OHCI_CNTL_DMA_ACTIVE) 1671 return 0; 1672 if (stat & OHCI_CNTL_DMA_RUN) { 1673 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1674 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1675 } 1676 1677 if (firewire_debug) 1678 printf("start IR DMA 0x%x\n", stat); 1679 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1680 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1681 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1682 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1683 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1684 OWRITE(sc, OHCI_IRCMD(dmach), 1685 ((struct fwohcidb_tr *)(first->start))->bus_addr 1686 | dbch->ndesc); 1687 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1688 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1689#if 0 1690 dump_db(sc, IRX_CH + dmach); 1691#endif 1692 return err; 1693} 1694 1695int 1696fwohci_stop(struct fwohci_softc *sc, device_t dev) 1697{ 1698 u_int i; 1699 1700/* Now stopping all DMA channel */ 1701 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1702 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1703 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1704 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1705 1706 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1707 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1708 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1709 } 1710 1711/* FLUSH FIFO and reset Transmitter/Reciever */ 1712 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1713 1714/* Stop interrupt */ 1715 OWRITE(sc, FWOHCI_INTMASKCLR, 1716 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1717 | OHCI_INT_PHY_INT 1718 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1719 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1720 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1721 | OHCI_INT_PHY_BUS_R); 1722 1723 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1724 fw_drain_txq(&sc->fc); 1725 1726/* XXX Link down? Bus reset? */ 1727 return 0; 1728} 1729 1730int 1731fwohci_resume(struct fwohci_softc *sc, device_t dev) 1732{ 1733 int i; 1734 struct fw_xferq *ir; 1735 struct fw_bulkxfer *chunk; 1736 1737 fwohci_reset(sc, dev); 1738 /* XXX resume isochronous receive automatically. (how about TX?) */ 1739 for(i = 0; i < sc->fc.nisodma; i ++) { 1740 ir = &sc->ir[i].xferq; 1741 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1742 device_printf(sc->fc.dev, 1743 "resume iso receive ch: %d\n", i); 1744 ir->flag &= ~FWXFERQ_RUNNING; 1745 /* requeue stdma to stfree */ 1746 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1747 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1748 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1749 } 1750 sc->fc.irx_enable(&sc->fc, i); 1751 } 1752 } 1753 1754 bus_generic_resume(dev); 1755 sc->fc.ibr(&sc->fc); 1756 return 0; 1757} 1758 1759#define ACK_ALL 1760static void 1761fwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count) 1762{ 1763 uint32_t irstat, itstat; 1764 u_int i; 1765 struct firewire_comm *fc = (struct firewire_comm *)sc; 1766 1767#ifdef OHCI_DEBUG 1768 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1769 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1770 stat & OHCI_INT_EN ? "DMA_EN ":"", 1771 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1772 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1773 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1774 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1775 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1776 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1777 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1778 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1779 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1780 stat & OHCI_INT_PHY_SID ? "SID ":"", 1781 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1782 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1783 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1784 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1785 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1786 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1787 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1788 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1789 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1790 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1791 stat, OREAD(sc, FWOHCI_INTMASK) 1792 ); 1793#endif 1794/* Bus reset */ 1795 if(stat & OHCI_INT_PHY_BUS_R ){ 1796 if (fc->status == FWBUSRESET) 1797 goto busresetout; 1798 /* Disable bus reset interrupt until sid recv. */ 1799 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1800 1801 device_printf(fc->dev, "BUS reset\n"); 1802 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1803 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1804 1805 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1806 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1807 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1808 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1809 1810#ifndef ACK_ALL 1811 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1812#endif 1813 fw_busreset(fc); 1814 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1815 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1816 } 1817busresetout: 1818 if((stat & OHCI_INT_DMA_IR )){ 1819#ifndef ACK_ALL 1820 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1821#endif 1822#if defined(__DragonFly__) || __FreeBSD_version < 500000 1823 irstat = sc->irstat; 1824 sc->irstat = 0; 1825#else 1826 irstat = atomic_readandclear_int(&sc->irstat); 1827#endif 1828 for(i = 0; i < fc->nisodma ; i++){ 1829 struct fwohci_dbch *dbch; 1830 1831 if((irstat & (1 << i)) != 0){ 1832 dbch = &sc->ir[i]; 1833 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1834 device_printf(sc->fc.dev, 1835 "dma(%d) not active\n", i); 1836 continue; 1837 } 1838 fwohci_rbuf_update(sc, i); 1839 } 1840 } 1841 } 1842 if((stat & OHCI_INT_DMA_IT )){ 1843#ifndef ACK_ALL 1844 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1845#endif 1846#if defined(__DragonFly__) || __FreeBSD_version < 500000 1847 itstat = sc->itstat; 1848 sc->itstat = 0; 1849#else 1850 itstat = atomic_readandclear_int(&sc->itstat); 1851#endif 1852 for(i = 0; i < fc->nisodma ; i++){ 1853 if((itstat & (1 << i)) != 0){ 1854 fwohci_tbuf_update(sc, i); 1855 } 1856 } 1857 } 1858 if((stat & OHCI_INT_DMA_PRRS )){ 1859#ifndef ACK_ALL 1860 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1861#endif 1862#if 0 1863 dump_dma(sc, ARRS_CH); 1864 dump_db(sc, ARRS_CH); 1865#endif 1866 fwohci_arcv(sc, &sc->arrs, count); 1867 } 1868 if((stat & OHCI_INT_DMA_PRRQ )){ 1869#ifndef ACK_ALL 1870 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1871#endif 1872#if 0 1873 dump_dma(sc, ARRQ_CH); 1874 dump_db(sc, ARRQ_CH); 1875#endif 1876 fwohci_arcv(sc, &sc->arrq, count); 1877 } 1878 if (stat & OHCI_INT_CYC_LOST) { 1879 if (sc->cycle_lost >= 0) 1880 sc->cycle_lost ++; 1881 if (sc->cycle_lost > 10) { 1882 sc->cycle_lost = -1; 1883#if 0 1884 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER); 1885#endif 1886 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1887 device_printf(fc->dev, "too many cycle lost, " 1888 "no cycle master presents?\n"); 1889 } 1890 } 1891 if(stat & OHCI_INT_PHY_SID){ 1892 uint32_t *buf, node_id; 1893 int plen; 1894 1895#ifndef ACK_ALL 1896 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1897#endif 1898 /* Enable bus reset interrupt */ 1899 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1900 /* Allow async. request to us */ 1901 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1902 /* XXX insecure ?? */ 1903 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1904 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1905 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1906 /* Set ATRetries register */ 1907 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1908/* 1909** Checking whether the node is root or not. If root, turn on 1910** cycle master. 1911*/ 1912 node_id = OREAD(sc, FWOHCI_NODEID); 1913 plen = OREAD(sc, OHCI_SID_CNT); 1914 1915 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 1916 node_id, (plen >> 16) & 0xff); 1917 if (!(node_id & OHCI_NODE_VALID)) { 1918 printf("Bus reset failure\n"); 1919 goto sidout; 1920 } 1921 1922 /* cycle timer */ 1923 sc->cycle_lost = 0; 1924 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST); 1925 if (node_id & OHCI_NODE_ROOT) { 1926 printf("CYCLEMASTER mode\n"); 1927 OWRITE(sc, OHCI_LNKCTL, 1928 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1929 } else { 1930 printf("non CYCLEMASTER mode\n"); 1931 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1932 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1933 } 1934 1935 fc->nodeid = node_id & 0x3f; 1936 1937 if (plen & OHCI_SID_ERR) { 1938 device_printf(fc->dev, "SID Error\n"); 1939 goto sidout; 1940 } 1941 plen &= OHCI_SID_CNT_MASK; 1942 if (plen < 4 || plen > OHCI_SIDSIZE) { 1943 device_printf(fc->dev, "invalid SID len = %d\n", plen); 1944 goto sidout; 1945 } 1946 plen -= 4; /* chop control info */ 1947 buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1948 if (buf == NULL) { 1949 device_printf(fc->dev, "malloc failed\n"); 1950 goto sidout; 1951 } 1952 for (i = 0; i < plen / 4; i ++) 1953 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 1954#if 1 /* XXX needed?? */ 1955 /* pending all pre-bus_reset packets */ 1956 fwohci_txd(sc, &sc->atrq); 1957 fwohci_txd(sc, &sc->atrs); 1958 fwohci_arcv(sc, &sc->arrs, -1); 1959 fwohci_arcv(sc, &sc->arrq, -1); 1960 fw_drain_txq(fc); 1961#endif 1962 fw_sidrcv(fc, buf, plen); 1963 free(buf, M_FW); 1964 } 1965sidout: 1966 if((stat & OHCI_INT_DMA_ATRQ )){ 1967#ifndef ACK_ALL 1968 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1969#endif 1970 fwohci_txd(sc, &(sc->atrq)); 1971 } 1972 if((stat & OHCI_INT_DMA_ATRS )){ 1973#ifndef ACK_ALL 1974 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1975#endif 1976 fwohci_txd(sc, &(sc->atrs)); 1977 } 1978 if((stat & OHCI_INT_PW_ERR )){ 1979#ifndef ACK_ALL 1980 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1981#endif 1982 device_printf(fc->dev, "posted write error\n"); 1983 } 1984 if((stat & OHCI_INT_ERR )){ 1985#ifndef ACK_ALL 1986 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1987#endif 1988 device_printf(fc->dev, "unrecoverable error\n"); 1989 } 1990 if((stat & OHCI_INT_PHY_INT)) { 1991#ifndef ACK_ALL 1992 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1993#endif 1994 device_printf(fc->dev, "phy int\n"); 1995 } 1996 1997 return; 1998} 1999 2000#if FWOHCI_TASKQUEUE 2001static void 2002fwohci_complete(void *arg, int pending) 2003{ 2004 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2005 uint32_t stat; 2006 2007again: 2008 stat = atomic_readandclear_int(&sc->intstat); 2009 if (stat) 2010 fwohci_intr_body(sc, stat, -1); 2011 else 2012 return; 2013 goto again; 2014} 2015#endif 2016 2017static uint32_t 2018fwochi_check_stat(struct fwohci_softc *sc) 2019{ 2020 uint32_t stat, irstat, itstat; 2021 2022 stat = OREAD(sc, FWOHCI_INTSTAT); 2023 if (stat == 0xffffffff) { 2024 device_printf(sc->fc.dev, 2025 "device physically ejected?\n"); 2026 return(stat); 2027 } 2028#ifdef ACK_ALL 2029 if (stat) 2030 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2031#endif 2032 if (stat & OHCI_INT_DMA_IR) { 2033 irstat = OREAD(sc, OHCI_IR_STAT); 2034 OWRITE(sc, OHCI_IR_STATCLR, irstat); 2035 atomic_set_int(&sc->irstat, irstat); 2036 } 2037 if (stat & OHCI_INT_DMA_IT) { 2038 itstat = OREAD(sc, OHCI_IT_STAT); 2039 OWRITE(sc, OHCI_IT_STATCLR, itstat); 2040 atomic_set_int(&sc->itstat, itstat); 2041 } 2042 return(stat); 2043} 2044 2045void 2046fwohci_intr(void *arg) 2047{ 2048 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2049 uint32_t stat; 2050#if !FWOHCI_TASKQUEUE 2051 uint32_t bus_reset = 0; 2052#endif 2053 2054 if (!(sc->intmask & OHCI_INT_EN)) { 2055 /* polling mode */ 2056 return; 2057 } 2058 2059#if !FWOHCI_TASKQUEUE 2060again: 2061#endif 2062 stat = fwochi_check_stat(sc); 2063 if (stat == 0 || stat == 0xffffffff) 2064 return; 2065#if FWOHCI_TASKQUEUE 2066 atomic_set_int(&sc->intstat, stat); 2067 /* XXX mask bus reset intr. during bus reset phase */ 2068 if (stat) 2069 taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete); 2070#else 2071 /* We cannot clear bus reset event during bus reset phase */ 2072 if ((stat & ~bus_reset) == 0) 2073 return; 2074 bus_reset = stat & OHCI_INT_PHY_BUS_R; 2075 fwohci_intr_body(sc, stat, -1); 2076 goto again; 2077#endif 2078} 2079 2080void 2081fwohci_poll(struct firewire_comm *fc, int quick, int count) 2082{ 2083 int s; 2084 uint32_t stat; 2085 struct fwohci_softc *sc; 2086 2087 2088 sc = (struct fwohci_softc *)fc; 2089 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2090 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2091 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2092#if 0 2093 if (!quick) { 2094#else 2095 if (1) { 2096#endif 2097 stat = fwochi_check_stat(sc); 2098 if (stat == 0 || stat == 0xffffffff) 2099 return; 2100 } 2101 s = splfw(); 2102 fwohci_intr_body(sc, stat, count); 2103 splx(s); 2104} 2105 2106static void 2107fwohci_set_intr(struct firewire_comm *fc, int enable) 2108{ 2109 struct fwohci_softc *sc; 2110 2111 sc = (struct fwohci_softc *)fc; 2112 if (firewire_debug) 2113 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2114 if (enable) { 2115 sc->intmask |= OHCI_INT_EN; 2116 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2117 } else { 2118 sc->intmask &= ~OHCI_INT_EN; 2119 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2120 } 2121} 2122 2123static void 2124fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2125{ 2126 struct firewire_comm *fc = &sc->fc; 2127 struct fwohcidb *db; 2128 struct fw_bulkxfer *chunk; 2129 struct fw_xferq *it; 2130 uint32_t stat, count; 2131 int s, w=0, ldesc; 2132 2133 it = fc->it[dmach]; 2134 ldesc = sc->it[dmach].ndesc - 1; 2135 s = splfw(); /* unnecessary ? */ 2136 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2137 if (firewire_debug) 2138 dump_db(sc, ITX_CH + dmach); 2139 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2140 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2141 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2142 >> OHCI_STATUS_SHIFT; 2143 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2144 /* timestamp */ 2145 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2146 & OHCI_COUNT_MASK; 2147 if (stat == 0) 2148 break; 2149 STAILQ_REMOVE_HEAD(&it->stdma, link); 2150 switch (stat & FWOHCIEV_MASK){ 2151 case FWOHCIEV_ACKCOMPL: 2152#if 0 2153 device_printf(fc->dev, "0x%08x\n", count); 2154#endif 2155 break; 2156 default: 2157 device_printf(fc->dev, 2158 "Isochronous transmit err %02x(%s)\n", 2159 stat, fwohcicode[stat & 0x1f]); 2160 } 2161 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2162 w++; 2163 } 2164 splx(s); 2165 if (w) 2166 wakeup(it); 2167} 2168 2169static void 2170fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2171{ 2172 struct firewire_comm *fc = &sc->fc; 2173 struct fwohcidb_tr *db_tr; 2174 struct fw_bulkxfer *chunk; 2175 struct fw_xferq *ir; 2176 uint32_t stat; 2177 int s, w=0, ldesc; 2178 2179 ir = fc->ir[dmach]; 2180 ldesc = sc->ir[dmach].ndesc - 1; 2181#if 0 2182 dump_db(sc, dmach); 2183#endif 2184 s = splfw(); 2185 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2186 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2187 db_tr = (struct fwohcidb_tr *)chunk->end; 2188 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2189 >> OHCI_STATUS_SHIFT; 2190 if (stat == 0) 2191 break; 2192 2193 if (chunk->mbuf != NULL) { 2194 bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2195 BUS_DMASYNC_POSTREAD); 2196 bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 2197 } else if (ir->buf != NULL) { 2198 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2199 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2200 } else { 2201 /* XXX */ 2202 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2203 } 2204 2205 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2206 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2207 switch (stat & FWOHCIEV_MASK) { 2208 case FWOHCIEV_ACKCOMPL: 2209 chunk->resp = 0; 2210 break; 2211 default: 2212 chunk->resp = EINVAL; 2213 device_printf(fc->dev, 2214 "Isochronous receive err %02x(%s)\n", 2215 stat, fwohcicode[stat & 0x1f]); 2216 } 2217 w++; 2218 } 2219 splx(s); 2220 if (w) { 2221 if (ir->flag & FWXFERQ_HANDLER) 2222 ir->hand(ir); 2223 else 2224 wakeup(ir); 2225 } 2226} 2227 2228void 2229dump_dma(struct fwohci_softc *sc, uint32_t ch) 2230{ 2231 uint32_t off, cntl, stat, cmd, match; 2232 2233 if(ch == 0){ 2234 off = OHCI_ATQOFF; 2235 }else if(ch == 1){ 2236 off = OHCI_ATSOFF; 2237 }else if(ch == 2){ 2238 off = OHCI_ARQOFF; 2239 }else if(ch == 3){ 2240 off = OHCI_ARSOFF; 2241 }else if(ch < IRX_CH){ 2242 off = OHCI_ITCTL(ch - ITX_CH); 2243 }else{ 2244 off = OHCI_IRCTL(ch - IRX_CH); 2245 } 2246 cntl = stat = OREAD(sc, off); 2247 cmd = OREAD(sc, off + 0xc); 2248 match = OREAD(sc, off + 0x10); 2249 2250 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2251 ch, 2252 cntl, 2253 cmd, 2254 match); 2255 stat &= 0xffff ; 2256 if (stat) { 2257 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2258 ch, 2259 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2260 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2261 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2262 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2263 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2264 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2265 fwohcicode[stat & 0x1f], 2266 stat & 0x1f 2267 ); 2268 }else{ 2269 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2270 } 2271} 2272 2273void 2274dump_db(struct fwohci_softc *sc, uint32_t ch) 2275{ 2276 struct fwohci_dbch *dbch; 2277 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2278 struct fwohcidb *curr = NULL, *prev, *next = NULL; 2279 int idb, jdb; 2280 uint32_t cmd, off; 2281 if(ch == 0){ 2282 off = OHCI_ATQOFF; 2283 dbch = &sc->atrq; 2284 }else if(ch == 1){ 2285 off = OHCI_ATSOFF; 2286 dbch = &sc->atrs; 2287 }else if(ch == 2){ 2288 off = OHCI_ARQOFF; 2289 dbch = &sc->arrq; 2290 }else if(ch == 3){ 2291 off = OHCI_ARSOFF; 2292 dbch = &sc->arrs; 2293 }else if(ch < IRX_CH){ 2294 off = OHCI_ITCTL(ch - ITX_CH); 2295 dbch = &sc->it[ch - ITX_CH]; 2296 }else { 2297 off = OHCI_IRCTL(ch - IRX_CH); 2298 dbch = &sc->ir[ch - IRX_CH]; 2299 } 2300 cmd = OREAD(sc, off + 0xc); 2301 2302 if( dbch->ndb == 0 ){ 2303 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2304 return; 2305 } 2306 pp = dbch->top; 2307 prev = pp->db; 2308 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2309 cp = STAILQ_NEXT(pp, link); 2310 if(cp == NULL){ 2311 curr = NULL; 2312 goto outdb; 2313 } 2314 np = STAILQ_NEXT(cp, link); 2315 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2316 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2317 curr = cp->db; 2318 if(np != NULL){ 2319 next = np->db; 2320 }else{ 2321 next = NULL; 2322 } 2323 goto outdb; 2324 } 2325 } 2326 pp = STAILQ_NEXT(pp, link); 2327 if(pp == NULL){ 2328 curr = NULL; 2329 goto outdb; 2330 } 2331 prev = pp->db; 2332 } 2333outdb: 2334 if( curr != NULL){ 2335#if 0 2336 printf("Prev DB %d\n", ch); 2337 print_db(pp, prev, ch, dbch->ndesc); 2338#endif 2339 printf("Current DB %d\n", ch); 2340 print_db(cp, curr, ch, dbch->ndesc); 2341#if 0 2342 printf("Next DB %d\n", ch); 2343 print_db(np, next, ch, dbch->ndesc); 2344#endif 2345 }else{ 2346 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2347 } 2348 return; 2349} 2350 2351void 2352print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2353 uint32_t ch, uint32_t max) 2354{ 2355 fwohcireg_t stat; 2356 int i, key; 2357 uint32_t cmd, res; 2358 2359 if(db == NULL){ 2360 printf("No Descriptor is found\n"); 2361 return; 2362 } 2363 2364 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2365 ch, 2366 "Current", 2367 "OP ", 2368 "KEY", 2369 "INT", 2370 "BR ", 2371 "len", 2372 "Addr", 2373 "Depend", 2374 "Stat", 2375 "Cnt"); 2376 for( i = 0 ; i <= max ; i ++){ 2377 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2378 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2379 key = cmd & OHCI_KEY_MASK; 2380 stat = res >> OHCI_STATUS_SHIFT; 2381#if defined(__DragonFly__) || __FreeBSD_version < 500000 2382 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2383 db_tr->bus_addr, 2384#else 2385 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2386 (uintmax_t)db_tr->bus_addr, 2387#endif 2388 dbcode[(cmd >> 28) & 0xf], 2389 dbkey[(cmd >> 24) & 0x7], 2390 dbcond[(cmd >> 20) & 0x3], 2391 dbcond[(cmd >> 18) & 0x3], 2392 cmd & OHCI_COUNT_MASK, 2393 FWOHCI_DMA_READ(db[i].db.desc.addr), 2394 FWOHCI_DMA_READ(db[i].db.desc.depend), 2395 stat, 2396 res & OHCI_COUNT_MASK); 2397 if(stat & 0xff00){ 2398 printf(" %s%s%s%s%s%s %s(%x)\n", 2399 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2400 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2401 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2402 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2403 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2404 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2405 fwohcicode[stat & 0x1f], 2406 stat & 0x1f 2407 ); 2408 }else{ 2409 printf(" Nostat\n"); 2410 } 2411 if(key == OHCI_KEY_ST2 ){ 2412 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2413 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2414 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2415 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2416 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2417 } 2418 if(key == OHCI_KEY_DEVICE){ 2419 return; 2420 } 2421 if((cmd & OHCI_BRANCH_MASK) 2422 == OHCI_BRANCH_ALWAYS){ 2423 return; 2424 } 2425 if((cmd & OHCI_CMD_MASK) 2426 == OHCI_OUTPUT_LAST){ 2427 return; 2428 } 2429 if((cmd & OHCI_CMD_MASK) 2430 == OHCI_INPUT_LAST){ 2431 return; 2432 } 2433 if(key == OHCI_KEY_ST2 ){ 2434 i++; 2435 } 2436 } 2437 return; 2438} 2439 2440void 2441fwohci_ibr(struct firewire_comm *fc) 2442{ 2443 struct fwohci_softc *sc; 2444 uint32_t fun; 2445 2446 device_printf(fc->dev, "Initiate bus reset\n"); 2447 sc = (struct fwohci_softc *)fc; 2448 2449 /* 2450 * Make sure our cached values from the config rom are 2451 * initialised. 2452 */ 2453 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 2454 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 2455 2456 /* 2457 * Set root hold-off bit so that non cyclemaster capable node 2458 * shouldn't became the root node. 2459 */ 2460#if 1 2461 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2462 fun |= FW_PHY_IBR | FW_PHY_RHB; 2463 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2464#else /* Short bus reset */ 2465 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2466 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2467 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2468#endif 2469} 2470 2471void 2472fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2473{ 2474 struct fwohcidb_tr *db_tr, *fdb_tr; 2475 struct fwohci_dbch *dbch; 2476 struct fwohcidb *db; 2477 struct fw_pkt *fp; 2478 struct fwohci_txpkthdr *ohcifp; 2479 unsigned short chtag; 2480 int idb; 2481 2482 dbch = &sc->it[dmach]; 2483 chtag = sc->it[dmach].xferq.flag & 0xff; 2484 2485 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2486 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2487/* 2488device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2489*/ 2490 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2491 db = db_tr->db; 2492 fp = (struct fw_pkt *)db_tr->buf; 2493 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2494 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2495 ohcifp->mode.common.spd = 0 & 0x7; 2496 ohcifp->mode.stream.len = fp->mode.stream.len; 2497 ohcifp->mode.stream.chtag = chtag; 2498 ohcifp->mode.stream.tcode = 0xa; 2499#if BYTE_ORDER == BIG_ENDIAN 2500 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2501 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2502#endif 2503 2504 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2505 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2506 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2507#if 0 /* if bulkxfer->npackets changes */ 2508 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2509 | OHCI_UPDATE 2510 | OHCI_BRANCH_ALWAYS; 2511 db[0].db.desc.depend = 2512 = db[dbch->ndesc - 1].db.desc.depend 2513 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2514#else 2515 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2516 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2517#endif 2518 bulkxfer->end = (caddr_t)db_tr; 2519 db_tr = STAILQ_NEXT(db_tr, link); 2520 } 2521 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2522 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2523 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2524#if 0 /* if bulkxfer->npackets changes */ 2525 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2526 /* OHCI 1.1 and above */ 2527 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2528#endif 2529/* 2530 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2531 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2532device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2533*/ 2534 return; 2535} 2536 2537static int 2538fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2539 int poffset) 2540{ 2541 struct fwohcidb *db = db_tr->db; 2542 struct fw_xferq *it; 2543 int err = 0; 2544 2545 it = &dbch->xferq; 2546 if(it->buf == 0){ 2547 err = EINVAL; 2548 return err; 2549 } 2550 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2551 db_tr->dbcnt = 3; 2552 2553 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2554 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2555 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2556 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2557 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2558 fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t)); 2559 2560 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2561 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2562#if 1 2563 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2564 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2565#endif 2566 return 0; 2567} 2568 2569int 2570fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2571 int poffset, struct fwdma_alloc *dummy_dma) 2572{ 2573 struct fwohcidb *db = db_tr->db; 2574 struct fw_xferq *ir; 2575 int i, ldesc; 2576 bus_addr_t dbuf[2]; 2577 int dsiz[2]; 2578 2579 ir = &dbch->xferq; 2580 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2581 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2582 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2583 if (db_tr->buf == NULL) 2584 return(ENOMEM); 2585 db_tr->dbcnt = 1; 2586 dsiz[0] = ir->psize; 2587 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2588 BUS_DMASYNC_PREREAD); 2589 } else { 2590 db_tr->dbcnt = 0; 2591 if (dummy_dma != NULL) { 2592 dsiz[db_tr->dbcnt] = sizeof(uint32_t); 2593 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2594 } 2595 dsiz[db_tr->dbcnt] = ir->psize; 2596 if (ir->buf != NULL) { 2597 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2598 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2599 } 2600 db_tr->dbcnt++; 2601 } 2602 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2603 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2604 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2605 if (ir->flag & FWXFERQ_STREAM) { 2606 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2607 } 2608 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2609 } 2610 ldesc = db_tr->dbcnt - 1; 2611 if (ir->flag & FWXFERQ_STREAM) { 2612 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2613 } 2614 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2615 return 0; 2616} 2617 2618 2619static int 2620fwohci_arcv_swap(struct fw_pkt *fp, int len) 2621{ 2622 struct fw_pkt *fp0; 2623 uint32_t ld0; 2624 int slen, hlen; 2625#if BYTE_ORDER == BIG_ENDIAN 2626 int i; 2627#endif 2628 2629 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2630#if 0 2631 printf("ld0: x%08x\n", ld0); 2632#endif 2633 fp0 = (struct fw_pkt *)&ld0; 2634 /* determine length to swap */ 2635 switch (fp0->mode.common.tcode) { 2636 case FWTCODE_RREQQ: 2637 case FWTCODE_WRES: 2638 case FWTCODE_WREQQ: 2639 case FWTCODE_RRESQ: 2640 case FWOHCITCODE_PHY: 2641 slen = 12; 2642 break; 2643 case FWTCODE_RREQB: 2644 case FWTCODE_WREQB: 2645 case FWTCODE_LREQ: 2646 case FWTCODE_RRESB: 2647 case FWTCODE_LRES: 2648 slen = 16; 2649 break; 2650 default: 2651 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2652 return(0); 2653 } 2654 hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2655 if (hlen > len) { 2656 if (firewire_debug) 2657 printf("splitted header\n"); 2658 return(-hlen); 2659 } 2660#if BYTE_ORDER == BIG_ENDIAN 2661 for(i = 0; i < slen/4; i ++) 2662 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2663#endif 2664 return(hlen); 2665} 2666 2667static int 2668fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2669{ 2670 struct tcode_info *info; 2671 int r; 2672 2673 info = &tinfo[fp->mode.common.tcode]; 2674 r = info->hdr_len + sizeof(uint32_t); 2675 if ((info->flag & FWTI_BLOCK_ASY) != 0) 2676 r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t)); 2677 2678 if (r == sizeof(uint32_t)) 2679 /* XXX */ 2680 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2681 fp->mode.common.tcode); 2682 2683 if (r > dbch->xferq.psize) { 2684 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2685 /* panic ? */ 2686 } 2687 2688 return r; 2689} 2690 2691static void 2692fwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr) 2693{ 2694 struct fwohcidb *db = &db_tr->db[0]; 2695 2696 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2697 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2698 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2699 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 2700 dbch->bottom = db_tr; 2701} 2702 2703static void 2704fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2705{ 2706 struct fwohcidb_tr *db_tr; 2707 struct iovec vec[2]; 2708 struct fw_pkt pktbuf; 2709 int nvec; 2710 struct fw_pkt *fp; 2711 uint8_t *ld; 2712 uint32_t stat, off, status; 2713 u_int spd; 2714 int len, plen, hlen, pcnt, offset; 2715 int s; 2716 caddr_t buf; 2717 int resCount; 2718 2719 if(&sc->arrq == dbch){ 2720 off = OHCI_ARQOFF; 2721 }else if(&sc->arrs == dbch){ 2722 off = OHCI_ARSOFF; 2723 }else{ 2724 return; 2725 } 2726 2727 s = splfw(); 2728 db_tr = dbch->top; 2729 pcnt = 0; 2730 /* XXX we cannot handle a packet which lies in more than two buf */ 2731 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 2732 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 2733 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2734 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2735#if 0 2736 printf("status 0x%04x, resCount 0x%04x\n", status, resCount); 2737#endif 2738 while (status & OHCI_CNTL_DMA_ACTIVE) { 2739 len = dbch->xferq.psize - resCount; 2740 ld = (uint8_t *)db_tr->buf; 2741 if (dbch->pdb_tr == NULL) { 2742 len -= dbch->buf_offset; 2743 ld += dbch->buf_offset; 2744 } 2745 if (len > 0) 2746 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2747 BUS_DMASYNC_POSTREAD); 2748 while (len > 0 ) { 2749 if (count >= 0 && count-- == 0) 2750 goto out; 2751 if(dbch->pdb_tr != NULL){ 2752 /* we have a fragment in previous buffer */ 2753 int rlen; 2754 2755 offset = dbch->buf_offset; 2756 if (offset < 0) 2757 offset = - offset; 2758 buf = dbch->pdb_tr->buf + offset; 2759 rlen = dbch->xferq.psize - offset; 2760 if (firewire_debug) 2761 printf("rlen=%d, offset=%d\n", 2762 rlen, dbch->buf_offset); 2763 if (dbch->buf_offset < 0) { 2764 /* splitted in header, pull up */ 2765 char *p; 2766 2767 p = (char *)&pktbuf; 2768 bcopy(buf, p, rlen); 2769 p += rlen; 2770 /* this must be too long but harmless */ 2771 rlen = sizeof(pktbuf) - rlen; 2772 if (rlen < 0) 2773 printf("why rlen < 0\n"); 2774 bcopy(db_tr->buf, p, rlen); 2775 ld += rlen; 2776 len -= rlen; 2777 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2778 if (hlen < 0) { 2779 printf("hlen < 0 shouldn't happen"); 2780 } 2781 offset = sizeof(pktbuf); 2782 vec[0].iov_base = (char *)&pktbuf; 2783 vec[0].iov_len = offset; 2784 } else { 2785 /* splitted in payload */ 2786 offset = rlen; 2787 vec[0].iov_base = buf; 2788 vec[0].iov_len = rlen; 2789 } 2790 fp=(struct fw_pkt *)vec[0].iov_base; 2791 nvec = 1; 2792 } else { 2793 /* no fragment in previous buffer */ 2794 fp=(struct fw_pkt *)ld; 2795 hlen = fwohci_arcv_swap(fp, len); 2796 if (hlen == 0) 2797 /* XXX need reset */ 2798 goto out; 2799 if (hlen < 0) { 2800 dbch->pdb_tr = db_tr; 2801 dbch->buf_offset = - dbch->buf_offset; 2802 /* sanity check */ 2803 if (resCount != 0) 2804 printf("resCount = %d !?\n", 2805 resCount); 2806 /* XXX clear pdb_tr */ 2807 goto out; 2808 } 2809 offset = 0; 2810 nvec = 0; 2811 } 2812 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2813 if (plen < 0) { 2814 /* minimum header size + trailer 2815 = sizeof(fw_pkt) so this shouldn't happens */ 2816 printf("plen(%d) is negative! offset=%d\n", 2817 plen, offset); 2818 /* XXX clear pdb_tr */ 2819 goto out; 2820 } 2821 if (plen > 0) { 2822 len -= plen; 2823 if (len < 0) { 2824 dbch->pdb_tr = db_tr; 2825 if (firewire_debug) 2826 printf("splitted payload\n"); 2827 /* sanity check */ 2828 if (resCount != 0) 2829 printf("resCount = %d !?\n", 2830 resCount); 2831 /* XXX clear pdb_tr */ 2832 goto out; 2833 } 2834 vec[nvec].iov_base = ld; 2835 vec[nvec].iov_len = plen; 2836 nvec ++; 2837 ld += plen; 2838 } 2839 dbch->buf_offset = ld - (uint8_t *)db_tr->buf; 2840 if (nvec == 0) 2841 printf("nvec == 0\n"); 2842 2843/* DMA result-code will be written at the tail of packet */ 2844#if BYTE_ORDER == BIG_ENDIAN 2845 stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16; 2846#else 2847 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2848#endif 2849#if 0 2850 printf("plen: %d, stat %x\n", 2851 plen ,stat); 2852#endif 2853 spd = (stat >> 5) & 0x3; 2854 stat &= 0x1f; 2855 switch(stat){ 2856 case FWOHCIEV_ACKPEND: 2857#if 0 2858 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2859#endif 2860 /* fall through */ 2861 case FWOHCIEV_ACKCOMPL: 2862 { 2863 struct fw_rcv_buf rb; 2864 2865 if ((vec[nvec-1].iov_len -= 2866 sizeof(struct fwohci_trailer)) == 0) 2867 nvec--; 2868 rb.fc = &sc->fc; 2869 rb.vec = vec; 2870 rb.nvec = nvec; 2871 rb.spd = spd; 2872 fw_rcv(&rb); 2873 break; 2874 } 2875 case FWOHCIEV_BUSRST: 2876 if (sc->fc.status != FWBUSRESET) 2877 printf("got BUSRST packet!?\n"); 2878 break; 2879 default: 2880 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2881#if 0 /* XXX */ 2882 goto out; 2883#endif 2884 break; 2885 } 2886 pcnt ++; 2887 if (dbch->pdb_tr != NULL) { 2888 fwohci_arcv_free_buf(dbch, dbch->pdb_tr); 2889 dbch->pdb_tr = NULL; 2890 } 2891 2892 } 2893out: 2894 if (resCount == 0) { 2895 /* done on this buffer */ 2896 if (dbch->pdb_tr == NULL) { 2897 fwohci_arcv_free_buf(dbch, db_tr); 2898 dbch->buf_offset = 0; 2899 } else 2900 if (dbch->pdb_tr != db_tr) 2901 printf("pdb_tr != db_tr\n"); 2902 db_tr = STAILQ_NEXT(db_tr, link); 2903 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2904 >> OHCI_STATUS_SHIFT; 2905 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2906 & OHCI_COUNT_MASK; 2907 /* XXX check buffer overrun */ 2908 dbch->top = db_tr; 2909 } else { 2910 dbch->buf_offset = dbch->xferq.psize - resCount; 2911 break; 2912 } 2913 /* XXX make sure DMA is not dead */ 2914 } 2915#if 0 2916 if (pcnt < 1) 2917 printf("fwohci_arcv: no packets\n"); 2918#endif 2919 splx(s); 2920} 2921