fwohci.c revision 124836
1103285Sikob/* 2113584Ssimokawa * Copyright (c) 2003 Hidetoshi Shimokawa 3103285Sikob * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4103285Sikob * All rights reserved. 5103285Sikob * 6103285Sikob * Redistribution and use in source and binary forms, with or without 7103285Sikob * modification, are permitted provided that the following conditions 8103285Sikob * are met: 9103285Sikob * 1. Redistributions of source code must retain the above copyright 10103285Sikob * notice, this list of conditions and the following disclaimer. 11103285Sikob * 2. Redistributions in binary form must reproduce the above copyright 12103285Sikob * notice, this list of conditions and the following disclaimer in the 13103285Sikob * documentation and/or other materials provided with the distribution. 14103285Sikob * 3. All advertising materials mentioning features or use of this software 15103285Sikob * must display the acknowledgement as bellow: 16103285Sikob * 17106802Ssimokawa * This product includes software developed by K. Kobayashi and H. Shimokawa 18103285Sikob * 19103285Sikob * 4. The name of the author may not be used to endorse or promote products 20103285Sikob * derived from this software without specific prior written permission. 21103285Sikob * 22103285Sikob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23103285Sikob * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24103285Sikob * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25103285Sikob * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26103285Sikob * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27103285Sikob * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28103285Sikob * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29103285Sikob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30103285Sikob * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31103285Sikob * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32103285Sikob * POSSIBILITY OF SUCH DAMAGE. 33103285Sikob * 34103285Sikob * $FreeBSD: head/sys/dev/firewire/fwohci.c 124836 2004-01-22 14:41:17Z simokawa $ 35103285Sikob * 36103285Sikob */ 37106802Ssimokawa 38103285Sikob#define ATRQ_CH 0 39103285Sikob#define ATRS_CH 1 40103285Sikob#define ARRQ_CH 2 41103285Sikob#define ARRS_CH 3 42103285Sikob#define ITX_CH 4 43103285Sikob#define IRX_CH 0x24 44103285Sikob 45103285Sikob#include <sys/param.h> 46103285Sikob#include <sys/systm.h> 47103285Sikob#include <sys/mbuf.h> 48103285Sikob#include <sys/malloc.h> 49103285Sikob#include <sys/sockio.h> 50103285Sikob#include <sys/bus.h> 51103285Sikob#include <sys/kernel.h> 52103285Sikob#include <sys/conf.h> 53113584Ssimokawa#include <sys/endian.h> 54103285Sikob 55103285Sikob#include <machine/bus.h> 56103285Sikob 57117067Ssimokawa#if __FreeBSD_version < 500000 58117067Ssimokawa#include <machine/clock.h> /* for DELAY() */ 59117067Ssimokawa#endif 60117067Ssimokawa 61103285Sikob#include <dev/firewire/firewire.h> 62103285Sikob#include <dev/firewire/firewirereg.h> 63113584Ssimokawa#include <dev/firewire/fwdma.h> 64103285Sikob#include <dev/firewire/fwohcireg.h> 65103285Sikob#include <dev/firewire/fwohcivar.h> 66103285Sikob#include <dev/firewire/firewire_phy.h> 67103285Sikob 68103285Sikob#undef OHCI_DEBUG 69106802Ssimokawa 70103285Sikobstatic char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 71103285Sikob "STOR","LOAD","NOP ","STOP",}; 72113584Ssimokawa 73103285Sikobstatic char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 74103285Sikob "UNDEF","REG","SYS","DEV"}; 75113584Ssimokawastatic char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 76103285Sikobchar fwohcicode[32][0x20]={ 77103285Sikob "No stat","Undef","long","miss Ack err", 78103285Sikob "underrun","overrun","desc err", "data read err", 79103285Sikob "data write err","bus reset","timeout","tcode err", 80103285Sikob "Undef","Undef","unknown event","flushed", 81103285Sikob "Undef","ack complete","ack pend","Undef", 82103285Sikob "ack busy_X","ack busy_A","ack busy_B","Undef", 83103285Sikob "Undef","Undef","Undef","ack tardy", 84103285Sikob "Undef","ack data_err","ack type_err",""}; 85113584Ssimokawa 86116376Ssimokawa#define MAX_SPEED 3 87124378Ssimokawaextern char *linkspeed[]; 88103285Sikobu_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 89103285Sikob 90103285Sikobstatic struct tcode_info tinfo[] = { 91103285Sikob/* hdr_len block flag*/ 92103285Sikob/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 93103285Sikob/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 94103285Sikob/* 2 WRES */ {12, FWTI_RES}, 95103285Sikob/* 3 XXX */ { 0, 0}, 96103285Sikob/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 97103285Sikob/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 98103285Sikob/* 6 RRESQ */ {16, FWTI_RES}, 99103285Sikob/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 100103285Sikob/* 8 CYCS */ { 0, 0}, 101103285Sikob/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 102103285Sikob/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 103103285Sikob/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 104103285Sikob/* c XXX */ { 0, 0}, 105103285Sikob/* d XXX */ { 0, 0}, 106103285Sikob/* e PHY */ {12, FWTI_REQ}, 107103285Sikob/* f XXX */ { 0, 0} 108103285Sikob}; 109103285Sikob 110103285Sikob#define OHCI_WRITE_SIGMASK 0xffff0000 111103285Sikob#define OHCI_READ_SIGMASK 0xffff0000 112103285Sikob 113103285Sikob#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 114103285Sikob#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 115103285Sikob 116124169Ssimokawastatic void fwohci_ibr (struct firewire_comm *); 117124169Ssimokawastatic void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); 118124169Ssimokawastatic void fwohci_db_free (struct fwohci_dbch *); 119124169Ssimokawastatic void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); 120124169Ssimokawastatic void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); 121124169Ssimokawastatic void fwohci_start_atq (struct firewire_comm *); 122124169Ssimokawastatic void fwohci_start_ats (struct firewire_comm *); 123124169Ssimokawastatic void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); 124124169Ssimokawastatic u_int32_t fwphy_wrdata ( struct fwohci_softc *, u_int32_t, u_int32_t); 125124169Ssimokawastatic u_int32_t fwphy_rddata ( struct fwohci_softc *, u_int32_t); 126124169Ssimokawastatic int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); 127124169Ssimokawastatic int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); 128124169Ssimokawastatic int fwohci_irx_enable (struct firewire_comm *, int); 129124169Ssimokawastatic int fwohci_irx_disable (struct firewire_comm *, int); 130113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 131124169Ssimokawastatic void fwohci_irx_post (struct firewire_comm *, u_int32_t *); 132113584Ssimokawa#endif 133124169Ssimokawastatic int fwohci_itxbuf_enable (struct firewire_comm *, int); 134124169Ssimokawastatic int fwohci_itx_disable (struct firewire_comm *, int); 135124169Ssimokawastatic void fwohci_timeout (void *); 136124169Ssimokawastatic void fwohci_set_intr (struct firewire_comm *, int); 137113584Ssimokawa 138124169Ssimokawastatic int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); 139124169Ssimokawastatic int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); 140124169Ssimokawastatic void dump_db (struct fwohci_softc *, u_int32_t); 141124169Ssimokawastatic void print_db (struct fwohcidb_tr *, struct fwohcidb *, u_int32_t , u_int32_t); 142124169Ssimokawastatic void dump_dma (struct fwohci_softc *, u_int32_t); 143124169Ssimokawastatic u_int32_t fwohci_cyctimer (struct firewire_comm *); 144124169Ssimokawastatic void fwohci_rbuf_update (struct fwohci_softc *, int); 145124169Ssimokawastatic void fwohci_tbuf_update (struct fwohci_softc *, int); 146124169Ssimokawavoid fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); 147113584Ssimokawa#if FWOHCI_TASKQUEUE 148113584Ssimokawastatic void fwohci_complete(void *, int); 149113584Ssimokawa#endif 150103285Sikob 151103285Sikob/* 152103285Sikob * memory allocated for DMA programs 153103285Sikob */ 154103285Sikob#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 155103285Sikob 156103285Sikob#define NDB FWMAXQUEUE 157103285Sikob 158103285Sikob#define OHCI_VERSION 0x00 159112523Ssimokawa#define OHCI_ATRETRY 0x08 160103285Sikob#define OHCI_CROMHDR 0x18 161103285Sikob#define OHCI_BUS_OPT 0x20 162103285Sikob#define OHCI_BUSIRMC (1 << 31) 163103285Sikob#define OHCI_BUSCMC (1 << 30) 164103285Sikob#define OHCI_BUSISC (1 << 29) 165103285Sikob#define OHCI_BUSBMC (1 << 28) 166103285Sikob#define OHCI_BUSPMC (1 << 27) 167103285Sikob#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 168103285Sikob OHCI_BUSBMC | OHCI_BUSPMC 169103285Sikob 170103285Sikob#define OHCI_EUID_HI 0x24 171103285Sikob#define OHCI_EUID_LO 0x28 172103285Sikob 173103285Sikob#define OHCI_CROMPTR 0x34 174103285Sikob#define OHCI_HCCCTL 0x50 175103285Sikob#define OHCI_HCCCTLCLR 0x54 176103285Sikob#define OHCI_AREQHI 0x100 177103285Sikob#define OHCI_AREQHICLR 0x104 178103285Sikob#define OHCI_AREQLO 0x108 179103285Sikob#define OHCI_AREQLOCLR 0x10c 180103285Sikob#define OHCI_PREQHI 0x110 181103285Sikob#define OHCI_PREQHICLR 0x114 182103285Sikob#define OHCI_PREQLO 0x118 183103285Sikob#define OHCI_PREQLOCLR 0x11c 184103285Sikob#define OHCI_PREQUPPER 0x120 185103285Sikob 186103285Sikob#define OHCI_SID_BUF 0x64 187103285Sikob#define OHCI_SID_CNT 0x68 188113584Ssimokawa#define OHCI_SID_ERR (1 << 31) 189103285Sikob#define OHCI_SID_CNT_MASK 0xffc 190103285Sikob 191103285Sikob#define OHCI_IT_STAT 0x90 192103285Sikob#define OHCI_IT_STATCLR 0x94 193103285Sikob#define OHCI_IT_MASK 0x98 194103285Sikob#define OHCI_IT_MASKCLR 0x9c 195103285Sikob 196103285Sikob#define OHCI_IR_STAT 0xa0 197103285Sikob#define OHCI_IR_STATCLR 0xa4 198103285Sikob#define OHCI_IR_MASK 0xa8 199103285Sikob#define OHCI_IR_MASKCLR 0xac 200103285Sikob 201103285Sikob#define OHCI_LNKCTL 0xe0 202103285Sikob#define OHCI_LNKCTLCLR 0xe4 203103285Sikob 204103285Sikob#define OHCI_PHYACCESS 0xec 205103285Sikob#define OHCI_CYCLETIMER 0xf0 206103285Sikob 207103285Sikob#define OHCI_DMACTL(off) (off) 208103285Sikob#define OHCI_DMACTLCLR(off) (off + 4) 209103285Sikob#define OHCI_DMACMD(off) (off + 0xc) 210103285Sikob#define OHCI_DMAMATCH(off) (off + 0x10) 211103285Sikob 212103285Sikob#define OHCI_ATQOFF 0x180 213103285Sikob#define OHCI_ATQCTL OHCI_ATQOFF 214103285Sikob#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 215103285Sikob#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 216103285Sikob#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 217103285Sikob 218103285Sikob#define OHCI_ATSOFF 0x1a0 219103285Sikob#define OHCI_ATSCTL OHCI_ATSOFF 220103285Sikob#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 221103285Sikob#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 222103285Sikob#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 223103285Sikob 224103285Sikob#define OHCI_ARQOFF 0x1c0 225103285Sikob#define OHCI_ARQCTL OHCI_ARQOFF 226103285Sikob#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 227103285Sikob#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 228103285Sikob#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 229103285Sikob 230103285Sikob#define OHCI_ARSOFF 0x1e0 231103285Sikob#define OHCI_ARSCTL OHCI_ARSOFF 232103285Sikob#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 233103285Sikob#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 234103285Sikob#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 235103285Sikob 236103285Sikob#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 237103285Sikob#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 238103285Sikob#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 239103285Sikob#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 240103285Sikob 241103285Sikob#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 242103285Sikob#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 243103285Sikob#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 244103285Sikob#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 245103285Sikob#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 246103285Sikob 247103285Sikobd_ioctl_t fwohci_ioctl; 248103285Sikob 249103285Sikob/* 250103285Sikob * Communication with PHY device 251103285Sikob */ 252106790Ssimokawastatic u_int32_t 253106790Ssimokawafwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 254103285Sikob{ 255103285Sikob u_int32_t fun; 256103285Sikob 257103285Sikob addr &= 0xf; 258103285Sikob data &= 0xff; 259103285Sikob 260103285Sikob fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 261103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 262103285Sikob DELAY(100); 263103285Sikob 264103285Sikob return(fwphy_rddata( sc, addr)); 265103285Sikob} 266103285Sikob 267103285Sikobstatic u_int32_t 268103285Sikobfwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 269103285Sikob{ 270103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 271103285Sikob int i; 272103285Sikob u_int32_t bm; 273103285Sikob 274103285Sikob#define OHCI_CSR_DATA 0x0c 275103285Sikob#define OHCI_CSR_COMP 0x10 276103285Sikob#define OHCI_CSR_CONT 0x14 277103285Sikob#define OHCI_BUS_MANAGER_ID 0 278103285Sikob 279103285Sikob OWRITE(sc, OHCI_CSR_DATA, node); 280103285Sikob OWRITE(sc, OHCI_CSR_COMP, 0x3f); 281103285Sikob OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 282103285Sikob for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 283109280Ssimokawa DELAY(10); 284103285Sikob bm = OREAD(sc, OHCI_CSR_DATA); 285107653Ssimokawa if((bm & 0x3f) == 0x3f) 286103285Sikob bm = node; 287107653Ssimokawa if (bootverbose) 288107653Ssimokawa device_printf(sc->fc.dev, 289107653Ssimokawa "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 290103285Sikob 291103285Sikob return(bm); 292103285Sikob} 293103285Sikob 294106790Ssimokawastatic u_int32_t 295106790Ssimokawafwphy_rddata(struct fwohci_softc *sc, u_int addr) 296103285Sikob{ 297108500Ssimokawa u_int32_t fun, stat; 298108500Ssimokawa u_int i, retry = 0; 299103285Sikob 300103285Sikob addr &= 0xf; 301108500Ssimokawa#define MAX_RETRY 100 302108500Ssimokawaagain: 303108500Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 304103285Sikob fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 305103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 306108500Ssimokawa for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 307103285Sikob fun = OREAD(sc, OHCI_PHYACCESS); 308103285Sikob if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 309103285Sikob break; 310109280Ssimokawa DELAY(100); 311103285Sikob } 312108500Ssimokawa if(i >= MAX_RETRY) { 313109280Ssimokawa if (bootverbose) 314109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(1).\n"); 315108527Ssimokawa if (++retry < MAX_RETRY) { 316109280Ssimokawa DELAY(100); 317108527Ssimokawa goto again; 318108527Ssimokawa } 319108500Ssimokawa } 320108500Ssimokawa /* Make sure that SCLK is started */ 321108500Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 322108500Ssimokawa if ((stat & OHCI_INT_REG_FAIL) != 0 || 323108500Ssimokawa ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 324109280Ssimokawa if (bootverbose) 325109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(2).\n"); 326108500Ssimokawa if (++retry < MAX_RETRY) { 327109280Ssimokawa DELAY(100); 328108500Ssimokawa goto again; 329108500Ssimokawa } 330108500Ssimokawa } 331108500Ssimokawa if (bootverbose || retry >= MAX_RETRY) 332108500Ssimokawa device_printf(sc->fc.dev, 333119118Ssimokawa "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 334108500Ssimokawa#undef MAX_RETRY 335103285Sikob return((fun >> PHYDEV_RDDATA )& 0xff); 336103285Sikob} 337103285Sikob/* Device specific ioctl. */ 338103285Sikobint 339103285Sikobfwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 340103285Sikob{ 341103285Sikob struct firewire_softc *sc; 342103285Sikob struct fwohci_softc *fc; 343103285Sikob int unit = DEV2UNIT(dev); 344103285Sikob int err = 0; 345103285Sikob struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 346103285Sikob u_int32_t *dmach = (u_int32_t *) data; 347103285Sikob 348103285Sikob sc = devclass_get_softc(firewire_devclass, unit); 349103285Sikob if(sc == NULL){ 350103285Sikob return(EINVAL); 351103285Sikob } 352103285Sikob fc = (struct fwohci_softc *)sc->fc; 353103285Sikob 354103285Sikob if (!data) 355103285Sikob return(EINVAL); 356103285Sikob 357103285Sikob switch (cmd) { 358103285Sikob case FWOHCI_WRREG: 359103285Sikob#define OHCI_MAX_REG 0x800 360103285Sikob if(reg->addr <= OHCI_MAX_REG){ 361103285Sikob OWRITE(fc, reg->addr, reg->data); 362103285Sikob reg->data = OREAD(fc, reg->addr); 363103285Sikob }else{ 364103285Sikob err = EINVAL; 365103285Sikob } 366103285Sikob break; 367103285Sikob case FWOHCI_RDREG: 368103285Sikob if(reg->addr <= OHCI_MAX_REG){ 369103285Sikob reg->data = OREAD(fc, reg->addr); 370103285Sikob }else{ 371103285Sikob err = EINVAL; 372103285Sikob } 373103285Sikob break; 374103285Sikob/* Read DMA descriptors for debug */ 375103285Sikob case DUMPDMA: 376103285Sikob if(*dmach <= OHCI_MAX_DMA_CH ){ 377103285Sikob dump_dma(fc, *dmach); 378103285Sikob dump_db(fc, *dmach); 379103285Sikob }else{ 380103285Sikob err = EINVAL; 381103285Sikob } 382103285Sikob break; 383119118Ssimokawa/* Read/Write Phy registers */ 384119118Ssimokawa#define OHCI_MAX_PHY_REG 0xf 385119118Ssimokawa case FWOHCI_RDPHYREG: 386119118Ssimokawa if (reg->addr <= OHCI_MAX_PHY_REG) 387119118Ssimokawa reg->data = fwphy_rddata(fc, reg->addr); 388119118Ssimokawa else 389119118Ssimokawa err = EINVAL; 390119118Ssimokawa break; 391119118Ssimokawa case FWOHCI_WRPHYREG: 392119118Ssimokawa if (reg->addr <= OHCI_MAX_PHY_REG) 393119118Ssimokawa reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 394119118Ssimokawa else 395119118Ssimokawa err = EINVAL; 396119118Ssimokawa break; 397103285Sikob default: 398119118Ssimokawa err = EINVAL; 399103285Sikob break; 400103285Sikob } 401103285Sikob return err; 402103285Sikob} 403106790Ssimokawa 404108530Ssimokawastatic int 405108530Ssimokawafwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 406103285Sikob{ 407108530Ssimokawa u_int32_t reg, reg2; 408108530Ssimokawa int e1394a = 1; 409108530Ssimokawa/* 410108530Ssimokawa * probe PHY parameters 411108530Ssimokawa * 0. to prove PHY version, whether compliance of 1394a. 412108530Ssimokawa * 1. to probe maximum speed supported by the PHY and 413108530Ssimokawa * number of port supported by core-logic. 414108530Ssimokawa * It is not actually available port on your PC . 415108530Ssimokawa */ 416108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 417108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 418108530Ssimokawa 419108530Ssimokawa if((reg >> 5) != 7 ){ 420108530Ssimokawa sc->fc.mode &= ~FWPHYASYST; 421108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 422108530Ssimokawa sc->fc.speed = reg & FW_PHY_SPD >> 6; 423108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 424108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 425108530Ssimokawa sc->fc.speed, MAX_SPEED); 426108530Ssimokawa sc->fc.speed = MAX_SPEED; 427108530Ssimokawa } 428108530Ssimokawa device_printf(dev, 429108701Ssimokawa "Phy 1394 only %s, %d ports.\n", 430108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 431108530Ssimokawa }else{ 432108530Ssimokawa reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 433108530Ssimokawa sc->fc.mode |= FWPHYASYST; 434108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 435108530Ssimokawa sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 436108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 437108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 438108530Ssimokawa sc->fc.speed, MAX_SPEED); 439108530Ssimokawa sc->fc.speed = MAX_SPEED; 440108530Ssimokawa } 441108530Ssimokawa device_printf(dev, 442108701Ssimokawa "Phy 1394a available %s, %d ports.\n", 443108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 444108530Ssimokawa 445108530Ssimokawa /* check programPhyEnable */ 446108530Ssimokawa reg2 = fwphy_rddata(sc, 5); 447108530Ssimokawa#if 0 448108530Ssimokawa if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 449108530Ssimokawa#else /* XXX force to enable 1394a */ 450108530Ssimokawa if (e1394a) { 451108530Ssimokawa#endif 452108530Ssimokawa if (bootverbose) 453108530Ssimokawa device_printf(dev, 454108530Ssimokawa "Enable 1394a Enhancements\n"); 455108530Ssimokawa /* enable EAA EMC */ 456108530Ssimokawa reg2 |= 0x03; 457108530Ssimokawa /* set aPhyEnhanceEnable */ 458108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 459108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 460108530Ssimokawa } else { 461108530Ssimokawa /* for safe */ 462108530Ssimokawa reg2 &= ~0x83; 463108530Ssimokawa } 464108530Ssimokawa reg2 = fwphy_wrdata(sc, 5, reg2); 465108530Ssimokawa } 466108530Ssimokawa 467108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 468108530Ssimokawa if((reg >> 5) == 7 ){ 469108530Ssimokawa reg = fwphy_rddata(sc, 4); 470108530Ssimokawa reg |= 1 << 6; 471108530Ssimokawa fwphy_wrdata(sc, 4, reg); 472108530Ssimokawa reg = fwphy_rddata(sc, 4); 473108530Ssimokawa } 474108530Ssimokawa return 0; 475108530Ssimokawa} 476108530Ssimokawa 477108530Ssimokawa 478108530Ssimokawavoid 479108530Ssimokawafwohci_reset(struct fwohci_softc *sc, device_t dev) 480108530Ssimokawa{ 481108701Ssimokawa int i, max_rec, speed; 482103285Sikob u_int32_t reg, reg2; 483103285Sikob struct fwohcidb_tr *db_tr; 484103285Sikob 485108701Ssimokawa /* Disable interrupt */ 486108530Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 487108530Ssimokawa 488108701Ssimokawa /* Now stopping all DMA channel */ 489108530Ssimokawa OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 490108530Ssimokawa OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 491108530Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 492108530Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 493108530Ssimokawa 494108530Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, ~0); 495108530Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 496108530Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 497108530Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 498108530Ssimokawa } 499108530Ssimokawa 500108701Ssimokawa /* FLUSH FIFO and reset Transmitter/Reciever */ 501108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 502108530Ssimokawa if (bootverbose) 503108530Ssimokawa device_printf(dev, "resetting OHCI..."); 504108530Ssimokawa i = 0; 505108530Ssimokawa while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 506108530Ssimokawa if (i++ > 100) break; 507108530Ssimokawa DELAY(1000); 508108530Ssimokawa } 509108530Ssimokawa if (bootverbose) 510108530Ssimokawa printf("done (loop=%d)\n", i); 511108530Ssimokawa 512108701Ssimokawa /* Probe phy */ 513108701Ssimokawa fwohci_probe_phy(sc, dev); 514108701Ssimokawa 515108701Ssimokawa /* Probe link */ 516108530Ssimokawa reg = OREAD(sc, OHCI_BUS_OPT); 517108530Ssimokawa reg2 = reg | OHCI_BUSFNC; 518108701Ssimokawa max_rec = (reg & 0x0000f000) >> 12; 519108701Ssimokawa speed = (reg & 0x00000007); 520108701Ssimokawa device_printf(dev, "Link %s, max_rec %d bytes.\n", 521108701Ssimokawa linkspeed[speed], MAXREC(max_rec)); 522108701Ssimokawa /* XXX fix max_rec */ 523108701Ssimokawa sc->fc.maxrec = sc->fc.speed + 8; 524108701Ssimokawa if (max_rec != sc->fc.maxrec) { 525108701Ssimokawa reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 526108701Ssimokawa device_printf(dev, "max_rec %d -> %d\n", 527108701Ssimokawa MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 528108701Ssimokawa } 529108530Ssimokawa if (bootverbose) 530108530Ssimokawa device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 531108530Ssimokawa OWRITE(sc, OHCI_BUS_OPT, reg2); 532108530Ssimokawa 533108701Ssimokawa /* Initialize registers */ 534108530Ssimokawa OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 535113584Ssimokawa OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 536108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 537108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 538113584Ssimokawa OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 539108530Ssimokawa OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 540108701Ssimokawa fw_busreset(&sc->fc); 541108530Ssimokawa 542108701Ssimokawa /* Enable link */ 543108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 544108642Ssimokawa 545108701Ssimokawa /* Force to start async RX DMA */ 546108642Ssimokawa sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 547108642Ssimokawa sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 548108530Ssimokawa fwohci_rx_enable(sc, &sc->arrq); 549108530Ssimokawa fwohci_rx_enable(sc, &sc->arrs); 550108530Ssimokawa 551108701Ssimokawa /* Initialize async TX */ 552108701Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 553108701Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 554116978Ssimokawa 555108701Ssimokawa /* AT Retries */ 556108701Ssimokawa OWRITE(sc, FWOHCI_RETRY, 557108701Ssimokawa /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 558108701Ssimokawa (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 559116978Ssimokawa 560116978Ssimokawa sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 561116978Ssimokawa sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 562116978Ssimokawa sc->atrq.bottom = sc->atrq.top; 563116978Ssimokawa sc->atrs.bottom = sc->atrs.top; 564116978Ssimokawa 565108530Ssimokawa for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 566108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 567108530Ssimokawa db_tr->xfer = NULL; 568108530Ssimokawa } 569108530Ssimokawa for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 570108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 571108530Ssimokawa db_tr->xfer = NULL; 572108530Ssimokawa } 573108530Ssimokawa 574108701Ssimokawa 575108701Ssimokawa /* Enable interrupt */ 576108530Ssimokawa OWRITE(sc, FWOHCI_INTMASK, 577108530Ssimokawa OHCI_INT_ERR | OHCI_INT_PHY_SID 578108530Ssimokawa | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 579108530Ssimokawa | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 580108530Ssimokawa | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 581108530Ssimokawa fwohci_set_intr(&sc->fc, 1); 582108530Ssimokawa 583108530Ssimokawa} 584108530Ssimokawa 585108530Ssimokawaint 586108530Ssimokawafwohci_init(struct fwohci_softc *sc, device_t dev) 587108530Ssimokawa{ 588121781Ssimokawa int i, mver; 589108530Ssimokawa u_int32_t reg; 590109814Ssimokawa u_int8_t ui[8]; 591108530Ssimokawa 592113584Ssimokawa#if FWOHCI_TASKQUEUE 593113584Ssimokawa TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 594113584Ssimokawa#endif 595113584Ssimokawa 596121781Ssimokawa/* OHCI version */ 597103285Sikob reg = OREAD(sc, OHCI_VERSION); 598121781Ssimokawa mver = (reg >> 16) & 0xff; 599103285Sikob device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 600121781Ssimokawa mver, reg & 0xff, (reg>>24) & 1); 601121781Ssimokawa if (mver < 1 || mver > 9) { 602118416Ssimokawa device_printf(dev, "invalid OHCI version\n"); 603118416Ssimokawa return (ENXIO); 604118416Ssimokawa } 605118416Ssimokawa 606110045Ssimokawa/* Available Isochrounous DMA channel probe */ 607110045Ssimokawa OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 608110045Ssimokawa OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 609110045Ssimokawa reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 610110045Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 611110045Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 612110045Ssimokawa for (i = 0; i < 0x20; i++) 613110045Ssimokawa if ((reg & (1 << i)) == 0) 614110045Ssimokawa break; 615103285Sikob sc->fc.nisodma = i; 616103285Sikob device_printf(dev, "No. of Isochronous channel is %d.\n", i); 617118820Ssimokawa if (i == 0) 618118820Ssimokawa return (ENXIO); 619103285Sikob 620103285Sikob sc->fc.arq = &sc->arrq.xferq; 621103285Sikob sc->fc.ars = &sc->arrs.xferq; 622103285Sikob sc->fc.atq = &sc->atrq.xferq; 623103285Sikob sc->fc.ats = &sc->atrs.xferq; 624103285Sikob 625113584Ssimokawa sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 626113584Ssimokawa sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 627113584Ssimokawa sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 628113584Ssimokawa sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 629113584Ssimokawa 630103285Sikob sc->arrq.xferq.start = NULL; 631103285Sikob sc->arrs.xferq.start = NULL; 632103285Sikob sc->atrq.xferq.start = fwohci_start_atq; 633103285Sikob sc->atrs.xferq.start = fwohci_start_ats; 634103285Sikob 635113584Ssimokawa sc->arrq.xferq.buf = NULL; 636113584Ssimokawa sc->arrs.xferq.buf = NULL; 637113584Ssimokawa sc->atrq.xferq.buf = NULL; 638113584Ssimokawa sc->atrs.xferq.buf = NULL; 639103285Sikob 640118293Ssimokawa sc->arrq.xferq.dmach = -1; 641118293Ssimokawa sc->arrs.xferq.dmach = -1; 642118293Ssimokawa sc->atrq.xferq.dmach = -1; 643118293Ssimokawa sc->atrs.xferq.dmach = -1; 644118293Ssimokawa 645103285Sikob sc->arrq.ndesc = 1; 646103285Sikob sc->arrs.ndesc = 1; 647110593Ssimokawa sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 648110593Ssimokawa sc->atrs.ndesc = 2; 649103285Sikob 650103285Sikob sc->arrq.ndb = NDB; 651103285Sikob sc->arrs.ndb = NDB / 2; 652103285Sikob sc->atrq.ndb = NDB; 653103285Sikob sc->atrs.ndb = NDB / 2; 654103285Sikob 655103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 656103285Sikob sc->fc.it[i] = &sc->it[i].xferq; 657103285Sikob sc->fc.ir[i] = &sc->ir[i].xferq; 658118293Ssimokawa sc->it[i].xferq.dmach = i; 659118293Ssimokawa sc->ir[i].xferq.dmach = i; 660103285Sikob sc->it[i].ndb = 0; 661103285Sikob sc->ir[i].ndb = 0; 662103285Sikob } 663103285Sikob 664103285Sikob sc->fc.tcode = tinfo; 665113584Ssimokawa sc->fc.dev = dev; 666103285Sikob 667113584Ssimokawa sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 668113584Ssimokawa &sc->crom_dma, BUS_DMA_WAITOK); 669113584Ssimokawa if(sc->fc.config_rom == NULL){ 670113584Ssimokawa device_printf(dev, "config_rom alloc failed."); 671103285Sikob return ENOMEM; 672103285Sikob } 673103285Sikob 674116376Ssimokawa#if 0 675116376Ssimokawa bzero(&sc->fc.config_rom[0], CROMSIZE); 676103285Sikob sc->fc.config_rom[1] = 0x31333934; 677103285Sikob sc->fc.config_rom[2] = 0xf000a002; 678103285Sikob sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 679103285Sikob sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 680103285Sikob sc->fc.config_rom[5] = 0; 681103285Sikob sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 682103285Sikob 683103285Sikob sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 684113584Ssimokawa#endif 685103285Sikob 686103285Sikob 687103285Sikob/* SID recieve buffer must allign 2^11 */ 688103285Sikob#define OHCI_SIDSIZE (1 << 11) 689113584Ssimokawa sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 690113584Ssimokawa &sc->sid_dma, BUS_DMA_WAITOK); 691113584Ssimokawa if (sc->sid_buf == NULL) { 692113584Ssimokawa device_printf(dev, "sid_buf alloc failed."); 693108527Ssimokawa return ENOMEM; 694108527Ssimokawa } 695113584Ssimokawa 696113584Ssimokawa fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t), 697113584Ssimokawa &sc->dummy_dma, BUS_DMA_WAITOK); 698113584Ssimokawa 699113584Ssimokawa if (sc->dummy_dma.v_addr == NULL) { 700113584Ssimokawa device_printf(dev, "dummy_dma alloc failed."); 701109736Ssimokawa return ENOMEM; 702109736Ssimokawa } 703113584Ssimokawa 704113584Ssimokawa fwohci_db_init(sc, &sc->arrq); 705108527Ssimokawa if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 706108527Ssimokawa return ENOMEM; 707108527Ssimokawa 708113584Ssimokawa fwohci_db_init(sc, &sc->arrs); 709108527Ssimokawa if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 710108527Ssimokawa return ENOMEM; 711103285Sikob 712113584Ssimokawa fwohci_db_init(sc, &sc->atrq); 713108527Ssimokawa if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 714108527Ssimokawa return ENOMEM; 715108527Ssimokawa 716113584Ssimokawa fwohci_db_init(sc, &sc->atrs); 717108527Ssimokawa if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 718108527Ssimokawa return ENOMEM; 719103285Sikob 720109814Ssimokawa sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 721109814Ssimokawa sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 722109814Ssimokawa for( i = 0 ; i < 8 ; i ++) 723109814Ssimokawa ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 724103285Sikob device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 725109814Ssimokawa ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 726109814Ssimokawa 727103285Sikob sc->fc.ioctl = fwohci_ioctl; 728103285Sikob sc->fc.cyctimer = fwohci_cyctimer; 729103285Sikob sc->fc.set_bmr = fwohci_set_bus_manager; 730103285Sikob sc->fc.ibr = fwohci_ibr; 731103285Sikob sc->fc.irx_enable = fwohci_irx_enable; 732103285Sikob sc->fc.irx_disable = fwohci_irx_disable; 733103285Sikob 734103285Sikob sc->fc.itx_enable = fwohci_itxbuf_enable; 735103285Sikob sc->fc.itx_disable = fwohci_itx_disable; 736113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 737103285Sikob sc->fc.irx_post = fwohci_irx_post; 738113584Ssimokawa#else 739113584Ssimokawa sc->fc.irx_post = NULL; 740113584Ssimokawa#endif 741103285Sikob sc->fc.itx_post = NULL; 742103285Sikob sc->fc.timeout = fwohci_timeout; 743103285Sikob sc->fc.poll = fwohci_poll; 744103285Sikob sc->fc.set_intr = fwohci_set_intr; 745106790Ssimokawa 746113584Ssimokawa sc->intmask = sc->irstat = sc->itstat = 0; 747113584Ssimokawa 748108530Ssimokawa fw_init(&sc->fc); 749108530Ssimokawa fwohci_reset(sc, dev); 750103285Sikob 751108530Ssimokawa return 0; 752103285Sikob} 753106790Ssimokawa 754106790Ssimokawavoid 755106790Ssimokawafwohci_timeout(void *arg) 756103285Sikob{ 757103285Sikob struct fwohci_softc *sc; 758103285Sikob 759103285Sikob sc = (struct fwohci_softc *)arg; 760103285Sikob} 761106790Ssimokawa 762106790Ssimokawau_int32_t 763106790Ssimokawafwohci_cyctimer(struct firewire_comm *fc) 764103285Sikob{ 765103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 766103285Sikob return(OREAD(sc, OHCI_CYCLETIMER)); 767103285Sikob} 768103285Sikob 769108527Ssimokawaint 770108527Ssimokawafwohci_detach(struct fwohci_softc *sc, device_t dev) 771108527Ssimokawa{ 772108527Ssimokawa int i; 773108527Ssimokawa 774113584Ssimokawa if (sc->sid_buf != NULL) 775113584Ssimokawa fwdma_free(&sc->fc, &sc->sid_dma); 776113584Ssimokawa if (sc->fc.config_rom != NULL) 777113584Ssimokawa fwdma_free(&sc->fc, &sc->crom_dma); 778108527Ssimokawa 779108527Ssimokawa fwohci_db_free(&sc->arrq); 780108527Ssimokawa fwohci_db_free(&sc->arrs); 781108527Ssimokawa 782108527Ssimokawa fwohci_db_free(&sc->atrq); 783108527Ssimokawa fwohci_db_free(&sc->atrs); 784108527Ssimokawa 785108527Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 786108527Ssimokawa fwohci_db_free(&sc->it[i]); 787108527Ssimokawa fwohci_db_free(&sc->ir[i]); 788108527Ssimokawa } 789108527Ssimokawa 790108527Ssimokawa return 0; 791108527Ssimokawa} 792108527Ssimokawa 793108655Ssimokawa#define LAST_DB(dbtr, db) do { \ 794108655Ssimokawa struct fwohcidb_tr *_dbtr = (dbtr); \ 795108655Ssimokawa int _cnt = _dbtr->dbcnt; \ 796108655Ssimokawa db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 797108655Ssimokawa} while (0) 798108655Ssimokawa 799106790Ssimokawastatic void 800113584Ssimokawafwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 801113584Ssimokawa{ 802113584Ssimokawa struct fwohcidb_tr *db_tr; 803120660Ssimokawa struct fwohcidb *db; 804113584Ssimokawa bus_dma_segment_t *s; 805113584Ssimokawa int i; 806113584Ssimokawa 807113584Ssimokawa db_tr = (struct fwohcidb_tr *)arg; 808113584Ssimokawa db = &db_tr->db[db_tr->dbcnt]; 809113584Ssimokawa if (error) { 810113584Ssimokawa if (firewire_debug || error != EFBIG) 811113584Ssimokawa printf("fwohci_execute_db: error=%d\n", error); 812113584Ssimokawa return; 813113584Ssimokawa } 814113584Ssimokawa for (i = 0; i < nseg; i++) { 815113584Ssimokawa s = &segs[i]; 816113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 817113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 818113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 0); 819113584Ssimokawa db++; 820113584Ssimokawa db_tr->dbcnt++; 821113584Ssimokawa } 822113584Ssimokawa} 823113584Ssimokawa 824113584Ssimokawastatic void 825113584Ssimokawafwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 826113584Ssimokawa bus_size_t size, int error) 827113584Ssimokawa{ 828113584Ssimokawa fwohci_execute_db(arg, segs, nseg, error); 829113584Ssimokawa} 830113584Ssimokawa 831113584Ssimokawastatic void 832106790Ssimokawafwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 833103285Sikob{ 834103285Sikob int i, s; 835120660Ssimokawa int tcode, hdr_len, pl_off; 836103285Sikob int fsegment = -1; 837103285Sikob u_int32_t off; 838103285Sikob struct fw_xfer *xfer; 839103285Sikob struct fw_pkt *fp; 840120660Ssimokawa struct fwohci_txpkthdr *ohcifp; 841103285Sikob struct fwohcidb_tr *db_tr; 842120660Ssimokawa struct fwohcidb *db; 843120660Ssimokawa u_int32_t *ld; 844103285Sikob struct tcode_info *info; 845108655Ssimokawa static int maxdesc=0; 846103285Sikob 847103285Sikob if(&sc->atrq == dbch){ 848103285Sikob off = OHCI_ATQOFF; 849103285Sikob }else if(&sc->atrs == dbch){ 850103285Sikob off = OHCI_ATSOFF; 851103285Sikob }else{ 852103285Sikob return; 853103285Sikob } 854103285Sikob 855103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) 856103285Sikob return; 857103285Sikob 858103285Sikob s = splfw(); 859103285Sikob db_tr = dbch->top; 860103285Sikobtxloop: 861103285Sikob xfer = STAILQ_FIRST(&dbch->xferq.q); 862103285Sikob if(xfer == NULL){ 863103285Sikob goto kick; 864103285Sikob } 865103285Sikob if(dbch->xferq.queued == 0 ){ 866103285Sikob device_printf(sc->fc.dev, "TX queue empty\n"); 867103285Sikob } 868103285Sikob STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 869103285Sikob db_tr->xfer = xfer; 870103285Sikob xfer->state = FWXF_START; 871103285Sikob 872120660Ssimokawa fp = &xfer->send.hdr; 873103285Sikob tcode = fp->mode.common.tcode; 874103285Sikob 875120660Ssimokawa ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 876103285Sikob info = &tinfo[tcode]; 877113584Ssimokawa hdr_len = pl_off = info->hdr_len; 878119155Ssimokawa 879119155Ssimokawa ld = &ohcifp->mode.ld[0]; 880119155Ssimokawa ld[0] = ld[1] = ld[2] = ld[3] = 0; 881119155Ssimokawa for( i = 0 ; i < pl_off ; i+= 4) 882119155Ssimokawa ld[i/4] = fp->mode.ld[i/4]; 883119155Ssimokawa 884120660Ssimokawa ohcifp->mode.common.spd = xfer->send.spd & 0x7; 885103285Sikob if (tcode == FWTCODE_STREAM ){ 886103285Sikob hdr_len = 8; 887113584Ssimokawa ohcifp->mode.stream.len = fp->mode.stream.len; 888103285Sikob } else if (tcode == FWTCODE_PHY) { 889103285Sikob hdr_len = 12; 890119155Ssimokawa ld[1] = fp->mode.ld[1]; 891119155Ssimokawa ld[2] = fp->mode.ld[2]; 892103285Sikob ohcifp->mode.common.spd = 0; 893103285Sikob ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 894103285Sikob } else { 895113584Ssimokawa ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 896103285Sikob ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 897103285Sikob ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 898103285Sikob } 899103285Sikob db = &db_tr->db[0]; 900113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.cmd, 901113584Ssimokawa OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 902119155Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 903113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 0); 904103285Sikob/* Specify bound timer of asy. responce */ 905103285Sikob if(&sc->atrs == dbch){ 906113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 907113584Ssimokawa (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 908103285Sikob } 909113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 910113584Ssimokawa if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 911113584Ssimokawa hdr_len = 12; 912113584Ssimokawa for (i = 0; i < hdr_len/4; i ++) 913119155Ssimokawa FWOHCI_DMA_WRITE(ld[i], ld[i]); 914113584Ssimokawa#endif 915103285Sikob 916111942Ssimokawaagain: 917103285Sikob db_tr->dbcnt = 2; 918103285Sikob db = &db_tr->db[db_tr->dbcnt]; 919120660Ssimokawa if (xfer->send.pay_len > 0) { 920113584Ssimokawa int err; 921113584Ssimokawa /* handle payload */ 922103285Sikob if (xfer->mbuf == NULL) { 923113584Ssimokawa err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 924120660Ssimokawa &xfer->send.payload[0], xfer->send.pay_len, 925113584Ssimokawa fwohci_execute_db, db_tr, 926113584Ssimokawa /*flags*/0); 927103285Sikob } else { 928111942Ssimokawa /* XXX we can handle only 6 (=8-2) mbuf chains */ 929113584Ssimokawa err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 930113584Ssimokawa xfer->mbuf, 931113584Ssimokawa fwohci_execute_db2, db_tr, 932113584Ssimokawa /* flags */0); 933113584Ssimokawa if (err == EFBIG) { 934113584Ssimokawa struct mbuf *m0; 935113584Ssimokawa 936113584Ssimokawa if (firewire_debug) 937113584Ssimokawa device_printf(sc->fc.dev, "EFBIG.\n"); 938113584Ssimokawa m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 939113584Ssimokawa if (m0 != NULL) { 940111942Ssimokawa m_copydata(xfer->mbuf, 0, 941111942Ssimokawa xfer->mbuf->m_pkthdr.len, 942113584Ssimokawa mtod(m0, caddr_t)); 943113584Ssimokawa m0->m_len = m0->m_pkthdr.len = 944111942Ssimokawa xfer->mbuf->m_pkthdr.len; 945111942Ssimokawa m_freem(xfer->mbuf); 946113584Ssimokawa xfer->mbuf = m0; 947111942Ssimokawa goto again; 948111942Ssimokawa } 949111942Ssimokawa device_printf(sc->fc.dev, "m_getcl failed.\n"); 950111942Ssimokawa } 951103285Sikob } 952113584Ssimokawa if (err) 953113584Ssimokawa printf("dmamap_load: err=%d\n", err); 954113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 955113584Ssimokawa BUS_DMASYNC_PREWRITE); 956113584Ssimokawa#if 0 /* OHCI_OUTPUT_MODE == 0 */ 957113584Ssimokawa for (i = 2; i < db_tr->dbcnt; i++) 958113584Ssimokawa FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 959113584Ssimokawa OHCI_OUTPUT_MORE); 960113584Ssimokawa#endif 961103285Sikob } 962108655Ssimokawa if (maxdesc < db_tr->dbcnt) { 963108655Ssimokawa maxdesc = db_tr->dbcnt; 964108655Ssimokawa if (bootverbose) 965108655Ssimokawa device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 966108655Ssimokawa } 967103285Sikob /* last db */ 968103285Sikob LAST_DB(db_tr, db); 969113584Ssimokawa FWOHCI_DMA_SET(db->db.desc.cmd, 970113584Ssimokawa OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 971113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.depend, 972113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr); 973103285Sikob 974103285Sikob if(fsegment == -1 ) 975103285Sikob fsegment = db_tr->dbcnt; 976103285Sikob if (dbch->pdb_tr != NULL) { 977103285Sikob LAST_DB(dbch->pdb_tr, db); 978113584Ssimokawa FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 979103285Sikob } 980103285Sikob dbch->pdb_tr = db_tr; 981103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 982103285Sikob if(db_tr != dbch->bottom){ 983103285Sikob goto txloop; 984103285Sikob } else { 985107653Ssimokawa device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 986103285Sikob dbch->flags |= FWOHCI_DBCH_FULL; 987103285Sikob } 988103285Sikobkick: 989103285Sikob /* kick asy q */ 990113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 991113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 992103285Sikob 993103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) { 994103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 995103285Sikob } else { 996107653Ssimokawa if (bootverbose) 997107653Ssimokawa device_printf(sc->fc.dev, "start AT DMA status=%x\n", 998103285Sikob OREAD(sc, OHCI_DMACTL(off))); 999113584Ssimokawa OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1000103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1001103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1002103285Sikob } 1003106790Ssimokawa 1004103285Sikob dbch->top = db_tr; 1005103285Sikob splx(s); 1006103285Sikob return; 1007103285Sikob} 1008106790Ssimokawa 1009106790Ssimokawastatic void 1010106790Ssimokawafwohci_start_atq(struct firewire_comm *fc) 1011103285Sikob{ 1012103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1013103285Sikob fwohci_start( sc, &(sc->atrq)); 1014103285Sikob return; 1015103285Sikob} 1016106790Ssimokawa 1017106790Ssimokawastatic void 1018106790Ssimokawafwohci_start_ats(struct firewire_comm *fc) 1019103285Sikob{ 1020103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1021103285Sikob fwohci_start( sc, &(sc->atrs)); 1022103285Sikob return; 1023103285Sikob} 1024106790Ssimokawa 1025106790Ssimokawavoid 1026106790Ssimokawafwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1027103285Sikob{ 1028113584Ssimokawa int s, ch, err = 0; 1029103285Sikob struct fwohcidb_tr *tr; 1030120660Ssimokawa struct fwohcidb *db; 1031103285Sikob struct fw_xfer *xfer; 1032103285Sikob u_int32_t off; 1033113584Ssimokawa u_int stat, status; 1034103285Sikob int packets; 1035103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1036113584Ssimokawa 1037103285Sikob if(&sc->atrq == dbch){ 1038103285Sikob off = OHCI_ATQOFF; 1039113584Ssimokawa ch = ATRQ_CH; 1040103285Sikob }else if(&sc->atrs == dbch){ 1041103285Sikob off = OHCI_ATSOFF; 1042113584Ssimokawa ch = ATRS_CH; 1043103285Sikob }else{ 1044103285Sikob return; 1045103285Sikob } 1046103285Sikob s = splfw(); 1047103285Sikob tr = dbch->bottom; 1048103285Sikob packets = 0; 1049113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 1050113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 1051103285Sikob while(dbch->xferq.queued > 0){ 1052103285Sikob LAST_DB(tr, db); 1053113584Ssimokawa status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1054113584Ssimokawa if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1055103285Sikob if (fc->status != FWBUSRESET) 1056103285Sikob /* maybe out of order?? */ 1057103285Sikob goto out; 1058103285Sikob } 1059113584Ssimokawa bus_dmamap_sync(dbch->dmat, tr->dma_map, 1060113584Ssimokawa BUS_DMASYNC_POSTWRITE); 1061113584Ssimokawa bus_dmamap_unload(dbch->dmat, tr->dma_map); 1062119155Ssimokawa#if 1 1063119155Ssimokawa if (firewire_debug) 1064119155Ssimokawa dump_db(sc, ch); 1065103285Sikob#endif 1066113584Ssimokawa if(status & OHCI_CNTL_DMA_DEAD) { 1067113584Ssimokawa /* Stop DMA */ 1068103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1069103285Sikob device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1070103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1071103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1072103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1073103285Sikob } 1074113584Ssimokawa stat = status & FWOHCIEV_MASK; 1075103285Sikob switch(stat){ 1076110577Ssimokawa case FWOHCIEV_ACKPEND: 1077103285Sikob case FWOHCIEV_ACKCOMPL: 1078103285Sikob err = 0; 1079103285Sikob break; 1080103285Sikob case FWOHCIEV_ACKBSA: 1081103285Sikob case FWOHCIEV_ACKBSB: 1082110577Ssimokawa case FWOHCIEV_ACKBSX: 1083103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1084103285Sikob err = EBUSY; 1085103285Sikob break; 1086103285Sikob case FWOHCIEV_FLUSHED: 1087103285Sikob case FWOHCIEV_ACKTARD: 1088103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1089103285Sikob err = EAGAIN; 1090103285Sikob break; 1091103285Sikob case FWOHCIEV_MISSACK: 1092103285Sikob case FWOHCIEV_UNDRRUN: 1093103285Sikob case FWOHCIEV_OVRRUN: 1094103285Sikob case FWOHCIEV_DESCERR: 1095103285Sikob case FWOHCIEV_DTRDERR: 1096103285Sikob case FWOHCIEV_TIMEOUT: 1097103285Sikob case FWOHCIEV_TCODERR: 1098103285Sikob case FWOHCIEV_UNKNOWN: 1099103285Sikob case FWOHCIEV_ACKDERR: 1100103285Sikob case FWOHCIEV_ACKTERR: 1101103285Sikob default: 1102103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", 1103103285Sikob stat, fwohcicode[stat]); 1104103285Sikob err = EINVAL; 1105103285Sikob break; 1106103285Sikob } 1107110577Ssimokawa if (tr->xfer != NULL) { 1108103285Sikob xfer = tr->xfer; 1109113584Ssimokawa if (xfer->state == FWXF_RCVD) { 1110119289Ssimokawa#if 0 1111113584Ssimokawa if (firewire_debug) 1112113584Ssimokawa printf("already rcvd\n"); 1113119289Ssimokawa#endif 1114113584Ssimokawa fw_xfer_done(xfer); 1115113584Ssimokawa } else { 1116114218Ssimokawa xfer->state = FWXF_SENT; 1117114218Ssimokawa if (err == EBUSY && fc->status != FWBUSRESET) { 1118114218Ssimokawa xfer->state = FWXF_BUSY; 1119114218Ssimokawa xfer->resp = err; 1120114218Ssimokawa if (xfer->retry_req != NULL) 1121114218Ssimokawa xfer->retry_req(xfer); 1122114224Ssimokawa else { 1123120660Ssimokawa xfer->recv.pay_len = 0; 1124114218Ssimokawa fw_xfer_done(xfer); 1125114224Ssimokawa } 1126114218Ssimokawa } else if (stat != FWOHCIEV_ACKPEND) { 1127114218Ssimokawa if (stat != FWOHCIEV_ACKCOMPL) 1128114218Ssimokawa xfer->state = FWXF_SENTERR; 1129114218Ssimokawa xfer->resp = err; 1130120660Ssimokawa xfer->recv.pay_len = 0; 1131113584Ssimokawa fw_xfer_done(xfer); 1132114218Ssimokawa } 1133103285Sikob } 1134110577Ssimokawa /* 1135110577Ssimokawa * The watchdog timer takes care of split 1136110577Ssimokawa * transcation timeout for ACKPEND case. 1137110577Ssimokawa */ 1138113584Ssimokawa } else { 1139113584Ssimokawa printf("this shouldn't happen\n"); 1140103285Sikob } 1141110269Ssimokawa dbch->xferq.queued --; 1142103285Sikob tr->xfer = NULL; 1143103285Sikob 1144103285Sikob packets ++; 1145103285Sikob tr = STAILQ_NEXT(tr, link); 1146103285Sikob dbch->bottom = tr; 1147111956Ssimokawa if (dbch->bottom == dbch->top) { 1148111956Ssimokawa /* we reaches the end of context program */ 1149111956Ssimokawa if (firewire_debug && dbch->xferq.queued > 0) 1150111956Ssimokawa printf("queued > 0\n"); 1151111956Ssimokawa break; 1152111956Ssimokawa } 1153103285Sikob } 1154103285Sikobout: 1155103285Sikob if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1156103285Sikob printf("make free slot\n"); 1157103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1158103285Sikob fwohci_start(sc, dbch); 1159103285Sikob } 1160103285Sikob splx(s); 1161103285Sikob} 1162106790Ssimokawa 1163106790Ssimokawastatic void 1164106790Ssimokawafwohci_db_free(struct fwohci_dbch *dbch) 1165103285Sikob{ 1166103285Sikob struct fwohcidb_tr *db_tr; 1167113584Ssimokawa int idb; 1168103285Sikob 1169108527Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1170108527Ssimokawa return; 1171108527Ssimokawa 1172113584Ssimokawa for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1173103285Sikob db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1174113584Ssimokawa if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1175113584Ssimokawa db_tr->buf != NULL) { 1176113584Ssimokawa fwdma_free_size(dbch->dmat, db_tr->dma_map, 1177113584Ssimokawa db_tr->buf, dbch->xferq.psize); 1178113584Ssimokawa db_tr->buf = NULL; 1179113584Ssimokawa } else if (db_tr->dma_map != NULL) 1180113584Ssimokawa bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1181103285Sikob } 1182103285Sikob dbch->ndb = 0; 1183103285Sikob db_tr = STAILQ_FIRST(&dbch->db_trq); 1184113584Ssimokawa fwdma_free_multiseg(dbch->am); 1185110195Ssimokawa free(db_tr, M_FW); 1186103285Sikob STAILQ_INIT(&dbch->db_trq); 1187108527Ssimokawa dbch->flags &= ~FWOHCI_DBCH_INIT; 1188103285Sikob} 1189106790Ssimokawa 1190106790Ssimokawastatic void 1191113584Ssimokawafwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1192103285Sikob{ 1193103285Sikob int idb; 1194103285Sikob struct fwohcidb_tr *db_tr; 1195108642Ssimokawa 1196108642Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1197108642Ssimokawa goto out; 1198108642Ssimokawa 1199113584Ssimokawa /* create dma_tag for buffers */ 1200113584Ssimokawa#define MAX_REQCOUNT 0xffff 1201113584Ssimokawa if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1202113584Ssimokawa /*alignment*/ 1, /*boundary*/ 0, 1203113584Ssimokawa /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1204113584Ssimokawa /*highaddr*/ BUS_SPACE_MAXADDR, 1205113584Ssimokawa /*filter*/NULL, /*filterarg*/NULL, 1206113584Ssimokawa /*maxsize*/ dbch->xferq.psize, 1207113584Ssimokawa /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1208113584Ssimokawa /*maxsegsz*/ MAX_REQCOUNT, 1209117126Sscottl /*flags*/ 0, 1210117228Ssimokawa#if __FreeBSD_version >= 501102 1211117126Sscottl /*lockfunc*/busdma_lock_mutex, 1212117228Ssimokawa /*lockarg*/&Giant, 1213117228Ssimokawa#endif 1214117228Ssimokawa &dbch->dmat)) 1215113584Ssimokawa return; 1216113584Ssimokawa 1217103285Sikob /* allocate DB entries and attach one to each DMA channels */ 1218103285Sikob /* DB entry must start at 16 bytes bounary. */ 1219103285Sikob STAILQ_INIT(&dbch->db_trq); 1220103285Sikob db_tr = (struct fwohcidb_tr *) 1221103285Sikob malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1222113584Ssimokawa M_FW, M_WAITOK | M_ZERO); 1223103285Sikob if(db_tr == NULL){ 1224109379Ssimokawa printf("fwohci_db_init: malloc(1) failed\n"); 1225103285Sikob return; 1226103285Sikob } 1227109379Ssimokawa 1228113584Ssimokawa#define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1229113584Ssimokawa dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1230113584Ssimokawa DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1231113584Ssimokawa if (dbch->am == NULL) { 1232113584Ssimokawa printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1233124836Ssimokawa free(db_tr, M_FW); 1234103285Sikob return; 1235103285Sikob } 1236103285Sikob /* Attach DB to DMA ch. */ 1237103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb++){ 1238103285Sikob db_tr->dbcnt = 0; 1239113584Ssimokawa db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1240113584Ssimokawa db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1241113584Ssimokawa /* create dmamap for buffers */ 1242113584Ssimokawa /* XXX do we need 4bytes alignment tag? */ 1243113584Ssimokawa /* XXX don't alloc dma_map for AR */ 1244113584Ssimokawa if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1245113584Ssimokawa printf("bus_dmamap_create failed\n"); 1246113584Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1247113584Ssimokawa fwohci_db_free(dbch); 1248113584Ssimokawa return; 1249113584Ssimokawa } 1250103285Sikob STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1251113584Ssimokawa if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1252108530Ssimokawa if (idb % dbch->xferq.bnpacket == 0) 1253108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1254108530Ssimokawa ].start = (caddr_t)db_tr; 1255108530Ssimokawa if ((idb + 1) % dbch->xferq.bnpacket == 0) 1256108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1257108530Ssimokawa ].end = (caddr_t)db_tr; 1258103285Sikob } 1259103285Sikob db_tr++; 1260103285Sikob } 1261103285Sikob STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1262103285Sikob = STAILQ_FIRST(&dbch->db_trq); 1263108642Ssimokawaout: 1264108642Ssimokawa dbch->xferq.queued = 0; 1265108642Ssimokawa dbch->pdb_tr = NULL; 1266103285Sikob dbch->top = STAILQ_FIRST(&dbch->db_trq); 1267103285Sikob dbch->bottom = dbch->top; 1268108527Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; 1269103285Sikob} 1270106790Ssimokawa 1271106790Ssimokawastatic int 1272106790Ssimokawafwohci_itx_disable(struct firewire_comm *fc, int dmach) 1273103285Sikob{ 1274103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1275113584Ssimokawa int sleepch; 1276109890Ssimokawa 1277113584Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 1278113584Ssimokawa OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1279103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1280103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1281109890Ssimokawa /* XXX we cannot free buffers until the DMA really stops */ 1282113584Ssimokawa tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1283103285Sikob fwohci_db_free(&sc->it[dmach]); 1284103285Sikob sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1285103285Sikob return 0; 1286103285Sikob} 1287106790Ssimokawa 1288106790Ssimokawastatic int 1289106790Ssimokawafwohci_irx_disable(struct firewire_comm *fc, int dmach) 1290103285Sikob{ 1291103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1292113584Ssimokawa int sleepch; 1293103285Sikob 1294103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1295103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1296103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1297109890Ssimokawa /* XXX we cannot free buffers until the DMA really stops */ 1298113584Ssimokawa tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1299103285Sikob fwohci_db_free(&sc->ir[dmach]); 1300103285Sikob sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1301103285Sikob return 0; 1302103285Sikob} 1303106790Ssimokawa 1304113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 1305106790Ssimokawastatic void 1306106790Ssimokawafwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1307103285Sikob{ 1308113584Ssimokawa qld[0] = FWOHCI_DMA_READ(qld[0]); 1309103285Sikob return; 1310103285Sikob} 1311103285Sikob#endif 1312103285Sikob 1313106790Ssimokawastatic int 1314106790Ssimokawafwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1315103285Sikob{ 1316103285Sikob int err = 0; 1317113584Ssimokawa int idb, z, i, dmach = 0, ldesc; 1318123740Speter u_int32_t off = 0; 1319103285Sikob struct fwohcidb_tr *db_tr; 1320120660Ssimokawa struct fwohcidb *db; 1321103285Sikob 1322103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1323103285Sikob err = EINVAL; 1324103285Sikob return err; 1325103285Sikob } 1326103285Sikob z = dbch->ndesc; 1327103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1328103285Sikob if( &sc->it[dmach] == dbch){ 1329103285Sikob off = OHCI_ITOFF(dmach); 1330103285Sikob break; 1331103285Sikob } 1332103285Sikob } 1333123740Speter if(off == 0){ 1334103285Sikob err = EINVAL; 1335103285Sikob return err; 1336103285Sikob } 1337103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1338103285Sikob return err; 1339103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1340103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1341103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1342103285Sikob } 1343103285Sikob db_tr = dbch->top; 1344113584Ssimokawa for (idb = 0; idb < dbch->ndb; idb ++) { 1345113584Ssimokawa fwohci_add_tx_buf(dbch, db_tr, idb); 1346103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1347103285Sikob break; 1348103285Sikob } 1349109892Ssimokawa db = db_tr->db; 1350113584Ssimokawa ldesc = db_tr->dbcnt - 1; 1351113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1352113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr | z); 1353113584Ssimokawa db[ldesc].db.desc.depend = db[0].db.desc.depend; 1354103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1355103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1356113584Ssimokawa FWOHCI_DMA_SET( 1357113584Ssimokawa db[ldesc].db.desc.cmd, 1358113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1359109280Ssimokawa /* OHCI 1.1 and above */ 1360113584Ssimokawa FWOHCI_DMA_SET( 1361113584Ssimokawa db[0].db.desc.cmd, 1362113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1363103285Sikob } 1364103285Sikob } 1365103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1366103285Sikob } 1367113584Ssimokawa FWOHCI_DMA_CLEAR( 1368113584Ssimokawa dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1369103285Sikob return err; 1370103285Sikob} 1371106790Ssimokawa 1372106790Ssimokawastatic int 1373106790Ssimokawafwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1374103285Sikob{ 1375103285Sikob int err = 0; 1376109892Ssimokawa int idb, z, i, dmach = 0, ldesc; 1377123740Speter u_int32_t off = 0; 1378103285Sikob struct fwohcidb_tr *db_tr; 1379120660Ssimokawa struct fwohcidb *db; 1380103285Sikob 1381103285Sikob z = dbch->ndesc; 1382103285Sikob if(&sc->arrq == dbch){ 1383103285Sikob off = OHCI_ARQOFF; 1384103285Sikob }else if(&sc->arrs == dbch){ 1385103285Sikob off = OHCI_ARSOFF; 1386103285Sikob }else{ 1387103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1388103285Sikob if( &sc->ir[dmach] == dbch){ 1389103285Sikob off = OHCI_IROFF(dmach); 1390103285Sikob break; 1391103285Sikob } 1392103285Sikob } 1393103285Sikob } 1394123740Speter if(off == 0){ 1395103285Sikob err = EINVAL; 1396103285Sikob return err; 1397103285Sikob } 1398103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1399103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1400103285Sikob return err; 1401103285Sikob }else{ 1402103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1403103285Sikob err = EBUSY; 1404103285Sikob return err; 1405103285Sikob } 1406103285Sikob } 1407103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1408108642Ssimokawa dbch->top = STAILQ_FIRST(&dbch->db_trq); 1409103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1410103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1411103285Sikob } 1412103285Sikob db_tr = dbch->top; 1413113584Ssimokawa for (idb = 0; idb < dbch->ndb; idb ++) { 1414113584Ssimokawa fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1415113584Ssimokawa if (STAILQ_NEXT(db_tr, link) == NULL) 1416103285Sikob break; 1417109892Ssimokawa db = db_tr->db; 1418109892Ssimokawa ldesc = db_tr->dbcnt - 1; 1419113584Ssimokawa FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1420113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr | z); 1421103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1422103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1423113584Ssimokawa FWOHCI_DMA_SET( 1424113584Ssimokawa db[ldesc].db.desc.cmd, 1425113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1426113584Ssimokawa FWOHCI_DMA_CLEAR( 1427113584Ssimokawa db[ldesc].db.desc.depend, 1428113584Ssimokawa 0xf); 1429103285Sikob } 1430103285Sikob } 1431103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1432103285Sikob } 1433113584Ssimokawa FWOHCI_DMA_CLEAR( 1434113584Ssimokawa dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1435103285Sikob dbch->buf_offset = 0; 1436113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1437113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1438103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1439103285Sikob return err; 1440103285Sikob }else{ 1441113584Ssimokawa OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1442103285Sikob } 1443103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1444103285Sikob return err; 1445103285Sikob} 1446106790Ssimokawa 1447106790Ssimokawastatic int 1448113584Ssimokawafwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1449109890Ssimokawa{ 1450109890Ssimokawa int sec, cycle, cycle_match; 1451109890Ssimokawa 1452109890Ssimokawa cycle = cycle_now & 0x1fff; 1453109890Ssimokawa sec = cycle_now >> 13; 1454109890Ssimokawa#define CYCLE_MOD 0x10 1455113584Ssimokawa#if 1 1456109890Ssimokawa#define CYCLE_DELAY 8 /* min delay to start DMA */ 1457113584Ssimokawa#else 1458113584Ssimokawa#define CYCLE_DELAY 7000 /* min delay to start DMA */ 1459113584Ssimokawa#endif 1460109890Ssimokawa cycle = cycle + CYCLE_DELAY; 1461109890Ssimokawa if (cycle >= 8000) { 1462109890Ssimokawa sec ++; 1463109890Ssimokawa cycle -= 8000; 1464109890Ssimokawa } 1465113584Ssimokawa cycle = roundup2(cycle, CYCLE_MOD); 1466109890Ssimokawa if (cycle >= 8000) { 1467109890Ssimokawa sec ++; 1468109890Ssimokawa if (cycle == 8000) 1469109890Ssimokawa cycle = 0; 1470109890Ssimokawa else 1471109890Ssimokawa cycle = CYCLE_MOD; 1472109890Ssimokawa } 1473109890Ssimokawa cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1474109890Ssimokawa 1475109890Ssimokawa return(cycle_match); 1476109890Ssimokawa} 1477109890Ssimokawa 1478109890Ssimokawastatic int 1479106790Ssimokawafwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1480103285Sikob{ 1481103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1482103285Sikob int err = 0; 1483103285Sikob unsigned short tag, ich; 1484103285Sikob struct fwohci_dbch *dbch; 1485109890Ssimokawa int cycle_match, cycle_now, s, ldesc; 1486109356Ssimokawa u_int32_t stat; 1487109890Ssimokawa struct fw_bulkxfer *first, *chunk, *prev; 1488109890Ssimokawa struct fw_xferq *it; 1489103285Sikob 1490103285Sikob dbch = &sc->it[dmach]; 1491109890Ssimokawa it = &dbch->xferq; 1492109890Ssimokawa 1493109890Ssimokawa tag = (it->flag >> 6) & 3; 1494109890Ssimokawa ich = it->flag & 0x3f; 1495109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1496109890Ssimokawa dbch->ndb = it->bnpacket * it->bnchunk; 1497103285Sikob dbch->ndesc = 3; 1498113584Ssimokawa fwohci_db_init(sc, dbch); 1499109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1500109179Ssimokawa return ENOMEM; 1501103285Sikob err = fwohci_tx_enable(sc, dbch); 1502103285Sikob } 1503103285Sikob if(err) 1504103285Sikob return err; 1505109890Ssimokawa 1506109892Ssimokawa ldesc = dbch->ndesc - 1; 1507109890Ssimokawa s = splfw(); 1508109890Ssimokawa prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1509109890Ssimokawa while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1510120660Ssimokawa struct fwohcidb *db; 1511109890Ssimokawa 1512113584Ssimokawa fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1513113584Ssimokawa BUS_DMASYNC_PREWRITE); 1514109890Ssimokawa fwohci_txbufdb(sc, dmach, chunk); 1515109890Ssimokawa if (prev != NULL) { 1516109890Ssimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 1517113584Ssimokawa#if 0 /* XXX necessary? */ 1518113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1519113584Ssimokawa OHCI_BRANCH_ALWAYS); 1520113584Ssimokawa#endif 1521109892Ssimokawa#if 0 /* if bulkxfer->npacket changes */ 1522109890Ssimokawa db[ldesc].db.desc.depend = db[0].db.desc.depend = 1523113584Ssimokawa ((struct fwohcidb_tr *) 1524113584Ssimokawa (chunk->start))->bus_addr | dbch->ndesc; 1525109892Ssimokawa#else 1526113584Ssimokawa FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1527113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1528109892Ssimokawa#endif 1529103285Sikob } 1530109890Ssimokawa STAILQ_REMOVE_HEAD(&it->stvalid, link); 1531109890Ssimokawa STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1532109890Ssimokawa prev = chunk; 1533109403Ssimokawa } 1534113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1535113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1536109890Ssimokawa splx(s); 1537109890Ssimokawa stat = OREAD(sc, OHCI_ITCTL(dmach)); 1538113584Ssimokawa if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1539113584Ssimokawa printf("stat 0x%x\n", stat); 1540113584Ssimokawa 1541109890Ssimokawa if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1542109890Ssimokawa return 0; 1543109890Ssimokawa 1544113584Ssimokawa#if 0 1545109890Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1546113584Ssimokawa#endif 1547109403Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1548109403Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1549109403Ssimokawa OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1550113584Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1551109890Ssimokawa 1552109890Ssimokawa first = STAILQ_FIRST(&it->stdma); 1553113584Ssimokawa OWRITE(sc, OHCI_ITCMD(dmach), 1554113584Ssimokawa ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1555113584Ssimokawa if (firewire_debug) { 1556109890Ssimokawa printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1557113584Ssimokawa#if 1 1558113584Ssimokawa dump_dma(sc, ITX_CH + dmach); 1559113584Ssimokawa#endif 1560113584Ssimokawa } 1561109403Ssimokawa if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1562109890Ssimokawa#if 1 1563109890Ssimokawa /* Don't start until all chunks are buffered */ 1564109890Ssimokawa if (STAILQ_FIRST(&it->stfree) != NULL) 1565109890Ssimokawa goto out; 1566109890Ssimokawa#endif 1567113584Ssimokawa#if 1 1568109890Ssimokawa /* Clear cycle match counter bits */ 1569109890Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1570109890Ssimokawa 1571109356Ssimokawa /* 2bit second + 13bit cycle */ 1572109356Ssimokawa cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1573113584Ssimokawa cycle_match = fwohci_next_cycle(fc, cycle_now); 1574109890Ssimokawa 1575109356Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), 1576109356Ssimokawa OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1577109356Ssimokawa | OHCI_CNTL_DMA_RUN); 1578113584Ssimokawa#else 1579113584Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1580113584Ssimokawa#endif 1581113584Ssimokawa if (firewire_debug) { 1582109403Ssimokawa printf("cycle_match: 0x%04x->0x%04x\n", 1583109403Ssimokawa cycle_now, cycle_match); 1584113584Ssimokawa dump_dma(sc, ITX_CH + dmach); 1585113584Ssimokawa dump_db(sc, ITX_CH + dmach); 1586113584Ssimokawa } 1587109403Ssimokawa } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1588109890Ssimokawa device_printf(sc->fc.dev, 1589109890Ssimokawa "IT DMA underrun (0x%08x)\n", stat); 1590113584Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1591103285Sikob } 1592109890Ssimokawaout: 1593103285Sikob return err; 1594103285Sikob} 1595106790Ssimokawa 1596106790Ssimokawastatic int 1597113584Ssimokawafwohci_irx_enable(struct firewire_comm *fc, int dmach) 1598103285Sikob{ 1599103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1600109890Ssimokawa int err = 0, s, ldesc; 1601103285Sikob unsigned short tag, ich; 1602109736Ssimokawa u_int32_t stat; 1603109890Ssimokawa struct fwohci_dbch *dbch; 1604113584Ssimokawa struct fwohcidb_tr *db_tr; 1605109890Ssimokawa struct fw_bulkxfer *first, *prev, *chunk; 1606109890Ssimokawa struct fw_xferq *ir; 1607103285Sikob 1608109890Ssimokawa dbch = &sc->ir[dmach]; 1609109890Ssimokawa ir = &dbch->xferq; 1610109890Ssimokawa 1611109890Ssimokawa if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1612109890Ssimokawa tag = (ir->flag >> 6) & 3; 1613109890Ssimokawa ich = ir->flag & 0x3f; 1614108995Ssimokawa OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1615108995Ssimokawa 1616109890Ssimokawa ir->queued = 0; 1617109890Ssimokawa dbch->ndb = ir->bnpacket * ir->bnchunk; 1618109890Ssimokawa dbch->ndesc = 2; 1619113584Ssimokawa fwohci_db_init(sc, dbch); 1620109890Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1621109179Ssimokawa return ENOMEM; 1622109890Ssimokawa err = fwohci_rx_enable(sc, dbch); 1623103285Sikob } 1624103285Sikob if(err) 1625103285Sikob return err; 1626103285Sikob 1627109890Ssimokawa first = STAILQ_FIRST(&ir->stfree); 1628109890Ssimokawa if (first == NULL) { 1629109890Ssimokawa device_printf(fc->dev, "IR DMA no free chunk\n"); 1630109890Ssimokawa return 0; 1631109890Ssimokawa } 1632109890Ssimokawa 1633111892Ssimokawa ldesc = dbch->ndesc - 1; 1634111892Ssimokawa s = splfw(); 1635109890Ssimokawa prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1636109890Ssimokawa while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1637120660Ssimokawa struct fwohcidb *db; 1638109890Ssimokawa 1639111942Ssimokawa#if 1 /* XXX for if_fwe */ 1640113584Ssimokawa if (chunk->mbuf != NULL) { 1641113584Ssimokawa db_tr = (struct fwohcidb_tr *)(chunk->start); 1642113584Ssimokawa db_tr->dbcnt = 1; 1643113584Ssimokawa err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 1644113584Ssimokawa chunk->mbuf, fwohci_execute_db2, db_tr, 1645113584Ssimokawa /* flags */0); 1646113584Ssimokawa FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1647113584Ssimokawa OHCI_UPDATE | OHCI_INPUT_LAST | 1648113584Ssimokawa OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1649113584Ssimokawa } 1650111942Ssimokawa#endif 1651109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 1652113584Ssimokawa FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1653113584Ssimokawa FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1654109890Ssimokawa if (prev != NULL) { 1655109890Ssimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 1656113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1657103285Sikob } 1658109890Ssimokawa STAILQ_REMOVE_HEAD(&ir->stfree, link); 1659109890Ssimokawa STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1660109890Ssimokawa prev = chunk; 1661103285Sikob } 1662113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1663113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1664109890Ssimokawa splx(s); 1665109890Ssimokawa stat = OREAD(sc, OHCI_IRCTL(dmach)); 1666109890Ssimokawa if (stat & OHCI_CNTL_DMA_ACTIVE) 1667109890Ssimokawa return 0; 1668109890Ssimokawa if (stat & OHCI_CNTL_DMA_RUN) { 1669109890Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1670109890Ssimokawa device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1671109890Ssimokawa } 1672109890Ssimokawa 1673113584Ssimokawa if (firewire_debug) 1674113584Ssimokawa printf("start IR DMA 0x%x\n", stat); 1675109890Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1676109890Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1677109890Ssimokawa OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1678109890Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1679109890Ssimokawa OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1680109890Ssimokawa OWRITE(sc, OHCI_IRCMD(dmach), 1681113584Ssimokawa ((struct fwohcidb_tr *)(first->start))->bus_addr 1682109890Ssimokawa | dbch->ndesc); 1683109890Ssimokawa OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1684109890Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1685113584Ssimokawa#if 0 1686113584Ssimokawa dump_db(sc, IRX_CH + dmach); 1687113584Ssimokawa#endif 1688103285Sikob return err; 1689103285Sikob} 1690106790Ssimokawa 1691106790Ssimokawaint 1692110145Ssimokawafwohci_stop(struct fwohci_softc *sc, device_t dev) 1693103285Sikob{ 1694103285Sikob u_int i; 1695103285Sikob 1696103285Sikob/* Now stopping all DMA channel */ 1697103285Sikob OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1698103285Sikob OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1699103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1700103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1701103285Sikob 1702103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1703103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1704103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1705103285Sikob } 1706103285Sikob 1707103285Sikob/* FLUSH FIFO and reset Transmitter/Reciever */ 1708103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1709103285Sikob 1710103285Sikob/* Stop interrupt */ 1711103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, 1712103285Sikob OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1713103285Sikob | OHCI_INT_PHY_INT 1714103285Sikob | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1715103285Sikob | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1716103285Sikob | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1717103285Sikob | OHCI_INT_PHY_BUS_R); 1718116978Ssimokawa 1719118416Ssimokawa if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1720118416Ssimokawa fw_drain_txq(&sc->fc); 1721116978Ssimokawa 1722108642Ssimokawa/* XXX Link down? Bus reset? */ 1723103285Sikob return 0; 1724103285Sikob} 1725103285Sikob 1726108642Ssimokawaint 1727108642Ssimokawafwohci_resume(struct fwohci_softc *sc, device_t dev) 1728108642Ssimokawa{ 1729108642Ssimokawa int i; 1730116978Ssimokawa struct fw_xferq *ir; 1731116978Ssimokawa struct fw_bulkxfer *chunk; 1732108642Ssimokawa 1733108642Ssimokawa fwohci_reset(sc, dev); 1734108642Ssimokawa /* XXX resume isochronus receive automatically. (how about TX?) */ 1735108642Ssimokawa for(i = 0; i < sc->fc.nisodma; i ++) { 1736116978Ssimokawa ir = &sc->ir[i].xferq; 1737116978Ssimokawa if((ir->flag & FWXFERQ_RUNNING) != 0) { 1738108642Ssimokawa device_printf(sc->fc.dev, 1739108642Ssimokawa "resume iso receive ch: %d\n", i); 1740116978Ssimokawa ir->flag &= ~FWXFERQ_RUNNING; 1741116978Ssimokawa /* requeue stdma to stfree */ 1742116978Ssimokawa while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1743116978Ssimokawa STAILQ_REMOVE_HEAD(&ir->stdma, link); 1744116978Ssimokawa STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1745116978Ssimokawa } 1746108642Ssimokawa sc->fc.irx_enable(&sc->fc, i); 1747108642Ssimokawa } 1748108642Ssimokawa } 1749108642Ssimokawa 1750108642Ssimokawa bus_generic_resume(dev); 1751108642Ssimokawa sc->fc.ibr(&sc->fc); 1752108642Ssimokawa return 0; 1753108642Ssimokawa} 1754108642Ssimokawa 1755103285Sikob#define ACK_ALL 1756103285Sikobstatic void 1757106789Ssimokawafwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1758103285Sikob{ 1759103285Sikob u_int32_t irstat, itstat; 1760103285Sikob u_int i; 1761103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1762103285Sikob 1763103285Sikob#ifdef OHCI_DEBUG 1764103285Sikob if(stat & OREAD(sc, FWOHCI_INTMASK)) 1765103285Sikob device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1766103285Sikob stat & OHCI_INT_EN ? "DMA_EN ":"", 1767103285Sikob stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1768103285Sikob stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1769103285Sikob stat & OHCI_INT_ERR ? "INT_ERR ":"", 1770103285Sikob stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1771103285Sikob stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1772103285Sikob stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1773103285Sikob stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1774103285Sikob stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1775103285Sikob stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1776103285Sikob stat & OHCI_INT_PHY_SID ? "SID ":"", 1777103285Sikob stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1778103285Sikob stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1779103285Sikob stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1780103285Sikob stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1781103285Sikob stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1782103285Sikob stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1783103285Sikob stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1784103285Sikob stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1785103285Sikob stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1786103285Sikob stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1787103285Sikob stat, OREAD(sc, FWOHCI_INTMASK) 1788103285Sikob ); 1789103285Sikob#endif 1790103285Sikob/* Bus reset */ 1791103285Sikob if(stat & OHCI_INT_PHY_BUS_R ){ 1792111074Ssimokawa if (fc->status == FWBUSRESET) 1793111074Ssimokawa goto busresetout; 1794111074Ssimokawa /* Disable bus reset interrupt until sid recv. */ 1795111074Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1796111074Ssimokawa 1797103285Sikob device_printf(fc->dev, "BUS reset\n"); 1798103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1799103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1800103285Sikob 1801103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1802103285Sikob sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1803103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1804103285Sikob sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1805103285Sikob 1806103285Sikob#ifndef ACK_ALL 1807103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1808103285Sikob#endif 1809110798Ssimokawa fw_busreset(fc); 1810116376Ssimokawa OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1811116376Ssimokawa OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1812103285Sikob } 1813111074Ssimokawabusresetout: 1814103285Sikob if((stat & OHCI_INT_DMA_IR )){ 1815103285Sikob#ifndef ACK_ALL 1816103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1817103285Sikob#endif 1818113584Ssimokawa#if __FreeBSD_version >= 500000 1819113584Ssimokawa irstat = atomic_readandclear_int(&sc->irstat); 1820113584Ssimokawa#else 1821113584Ssimokawa irstat = sc->irstat; 1822113584Ssimokawa sc->irstat = 0; 1823113584Ssimokawa#endif 1824103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1825109644Ssimokawa struct fwohci_dbch *dbch; 1826109644Ssimokawa 1827103285Sikob if((irstat & (1 << i)) != 0){ 1828109644Ssimokawa dbch = &sc->ir[i]; 1829109644Ssimokawa if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1830109644Ssimokawa device_printf(sc->fc.dev, 1831109644Ssimokawa "dma(%d) not active\n", i); 1832109644Ssimokawa continue; 1833109644Ssimokawa } 1834113584Ssimokawa fwohci_rbuf_update(sc, i); 1835103285Sikob } 1836103285Sikob } 1837103285Sikob } 1838103285Sikob if((stat & OHCI_INT_DMA_IT )){ 1839103285Sikob#ifndef ACK_ALL 1840103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1841103285Sikob#endif 1842113584Ssimokawa#if __FreeBSD_version >= 500000 1843113584Ssimokawa itstat = atomic_readandclear_int(&sc->itstat); 1844113584Ssimokawa#else 1845113584Ssimokawa itstat = sc->itstat; 1846113584Ssimokawa sc->itstat = 0; 1847113584Ssimokawa#endif 1848103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1849103285Sikob if((itstat & (1 << i)) != 0){ 1850103285Sikob fwohci_tbuf_update(sc, i); 1851103285Sikob } 1852103285Sikob } 1853103285Sikob } 1854103285Sikob if((stat & OHCI_INT_DMA_PRRS )){ 1855103285Sikob#ifndef ACK_ALL 1856103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1857103285Sikob#endif 1858103285Sikob#if 0 1859103285Sikob dump_dma(sc, ARRS_CH); 1860103285Sikob dump_db(sc, ARRS_CH); 1861103285Sikob#endif 1862106789Ssimokawa fwohci_arcv(sc, &sc->arrs, count); 1863103285Sikob } 1864103285Sikob if((stat & OHCI_INT_DMA_PRRQ )){ 1865103285Sikob#ifndef ACK_ALL 1866103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1867103285Sikob#endif 1868103285Sikob#if 0 1869103285Sikob dump_dma(sc, ARRQ_CH); 1870103285Sikob dump_db(sc, ARRQ_CH); 1871103285Sikob#endif 1872106789Ssimokawa fwohci_arcv(sc, &sc->arrq, count); 1873103285Sikob } 1874103285Sikob if(stat & OHCI_INT_PHY_SID){ 1875113584Ssimokawa u_int32_t *buf, node_id; 1876103285Sikob int plen; 1877103285Sikob 1878103285Sikob#ifndef ACK_ALL 1879103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1880103285Sikob#endif 1881111074Ssimokawa /* Enable bus reset interrupt */ 1882111074Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1883111787Ssimokawa /* Allow async. request to us */ 1884111787Ssimokawa OWRITE(sc, OHCI_AREQHI, 1 << 31); 1885111787Ssimokawa /* XXX insecure ?? */ 1886111787Ssimokawa OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1887111787Ssimokawa OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1888111787Ssimokawa OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1889112523Ssimokawa /* Set ATRetries register */ 1890112523Ssimokawa OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1891103285Sikob/* 1892103285Sikob** Checking whether the node is root or not. If root, turn on 1893103285Sikob** cycle master. 1894103285Sikob*/ 1895113584Ssimokawa node_id = OREAD(sc, FWOHCI_NODEID); 1896113584Ssimokawa plen = OREAD(sc, OHCI_SID_CNT); 1897113584Ssimokawa 1898113584Ssimokawa device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 1899113584Ssimokawa node_id, (plen >> 16) & 0xff); 1900113584Ssimokawa if (!(node_id & OHCI_NODE_VALID)) { 1901103285Sikob printf("Bus reset failure\n"); 1902103285Sikob goto sidout; 1903103285Sikob } 1904113584Ssimokawa if (node_id & OHCI_NODE_ROOT) { 1905103285Sikob printf("CYCLEMASTER mode\n"); 1906103285Sikob OWRITE(sc, OHCI_LNKCTL, 1907103285Sikob OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1908113584Ssimokawa } else { 1909103285Sikob printf("non CYCLEMASTER mode\n"); 1910103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1911103285Sikob OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1912103285Sikob } 1913113584Ssimokawa fc->nodeid = node_id & 0x3f; 1914103285Sikob 1915113584Ssimokawa if (plen & OHCI_SID_ERR) { 1916113584Ssimokawa device_printf(fc->dev, "SID Error\n"); 1917113584Ssimokawa goto sidout; 1918113584Ssimokawa } 1919113584Ssimokawa plen &= OHCI_SID_CNT_MASK; 1920109736Ssimokawa if (plen < 4 || plen > OHCI_SIDSIZE) { 1921109736Ssimokawa device_printf(fc->dev, "invalid SID len = %d\n", plen); 1922109736Ssimokawa goto sidout; 1923109736Ssimokawa } 1924103285Sikob plen -= 4; /* chop control info */ 1925113584Ssimokawa buf = (u_int32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1926113584Ssimokawa if (buf == NULL) { 1927113584Ssimokawa device_printf(fc->dev, "malloc failed\n"); 1928113584Ssimokawa goto sidout; 1929113584Ssimokawa } 1930113584Ssimokawa for (i = 0; i < plen / 4; i ++) 1931113584Ssimokawa buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 1932110269Ssimokawa#if 1 1933110269Ssimokawa /* pending all pre-bus_reset packets */ 1934110269Ssimokawa fwohci_txd(sc, &sc->atrq); 1935110269Ssimokawa fwohci_txd(sc, &sc->atrs); 1936110269Ssimokawa fwohci_arcv(sc, &sc->arrs, -1); 1937110269Ssimokawa fwohci_arcv(sc, &sc->arrq, -1); 1938110798Ssimokawa fw_drain_txq(fc); 1939110269Ssimokawa#endif 1940113584Ssimokawa fw_sidrcv(fc, buf, plen); 1941113584Ssimokawa free(buf, M_FW); 1942103285Sikob } 1943103285Sikobsidout: 1944103285Sikob if((stat & OHCI_INT_DMA_ATRQ )){ 1945103285Sikob#ifndef ACK_ALL 1946103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1947103285Sikob#endif 1948103285Sikob fwohci_txd(sc, &(sc->atrq)); 1949103285Sikob } 1950103285Sikob if((stat & OHCI_INT_DMA_ATRS )){ 1951103285Sikob#ifndef ACK_ALL 1952103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1953103285Sikob#endif 1954103285Sikob fwohci_txd(sc, &(sc->atrs)); 1955103285Sikob } 1956103285Sikob if((stat & OHCI_INT_PW_ERR )){ 1957103285Sikob#ifndef ACK_ALL 1958103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1959103285Sikob#endif 1960103285Sikob device_printf(fc->dev, "posted write error\n"); 1961103285Sikob } 1962103285Sikob if((stat & OHCI_INT_ERR )){ 1963103285Sikob#ifndef ACK_ALL 1964103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1965103285Sikob#endif 1966103285Sikob device_printf(fc->dev, "unrecoverable error\n"); 1967103285Sikob } 1968103285Sikob if((stat & OHCI_INT_PHY_INT)) { 1969103285Sikob#ifndef ACK_ALL 1970103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1971103285Sikob#endif 1972103285Sikob device_printf(fc->dev, "phy int\n"); 1973103285Sikob } 1974103285Sikob 1975103285Sikob return; 1976103285Sikob} 1977103285Sikob 1978113584Ssimokawa#if FWOHCI_TASKQUEUE 1979113584Ssimokawastatic void 1980113584Ssimokawafwohci_complete(void *arg, int pending) 1981113584Ssimokawa{ 1982113584Ssimokawa struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1983113584Ssimokawa u_int32_t stat; 1984113584Ssimokawa 1985113584Ssimokawaagain: 1986113584Ssimokawa stat = atomic_readandclear_int(&sc->intstat); 1987113584Ssimokawa if (stat) 1988113584Ssimokawa fwohci_intr_body(sc, stat, -1); 1989113584Ssimokawa else 1990113584Ssimokawa return; 1991113584Ssimokawa goto again; 1992113584Ssimokawa} 1993113584Ssimokawa#endif 1994113584Ssimokawa 1995113584Ssimokawastatic u_int32_t 1996113584Ssimokawafwochi_check_stat(struct fwohci_softc *sc) 1997113584Ssimokawa{ 1998113584Ssimokawa u_int32_t stat, irstat, itstat; 1999113584Ssimokawa 2000113584Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 2001113584Ssimokawa if (stat == 0xffffffff) { 2002113584Ssimokawa device_printf(sc->fc.dev, 2003113584Ssimokawa "device physically ejected?\n"); 2004113584Ssimokawa return(stat); 2005113584Ssimokawa } 2006113584Ssimokawa#ifdef ACK_ALL 2007113584Ssimokawa if (stat) 2008113584Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2009113584Ssimokawa#endif 2010113584Ssimokawa if (stat & OHCI_INT_DMA_IR) { 2011113584Ssimokawa irstat = OREAD(sc, OHCI_IR_STAT); 2012113584Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, irstat); 2013113584Ssimokawa atomic_set_int(&sc->irstat, irstat); 2014113584Ssimokawa } 2015113584Ssimokawa if (stat & OHCI_INT_DMA_IT) { 2016113584Ssimokawa itstat = OREAD(sc, OHCI_IT_STAT); 2017113584Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, itstat); 2018113584Ssimokawa atomic_set_int(&sc->itstat, itstat); 2019113584Ssimokawa } 2020113584Ssimokawa return(stat); 2021113584Ssimokawa} 2022113584Ssimokawa 2023103285Sikobvoid 2024103285Sikobfwohci_intr(void *arg) 2025103285Sikob{ 2026103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2027113584Ssimokawa u_int32_t stat; 2028113584Ssimokawa#if !FWOHCI_TASKQUEUE 2029113584Ssimokawa u_int32_t bus_reset = 0; 2030113584Ssimokawa#endif 2031103285Sikob 2032103285Sikob if (!(sc->intmask & OHCI_INT_EN)) { 2033103285Sikob /* polling mode */ 2034103285Sikob return; 2035103285Sikob } 2036103285Sikob 2037113584Ssimokawa#if !FWOHCI_TASKQUEUE 2038113584Ssimokawaagain: 2039103285Sikob#endif 2040113584Ssimokawa stat = fwochi_check_stat(sc); 2041113584Ssimokawa if (stat == 0 || stat == 0xffffffff) 2042113584Ssimokawa return; 2043113584Ssimokawa#if FWOHCI_TASKQUEUE 2044113584Ssimokawa atomic_set_int(&sc->intstat, stat); 2045113584Ssimokawa /* XXX mask bus reset intr. during bus reset phase */ 2046113584Ssimokawa if (stat) 2047113584Ssimokawa taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete); 2048113584Ssimokawa#else 2049113584Ssimokawa /* We cannot clear bus reset event during bus reset phase */ 2050113584Ssimokawa if ((stat & ~bus_reset) == 0) 2051113584Ssimokawa return; 2052113584Ssimokawa bus_reset = stat & OHCI_INT_PHY_BUS_R; 2053113584Ssimokawa fwohci_intr_body(sc, stat, -1); 2054113584Ssimokawa goto again; 2055113584Ssimokawa#endif 2056103285Sikob} 2057103285Sikob 2058116897Ssimokawavoid 2059103285Sikobfwohci_poll(struct firewire_comm *fc, int quick, int count) 2060103285Sikob{ 2061103285Sikob int s; 2062103285Sikob u_int32_t stat; 2063103285Sikob struct fwohci_softc *sc; 2064103285Sikob 2065103285Sikob 2066103285Sikob sc = (struct fwohci_softc *)fc; 2067103285Sikob stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2068103285Sikob OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2069103285Sikob OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2070103285Sikob#if 0 2071103285Sikob if (!quick) { 2072103285Sikob#else 2073103285Sikob if (1) { 2074103285Sikob#endif 2075113584Ssimokawa stat = fwochi_check_stat(sc); 2076113584Ssimokawa if (stat == 0 || stat == 0xffffffff) 2077103285Sikob return; 2078103285Sikob } 2079103285Sikob s = splfw(); 2080106789Ssimokawa fwohci_intr_body(sc, stat, count); 2081103285Sikob splx(s); 2082103285Sikob} 2083103285Sikob 2084103285Sikobstatic void 2085103285Sikobfwohci_set_intr(struct firewire_comm *fc, int enable) 2086103285Sikob{ 2087103285Sikob struct fwohci_softc *sc; 2088103285Sikob 2089103285Sikob sc = (struct fwohci_softc *)fc; 2090107653Ssimokawa if (bootverbose) 2091108642Ssimokawa device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2092103285Sikob if (enable) { 2093103285Sikob sc->intmask |= OHCI_INT_EN; 2094103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2095103285Sikob } else { 2096103285Sikob sc->intmask &= ~OHCI_INT_EN; 2097103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2098103285Sikob } 2099103285Sikob} 2100103285Sikob 2101106790Ssimokawastatic void 2102106790Ssimokawafwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2103103285Sikob{ 2104103285Sikob struct firewire_comm *fc = &sc->fc; 2105120660Ssimokawa struct fwohcidb *db; 2106109890Ssimokawa struct fw_bulkxfer *chunk; 2107109890Ssimokawa struct fw_xferq *it; 2108109890Ssimokawa u_int32_t stat, count; 2109113584Ssimokawa int s, w=0, ldesc; 2110103285Sikob 2111109890Ssimokawa it = fc->it[dmach]; 2112113584Ssimokawa ldesc = sc->it[dmach].ndesc - 1; 2113109890Ssimokawa s = splfw(); /* unnecessary ? */ 2114113584Ssimokawa fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2115119155Ssimokawa if (firewire_debug) 2116119155Ssimokawa dump_db(sc, ITX_CH + dmach); 2117109890Ssimokawa while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2118109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 2119113584Ssimokawa stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2120113584Ssimokawa >> OHCI_STATUS_SHIFT; 2121109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->start))->db; 2122119155Ssimokawa /* timestamp */ 2123113584Ssimokawa count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2124113584Ssimokawa & OHCI_COUNT_MASK; 2125109890Ssimokawa if (stat == 0) 2126109890Ssimokawa break; 2127109890Ssimokawa STAILQ_REMOVE_HEAD(&it->stdma, link); 2128109890Ssimokawa switch (stat & FWOHCIEV_MASK){ 2129109890Ssimokawa case FWOHCIEV_ACKCOMPL: 2130109890Ssimokawa#if 0 2131109890Ssimokawa device_printf(fc->dev, "0x%08x\n", count); 2132109179Ssimokawa#endif 2133109890Ssimokawa break; 2134109890Ssimokawa default: 2135109423Ssimokawa device_printf(fc->dev, 2136113584Ssimokawa "Isochronous transmit err %02x(%s)\n", 2137113584Ssimokawa stat, fwohcicode[stat & 0x1f]); 2138109890Ssimokawa } 2139109890Ssimokawa STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2140109890Ssimokawa w++; 2141109403Ssimokawa } 2142109890Ssimokawa splx(s); 2143109890Ssimokawa if (w) 2144109890Ssimokawa wakeup(it); 2145103285Sikob} 2146106790Ssimokawa 2147106790Ssimokawastatic void 2148106790Ssimokawafwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2149103285Sikob{ 2150109179Ssimokawa struct firewire_comm *fc = &sc->fc; 2151120660Ssimokawa struct fwohcidb_tr *db_tr; 2152109890Ssimokawa struct fw_bulkxfer *chunk; 2153109890Ssimokawa struct fw_xferq *ir; 2154109890Ssimokawa u_int32_t stat; 2155113584Ssimokawa int s, w=0, ldesc; 2156109179Ssimokawa 2157109890Ssimokawa ir = fc->ir[dmach]; 2158113584Ssimokawa ldesc = sc->ir[dmach].ndesc - 1; 2159113584Ssimokawa#if 0 2160113584Ssimokawa dump_db(sc, dmach); 2161113584Ssimokawa#endif 2162109890Ssimokawa s = splfw(); 2163113584Ssimokawa fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2164109890Ssimokawa while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2165113584Ssimokawa db_tr = (struct fwohcidb_tr *)chunk->end; 2166113584Ssimokawa stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2167113584Ssimokawa >> OHCI_STATUS_SHIFT; 2168109890Ssimokawa if (stat == 0) 2169109890Ssimokawa break; 2170113584Ssimokawa 2171113584Ssimokawa if (chunk->mbuf != NULL) { 2172113584Ssimokawa bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2173113584Ssimokawa BUS_DMASYNC_POSTREAD); 2174113584Ssimokawa bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 2175113584Ssimokawa } else if (ir->buf != NULL) { 2176113584Ssimokawa fwdma_sync_multiseg(ir->buf, chunk->poffset, 2177113584Ssimokawa ir->bnpacket, BUS_DMASYNC_POSTREAD); 2178113584Ssimokawa } else { 2179113584Ssimokawa /* XXX */ 2180113584Ssimokawa printf("fwohci_rbuf_update: this shouldn't happend\n"); 2181113584Ssimokawa } 2182113584Ssimokawa 2183109890Ssimokawa STAILQ_REMOVE_HEAD(&ir->stdma, link); 2184109890Ssimokawa STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2185109890Ssimokawa switch (stat & FWOHCIEV_MASK) { 2186109890Ssimokawa case FWOHCIEV_ACKCOMPL: 2187111942Ssimokawa chunk->resp = 0; 2188109890Ssimokawa break; 2189109890Ssimokawa default: 2190111942Ssimokawa chunk->resp = EINVAL; 2191109890Ssimokawa device_printf(fc->dev, 2192113584Ssimokawa "Isochronous receive err %02x(%s)\n", 2193113584Ssimokawa stat, fwohcicode[stat & 0x1f]); 2194109890Ssimokawa } 2195109890Ssimokawa w++; 2196103285Sikob } 2197109890Ssimokawa splx(s); 2198111942Ssimokawa if (w) { 2199111942Ssimokawa if (ir->flag & FWXFERQ_HANDLER) 2200111942Ssimokawa ir->hand(ir); 2201111942Ssimokawa else 2202111942Ssimokawa wakeup(ir); 2203111942Ssimokawa } 2204103285Sikob} 2205106790Ssimokawa 2206106790Ssimokawavoid 2207106790Ssimokawadump_dma(struct fwohci_softc *sc, u_int32_t ch) 2208106790Ssimokawa{ 2209103285Sikob u_int32_t off, cntl, stat, cmd, match; 2210103285Sikob 2211103285Sikob if(ch == 0){ 2212103285Sikob off = OHCI_ATQOFF; 2213103285Sikob }else if(ch == 1){ 2214103285Sikob off = OHCI_ATSOFF; 2215103285Sikob }else if(ch == 2){ 2216103285Sikob off = OHCI_ARQOFF; 2217103285Sikob }else if(ch == 3){ 2218103285Sikob off = OHCI_ARSOFF; 2219103285Sikob }else if(ch < IRX_CH){ 2220103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2221103285Sikob }else{ 2222103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2223103285Sikob } 2224103285Sikob cntl = stat = OREAD(sc, off); 2225103285Sikob cmd = OREAD(sc, off + 0xc); 2226103285Sikob match = OREAD(sc, off + 0x10); 2227103285Sikob 2228113584Ssimokawa device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2229103285Sikob ch, 2230103285Sikob cntl, 2231103285Sikob cmd, 2232103285Sikob match); 2233103285Sikob stat &= 0xffff ; 2234113584Ssimokawa if (stat) { 2235103285Sikob device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2236103285Sikob ch, 2237103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2238103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2239103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2240103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2241103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2242103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2243103285Sikob fwohcicode[stat & 0x1f], 2244103285Sikob stat & 0x1f 2245103285Sikob ); 2246103285Sikob }else{ 2247103285Sikob device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2248103285Sikob } 2249103285Sikob} 2250106790Ssimokawa 2251106790Ssimokawavoid 2252106790Ssimokawadump_db(struct fwohci_softc *sc, u_int32_t ch) 2253106790Ssimokawa{ 2254103285Sikob struct fwohci_dbch *dbch; 2255113584Ssimokawa struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2256120660Ssimokawa struct fwohcidb *curr = NULL, *prev, *next = NULL; 2257103285Sikob int idb, jdb; 2258103285Sikob u_int32_t cmd, off; 2259103285Sikob if(ch == 0){ 2260103285Sikob off = OHCI_ATQOFF; 2261103285Sikob dbch = &sc->atrq; 2262103285Sikob }else if(ch == 1){ 2263103285Sikob off = OHCI_ATSOFF; 2264103285Sikob dbch = &sc->atrs; 2265103285Sikob }else if(ch == 2){ 2266103285Sikob off = OHCI_ARQOFF; 2267103285Sikob dbch = &sc->arrq; 2268103285Sikob }else if(ch == 3){ 2269103285Sikob off = OHCI_ARSOFF; 2270103285Sikob dbch = &sc->arrs; 2271103285Sikob }else if(ch < IRX_CH){ 2272103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2273103285Sikob dbch = &sc->it[ch - ITX_CH]; 2274103285Sikob }else { 2275103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2276103285Sikob dbch = &sc->ir[ch - IRX_CH]; 2277103285Sikob } 2278103285Sikob cmd = OREAD(sc, off + 0xc); 2279103285Sikob 2280103285Sikob if( dbch->ndb == 0 ){ 2281103285Sikob device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2282103285Sikob return; 2283103285Sikob } 2284103285Sikob pp = dbch->top; 2285103285Sikob prev = pp->db; 2286103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2287103285Sikob if(pp == NULL){ 2288103285Sikob curr = NULL; 2289103285Sikob goto outdb; 2290103285Sikob } 2291103285Sikob cp = STAILQ_NEXT(pp, link); 2292103285Sikob if(cp == NULL){ 2293103285Sikob curr = NULL; 2294103285Sikob goto outdb; 2295103285Sikob } 2296103285Sikob np = STAILQ_NEXT(cp, link); 2297103285Sikob for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2298113584Ssimokawa if ((cmd & 0xfffffff0) == cp->bus_addr) { 2299103285Sikob curr = cp->db; 2300103285Sikob if(np != NULL){ 2301103285Sikob next = np->db; 2302103285Sikob }else{ 2303103285Sikob next = NULL; 2304103285Sikob } 2305103285Sikob goto outdb; 2306103285Sikob } 2307103285Sikob } 2308103285Sikob pp = STAILQ_NEXT(pp, link); 2309103285Sikob prev = pp->db; 2310103285Sikob } 2311103285Sikoboutdb: 2312103285Sikob if( curr != NULL){ 2313113584Ssimokawa#if 0 2314103285Sikob printf("Prev DB %d\n", ch); 2315113584Ssimokawa print_db(pp, prev, ch, dbch->ndesc); 2316113584Ssimokawa#endif 2317103285Sikob printf("Current DB %d\n", ch); 2318113584Ssimokawa print_db(cp, curr, ch, dbch->ndesc); 2319113584Ssimokawa#if 0 2320103285Sikob printf("Next DB %d\n", ch); 2321113584Ssimokawa print_db(np, next, ch, dbch->ndesc); 2322113584Ssimokawa#endif 2323103285Sikob }else{ 2324103285Sikob printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2325103285Sikob } 2326103285Sikob return; 2327103285Sikob} 2328106790Ssimokawa 2329106790Ssimokawavoid 2330120660Ssimokawaprint_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2331113584Ssimokawa u_int32_t ch, u_int32_t max) 2332106790Ssimokawa{ 2333103285Sikob fwohcireg_t stat; 2334103285Sikob int i, key; 2335113584Ssimokawa u_int32_t cmd, res; 2336103285Sikob 2337103285Sikob if(db == NULL){ 2338103285Sikob printf("No Descriptor is found\n"); 2339103285Sikob return; 2340103285Sikob } 2341103285Sikob 2342103285Sikob printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2343103285Sikob ch, 2344103285Sikob "Current", 2345103285Sikob "OP ", 2346103285Sikob "KEY", 2347103285Sikob "INT", 2348103285Sikob "BR ", 2349103285Sikob "len", 2350103285Sikob "Addr", 2351103285Sikob "Depend", 2352103285Sikob "Stat", 2353103285Sikob "Cnt"); 2354103285Sikob for( i = 0 ; i <= max ; i ++){ 2355113584Ssimokawa cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2356113584Ssimokawa res = FWOHCI_DMA_READ(db[i].db.desc.res); 2357113584Ssimokawa key = cmd & OHCI_KEY_MASK; 2358113584Ssimokawa stat = res >> OHCI_STATUS_SHIFT; 2359108712Ssimokawa#if __FreeBSD_version >= 500000 2360113972Ssimokawa printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2361114142Ssimokawa (uintmax_t)db_tr->bus_addr, 2362108712Ssimokawa#else 2363108712Ssimokawa printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2364114142Ssimokawa db_tr->bus_addr, 2365108712Ssimokawa#endif 2366113584Ssimokawa dbcode[(cmd >> 28) & 0xf], 2367113584Ssimokawa dbkey[(cmd >> 24) & 0x7], 2368113584Ssimokawa dbcond[(cmd >> 20) & 0x3], 2369113584Ssimokawa dbcond[(cmd >> 18) & 0x3], 2370113584Ssimokawa cmd & OHCI_COUNT_MASK, 2371113584Ssimokawa FWOHCI_DMA_READ(db[i].db.desc.addr), 2372113584Ssimokawa FWOHCI_DMA_READ(db[i].db.desc.depend), 2373113584Ssimokawa stat, 2374113584Ssimokawa res & OHCI_COUNT_MASK); 2375103285Sikob if(stat & 0xff00){ 2376103285Sikob printf(" %s%s%s%s%s%s %s(%x)\n", 2377103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2378103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2379103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2380103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2381103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2382103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2383103285Sikob fwohcicode[stat & 0x1f], 2384103285Sikob stat & 0x1f 2385103285Sikob ); 2386103285Sikob }else{ 2387103285Sikob printf(" Nostat\n"); 2388103285Sikob } 2389103285Sikob if(key == OHCI_KEY_ST2 ){ 2390103285Sikob printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2391113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2392113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2393113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2394113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2395103285Sikob } 2396103285Sikob if(key == OHCI_KEY_DEVICE){ 2397103285Sikob return; 2398103285Sikob } 2399113584Ssimokawa if((cmd & OHCI_BRANCH_MASK) 2400103285Sikob == OHCI_BRANCH_ALWAYS){ 2401103285Sikob return; 2402103285Sikob } 2403113584Ssimokawa if((cmd & OHCI_CMD_MASK) 2404103285Sikob == OHCI_OUTPUT_LAST){ 2405103285Sikob return; 2406103285Sikob } 2407113584Ssimokawa if((cmd & OHCI_CMD_MASK) 2408103285Sikob == OHCI_INPUT_LAST){ 2409103285Sikob return; 2410103285Sikob } 2411103285Sikob if(key == OHCI_KEY_ST2 ){ 2412103285Sikob i++; 2413103285Sikob } 2414103285Sikob } 2415103285Sikob return; 2416103285Sikob} 2417106790Ssimokawa 2418106790Ssimokawavoid 2419106790Ssimokawafwohci_ibr(struct firewire_comm *fc) 2420103285Sikob{ 2421103285Sikob struct fwohci_softc *sc; 2422103285Sikob u_int32_t fun; 2423103285Sikob 2424110577Ssimokawa device_printf(fc->dev, "Initiate bus reset\n"); 2425103285Sikob sc = (struct fwohci_softc *)fc; 2426108276Ssimokawa 2427108276Ssimokawa /* 2428108276Ssimokawa * Set root hold-off bit so that non cyclemaster capable node 2429108276Ssimokawa * shouldn't became the root node. 2430108276Ssimokawa */ 2431103285Sikob#if 1 2432103285Sikob fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2433109280Ssimokawa fun |= FW_PHY_IBR | FW_PHY_RHB; 2434103285Sikob fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2435109280Ssimokawa#else /* Short bus reset */ 2436103285Sikob fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2437109280Ssimokawa fun |= FW_PHY_ISBR | FW_PHY_RHB; 2438103285Sikob fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2439103285Sikob#endif 2440103285Sikob} 2441106790Ssimokawa 2442106790Ssimokawavoid 2443106790Ssimokawafwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2444103285Sikob{ 2445103285Sikob struct fwohcidb_tr *db_tr, *fdb_tr; 2446103285Sikob struct fwohci_dbch *dbch; 2447120660Ssimokawa struct fwohcidb *db; 2448103285Sikob struct fw_pkt *fp; 2449120660Ssimokawa struct fwohci_txpkthdr *ohcifp; 2450103285Sikob unsigned short chtag; 2451103285Sikob int idb; 2452103285Sikob 2453103285Sikob dbch = &sc->it[dmach]; 2454103285Sikob chtag = sc->it[dmach].xferq.flag & 0xff; 2455103285Sikob 2456103285Sikob db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2457103285Sikob fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2458103285Sikob/* 2459113584Ssimokawadevice_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2460103285Sikob*/ 2461113584Ssimokawa for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2462109892Ssimokawa db = db_tr->db; 2463103285Sikob fp = (struct fw_pkt *)db_tr->buf; 2464120660Ssimokawa ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2465113584Ssimokawa ohcifp->mode.ld[0] = fp->mode.ld[0]; 2466119155Ssimokawa ohcifp->mode.common.spd = 0 & 0x7; 2467113584Ssimokawa ohcifp->mode.stream.len = fp->mode.stream.len; 2468103285Sikob ohcifp->mode.stream.chtag = chtag; 2469103285Sikob ohcifp->mode.stream.tcode = 0xa; 2470113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2471113584Ssimokawa FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2472113584Ssimokawa FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2473113584Ssimokawa#endif 2474103285Sikob 2475113584Ssimokawa FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2476113584Ssimokawa FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2477113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2478109892Ssimokawa#if 0 /* if bulkxfer->npackets changes */ 2479113584Ssimokawa db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2480103285Sikob | OHCI_UPDATE 2481109892Ssimokawa | OHCI_BRANCH_ALWAYS; 2482109892Ssimokawa db[0].db.desc.depend = 2483109892Ssimokawa = db[dbch->ndesc - 1].db.desc.depend 2484113584Ssimokawa = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2485109892Ssimokawa#else 2486113584Ssimokawa FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2487113584Ssimokawa FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2488109892Ssimokawa#endif 2489103285Sikob bulkxfer->end = (caddr_t)db_tr; 2490103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2491103285Sikob } 2492109892Ssimokawa db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2493113584Ssimokawa FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2494113584Ssimokawa FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2495109892Ssimokawa#if 0 /* if bulkxfer->npackets changes */ 2496109892Ssimokawa db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2497109280Ssimokawa /* OHCI 1.1 and above */ 2498109892Ssimokawa db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2499109892Ssimokawa#endif 2500109892Ssimokawa/* 2501103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2502103285Sikob fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2503113584Ssimokawadevice_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2504103285Sikob*/ 2505103285Sikob return; 2506103285Sikob} 2507106790Ssimokawa 2508106790Ssimokawastatic int 2509113584Ssimokawafwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2510113584Ssimokawa int poffset) 2511103285Sikob{ 2512120660Ssimokawa struct fwohcidb *db = db_tr->db; 2513113584Ssimokawa struct fw_xferq *it; 2514103285Sikob int err = 0; 2515113584Ssimokawa 2516113584Ssimokawa it = &dbch->xferq; 2517113584Ssimokawa if(it->buf == 0){ 2518103285Sikob err = EINVAL; 2519103285Sikob return err; 2520103285Sikob } 2521113584Ssimokawa db_tr->buf = fwdma_v_addr(it->buf, poffset); 2522103285Sikob db_tr->dbcnt = 3; 2523103285Sikob 2524113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2525113584Ssimokawa OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2526119155Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2527120660Ssimokawa bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2528113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2529113584Ssimokawa fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t)); 2530113584Ssimokawa 2531113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2532113584Ssimokawa OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2533109892Ssimokawa#if 1 2534113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2535113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2536109892Ssimokawa#endif 2537113584Ssimokawa return 0; 2538103285Sikob} 2539106790Ssimokawa 2540106790Ssimokawaint 2541113584Ssimokawafwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2542113584Ssimokawa int poffset, struct fwdma_alloc *dummy_dma) 2543103285Sikob{ 2544120660Ssimokawa struct fwohcidb *db = db_tr->db; 2545113584Ssimokawa struct fw_xferq *ir; 2546113584Ssimokawa int i, ldesc; 2547113584Ssimokawa bus_addr_t dbuf[2]; 2548103285Sikob int dsiz[2]; 2549103285Sikob 2550113584Ssimokawa ir = &dbch->xferq; 2551113584Ssimokawa if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2552113584Ssimokawa db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2553113584Ssimokawa ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2554113584Ssimokawa if (db_tr->buf == NULL) 2555113584Ssimokawa return(ENOMEM); 2556103285Sikob db_tr->dbcnt = 1; 2557113584Ssimokawa dsiz[0] = ir->psize; 2558113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2559113584Ssimokawa BUS_DMASYNC_PREREAD); 2560113584Ssimokawa } else { 2561113584Ssimokawa db_tr->dbcnt = 0; 2562113584Ssimokawa if (dummy_dma != NULL) { 2563113584Ssimokawa dsiz[db_tr->dbcnt] = sizeof(u_int32_t); 2564113584Ssimokawa dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2565113584Ssimokawa } 2566113584Ssimokawa dsiz[db_tr->dbcnt] = ir->psize; 2567113584Ssimokawa if (ir->buf != NULL) { 2568113584Ssimokawa db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2569113584Ssimokawa dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2570113584Ssimokawa } 2571113584Ssimokawa db_tr->dbcnt++; 2572103285Sikob } 2573103285Sikob for(i = 0 ; i < db_tr->dbcnt ; i++){ 2574113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2575113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2576113584Ssimokawa if (ir->flag & FWXFERQ_STREAM) { 2577113584Ssimokawa FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2578103285Sikob } 2579113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2580103285Sikob } 2581113584Ssimokawa ldesc = db_tr->dbcnt - 1; 2582113584Ssimokawa if (ir->flag & FWXFERQ_STREAM) { 2583113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2584103285Sikob } 2585113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2586113584Ssimokawa return 0; 2587103285Sikob} 2588106790Ssimokawa 2589113584Ssimokawa 2590113584Ssimokawastatic int 2591113584Ssimokawafwohci_arcv_swap(struct fw_pkt *fp, int len) 2592103285Sikob{ 2593113584Ssimokawa struct fw_pkt *fp0; 2594113584Ssimokawa u_int32_t ld0; 2595120660Ssimokawa int slen, hlen; 2596113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2597113584Ssimokawa int i; 2598113584Ssimokawa#endif 2599103285Sikob 2600113584Ssimokawa ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2601113584Ssimokawa#if 0 2602113584Ssimokawa printf("ld0: x%08x\n", ld0); 2603113584Ssimokawa#endif 2604113584Ssimokawa fp0 = (struct fw_pkt *)&ld0; 2605120660Ssimokawa /* determine length to swap */ 2606113584Ssimokawa switch (fp0->mode.common.tcode) { 2607113584Ssimokawa case FWTCODE_RREQQ: 2608113584Ssimokawa case FWTCODE_WRES: 2609113584Ssimokawa case FWTCODE_WREQQ: 2610113584Ssimokawa case FWTCODE_RRESQ: 2611113584Ssimokawa case FWOHCITCODE_PHY: 2612113584Ssimokawa slen = 12; 2613113584Ssimokawa break; 2614113584Ssimokawa case FWTCODE_RREQB: 2615113584Ssimokawa case FWTCODE_WREQB: 2616113584Ssimokawa case FWTCODE_LREQ: 2617113584Ssimokawa case FWTCODE_RRESB: 2618113584Ssimokawa case FWTCODE_LRES: 2619113584Ssimokawa slen = 16; 2620113584Ssimokawa break; 2621113584Ssimokawa default: 2622113584Ssimokawa printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2623113584Ssimokawa return(0); 2624103285Sikob } 2625120660Ssimokawa hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2626120660Ssimokawa if (hlen > len) { 2627113584Ssimokawa if (firewire_debug) 2628113584Ssimokawa printf("splitted header\n"); 2629120660Ssimokawa return(-hlen); 2630103285Sikob } 2631113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2632113584Ssimokawa for(i = 0; i < slen/4; i ++) 2633113584Ssimokawa fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2634113584Ssimokawa#endif 2635120660Ssimokawa return(hlen); 2636103285Sikob} 2637103285Sikob 2638103285Sikobstatic int 2639113584Ssimokawafwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2640103285Sikob{ 2641120660Ssimokawa struct tcode_info *info; 2642113584Ssimokawa int r; 2643103285Sikob 2644120660Ssimokawa info = &tinfo[fp->mode.common.tcode]; 2645120660Ssimokawa r = info->hdr_len + sizeof(u_int32_t); 2646120660Ssimokawa if ((info->flag & FWTI_BLOCK_ASY) != 0) 2647120660Ssimokawa r += roundup2(fp->mode.wreqb.len, sizeof(u_int32_t)); 2648120660Ssimokawa 2649120660Ssimokawa if (r == sizeof(u_int32_t)) 2650120660Ssimokawa /* XXX */ 2651110798Ssimokawa device_printf(sc->fc.dev, "Unknown tcode %d\n", 2652110798Ssimokawa fp->mode.common.tcode); 2653120660Ssimokawa 2654110798Ssimokawa if (r > dbch->xferq.psize) { 2655110798Ssimokawa device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2656110798Ssimokawa /* panic ? */ 2657110798Ssimokawa } 2658120660Ssimokawa 2659110798Ssimokawa return r; 2660103285Sikob} 2661103285Sikob 2662106790Ssimokawastatic void 2663113584Ssimokawafwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr) 2664113584Ssimokawa{ 2665120660Ssimokawa struct fwohcidb *db = &db_tr->db[0]; 2666113584Ssimokawa 2667113584Ssimokawa FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2668113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2669113584Ssimokawa FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2670113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 2671113584Ssimokawa dbch->bottom = db_tr; 2672113584Ssimokawa} 2673113584Ssimokawa 2674113584Ssimokawastatic void 2675106790Ssimokawafwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2676103285Sikob{ 2677103285Sikob struct fwohcidb_tr *db_tr; 2678113584Ssimokawa struct iovec vec[2]; 2679113584Ssimokawa struct fw_pkt pktbuf; 2680113584Ssimokawa int nvec; 2681103285Sikob struct fw_pkt *fp; 2682103285Sikob u_int8_t *ld; 2683113584Ssimokawa u_int32_t stat, off, status; 2684103285Sikob u_int spd; 2685113584Ssimokawa int len, plen, hlen, pcnt, offset; 2686103285Sikob int s; 2687103285Sikob caddr_t buf; 2688103285Sikob int resCount; 2689103285Sikob 2690103285Sikob if(&sc->arrq == dbch){ 2691103285Sikob off = OHCI_ARQOFF; 2692103285Sikob }else if(&sc->arrs == dbch){ 2693103285Sikob off = OHCI_ARSOFF; 2694103285Sikob }else{ 2695103285Sikob return; 2696103285Sikob } 2697103285Sikob 2698103285Sikob s = splfw(); 2699103285Sikob db_tr = dbch->top; 2700103285Sikob pcnt = 0; 2701103285Sikob /* XXX we cannot handle a packet which lies in more than two buf */ 2702113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 2703113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 2704113584Ssimokawa status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2705113584Ssimokawa resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2706113584Ssimokawa#if 0 2707113584Ssimokawa printf("status 0x%04x, resCount 0x%04x\n", status, resCount); 2708113584Ssimokawa#endif 2709113584Ssimokawa while (status & OHCI_CNTL_DMA_ACTIVE) { 2710113584Ssimokawa len = dbch->xferq.psize - resCount; 2711113584Ssimokawa ld = (u_int8_t *)db_tr->buf; 2712113584Ssimokawa if (dbch->pdb_tr == NULL) { 2713113584Ssimokawa len -= dbch->buf_offset; 2714113584Ssimokawa ld += dbch->buf_offset; 2715113584Ssimokawa } 2716113584Ssimokawa if (len > 0) 2717113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2718113584Ssimokawa BUS_DMASYNC_POSTREAD); 2719103285Sikob while (len > 0 ) { 2720106789Ssimokawa if (count >= 0 && count-- == 0) 2721106789Ssimokawa goto out; 2722113584Ssimokawa if(dbch->pdb_tr != NULL){ 2723113584Ssimokawa /* we have a fragment in previous buffer */ 2724113584Ssimokawa int rlen; 2725103285Sikob 2726113584Ssimokawa offset = dbch->buf_offset; 2727113584Ssimokawa if (offset < 0) 2728113584Ssimokawa offset = - offset; 2729113584Ssimokawa buf = dbch->pdb_tr->buf + offset; 2730113584Ssimokawa rlen = dbch->xferq.psize - offset; 2731113584Ssimokawa if (firewire_debug) 2732113584Ssimokawa printf("rlen=%d, offset=%d\n", 2733113584Ssimokawa rlen, dbch->buf_offset); 2734113584Ssimokawa if (dbch->buf_offset < 0) { 2735113584Ssimokawa /* splitted in header, pull up */ 2736113584Ssimokawa char *p; 2737113584Ssimokawa 2738113584Ssimokawa p = (char *)&pktbuf; 2739113584Ssimokawa bcopy(buf, p, rlen); 2740113584Ssimokawa p += rlen; 2741113584Ssimokawa /* this must be too long but harmless */ 2742113584Ssimokawa rlen = sizeof(pktbuf) - rlen; 2743113584Ssimokawa if (rlen < 0) 2744113584Ssimokawa printf("why rlen < 0\n"); 2745113584Ssimokawa bcopy(db_tr->buf, p, rlen); 2746103285Sikob ld += rlen; 2747103285Sikob len -= rlen; 2748113584Ssimokawa hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2749113584Ssimokawa if (hlen < 0) { 2750113584Ssimokawa printf("hlen < 0 shouldn't happen"); 2751113584Ssimokawa } 2752113584Ssimokawa offset = sizeof(pktbuf); 2753113584Ssimokawa vec[0].iov_base = (char *)&pktbuf; 2754113584Ssimokawa vec[0].iov_len = offset; 2755113584Ssimokawa } else { 2756113584Ssimokawa /* splitted in payload */ 2757113584Ssimokawa offset = rlen; 2758113584Ssimokawa vec[0].iov_base = buf; 2759113584Ssimokawa vec[0].iov_len = rlen; 2760103285Sikob } 2761113584Ssimokawa fp=(struct fw_pkt *)vec[0].iov_base; 2762113584Ssimokawa nvec = 1; 2763113584Ssimokawa } else { 2764113584Ssimokawa /* no fragment in previous buffer */ 2765103285Sikob fp=(struct fw_pkt *)ld; 2766113584Ssimokawa hlen = fwohci_arcv_swap(fp, len); 2767113584Ssimokawa if (hlen == 0) 2768113584Ssimokawa /* XXX need reset */ 2769103285Sikob goto out; 2770113584Ssimokawa if (hlen < 0) { 2771113584Ssimokawa dbch->pdb_tr = db_tr; 2772113584Ssimokawa dbch->buf_offset = - dbch->buf_offset; 2773113584Ssimokawa /* sanity check */ 2774113584Ssimokawa if (resCount != 0) 2775124145Ssimokawa printf("resCount = %d !?\n", 2776124145Ssimokawa resCount); 2777124145Ssimokawa /* XXX clear pdb_tr */ 2778113584Ssimokawa goto out; 2779103285Sikob } 2780113584Ssimokawa offset = 0; 2781113584Ssimokawa nvec = 0; 2782113584Ssimokawa } 2783113584Ssimokawa plen = fwohci_get_plen(sc, dbch, fp) - offset; 2784113584Ssimokawa if (plen < 0) { 2785113584Ssimokawa /* minimum header size + trailer 2786113584Ssimokawa = sizeof(fw_pkt) so this shouldn't happens */ 2787120660Ssimokawa printf("plen(%d) is negative! offset=%d\n", 2788120660Ssimokawa plen, offset); 2789124145Ssimokawa /* XXX clear pdb_tr */ 2790113584Ssimokawa goto out; 2791113584Ssimokawa } 2792113584Ssimokawa if (plen > 0) { 2793113584Ssimokawa len -= plen; 2794113584Ssimokawa if (len < 0) { 2795113584Ssimokawa dbch->pdb_tr = db_tr; 2796113584Ssimokawa if (firewire_debug) 2797113584Ssimokawa printf("splitted payload\n"); 2798113584Ssimokawa /* sanity check */ 2799113584Ssimokawa if (resCount != 0) 2800124145Ssimokawa printf("resCount = %d !?\n", 2801124145Ssimokawa resCount); 2802124145Ssimokawa /* XXX clear pdb_tr */ 2803113584Ssimokawa goto out; 2804103285Sikob } 2805113584Ssimokawa vec[nvec].iov_base = ld; 2806113584Ssimokawa vec[nvec].iov_len = plen; 2807113584Ssimokawa nvec ++; 2808103285Sikob ld += plen; 2809103285Sikob } 2810113584Ssimokawa dbch->buf_offset = ld - (u_int8_t *)db_tr->buf; 2811113584Ssimokawa if (nvec == 0) 2812113584Ssimokawa printf("nvec == 0\n"); 2813113584Ssimokawa 2814103285Sikob/* DMA result-code will be written at the tail of packet */ 2815113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2816113584Ssimokawa stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16; 2817113584Ssimokawa#else 2818113584Ssimokawa stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2819113584Ssimokawa#endif 2820110577Ssimokawa#if 0 2821120660Ssimokawa printf("plen: %d, stat %x\n", 2822120660Ssimokawa plen ,stat); 2823103285Sikob#endif 2824113584Ssimokawa spd = (stat >> 5) & 0x3; 2825113584Ssimokawa stat &= 0x1f; 2826113584Ssimokawa switch(stat){ 2827113584Ssimokawa case FWOHCIEV_ACKPEND: 2828113584Ssimokawa#if 0 2829113584Ssimokawa printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2830113584Ssimokawa#endif 2831113584Ssimokawa /* fall through */ 2832113584Ssimokawa case FWOHCIEV_ACKCOMPL: 2833120660Ssimokawa { 2834120660Ssimokawa struct fw_rcv_buf rb; 2835120660Ssimokawa 2836113584Ssimokawa if ((vec[nvec-1].iov_len -= 2837113584Ssimokawa sizeof(struct fwohci_trailer)) == 0) 2838113584Ssimokawa nvec--; 2839120660Ssimokawa rb.fc = &sc->fc; 2840120660Ssimokawa rb.vec = vec; 2841120660Ssimokawa rb.nvec = nvec; 2842120660Ssimokawa rb.spd = spd; 2843120660Ssimokawa fw_rcv(&rb); 2844120660Ssimokawa break; 2845120660Ssimokawa } 2846113584Ssimokawa case FWOHCIEV_BUSRST: 2847113584Ssimokawa if (sc->fc.status != FWBUSRESET) 2848113584Ssimokawa printf("got BUSRST packet!?\n"); 2849113584Ssimokawa break; 2850113584Ssimokawa default: 2851113584Ssimokawa device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2852103285Sikob#if 0 /* XXX */ 2853113584Ssimokawa goto out; 2854103285Sikob#endif 2855113584Ssimokawa break; 2856103285Sikob } 2857103285Sikob pcnt ++; 2858113584Ssimokawa if (dbch->pdb_tr != NULL) { 2859113584Ssimokawa fwohci_arcv_free_buf(dbch, dbch->pdb_tr); 2860113584Ssimokawa dbch->pdb_tr = NULL; 2861113584Ssimokawa } 2862113584Ssimokawa 2863113584Ssimokawa } 2864103285Sikobout: 2865103285Sikob if (resCount == 0) { 2866103285Sikob /* done on this buffer */ 2867113584Ssimokawa if (dbch->pdb_tr == NULL) { 2868113584Ssimokawa fwohci_arcv_free_buf(dbch, db_tr); 2869113584Ssimokawa dbch->buf_offset = 0; 2870113584Ssimokawa } else 2871113584Ssimokawa if (dbch->pdb_tr != db_tr) 2872113584Ssimokawa printf("pdb_tr != db_tr\n"); 2873103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2874113584Ssimokawa status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2875113584Ssimokawa >> OHCI_STATUS_SHIFT; 2876113584Ssimokawa resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2877113584Ssimokawa & OHCI_COUNT_MASK; 2878113584Ssimokawa /* XXX check buffer overrun */ 2879103285Sikob dbch->top = db_tr; 2880103285Sikob } else { 2881103285Sikob dbch->buf_offset = dbch->xferq.psize - resCount; 2882103285Sikob break; 2883103285Sikob } 2884103285Sikob /* XXX make sure DMA is not dead */ 2885103285Sikob } 2886103285Sikob#if 0 2887103285Sikob if (pcnt < 1) 2888103285Sikob printf("fwohci_arcv: no packets\n"); 2889103285Sikob#endif 2890103285Sikob splx(s); 2891103285Sikob} 2892