fwohci.c revision 124836
1227569Sphilip/* 2300607Sarybchik * Copyright (c) 2003 Hidetoshi Shimokawa 3227569Sphilip * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4227569Sphilip * All rights reserved. 5227569Sphilip * 6227569Sphilip * Redistribution and use in source and binary forms, with or without 7227569Sphilip * modification, are permitted provided that the following conditions 8227569Sphilip * are met: 9283514Sarybchik * 1. Redistributions of source code must retain the above copyright 10227569Sphilip * notice, this list of conditions and the following disclaimer. 11283514Sarybchik * 2. Redistributions in binary form must reproduce the above copyright 12283514Sarybchik * notice, this list of conditions and the following disclaimer in the 13283514Sarybchik * documentation and/or other materials provided with the distribution. 14283514Sarybchik * 3. All advertising materials mentioning features or use of this software 15283514Sarybchik * must display the acknowledgement as bellow: 16227569Sphilip * 17283514Sarybchik * This product includes software developed by K. Kobayashi and H. Shimokawa 18283514Sarybchik * 19283514Sarybchik * 4. The name of the author may not be used to endorse or promote products 20283514Sarybchik * derived from this software without specific prior written permission. 21283514Sarybchik * 22283514Sarybchik * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23283514Sarybchik * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24283514Sarybchik * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25283514Sarybchik * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26283514Sarybchik * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27283514Sarybchik * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28283514Sarybchik * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29283514Sarybchik * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30283514Sarybchik * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31283514Sarybchik * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32283514Sarybchik * POSSIBILITY OF SUCH DAMAGE. 33227569Sphilip * 34227569Sphilip * $FreeBSD: head/sys/dev/firewire/fwohci.c 124836 2004-01-22 14:41:17Z simokawa $ 35227569Sphilip * 36227569Sphilip */ 37272325Sgnn 38227569Sphilip#define ATRQ_CH 0 39227569Sphilip#define ATRS_CH 1 40227569Sphilip#define ARRQ_CH 2 41227569Sphilip#define ARRS_CH 3 42227569Sphilip#define ITX_CH 4 43227569Sphilip#define IRX_CH 0x24 44227569Sphilip 45227569Sphilip#include <sys/param.h> 46227569Sphilip#include <sys/systm.h> 47227569Sphilip#include <sys/mbuf.h> 48257176Sglebius#include <sys/malloc.h> 49227569Sphilip#include <sys/sockio.h> 50227569Sphilip#include <sys/bus.h> 51227569Sphilip#include <sys/kernel.h> 52283514Sarybchik#include <sys/conf.h> 53283514Sarybchik#include <sys/endian.h> 54227569Sphilip 55283514Sarybchik#include <machine/bus.h> 56283514Sarybchik 57283514Sarybchik#if __FreeBSD_version < 500000 58283514Sarybchik#include <machine/clock.h> /* for DELAY() */ 59283514Sarybchik#endif 60283514Sarybchik 61283514Sarybchik#include <dev/firewire/firewire.h> 62283514Sarybchik#include <dev/firewire/firewirereg.h> 63283514Sarybchik#include <dev/firewire/fwdma.h> 64283514Sarybchik#include <dev/firewire/fwohcireg.h> 65227569Sphilip#include <dev/firewire/fwohcivar.h> 66227569Sphilip#include <dev/firewire/firewire_phy.h> 67227569Sphilip 68227569Sphilip#undef OHCI_DEBUG 69227569Sphilip 70227569Sphilipstatic char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 71272325Sgnn "STOR","LOAD","NOP ","STOP",}; 72227569Sphilip 73280432Sarybchikstatic char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 74227569Sphilip "UNDEF","REG","SYS","DEV"}; 75272325Sgnnstatic char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 76227569Sphilipchar fwohcicode[32][0x20]={ 77280432Sarybchik "No stat","Undef","long","miss Ack err", 78227569Sphilip "underrun","overrun","desc err", "data read err", 79272325Sgnn "data write err","bus reset","timeout","tcode err", 80227569Sphilip "Undef","Undef","unknown event","flushed", 81280432Sarybchik "Undef","ack complete","ack pend","Undef", 82227569Sphilip "ack busy_X","ack busy_A","ack busy_B","Undef", 83272325Sgnn "Undef","Undef","Undef","ack tardy", 84227569Sphilip "Undef","ack data_err","ack type_err",""}; 85280432Sarybchik 86227569Sphilip#define MAX_SPEED 3 87272325Sgnnextern char *linkspeed[]; 88227569Sphilipu_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 89280432Sarybchik 90283514Sarybchikstatic struct tcode_info tinfo[] = { 91283514Sarybchik/* hdr_len block flag*/ 92283514Sarybchik/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 93283514Sarybchik/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 94227569Sphilip/* 2 WRES */ {12, FWTI_RES}, 95227569Sphilip/* 3 XXX */ { 0, 0}, 96272325Sgnn/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 97227569Sphilip/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 98280432Sarybchik/* 6 RRESQ */ {16, FWTI_RES}, 99227569Sphilip/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 100272325Sgnn/* 8 CYCS */ { 0, 0}, 101227569Sphilip/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 102280432Sarybchik/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 103227569Sphilip/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 104272325Sgnn/* c XXX */ { 0, 0}, 105227569Sphilip/* d XXX */ { 0, 0}, 106227569Sphilip/* e PHY */ {12, FWTI_REQ}, 107227569Sphilip/* f XXX */ { 0, 0} 108227569Sphilip}; 109227569Sphilip 110272328Sgnn#define OHCI_WRITE_SIGMASK 0xffff0000 111272328Sgnn#define OHCI_READ_SIGMASK 0xffff0000 112272325Sgnn 113227569Sphilip#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 114272325Sgnn#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 115227569Sphilip 116301067Sarybchikstatic void fwohci_ibr (struct firewire_comm *); 117301067Sarybchikstatic void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); 118301067Sarybchikstatic void fwohci_db_free (struct fwohci_dbch *); 119301067Sarybchikstatic void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); 120301067Sarybchikstatic void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); 121301067Sarybchikstatic void fwohci_start_atq (struct firewire_comm *); 122301067Sarybchikstatic void fwohci_start_ats (struct firewire_comm *); 123301075Sarybchikstatic void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); 124301075Sarybchikstatic u_int32_t fwphy_wrdata ( struct fwohci_softc *, u_int32_t, u_int32_t); 125301075Sarybchikstatic u_int32_t fwphy_rddata ( struct fwohci_softc *, u_int32_t); 126301075Sarybchikstatic int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); 127301075Sarybchikstatic int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); 128301075Sarybchikstatic int fwohci_irx_enable (struct firewire_comm *, int); 129301067Sarybchikstatic int fwohci_irx_disable (struct firewire_comm *, int); 130301075Sarybchik#if BYTE_ORDER == BIG_ENDIAN 131301075Sarybchikstatic void fwohci_irx_post (struct firewire_comm *, u_int32_t *); 132301067Sarybchik#endif 133301105Sarybchikstatic int fwohci_itxbuf_enable (struct firewire_comm *, int); 134301105Sarybchikstatic int fwohci_itx_disable (struct firewire_comm *, int); 135301105Sarybchikstatic void fwohci_timeout (void *); 136301105Sarybchikstatic void fwohci_set_intr (struct firewire_comm *, int); 137301105Sarybchik 138301105Sarybchikstatic int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); 139301105Sarybchikstatic int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); 140301105Sarybchikstatic void dump_db (struct fwohci_softc *, u_int32_t); 141301105Sarybchikstatic void print_db (struct fwohcidb_tr *, struct fwohcidb *, u_int32_t , u_int32_t); 142301105Sarybchikstatic void dump_dma (struct fwohci_softc *, u_int32_t); 143301105Sarybchikstatic u_int32_t fwohci_cyctimer (struct firewire_comm *); 144301105Sarybchikstatic void fwohci_rbuf_update (struct fwohci_softc *, int); 145301105Sarybchikstatic void fwohci_tbuf_update (struct fwohci_softc *, int); 146301105Sarybchikvoid fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); 147301105Sarybchik#if FWOHCI_TASKQUEUE 148301105Sarybchikstatic void fwohci_complete(void *, int); 149301105Sarybchik#endif 150301105Sarybchik 151301105Sarybchik/* 152301105Sarybchik * memory allocated for DMA programs 153227569Sphilip */ 154227569Sphilip#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 155227569Sphilip 156227569Sphilip#define NDB FWMAXQUEUE 157227569Sphilip 158227569Sphilip#define OHCI_VERSION 0x00 159227569Sphilip#define OHCI_ATRETRY 0x08 160227569Sphilip#define OHCI_CROMHDR 0x18 161227569Sphilip#define OHCI_BUS_OPT 0x20 162227569Sphilip#define OHCI_BUSIRMC (1 << 31) 163277887Sarybchik#define OHCI_BUSCMC (1 << 30) 164277887Sarybchik#define OHCI_BUSISC (1 << 29) 165277887Sarybchik#define OHCI_BUSBMC (1 << 28) 166277887Sarybchik#define OHCI_BUSPMC (1 << 27) 167227569Sphilip#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 168227569Sphilip OHCI_BUSBMC | OHCI_BUSPMC 169227569Sphilip 170227569Sphilip#define OHCI_EUID_HI 0x24 171277887Sarybchik#define OHCI_EUID_LO 0x28 172227569Sphilip 173227569Sphilip#define OHCI_CROMPTR 0x34 174227569Sphilip#define OHCI_HCCCTL 0x50 175227569Sphilip#define OHCI_HCCCTLCLR 0x54 176227569Sphilip#define OHCI_AREQHI 0x100 177227569Sphilip#define OHCI_AREQHICLR 0x104 178227569Sphilip#define OHCI_AREQLO 0x108 179277887Sarybchik#define OHCI_AREQLOCLR 0x10c 180277887Sarybchik#define OHCI_PREQHI 0x110 181277887Sarybchik#define OHCI_PREQHICLR 0x114 182278250Sarybchik#define OHCI_PREQLO 0x118 183277887Sarybchik#define OHCI_PREQLOCLR 0x11c 184277887Sarybchik#define OHCI_PREQUPPER 0x120 185227569Sphilip 186227569Sphilip#define OHCI_SID_BUF 0x64 187227569Sphilip#define OHCI_SID_CNT 0x68 188227569Sphilip#define OHCI_SID_ERR (1 << 31) 189227569Sphilip#define OHCI_SID_CNT_MASK 0xffc 190227569Sphilip 191227569Sphilip#define OHCI_IT_STAT 0x90 192227569Sphilip#define OHCI_IT_STATCLR 0x94 193227569Sphilip#define OHCI_IT_MASK 0x98 194227569Sphilip#define OHCI_IT_MASKCLR 0x9c 195227569Sphilip 196272325Sgnn#define OHCI_IR_STAT 0xa0 197272325Sgnn#define OHCI_IR_STATCLR 0xa4 198272325Sgnn#define OHCI_IR_MASK 0xa8 199227569Sphilip#define OHCI_IR_MASKCLR 0xac 200227569Sphilip 201227569Sphilip#define OHCI_LNKCTL 0xe0 202227569Sphilip#define OHCI_LNKCTLCLR 0xe4 203227569Sphilip 204227569Sphilip#define OHCI_PHYACCESS 0xec 205227569Sphilip#define OHCI_CYCLETIMER 0xf0 206227569Sphilip 207227569Sphilip#define OHCI_DMACTL(off) (off) 208227569Sphilip#define OHCI_DMACTLCLR(off) (off + 4) 209227569Sphilip#define OHCI_DMACMD(off) (off + 0xc) 210227569Sphilip#define OHCI_DMAMATCH(off) (off + 0x10) 211227569Sphilip 212227569Sphilip#define OHCI_ATQOFF 0x180 213227569Sphilip#define OHCI_ATQCTL OHCI_ATQOFF 214227569Sphilip#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 215227569Sphilip#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 216227569Sphilip#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 217227569Sphilip 218227569Sphilip#define OHCI_ATSOFF 0x1a0 219227569Sphilip#define OHCI_ATSCTL OHCI_ATSOFF 220283514Sarybchik#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 221227569Sphilip#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 222227569Sphilip#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 223278250Sarybchik 224278250Sarybchik#define OHCI_ARQOFF 0x1c0 225278250Sarybchik#define OHCI_ARQCTL OHCI_ARQOFF 226227569Sphilip#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 227227569Sphilip#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 228227569Sphilip#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 229227569Sphilip 230227569Sphilip#define OHCI_ARSOFF 0x1e0 231227569Sphilip#define OHCI_ARSCTL OHCI_ARSOFF 232227569Sphilip#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 233227569Sphilip#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 234227569Sphilip#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 235227569Sphilip 236227569Sphilip#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 237227569Sphilip#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 238227569Sphilip#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 239227569Sphilip#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 240227569Sphilip 241227569Sphilip#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 242227569Sphilip#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 243227569Sphilip#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 244227569Sphilip#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 245227569Sphilip#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 246227569Sphilip 247227569Sphilipd_ioctl_t fwohci_ioctl; 248227569Sphilip 249227569Sphilip/* 250283514Sarybchik * Communication with PHY device 251283514Sarybchik */ 252283514Sarybchikstatic u_int32_t 253278250Sarybchikfwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 254278250Sarybchik{ 255278250Sarybchik u_int32_t fun; 256227569Sphilip 257227569Sphilip addr &= 0xf; 258227569Sphilip data &= 0xff; 259227569Sphilip 260227569Sphilip fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 261227569Sphilip OWRITE(sc, OHCI_PHYACCESS, fun); 262227569Sphilip DELAY(100); 263227569Sphilip 264227569Sphilip return(fwphy_rddata( sc, addr)); 265227569Sphilip} 266227569Sphilip 267227569Sphilipstatic u_int32_t 268278250Sarybchikfwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 269227569Sphilip{ 270272325Sgnn struct fwohci_softc *sc = (struct fwohci_softc *)fc; 271227569Sphilip int i; 272227569Sphilip u_int32_t bm; 273272330Sgnn 274227569Sphilip#define OHCI_CSR_DATA 0x0c 275227569Sphilip#define OHCI_CSR_COMP 0x10 276227569Sphilip#define OHCI_CSR_CONT 0x14 277227569Sphilip#define OHCI_BUS_MANAGER_ID 0 278227569Sphilip 279227569Sphilip OWRITE(sc, OHCI_CSR_DATA, node); 280227569Sphilip OWRITE(sc, OHCI_CSR_COMP, 0x3f); 281278250Sarybchik OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 282227569Sphilip for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 283272328Sgnn DELAY(10); 284272328Sgnn bm = OREAD(sc, OHCI_CSR_DATA); 285272328Sgnn if((bm & 0x3f) == 0x3f) 286272325Sgnn bm = node; 287227569Sphilip if (bootverbose) 288227569Sphilip device_printf(sc->fc.dev, 289227569Sphilip "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 290227569Sphilip 291227569Sphilip return(bm); 292227569Sphilip} 293227569Sphilip 294227569Sphilipstatic u_int32_t 295227569Sphilipfwphy_rddata(struct fwohci_softc *sc, u_int addr) 296277886Sarybchik{ 297227569Sphilip u_int32_t fun, stat; 298227569Sphilip u_int i, retry = 0; 299277886Sarybchik 300227569Sphilip addr &= 0xf; 301277894Sarybchik#define MAX_RETRY 100 302227569Sphilipagain: 303227569Sphilip OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 304310831Sarybchik fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 305227569Sphilip OWRITE(sc, OHCI_PHYACCESS, fun); 306227569Sphilip for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 307227569Sphilip fun = OREAD(sc, OHCI_PHYACCESS); 308227569Sphilip if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 309227569Sphilip break; 310227569Sphilip DELAY(100); 311227569Sphilip } 312283514Sarybchik if(i >= MAX_RETRY) { 313294996Sglebius if (bootverbose) 314227569Sphilip device_printf(sc->fc.dev, "phy read failed(1).\n"); 315283514Sarybchik if (++retry < MAX_RETRY) { 316278940Sarybchik DELAY(100); 317278939Sarybchik goto again; 318278938Sarybchik } 319283514Sarybchik } 320294077Sarybchik /* Make sure that SCLK is started */ 321294077Sarybchik stat = OREAD(sc, FWOHCI_INTSTAT); 322294077Sarybchik if ((stat & OHCI_INT_REG_FAIL) != 0 || 323294077Sarybchik ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 324291843Sarybchik if (bootverbose) 325291843Sarybchik device_printf(sc->fc.dev, "phy read failed(2).\n"); 326291843Sarybchik if (++retry < MAX_RETRY) { 327227569Sphilip DELAY(100); 328227569Sphilip goto again; 329311764Sarybchik } 330311764Sarybchik } 331311764Sarybchik if (bootverbose || retry >= MAX_RETRY) 332272325Sgnn device_printf(sc->fc.dev, 333227569Sphilip "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 334272328Sgnn#undef MAX_RETRY 335272328Sgnn return((fun >> PHYDEV_RDDATA )& 0xff); 336272328Sgnn} 337272328Sgnn/* Device specific ioctl. */ 338227569Sphilipint 339227569Sphilipfwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 340227569Sphilip{ 341227569Sphilip struct firewire_softc *sc; 342227569Sphilip struct fwohci_softc *fc; 343227569Sphilip int unit = DEV2UNIT(dev); 344227569Sphilip int err = 0; 345227569Sphilip struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 346227569Sphilip u_int32_t *dmach = (u_int32_t *) data; 347227569Sphilip 348227569Sphilip sc = devclass_get_softc(firewire_devclass, unit); 349227569Sphilip if(sc == NULL){ 350227569Sphilip return(EINVAL); 351283514Sarybchik } 352227569Sphilip fc = (struct fwohci_softc *)sc->fc; 353227569Sphilip 354283514Sarybchik if (!data) 355283514Sarybchik return(EINVAL); 356283514Sarybchik 357227569Sphilip switch (cmd) { 358227569Sphilip case FWOHCI_WRREG: 359227569Sphilip#define OHCI_MAX_REG 0x800 360227569Sphilip if(reg->addr <= OHCI_MAX_REG){ 361227569Sphilip OWRITE(fc, reg->addr, reg->data); 362227569Sphilip reg->data = OREAD(fc, reg->addr); 363227569Sphilip }else{ 364227569Sphilip err = EINVAL; 365277884Sarybchik } 366227569Sphilip break; 367227569Sphilip case FWOHCI_RDREG: 368227569Sphilip if(reg->addr <= OHCI_MAX_REG){ 369227569Sphilip reg->data = OREAD(fc, reg->addr); 370227569Sphilip }else{ 371227569Sphilip err = EINVAL; 372227569Sphilip } 373227569Sphilip break; 374227569Sphilip/* Read DMA descriptors for debug */ 375227569Sphilip case DUMPDMA: 376227569Sphilip if(*dmach <= OHCI_MAX_DMA_CH ){ 377227569Sphilip dump_dma(fc, *dmach); 378227569Sphilip dump_db(fc, *dmach); 379227569Sphilip }else{ 380283514Sarybchik err = EINVAL; 381227569Sphilip } 382227569Sphilip break; 383283514Sarybchik/* Read/Write Phy registers */ 384283514Sarybchik#define OHCI_MAX_PHY_REG 0xf 385283514Sarybchik case FWOHCI_RDPHYREG: 386283514Sarybchik if (reg->addr <= OHCI_MAX_PHY_REG) 387283514Sarybchik reg->data = fwphy_rddata(fc, reg->addr); 388227569Sphilip else 389227569Sphilip err = EINVAL; 390227569Sphilip break; 391227569Sphilip case FWOHCI_WRPHYREG: 392227569Sphilip if (reg->addr <= OHCI_MAX_PHY_REG) 393227569Sphilip reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 394227569Sphilip else 395283514Sarybchik err = EINVAL; 396227569Sphilip break; 397227569Sphilip default: 398279184Sarybchik err = EINVAL; 399227569Sphilip break; 400272325Sgnn } 401227569Sphilip return err; 402278250Sarybchik} 403278250Sarybchik 404278250Sarybchikstatic int 405278250Sarybchikfwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 406278250Sarybchik{ 407278250Sarybchik u_int32_t reg, reg2; 408278250Sarybchik int e1394a = 1; 409278250Sarybchik/* 410278250Sarybchik * probe PHY parameters 411278221Sarybchik * 0. to prove PHY version, whether compliance of 1394a. 412278221Sarybchik * 1. to probe maximum speed supported by the PHY and 413278221Sarybchik * number of port supported by core-logic. 414278221Sarybchik * It is not actually available port on your PC . 415278221Sarybchik */ 416278221Sarybchik OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 417278221Sarybchik reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 418278221Sarybchik 419278221Sarybchik if((reg >> 5) != 7 ){ 420278250Sarybchik sc->fc.mode &= ~FWPHYASYST; 421278250Sarybchik sc->fc.nport = reg & FW_PHY_NP; 422278250Sarybchik sc->fc.speed = reg & FW_PHY_SPD >> 6; 423278250Sarybchik if (sc->fc.speed > MAX_SPEED) { 424278250Sarybchik device_printf(dev, "invalid speed %d (fixed to %d).\n", 425278250Sarybchik sc->fc.speed, MAX_SPEED); 426278250Sarybchik sc->fc.speed = MAX_SPEED; 427278250Sarybchik } 428278250Sarybchik device_printf(dev, 429278250Sarybchik "Phy 1394 only %s, %d ports.\n", 430278221Sarybchik linkspeed[sc->fc.speed], sc->fc.nport); 431278221Sarybchik }else{ 432278221Sarybchik reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 433278221Sarybchik sc->fc.mode |= FWPHYASYST; 434278221Sarybchik sc->fc.nport = reg & FW_PHY_NP; 435278221Sarybchik sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 436278221Sarybchik if (sc->fc.speed > MAX_SPEED) { 437278221Sarybchik device_printf(dev, "invalid speed %d (fixed to %d).\n", 438278221Sarybchik sc->fc.speed, MAX_SPEED); 439278250Sarybchik sc->fc.speed = MAX_SPEED; 440278250Sarybchik } 441278250Sarybchik device_printf(dev, 442278250Sarybchik "Phy 1394a available %s, %d ports.\n", 443278250Sarybchik linkspeed[sc->fc.speed], sc->fc.nport); 444278250Sarybchik 445278250Sarybchik /* check programPhyEnable */ 446278250Sarybchik reg2 = fwphy_rddata(sc, 5); 447278250Sarybchik#if 0 448278250Sarybchik if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 449278221Sarybchik#else /* XXX force to enable 1394a */ 450278221Sarybchik if (e1394a) { 451278221Sarybchik#endif 452278221Sarybchik if (bootverbose) 453278221Sarybchik device_printf(dev, 454278221Sarybchik "Enable 1394a Enhancements\n"); 455278221Sarybchik /* enable EAA EMC */ 456278221Sarybchik reg2 |= 0x03; 457278221Sarybchik /* set aPhyEnhanceEnable */ 458278250Sarybchik OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 459278250Sarybchik OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 460278250Sarybchik } else { 461278250Sarybchik /* for safe */ 462278250Sarybchik reg2 &= ~0x83; 463278250Sarybchik } 464278250Sarybchik reg2 = fwphy_wrdata(sc, 5, reg2); 465278250Sarybchik } 466278250Sarybchik 467278250Sarybchik reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 468278221Sarybchik if((reg >> 5) == 7 ){ 469278221Sarybchik reg = fwphy_rddata(sc, 4); 470278221Sarybchik reg |= 1 << 6; 471278221Sarybchik fwphy_wrdata(sc, 4, reg); 472278221Sarybchik reg = fwphy_rddata(sc, 4); 473278221Sarybchik } 474278221Sarybchik return 0; 475278221Sarybchik} 476278221Sarybchik 477227569Sphilip 478void 479fwohci_reset(struct fwohci_softc *sc, device_t dev) 480{ 481 int i, max_rec, speed; 482 u_int32_t reg, reg2; 483 struct fwohcidb_tr *db_tr; 484 485 /* Disable interrupt */ 486 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 487 488 /* Now stopping all DMA channel */ 489 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 490 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 491 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 492 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 493 494 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 495 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 496 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 497 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 498 } 499 500 /* FLUSH FIFO and reset Transmitter/Reciever */ 501 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 502 if (bootverbose) 503 device_printf(dev, "resetting OHCI..."); 504 i = 0; 505 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 506 if (i++ > 100) break; 507 DELAY(1000); 508 } 509 if (bootverbose) 510 printf("done (loop=%d)\n", i); 511 512 /* Probe phy */ 513 fwohci_probe_phy(sc, dev); 514 515 /* Probe link */ 516 reg = OREAD(sc, OHCI_BUS_OPT); 517 reg2 = reg | OHCI_BUSFNC; 518 max_rec = (reg & 0x0000f000) >> 12; 519 speed = (reg & 0x00000007); 520 device_printf(dev, "Link %s, max_rec %d bytes.\n", 521 linkspeed[speed], MAXREC(max_rec)); 522 /* XXX fix max_rec */ 523 sc->fc.maxrec = sc->fc.speed + 8; 524 if (max_rec != sc->fc.maxrec) { 525 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 526 device_printf(dev, "max_rec %d -> %d\n", 527 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 528 } 529 if (bootverbose) 530 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 531 OWRITE(sc, OHCI_BUS_OPT, reg2); 532 533 /* Initialize registers */ 534 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 535 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 536 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 537 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 538 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 539 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 540 fw_busreset(&sc->fc); 541 542 /* Enable link */ 543 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 544 545 /* Force to start async RX DMA */ 546 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 547 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 548 fwohci_rx_enable(sc, &sc->arrq); 549 fwohci_rx_enable(sc, &sc->arrs); 550 551 /* Initialize async TX */ 552 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 553 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 554 555 /* AT Retries */ 556 OWRITE(sc, FWOHCI_RETRY, 557 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 558 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 559 560 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 561 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 562 sc->atrq.bottom = sc->atrq.top; 563 sc->atrs.bottom = sc->atrs.top; 564 565 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 566 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 567 db_tr->xfer = NULL; 568 } 569 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 570 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 571 db_tr->xfer = NULL; 572 } 573 574 575 /* Enable interrupt */ 576 OWRITE(sc, FWOHCI_INTMASK, 577 OHCI_INT_ERR | OHCI_INT_PHY_SID 578 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 579 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 580 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 581 fwohci_set_intr(&sc->fc, 1); 582 583} 584 585int 586fwohci_init(struct fwohci_softc *sc, device_t dev) 587{ 588 int i, mver; 589 u_int32_t reg; 590 u_int8_t ui[8]; 591 592#if FWOHCI_TASKQUEUE 593 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 594#endif 595 596/* OHCI version */ 597 reg = OREAD(sc, OHCI_VERSION); 598 mver = (reg >> 16) & 0xff; 599 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 600 mver, reg & 0xff, (reg>>24) & 1); 601 if (mver < 1 || mver > 9) { 602 device_printf(dev, "invalid OHCI version\n"); 603 return (ENXIO); 604 } 605 606/* Available Isochrounous DMA channel probe */ 607 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 608 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 609 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 610 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 611 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 612 for (i = 0; i < 0x20; i++) 613 if ((reg & (1 << i)) == 0) 614 break; 615 sc->fc.nisodma = i; 616 device_printf(dev, "No. of Isochronous channel is %d.\n", i); 617 if (i == 0) 618 return (ENXIO); 619 620 sc->fc.arq = &sc->arrq.xferq; 621 sc->fc.ars = &sc->arrs.xferq; 622 sc->fc.atq = &sc->atrq.xferq; 623 sc->fc.ats = &sc->atrs.xferq; 624 625 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 626 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 627 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 628 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 629 630 sc->arrq.xferq.start = NULL; 631 sc->arrs.xferq.start = NULL; 632 sc->atrq.xferq.start = fwohci_start_atq; 633 sc->atrs.xferq.start = fwohci_start_ats; 634 635 sc->arrq.xferq.buf = NULL; 636 sc->arrs.xferq.buf = NULL; 637 sc->atrq.xferq.buf = NULL; 638 sc->atrs.xferq.buf = NULL; 639 640 sc->arrq.xferq.dmach = -1; 641 sc->arrs.xferq.dmach = -1; 642 sc->atrq.xferq.dmach = -1; 643 sc->atrs.xferq.dmach = -1; 644 645 sc->arrq.ndesc = 1; 646 sc->arrs.ndesc = 1; 647 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 648 sc->atrs.ndesc = 2; 649 650 sc->arrq.ndb = NDB; 651 sc->arrs.ndb = NDB / 2; 652 sc->atrq.ndb = NDB; 653 sc->atrs.ndb = NDB / 2; 654 655 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 656 sc->fc.it[i] = &sc->it[i].xferq; 657 sc->fc.ir[i] = &sc->ir[i].xferq; 658 sc->it[i].xferq.dmach = i; 659 sc->ir[i].xferq.dmach = i; 660 sc->it[i].ndb = 0; 661 sc->ir[i].ndb = 0; 662 } 663 664 sc->fc.tcode = tinfo; 665 sc->fc.dev = dev; 666 667 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 668 &sc->crom_dma, BUS_DMA_WAITOK); 669 if(sc->fc.config_rom == NULL){ 670 device_printf(dev, "config_rom alloc failed."); 671 return ENOMEM; 672 } 673 674#if 0 675 bzero(&sc->fc.config_rom[0], CROMSIZE); 676 sc->fc.config_rom[1] = 0x31333934; 677 sc->fc.config_rom[2] = 0xf000a002; 678 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 679 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 680 sc->fc.config_rom[5] = 0; 681 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 682 683 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 684#endif 685 686 687/* SID recieve buffer must allign 2^11 */ 688#define OHCI_SIDSIZE (1 << 11) 689 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 690 &sc->sid_dma, BUS_DMA_WAITOK); 691 if (sc->sid_buf == NULL) { 692 device_printf(dev, "sid_buf alloc failed."); 693 return ENOMEM; 694 } 695 696 fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t), 697 &sc->dummy_dma, BUS_DMA_WAITOK); 698 699 if (sc->dummy_dma.v_addr == NULL) { 700 device_printf(dev, "dummy_dma alloc failed."); 701 return ENOMEM; 702 } 703 704 fwohci_db_init(sc, &sc->arrq); 705 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 706 return ENOMEM; 707 708 fwohci_db_init(sc, &sc->arrs); 709 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 710 return ENOMEM; 711 712 fwohci_db_init(sc, &sc->atrq); 713 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 714 return ENOMEM; 715 716 fwohci_db_init(sc, &sc->atrs); 717 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 718 return ENOMEM; 719 720 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 721 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 722 for( i = 0 ; i < 8 ; i ++) 723 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 724 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 725 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 726 727 sc->fc.ioctl = fwohci_ioctl; 728 sc->fc.cyctimer = fwohci_cyctimer; 729 sc->fc.set_bmr = fwohci_set_bus_manager; 730 sc->fc.ibr = fwohci_ibr; 731 sc->fc.irx_enable = fwohci_irx_enable; 732 sc->fc.irx_disable = fwohci_irx_disable; 733 734 sc->fc.itx_enable = fwohci_itxbuf_enable; 735 sc->fc.itx_disable = fwohci_itx_disable; 736#if BYTE_ORDER == BIG_ENDIAN 737 sc->fc.irx_post = fwohci_irx_post; 738#else 739 sc->fc.irx_post = NULL; 740#endif 741 sc->fc.itx_post = NULL; 742 sc->fc.timeout = fwohci_timeout; 743 sc->fc.poll = fwohci_poll; 744 sc->fc.set_intr = fwohci_set_intr; 745 746 sc->intmask = sc->irstat = sc->itstat = 0; 747 748 fw_init(&sc->fc); 749 fwohci_reset(sc, dev); 750 751 return 0; 752} 753 754void 755fwohci_timeout(void *arg) 756{ 757 struct fwohci_softc *sc; 758 759 sc = (struct fwohci_softc *)arg; 760} 761 762u_int32_t 763fwohci_cyctimer(struct firewire_comm *fc) 764{ 765 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 766 return(OREAD(sc, OHCI_CYCLETIMER)); 767} 768 769int 770fwohci_detach(struct fwohci_softc *sc, device_t dev) 771{ 772 int i; 773 774 if (sc->sid_buf != NULL) 775 fwdma_free(&sc->fc, &sc->sid_dma); 776 if (sc->fc.config_rom != NULL) 777 fwdma_free(&sc->fc, &sc->crom_dma); 778 779 fwohci_db_free(&sc->arrq); 780 fwohci_db_free(&sc->arrs); 781 782 fwohci_db_free(&sc->atrq); 783 fwohci_db_free(&sc->atrs); 784 785 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 786 fwohci_db_free(&sc->it[i]); 787 fwohci_db_free(&sc->ir[i]); 788 } 789 790 return 0; 791} 792 793#define LAST_DB(dbtr, db) do { \ 794 struct fwohcidb_tr *_dbtr = (dbtr); \ 795 int _cnt = _dbtr->dbcnt; \ 796 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 797} while (0) 798 799static void 800fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 801{ 802 struct fwohcidb_tr *db_tr; 803 struct fwohcidb *db; 804 bus_dma_segment_t *s; 805 int i; 806 807 db_tr = (struct fwohcidb_tr *)arg; 808 db = &db_tr->db[db_tr->dbcnt]; 809 if (error) { 810 if (firewire_debug || error != EFBIG) 811 printf("fwohci_execute_db: error=%d\n", error); 812 return; 813 } 814 for (i = 0; i < nseg; i++) { 815 s = &segs[i]; 816 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 817 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 818 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 819 db++; 820 db_tr->dbcnt++; 821 } 822} 823 824static void 825fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 826 bus_size_t size, int error) 827{ 828 fwohci_execute_db(arg, segs, nseg, error); 829} 830 831static void 832fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 833{ 834 int i, s; 835 int tcode, hdr_len, pl_off; 836 int fsegment = -1; 837 u_int32_t off; 838 struct fw_xfer *xfer; 839 struct fw_pkt *fp; 840 struct fwohci_txpkthdr *ohcifp; 841 struct fwohcidb_tr *db_tr; 842 struct fwohcidb *db; 843 u_int32_t *ld; 844 struct tcode_info *info; 845 static int maxdesc=0; 846 847 if(&sc->atrq == dbch){ 848 off = OHCI_ATQOFF; 849 }else if(&sc->atrs == dbch){ 850 off = OHCI_ATSOFF; 851 }else{ 852 return; 853 } 854 855 if (dbch->flags & FWOHCI_DBCH_FULL) 856 return; 857 858 s = splfw(); 859 db_tr = dbch->top; 860txloop: 861 xfer = STAILQ_FIRST(&dbch->xferq.q); 862 if(xfer == NULL){ 863 goto kick; 864 } 865 if(dbch->xferq.queued == 0 ){ 866 device_printf(sc->fc.dev, "TX queue empty\n"); 867 } 868 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 869 db_tr->xfer = xfer; 870 xfer->state = FWXF_START; 871 872 fp = &xfer->send.hdr; 873 tcode = fp->mode.common.tcode; 874 875 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 876 info = &tinfo[tcode]; 877 hdr_len = pl_off = info->hdr_len; 878 879 ld = &ohcifp->mode.ld[0]; 880 ld[0] = ld[1] = ld[2] = ld[3] = 0; 881 for( i = 0 ; i < pl_off ; i+= 4) 882 ld[i/4] = fp->mode.ld[i/4]; 883 884 ohcifp->mode.common.spd = xfer->send.spd & 0x7; 885 if (tcode == FWTCODE_STREAM ){ 886 hdr_len = 8; 887 ohcifp->mode.stream.len = fp->mode.stream.len; 888 } else if (tcode == FWTCODE_PHY) { 889 hdr_len = 12; 890 ld[1] = fp->mode.ld[1]; 891 ld[2] = fp->mode.ld[2]; 892 ohcifp->mode.common.spd = 0; 893 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 894 } else { 895 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 896 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 897 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 898 } 899 db = &db_tr->db[0]; 900 FWOHCI_DMA_WRITE(db->db.desc.cmd, 901 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 902 FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 903 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 904/* Specify bound timer of asy. responce */ 905 if(&sc->atrs == dbch){ 906 FWOHCI_DMA_WRITE(db->db.desc.res, 907 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 908 } 909#if BYTE_ORDER == BIG_ENDIAN 910 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 911 hdr_len = 12; 912 for (i = 0; i < hdr_len/4; i ++) 913 FWOHCI_DMA_WRITE(ld[i], ld[i]); 914#endif 915 916again: 917 db_tr->dbcnt = 2; 918 db = &db_tr->db[db_tr->dbcnt]; 919 if (xfer->send.pay_len > 0) { 920 int err; 921 /* handle payload */ 922 if (xfer->mbuf == NULL) { 923 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 924 &xfer->send.payload[0], xfer->send.pay_len, 925 fwohci_execute_db, db_tr, 926 /*flags*/0); 927 } else { 928 /* XXX we can handle only 6 (=8-2) mbuf chains */ 929 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 930 xfer->mbuf, 931 fwohci_execute_db2, db_tr, 932 /* flags */0); 933 if (err == EFBIG) { 934 struct mbuf *m0; 935 936 if (firewire_debug) 937 device_printf(sc->fc.dev, "EFBIG.\n"); 938 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 939 if (m0 != NULL) { 940 m_copydata(xfer->mbuf, 0, 941 xfer->mbuf->m_pkthdr.len, 942 mtod(m0, caddr_t)); 943 m0->m_len = m0->m_pkthdr.len = 944 xfer->mbuf->m_pkthdr.len; 945 m_freem(xfer->mbuf); 946 xfer->mbuf = m0; 947 goto again; 948 } 949 device_printf(sc->fc.dev, "m_getcl failed.\n"); 950 } 951 } 952 if (err) 953 printf("dmamap_load: err=%d\n", err); 954 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 955 BUS_DMASYNC_PREWRITE); 956#if 0 /* OHCI_OUTPUT_MODE == 0 */ 957 for (i = 2; i < db_tr->dbcnt; i++) 958 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 959 OHCI_OUTPUT_MORE); 960#endif 961 } 962 if (maxdesc < db_tr->dbcnt) { 963 maxdesc = db_tr->dbcnt; 964 if (bootverbose) 965 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 966 } 967 /* last db */ 968 LAST_DB(db_tr, db); 969 FWOHCI_DMA_SET(db->db.desc.cmd, 970 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 971 FWOHCI_DMA_WRITE(db->db.desc.depend, 972 STAILQ_NEXT(db_tr, link)->bus_addr); 973 974 if(fsegment == -1 ) 975 fsegment = db_tr->dbcnt; 976 if (dbch->pdb_tr != NULL) { 977 LAST_DB(dbch->pdb_tr, db); 978 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 979 } 980 dbch->pdb_tr = db_tr; 981 db_tr = STAILQ_NEXT(db_tr, link); 982 if(db_tr != dbch->bottom){ 983 goto txloop; 984 } else { 985 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 986 dbch->flags |= FWOHCI_DBCH_FULL; 987 } 988kick: 989 /* kick asy q */ 990 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 991 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 992 993 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 994 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 995 } else { 996 if (bootverbose) 997 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 998 OREAD(sc, OHCI_DMACTL(off))); 999 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1000 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1001 dbch->xferq.flag |= FWXFERQ_RUNNING; 1002 } 1003 1004 dbch->top = db_tr; 1005 splx(s); 1006 return; 1007} 1008 1009static void 1010fwohci_start_atq(struct firewire_comm *fc) 1011{ 1012 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1013 fwohci_start( sc, &(sc->atrq)); 1014 return; 1015} 1016 1017static void 1018fwohci_start_ats(struct firewire_comm *fc) 1019{ 1020 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1021 fwohci_start( sc, &(sc->atrs)); 1022 return; 1023} 1024 1025void 1026fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1027{ 1028 int s, ch, err = 0; 1029 struct fwohcidb_tr *tr; 1030 struct fwohcidb *db; 1031 struct fw_xfer *xfer; 1032 u_int32_t off; 1033 u_int stat, status; 1034 int packets; 1035 struct firewire_comm *fc = (struct firewire_comm *)sc; 1036 1037 if(&sc->atrq == dbch){ 1038 off = OHCI_ATQOFF; 1039 ch = ATRQ_CH; 1040 }else if(&sc->atrs == dbch){ 1041 off = OHCI_ATSOFF; 1042 ch = ATRS_CH; 1043 }else{ 1044 return; 1045 } 1046 s = splfw(); 1047 tr = dbch->bottom; 1048 packets = 0; 1049 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 1050 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 1051 while(dbch->xferq.queued > 0){ 1052 LAST_DB(tr, db); 1053 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1054 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1055 if (fc->status != FWBUSRESET) 1056 /* maybe out of order?? */ 1057 goto out; 1058 } 1059 bus_dmamap_sync(dbch->dmat, tr->dma_map, 1060 BUS_DMASYNC_POSTWRITE); 1061 bus_dmamap_unload(dbch->dmat, tr->dma_map); 1062#if 1 1063 if (firewire_debug) 1064 dump_db(sc, ch); 1065#endif 1066 if(status & OHCI_CNTL_DMA_DEAD) { 1067 /* Stop DMA */ 1068 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1069 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1070 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1071 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1072 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1073 } 1074 stat = status & FWOHCIEV_MASK; 1075 switch(stat){ 1076 case FWOHCIEV_ACKPEND: 1077 case FWOHCIEV_ACKCOMPL: 1078 err = 0; 1079 break; 1080 case FWOHCIEV_ACKBSA: 1081 case FWOHCIEV_ACKBSB: 1082 case FWOHCIEV_ACKBSX: 1083 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1084 err = EBUSY; 1085 break; 1086 case FWOHCIEV_FLUSHED: 1087 case FWOHCIEV_ACKTARD: 1088 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1089 err = EAGAIN; 1090 break; 1091 case FWOHCIEV_MISSACK: 1092 case FWOHCIEV_UNDRRUN: 1093 case FWOHCIEV_OVRRUN: 1094 case FWOHCIEV_DESCERR: 1095 case FWOHCIEV_DTRDERR: 1096 case FWOHCIEV_TIMEOUT: 1097 case FWOHCIEV_TCODERR: 1098 case FWOHCIEV_UNKNOWN: 1099 case FWOHCIEV_ACKDERR: 1100 case FWOHCIEV_ACKTERR: 1101 default: 1102 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1103 stat, fwohcicode[stat]); 1104 err = EINVAL; 1105 break; 1106 } 1107 if (tr->xfer != NULL) { 1108 xfer = tr->xfer; 1109 if (xfer->state == FWXF_RCVD) { 1110#if 0 1111 if (firewire_debug) 1112 printf("already rcvd\n"); 1113#endif 1114 fw_xfer_done(xfer); 1115 } else { 1116 xfer->state = FWXF_SENT; 1117 if (err == EBUSY && fc->status != FWBUSRESET) { 1118 xfer->state = FWXF_BUSY; 1119 xfer->resp = err; 1120 if (xfer->retry_req != NULL) 1121 xfer->retry_req(xfer); 1122 else { 1123 xfer->recv.pay_len = 0; 1124 fw_xfer_done(xfer); 1125 } 1126 } else if (stat != FWOHCIEV_ACKPEND) { 1127 if (stat != FWOHCIEV_ACKCOMPL) 1128 xfer->state = FWXF_SENTERR; 1129 xfer->resp = err; 1130 xfer->recv.pay_len = 0; 1131 fw_xfer_done(xfer); 1132 } 1133 } 1134 /* 1135 * The watchdog timer takes care of split 1136 * transcation timeout for ACKPEND case. 1137 */ 1138 } else { 1139 printf("this shouldn't happen\n"); 1140 } 1141 dbch->xferq.queued --; 1142 tr->xfer = NULL; 1143 1144 packets ++; 1145 tr = STAILQ_NEXT(tr, link); 1146 dbch->bottom = tr; 1147 if (dbch->bottom == dbch->top) { 1148 /* we reaches the end of context program */ 1149 if (firewire_debug && dbch->xferq.queued > 0) 1150 printf("queued > 0\n"); 1151 break; 1152 } 1153 } 1154out: 1155 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1156 printf("make free slot\n"); 1157 dbch->flags &= ~FWOHCI_DBCH_FULL; 1158 fwohci_start(sc, dbch); 1159 } 1160 splx(s); 1161} 1162 1163static void 1164fwohci_db_free(struct fwohci_dbch *dbch) 1165{ 1166 struct fwohcidb_tr *db_tr; 1167 int idb; 1168 1169 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1170 return; 1171 1172 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1173 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1174 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1175 db_tr->buf != NULL) { 1176 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1177 db_tr->buf, dbch->xferq.psize); 1178 db_tr->buf = NULL; 1179 } else if (db_tr->dma_map != NULL) 1180 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1181 } 1182 dbch->ndb = 0; 1183 db_tr = STAILQ_FIRST(&dbch->db_trq); 1184 fwdma_free_multiseg(dbch->am); 1185 free(db_tr, M_FW); 1186 STAILQ_INIT(&dbch->db_trq); 1187 dbch->flags &= ~FWOHCI_DBCH_INIT; 1188} 1189 1190static void 1191fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1192{ 1193 int idb; 1194 struct fwohcidb_tr *db_tr; 1195 1196 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1197 goto out; 1198 1199 /* create dma_tag for buffers */ 1200#define MAX_REQCOUNT 0xffff 1201 if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1202 /*alignment*/ 1, /*boundary*/ 0, 1203 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1204 /*highaddr*/ BUS_SPACE_MAXADDR, 1205 /*filter*/NULL, /*filterarg*/NULL, 1206 /*maxsize*/ dbch->xferq.psize, 1207 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1208 /*maxsegsz*/ MAX_REQCOUNT, 1209 /*flags*/ 0, 1210#if __FreeBSD_version >= 501102 1211 /*lockfunc*/busdma_lock_mutex, 1212 /*lockarg*/&Giant, 1213#endif 1214 &dbch->dmat)) 1215 return; 1216 1217 /* allocate DB entries and attach one to each DMA channels */ 1218 /* DB entry must start at 16 bytes bounary. */ 1219 STAILQ_INIT(&dbch->db_trq); 1220 db_tr = (struct fwohcidb_tr *) 1221 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1222 M_FW, M_WAITOK | M_ZERO); 1223 if(db_tr == NULL){ 1224 printf("fwohci_db_init: malloc(1) failed\n"); 1225 return; 1226 } 1227 1228#define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1229 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1230 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1231 if (dbch->am == NULL) { 1232 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1233 free(db_tr, M_FW); 1234 return; 1235 } 1236 /* Attach DB to DMA ch. */ 1237 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1238 db_tr->dbcnt = 0; 1239 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1240 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1241 /* create dmamap for buffers */ 1242 /* XXX do we need 4bytes alignment tag? */ 1243 /* XXX don't alloc dma_map for AR */ 1244 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1245 printf("bus_dmamap_create failed\n"); 1246 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1247 fwohci_db_free(dbch); 1248 return; 1249 } 1250 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1251 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1252 if (idb % dbch->xferq.bnpacket == 0) 1253 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1254 ].start = (caddr_t)db_tr; 1255 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1256 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1257 ].end = (caddr_t)db_tr; 1258 } 1259 db_tr++; 1260 } 1261 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1262 = STAILQ_FIRST(&dbch->db_trq); 1263out: 1264 dbch->xferq.queued = 0; 1265 dbch->pdb_tr = NULL; 1266 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1267 dbch->bottom = dbch->top; 1268 dbch->flags = FWOHCI_DBCH_INIT; 1269} 1270 1271static int 1272fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1273{ 1274 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1275 int sleepch; 1276 1277 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1278 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1279 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1280 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1281 /* XXX we cannot free buffers until the DMA really stops */ 1282 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1283 fwohci_db_free(&sc->it[dmach]); 1284 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1285 return 0; 1286} 1287 1288static int 1289fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1290{ 1291 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1292 int sleepch; 1293 1294 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1295 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1296 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1297 /* XXX we cannot free buffers until the DMA really stops */ 1298 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1299 fwohci_db_free(&sc->ir[dmach]); 1300 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1301 return 0; 1302} 1303 1304#if BYTE_ORDER == BIG_ENDIAN 1305static void 1306fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1307{ 1308 qld[0] = FWOHCI_DMA_READ(qld[0]); 1309 return; 1310} 1311#endif 1312 1313static int 1314fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1315{ 1316 int err = 0; 1317 int idb, z, i, dmach = 0, ldesc; 1318 u_int32_t off = 0; 1319 struct fwohcidb_tr *db_tr; 1320 struct fwohcidb *db; 1321 1322 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1323 err = EINVAL; 1324 return err; 1325 } 1326 z = dbch->ndesc; 1327 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1328 if( &sc->it[dmach] == dbch){ 1329 off = OHCI_ITOFF(dmach); 1330 break; 1331 } 1332 } 1333 if(off == 0){ 1334 err = EINVAL; 1335 return err; 1336 } 1337 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1338 return err; 1339 dbch->xferq.flag |= FWXFERQ_RUNNING; 1340 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1341 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1342 } 1343 db_tr = dbch->top; 1344 for (idb = 0; idb < dbch->ndb; idb ++) { 1345 fwohci_add_tx_buf(dbch, db_tr, idb); 1346 if(STAILQ_NEXT(db_tr, link) == NULL){ 1347 break; 1348 } 1349 db = db_tr->db; 1350 ldesc = db_tr->dbcnt - 1; 1351 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1352 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1353 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1354 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1355 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1356 FWOHCI_DMA_SET( 1357 db[ldesc].db.desc.cmd, 1358 OHCI_INTERRUPT_ALWAYS); 1359 /* OHCI 1.1 and above */ 1360 FWOHCI_DMA_SET( 1361 db[0].db.desc.cmd, 1362 OHCI_INTERRUPT_ALWAYS); 1363 } 1364 } 1365 db_tr = STAILQ_NEXT(db_tr, link); 1366 } 1367 FWOHCI_DMA_CLEAR( 1368 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1369 return err; 1370} 1371 1372static int 1373fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1374{ 1375 int err = 0; 1376 int idb, z, i, dmach = 0, ldesc; 1377 u_int32_t off = 0; 1378 struct fwohcidb_tr *db_tr; 1379 struct fwohcidb *db; 1380 1381 z = dbch->ndesc; 1382 if(&sc->arrq == dbch){ 1383 off = OHCI_ARQOFF; 1384 }else if(&sc->arrs == dbch){ 1385 off = OHCI_ARSOFF; 1386 }else{ 1387 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1388 if( &sc->ir[dmach] == dbch){ 1389 off = OHCI_IROFF(dmach); 1390 break; 1391 } 1392 } 1393 } 1394 if(off == 0){ 1395 err = EINVAL; 1396 return err; 1397 } 1398 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1399 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1400 return err; 1401 }else{ 1402 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1403 err = EBUSY; 1404 return err; 1405 } 1406 } 1407 dbch->xferq.flag |= FWXFERQ_RUNNING; 1408 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1409 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1410 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1411 } 1412 db_tr = dbch->top; 1413 for (idb = 0; idb < dbch->ndb; idb ++) { 1414 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1415 if (STAILQ_NEXT(db_tr, link) == NULL) 1416 break; 1417 db = db_tr->db; 1418 ldesc = db_tr->dbcnt - 1; 1419 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1420 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1421 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1422 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1423 FWOHCI_DMA_SET( 1424 db[ldesc].db.desc.cmd, 1425 OHCI_INTERRUPT_ALWAYS); 1426 FWOHCI_DMA_CLEAR( 1427 db[ldesc].db.desc.depend, 1428 0xf); 1429 } 1430 } 1431 db_tr = STAILQ_NEXT(db_tr, link); 1432 } 1433 FWOHCI_DMA_CLEAR( 1434 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1435 dbch->buf_offset = 0; 1436 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1437 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1438 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1439 return err; 1440 }else{ 1441 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1442 } 1443 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1444 return err; 1445} 1446 1447static int 1448fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1449{ 1450 int sec, cycle, cycle_match; 1451 1452 cycle = cycle_now & 0x1fff; 1453 sec = cycle_now >> 13; 1454#define CYCLE_MOD 0x10 1455#if 1 1456#define CYCLE_DELAY 8 /* min delay to start DMA */ 1457#else 1458#define CYCLE_DELAY 7000 /* min delay to start DMA */ 1459#endif 1460 cycle = cycle + CYCLE_DELAY; 1461 if (cycle >= 8000) { 1462 sec ++; 1463 cycle -= 8000; 1464 } 1465 cycle = roundup2(cycle, CYCLE_MOD); 1466 if (cycle >= 8000) { 1467 sec ++; 1468 if (cycle == 8000) 1469 cycle = 0; 1470 else 1471 cycle = CYCLE_MOD; 1472 } 1473 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1474 1475 return(cycle_match); 1476} 1477 1478static int 1479fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1480{ 1481 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1482 int err = 0; 1483 unsigned short tag, ich; 1484 struct fwohci_dbch *dbch; 1485 int cycle_match, cycle_now, s, ldesc; 1486 u_int32_t stat; 1487 struct fw_bulkxfer *first, *chunk, *prev; 1488 struct fw_xferq *it; 1489 1490 dbch = &sc->it[dmach]; 1491 it = &dbch->xferq; 1492 1493 tag = (it->flag >> 6) & 3; 1494 ich = it->flag & 0x3f; 1495 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1496 dbch->ndb = it->bnpacket * it->bnchunk; 1497 dbch->ndesc = 3; 1498 fwohci_db_init(sc, dbch); 1499 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1500 return ENOMEM; 1501 err = fwohci_tx_enable(sc, dbch); 1502 } 1503 if(err) 1504 return err; 1505 1506 ldesc = dbch->ndesc - 1; 1507 s = splfw(); 1508 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1509 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1510 struct fwohcidb *db; 1511 1512 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1513 BUS_DMASYNC_PREWRITE); 1514 fwohci_txbufdb(sc, dmach, chunk); 1515 if (prev != NULL) { 1516 db = ((struct fwohcidb_tr *)(prev->end))->db; 1517#if 0 /* XXX necessary? */ 1518 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1519 OHCI_BRANCH_ALWAYS); 1520#endif 1521#if 0 /* if bulkxfer->npacket changes */ 1522 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1523 ((struct fwohcidb_tr *) 1524 (chunk->start))->bus_addr | dbch->ndesc; 1525#else 1526 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1527 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1528#endif 1529 } 1530 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1531 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1532 prev = chunk; 1533 } 1534 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1535 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1536 splx(s); 1537 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1538 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1539 printf("stat 0x%x\n", stat); 1540 1541 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1542 return 0; 1543 1544#if 0 1545 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1546#endif 1547 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1548 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1549 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1550 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1551 1552 first = STAILQ_FIRST(&it->stdma); 1553 OWRITE(sc, OHCI_ITCMD(dmach), 1554 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1555 if (firewire_debug) { 1556 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1557#if 1 1558 dump_dma(sc, ITX_CH + dmach); 1559#endif 1560 } 1561 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1562#if 1 1563 /* Don't start until all chunks are buffered */ 1564 if (STAILQ_FIRST(&it->stfree) != NULL) 1565 goto out; 1566#endif 1567#if 1 1568 /* Clear cycle match counter bits */ 1569 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1570 1571 /* 2bit second + 13bit cycle */ 1572 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1573 cycle_match = fwohci_next_cycle(fc, cycle_now); 1574 1575 OWRITE(sc, OHCI_ITCTL(dmach), 1576 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1577 | OHCI_CNTL_DMA_RUN); 1578#else 1579 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1580#endif 1581 if (firewire_debug) { 1582 printf("cycle_match: 0x%04x->0x%04x\n", 1583 cycle_now, cycle_match); 1584 dump_dma(sc, ITX_CH + dmach); 1585 dump_db(sc, ITX_CH + dmach); 1586 } 1587 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1588 device_printf(sc->fc.dev, 1589 "IT DMA underrun (0x%08x)\n", stat); 1590 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1591 } 1592out: 1593 return err; 1594} 1595 1596static int 1597fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1598{ 1599 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1600 int err = 0, s, ldesc; 1601 unsigned short tag, ich; 1602 u_int32_t stat; 1603 struct fwohci_dbch *dbch; 1604 struct fwohcidb_tr *db_tr; 1605 struct fw_bulkxfer *first, *prev, *chunk; 1606 struct fw_xferq *ir; 1607 1608 dbch = &sc->ir[dmach]; 1609 ir = &dbch->xferq; 1610 1611 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1612 tag = (ir->flag >> 6) & 3; 1613 ich = ir->flag & 0x3f; 1614 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1615 1616 ir->queued = 0; 1617 dbch->ndb = ir->bnpacket * ir->bnchunk; 1618 dbch->ndesc = 2; 1619 fwohci_db_init(sc, dbch); 1620 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1621 return ENOMEM; 1622 err = fwohci_rx_enable(sc, dbch); 1623 } 1624 if(err) 1625 return err; 1626 1627 first = STAILQ_FIRST(&ir->stfree); 1628 if (first == NULL) { 1629 device_printf(fc->dev, "IR DMA no free chunk\n"); 1630 return 0; 1631 } 1632 1633 ldesc = dbch->ndesc - 1; 1634 s = splfw(); 1635 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1636 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1637 struct fwohcidb *db; 1638 1639#if 1 /* XXX for if_fwe */ 1640 if (chunk->mbuf != NULL) { 1641 db_tr = (struct fwohcidb_tr *)(chunk->start); 1642 db_tr->dbcnt = 1; 1643 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 1644 chunk->mbuf, fwohci_execute_db2, db_tr, 1645 /* flags */0); 1646 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1647 OHCI_UPDATE | OHCI_INPUT_LAST | 1648 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1649 } 1650#endif 1651 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1652 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1653 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1654 if (prev != NULL) { 1655 db = ((struct fwohcidb_tr *)(prev->end))->db; 1656 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1657 } 1658 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1659 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1660 prev = chunk; 1661 } 1662 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1663 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1664 splx(s); 1665 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1666 if (stat & OHCI_CNTL_DMA_ACTIVE) 1667 return 0; 1668 if (stat & OHCI_CNTL_DMA_RUN) { 1669 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1670 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1671 } 1672 1673 if (firewire_debug) 1674 printf("start IR DMA 0x%x\n", stat); 1675 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1676 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1677 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1678 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1679 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1680 OWRITE(sc, OHCI_IRCMD(dmach), 1681 ((struct fwohcidb_tr *)(first->start))->bus_addr 1682 | dbch->ndesc); 1683 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1684 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1685#if 0 1686 dump_db(sc, IRX_CH + dmach); 1687#endif 1688 return err; 1689} 1690 1691int 1692fwohci_stop(struct fwohci_softc *sc, device_t dev) 1693{ 1694 u_int i; 1695 1696/* Now stopping all DMA channel */ 1697 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1698 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1699 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1700 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1701 1702 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1703 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1704 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1705 } 1706 1707/* FLUSH FIFO and reset Transmitter/Reciever */ 1708 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1709 1710/* Stop interrupt */ 1711 OWRITE(sc, FWOHCI_INTMASKCLR, 1712 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1713 | OHCI_INT_PHY_INT 1714 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1715 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1716 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1717 | OHCI_INT_PHY_BUS_R); 1718 1719 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1720 fw_drain_txq(&sc->fc); 1721 1722/* XXX Link down? Bus reset? */ 1723 return 0; 1724} 1725 1726int 1727fwohci_resume(struct fwohci_softc *sc, device_t dev) 1728{ 1729 int i; 1730 struct fw_xferq *ir; 1731 struct fw_bulkxfer *chunk; 1732 1733 fwohci_reset(sc, dev); 1734 /* XXX resume isochronus receive automatically. (how about TX?) */ 1735 for(i = 0; i < sc->fc.nisodma; i ++) { 1736 ir = &sc->ir[i].xferq; 1737 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1738 device_printf(sc->fc.dev, 1739 "resume iso receive ch: %d\n", i); 1740 ir->flag &= ~FWXFERQ_RUNNING; 1741 /* requeue stdma to stfree */ 1742 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1743 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1744 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1745 } 1746 sc->fc.irx_enable(&sc->fc, i); 1747 } 1748 } 1749 1750 bus_generic_resume(dev); 1751 sc->fc.ibr(&sc->fc); 1752 return 0; 1753} 1754 1755#define ACK_ALL 1756static void 1757fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1758{ 1759 u_int32_t irstat, itstat; 1760 u_int i; 1761 struct firewire_comm *fc = (struct firewire_comm *)sc; 1762 1763#ifdef OHCI_DEBUG 1764 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1765 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1766 stat & OHCI_INT_EN ? "DMA_EN ":"", 1767 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1768 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1769 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1770 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1771 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1772 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1773 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1774 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1775 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1776 stat & OHCI_INT_PHY_SID ? "SID ":"", 1777 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1778 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1779 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1780 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1781 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1782 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1783 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1784 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1785 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1786 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1787 stat, OREAD(sc, FWOHCI_INTMASK) 1788 ); 1789#endif 1790/* Bus reset */ 1791 if(stat & OHCI_INT_PHY_BUS_R ){ 1792 if (fc->status == FWBUSRESET) 1793 goto busresetout; 1794 /* Disable bus reset interrupt until sid recv. */ 1795 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1796 1797 device_printf(fc->dev, "BUS reset\n"); 1798 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1799 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1800 1801 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1802 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1803 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1804 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1805 1806#ifndef ACK_ALL 1807 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1808#endif 1809 fw_busreset(fc); 1810 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1811 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1812 } 1813busresetout: 1814 if((stat & OHCI_INT_DMA_IR )){ 1815#ifndef ACK_ALL 1816 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1817#endif 1818#if __FreeBSD_version >= 500000 1819 irstat = atomic_readandclear_int(&sc->irstat); 1820#else 1821 irstat = sc->irstat; 1822 sc->irstat = 0; 1823#endif 1824 for(i = 0; i < fc->nisodma ; i++){ 1825 struct fwohci_dbch *dbch; 1826 1827 if((irstat & (1 << i)) != 0){ 1828 dbch = &sc->ir[i]; 1829 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1830 device_printf(sc->fc.dev, 1831 "dma(%d) not active\n", i); 1832 continue; 1833 } 1834 fwohci_rbuf_update(sc, i); 1835 } 1836 } 1837 } 1838 if((stat & OHCI_INT_DMA_IT )){ 1839#ifndef ACK_ALL 1840 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1841#endif 1842#if __FreeBSD_version >= 500000 1843 itstat = atomic_readandclear_int(&sc->itstat); 1844#else 1845 itstat = sc->itstat; 1846 sc->itstat = 0; 1847#endif 1848 for(i = 0; i < fc->nisodma ; i++){ 1849 if((itstat & (1 << i)) != 0){ 1850 fwohci_tbuf_update(sc, i); 1851 } 1852 } 1853 } 1854 if((stat & OHCI_INT_DMA_PRRS )){ 1855#ifndef ACK_ALL 1856 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1857#endif 1858#if 0 1859 dump_dma(sc, ARRS_CH); 1860 dump_db(sc, ARRS_CH); 1861#endif 1862 fwohci_arcv(sc, &sc->arrs, count); 1863 } 1864 if((stat & OHCI_INT_DMA_PRRQ )){ 1865#ifndef ACK_ALL 1866 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1867#endif 1868#if 0 1869 dump_dma(sc, ARRQ_CH); 1870 dump_db(sc, ARRQ_CH); 1871#endif 1872 fwohci_arcv(sc, &sc->arrq, count); 1873 } 1874 if(stat & OHCI_INT_PHY_SID){ 1875 u_int32_t *buf, node_id; 1876 int plen; 1877 1878#ifndef ACK_ALL 1879 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1880#endif 1881 /* Enable bus reset interrupt */ 1882 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1883 /* Allow async. request to us */ 1884 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1885 /* XXX insecure ?? */ 1886 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1887 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1888 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1889 /* Set ATRetries register */ 1890 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1891/* 1892** Checking whether the node is root or not. If root, turn on 1893** cycle master. 1894*/ 1895 node_id = OREAD(sc, FWOHCI_NODEID); 1896 plen = OREAD(sc, OHCI_SID_CNT); 1897 1898 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 1899 node_id, (plen >> 16) & 0xff); 1900 if (!(node_id & OHCI_NODE_VALID)) { 1901 printf("Bus reset failure\n"); 1902 goto sidout; 1903 } 1904 if (node_id & OHCI_NODE_ROOT) { 1905 printf("CYCLEMASTER mode\n"); 1906 OWRITE(sc, OHCI_LNKCTL, 1907 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1908 } else { 1909 printf("non CYCLEMASTER mode\n"); 1910 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1911 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1912 } 1913 fc->nodeid = node_id & 0x3f; 1914 1915 if (plen & OHCI_SID_ERR) { 1916 device_printf(fc->dev, "SID Error\n"); 1917 goto sidout; 1918 } 1919 plen &= OHCI_SID_CNT_MASK; 1920 if (plen < 4 || plen > OHCI_SIDSIZE) { 1921 device_printf(fc->dev, "invalid SID len = %d\n", plen); 1922 goto sidout; 1923 } 1924 plen -= 4; /* chop control info */ 1925 buf = (u_int32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1926 if (buf == NULL) { 1927 device_printf(fc->dev, "malloc failed\n"); 1928 goto sidout; 1929 } 1930 for (i = 0; i < plen / 4; i ++) 1931 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 1932#if 1 1933 /* pending all pre-bus_reset packets */ 1934 fwohci_txd(sc, &sc->atrq); 1935 fwohci_txd(sc, &sc->atrs); 1936 fwohci_arcv(sc, &sc->arrs, -1); 1937 fwohci_arcv(sc, &sc->arrq, -1); 1938 fw_drain_txq(fc); 1939#endif 1940 fw_sidrcv(fc, buf, plen); 1941 free(buf, M_FW); 1942 } 1943sidout: 1944 if((stat & OHCI_INT_DMA_ATRQ )){ 1945#ifndef ACK_ALL 1946 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1947#endif 1948 fwohci_txd(sc, &(sc->atrq)); 1949 } 1950 if((stat & OHCI_INT_DMA_ATRS )){ 1951#ifndef ACK_ALL 1952 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1953#endif 1954 fwohci_txd(sc, &(sc->atrs)); 1955 } 1956 if((stat & OHCI_INT_PW_ERR )){ 1957#ifndef ACK_ALL 1958 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1959#endif 1960 device_printf(fc->dev, "posted write error\n"); 1961 } 1962 if((stat & OHCI_INT_ERR )){ 1963#ifndef ACK_ALL 1964 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1965#endif 1966 device_printf(fc->dev, "unrecoverable error\n"); 1967 } 1968 if((stat & OHCI_INT_PHY_INT)) { 1969#ifndef ACK_ALL 1970 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1971#endif 1972 device_printf(fc->dev, "phy int\n"); 1973 } 1974 1975 return; 1976} 1977 1978#if FWOHCI_TASKQUEUE 1979static void 1980fwohci_complete(void *arg, int pending) 1981{ 1982 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1983 u_int32_t stat; 1984 1985again: 1986 stat = atomic_readandclear_int(&sc->intstat); 1987 if (stat) 1988 fwohci_intr_body(sc, stat, -1); 1989 else 1990 return; 1991 goto again; 1992} 1993#endif 1994 1995static u_int32_t 1996fwochi_check_stat(struct fwohci_softc *sc) 1997{ 1998 u_int32_t stat, irstat, itstat; 1999 2000 stat = OREAD(sc, FWOHCI_INTSTAT); 2001 if (stat == 0xffffffff) { 2002 device_printf(sc->fc.dev, 2003 "device physically ejected?\n"); 2004 return(stat); 2005 } 2006#ifdef ACK_ALL 2007 if (stat) 2008 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2009#endif 2010 if (stat & OHCI_INT_DMA_IR) { 2011 irstat = OREAD(sc, OHCI_IR_STAT); 2012 OWRITE(sc, OHCI_IR_STATCLR, irstat); 2013 atomic_set_int(&sc->irstat, irstat); 2014 } 2015 if (stat & OHCI_INT_DMA_IT) { 2016 itstat = OREAD(sc, OHCI_IT_STAT); 2017 OWRITE(sc, OHCI_IT_STATCLR, itstat); 2018 atomic_set_int(&sc->itstat, itstat); 2019 } 2020 return(stat); 2021} 2022 2023void 2024fwohci_intr(void *arg) 2025{ 2026 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2027 u_int32_t stat; 2028#if !FWOHCI_TASKQUEUE 2029 u_int32_t bus_reset = 0; 2030#endif 2031 2032 if (!(sc->intmask & OHCI_INT_EN)) { 2033 /* polling mode */ 2034 return; 2035 } 2036 2037#if !FWOHCI_TASKQUEUE 2038again: 2039#endif 2040 stat = fwochi_check_stat(sc); 2041 if (stat == 0 || stat == 0xffffffff) 2042 return; 2043#if FWOHCI_TASKQUEUE 2044 atomic_set_int(&sc->intstat, stat); 2045 /* XXX mask bus reset intr. during bus reset phase */ 2046 if (stat) 2047 taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete); 2048#else 2049 /* We cannot clear bus reset event during bus reset phase */ 2050 if ((stat & ~bus_reset) == 0) 2051 return; 2052 bus_reset = stat & OHCI_INT_PHY_BUS_R; 2053 fwohci_intr_body(sc, stat, -1); 2054 goto again; 2055#endif 2056} 2057 2058void 2059fwohci_poll(struct firewire_comm *fc, int quick, int count) 2060{ 2061 int s; 2062 u_int32_t stat; 2063 struct fwohci_softc *sc; 2064 2065 2066 sc = (struct fwohci_softc *)fc; 2067 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2068 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2069 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2070#if 0 2071 if (!quick) { 2072#else 2073 if (1) { 2074#endif 2075 stat = fwochi_check_stat(sc); 2076 if (stat == 0 || stat == 0xffffffff) 2077 return; 2078 } 2079 s = splfw(); 2080 fwohci_intr_body(sc, stat, count); 2081 splx(s); 2082} 2083 2084static void 2085fwohci_set_intr(struct firewire_comm *fc, int enable) 2086{ 2087 struct fwohci_softc *sc; 2088 2089 sc = (struct fwohci_softc *)fc; 2090 if (bootverbose) 2091 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2092 if (enable) { 2093 sc->intmask |= OHCI_INT_EN; 2094 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2095 } else { 2096 sc->intmask &= ~OHCI_INT_EN; 2097 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2098 } 2099} 2100 2101static void 2102fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2103{ 2104 struct firewire_comm *fc = &sc->fc; 2105 struct fwohcidb *db; 2106 struct fw_bulkxfer *chunk; 2107 struct fw_xferq *it; 2108 u_int32_t stat, count; 2109 int s, w=0, ldesc; 2110 2111 it = fc->it[dmach]; 2112 ldesc = sc->it[dmach].ndesc - 1; 2113 s = splfw(); /* unnecessary ? */ 2114 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2115 if (firewire_debug) 2116 dump_db(sc, ITX_CH + dmach); 2117 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2118 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2119 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2120 >> OHCI_STATUS_SHIFT; 2121 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2122 /* timestamp */ 2123 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2124 & OHCI_COUNT_MASK; 2125 if (stat == 0) 2126 break; 2127 STAILQ_REMOVE_HEAD(&it->stdma, link); 2128 switch (stat & FWOHCIEV_MASK){ 2129 case FWOHCIEV_ACKCOMPL: 2130#if 0 2131 device_printf(fc->dev, "0x%08x\n", count); 2132#endif 2133 break; 2134 default: 2135 device_printf(fc->dev, 2136 "Isochronous transmit err %02x(%s)\n", 2137 stat, fwohcicode[stat & 0x1f]); 2138 } 2139 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2140 w++; 2141 } 2142 splx(s); 2143 if (w) 2144 wakeup(it); 2145} 2146 2147static void 2148fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2149{ 2150 struct firewire_comm *fc = &sc->fc; 2151 struct fwohcidb_tr *db_tr; 2152 struct fw_bulkxfer *chunk; 2153 struct fw_xferq *ir; 2154 u_int32_t stat; 2155 int s, w=0, ldesc; 2156 2157 ir = fc->ir[dmach]; 2158 ldesc = sc->ir[dmach].ndesc - 1; 2159#if 0 2160 dump_db(sc, dmach); 2161#endif 2162 s = splfw(); 2163 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2164 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2165 db_tr = (struct fwohcidb_tr *)chunk->end; 2166 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2167 >> OHCI_STATUS_SHIFT; 2168 if (stat == 0) 2169 break; 2170 2171 if (chunk->mbuf != NULL) { 2172 bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2173 BUS_DMASYNC_POSTREAD); 2174 bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 2175 } else if (ir->buf != NULL) { 2176 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2177 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2178 } else { 2179 /* XXX */ 2180 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2181 } 2182 2183 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2184 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2185 switch (stat & FWOHCIEV_MASK) { 2186 case FWOHCIEV_ACKCOMPL: 2187 chunk->resp = 0; 2188 break; 2189 default: 2190 chunk->resp = EINVAL; 2191 device_printf(fc->dev, 2192 "Isochronous receive err %02x(%s)\n", 2193 stat, fwohcicode[stat & 0x1f]); 2194 } 2195 w++; 2196 } 2197 splx(s); 2198 if (w) { 2199 if (ir->flag & FWXFERQ_HANDLER) 2200 ir->hand(ir); 2201 else 2202 wakeup(ir); 2203 } 2204} 2205 2206void 2207dump_dma(struct fwohci_softc *sc, u_int32_t ch) 2208{ 2209 u_int32_t off, cntl, stat, cmd, match; 2210 2211 if(ch == 0){ 2212 off = OHCI_ATQOFF; 2213 }else if(ch == 1){ 2214 off = OHCI_ATSOFF; 2215 }else if(ch == 2){ 2216 off = OHCI_ARQOFF; 2217 }else if(ch == 3){ 2218 off = OHCI_ARSOFF; 2219 }else if(ch < IRX_CH){ 2220 off = OHCI_ITCTL(ch - ITX_CH); 2221 }else{ 2222 off = OHCI_IRCTL(ch - IRX_CH); 2223 } 2224 cntl = stat = OREAD(sc, off); 2225 cmd = OREAD(sc, off + 0xc); 2226 match = OREAD(sc, off + 0x10); 2227 2228 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2229 ch, 2230 cntl, 2231 cmd, 2232 match); 2233 stat &= 0xffff ; 2234 if (stat) { 2235 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2236 ch, 2237 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2238 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2239 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2240 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2241 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2242 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2243 fwohcicode[stat & 0x1f], 2244 stat & 0x1f 2245 ); 2246 }else{ 2247 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2248 } 2249} 2250 2251void 2252dump_db(struct fwohci_softc *sc, u_int32_t ch) 2253{ 2254 struct fwohci_dbch *dbch; 2255 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2256 struct fwohcidb *curr = NULL, *prev, *next = NULL; 2257 int idb, jdb; 2258 u_int32_t cmd, off; 2259 if(ch == 0){ 2260 off = OHCI_ATQOFF; 2261 dbch = &sc->atrq; 2262 }else if(ch == 1){ 2263 off = OHCI_ATSOFF; 2264 dbch = &sc->atrs; 2265 }else if(ch == 2){ 2266 off = OHCI_ARQOFF; 2267 dbch = &sc->arrq; 2268 }else if(ch == 3){ 2269 off = OHCI_ARSOFF; 2270 dbch = &sc->arrs; 2271 }else if(ch < IRX_CH){ 2272 off = OHCI_ITCTL(ch - ITX_CH); 2273 dbch = &sc->it[ch - ITX_CH]; 2274 }else { 2275 off = OHCI_IRCTL(ch - IRX_CH); 2276 dbch = &sc->ir[ch - IRX_CH]; 2277 } 2278 cmd = OREAD(sc, off + 0xc); 2279 2280 if( dbch->ndb == 0 ){ 2281 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2282 return; 2283 } 2284 pp = dbch->top; 2285 prev = pp->db; 2286 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2287 if(pp == NULL){ 2288 curr = NULL; 2289 goto outdb; 2290 } 2291 cp = STAILQ_NEXT(pp, link); 2292 if(cp == NULL){ 2293 curr = NULL; 2294 goto outdb; 2295 } 2296 np = STAILQ_NEXT(cp, link); 2297 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2298 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2299 curr = cp->db; 2300 if(np != NULL){ 2301 next = np->db; 2302 }else{ 2303 next = NULL; 2304 } 2305 goto outdb; 2306 } 2307 } 2308 pp = STAILQ_NEXT(pp, link); 2309 prev = pp->db; 2310 } 2311outdb: 2312 if( curr != NULL){ 2313#if 0 2314 printf("Prev DB %d\n", ch); 2315 print_db(pp, prev, ch, dbch->ndesc); 2316#endif 2317 printf("Current DB %d\n", ch); 2318 print_db(cp, curr, ch, dbch->ndesc); 2319#if 0 2320 printf("Next DB %d\n", ch); 2321 print_db(np, next, ch, dbch->ndesc); 2322#endif 2323 }else{ 2324 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2325 } 2326 return; 2327} 2328 2329void 2330print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2331 u_int32_t ch, u_int32_t max) 2332{ 2333 fwohcireg_t stat; 2334 int i, key; 2335 u_int32_t cmd, res; 2336 2337 if(db == NULL){ 2338 printf("No Descriptor is found\n"); 2339 return; 2340 } 2341 2342 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2343 ch, 2344 "Current", 2345 "OP ", 2346 "KEY", 2347 "INT", 2348 "BR ", 2349 "len", 2350 "Addr", 2351 "Depend", 2352 "Stat", 2353 "Cnt"); 2354 for( i = 0 ; i <= max ; i ++){ 2355 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2356 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2357 key = cmd & OHCI_KEY_MASK; 2358 stat = res >> OHCI_STATUS_SHIFT; 2359#if __FreeBSD_version >= 500000 2360 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2361 (uintmax_t)db_tr->bus_addr, 2362#else 2363 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2364 db_tr->bus_addr, 2365#endif 2366 dbcode[(cmd >> 28) & 0xf], 2367 dbkey[(cmd >> 24) & 0x7], 2368 dbcond[(cmd >> 20) & 0x3], 2369 dbcond[(cmd >> 18) & 0x3], 2370 cmd & OHCI_COUNT_MASK, 2371 FWOHCI_DMA_READ(db[i].db.desc.addr), 2372 FWOHCI_DMA_READ(db[i].db.desc.depend), 2373 stat, 2374 res & OHCI_COUNT_MASK); 2375 if(stat & 0xff00){ 2376 printf(" %s%s%s%s%s%s %s(%x)\n", 2377 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2378 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2379 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2380 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2381 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2382 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2383 fwohcicode[stat & 0x1f], 2384 stat & 0x1f 2385 ); 2386 }else{ 2387 printf(" Nostat\n"); 2388 } 2389 if(key == OHCI_KEY_ST2 ){ 2390 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2391 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2392 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2393 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2394 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2395 } 2396 if(key == OHCI_KEY_DEVICE){ 2397 return; 2398 } 2399 if((cmd & OHCI_BRANCH_MASK) 2400 == OHCI_BRANCH_ALWAYS){ 2401 return; 2402 } 2403 if((cmd & OHCI_CMD_MASK) 2404 == OHCI_OUTPUT_LAST){ 2405 return; 2406 } 2407 if((cmd & OHCI_CMD_MASK) 2408 == OHCI_INPUT_LAST){ 2409 return; 2410 } 2411 if(key == OHCI_KEY_ST2 ){ 2412 i++; 2413 } 2414 } 2415 return; 2416} 2417 2418void 2419fwohci_ibr(struct firewire_comm *fc) 2420{ 2421 struct fwohci_softc *sc; 2422 u_int32_t fun; 2423 2424 device_printf(fc->dev, "Initiate bus reset\n"); 2425 sc = (struct fwohci_softc *)fc; 2426 2427 /* 2428 * Set root hold-off bit so that non cyclemaster capable node 2429 * shouldn't became the root node. 2430 */ 2431#if 1 2432 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2433 fun |= FW_PHY_IBR | FW_PHY_RHB; 2434 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2435#else /* Short bus reset */ 2436 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2437 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2438 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2439#endif 2440} 2441 2442void 2443fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2444{ 2445 struct fwohcidb_tr *db_tr, *fdb_tr; 2446 struct fwohci_dbch *dbch; 2447 struct fwohcidb *db; 2448 struct fw_pkt *fp; 2449 struct fwohci_txpkthdr *ohcifp; 2450 unsigned short chtag; 2451 int idb; 2452 2453 dbch = &sc->it[dmach]; 2454 chtag = sc->it[dmach].xferq.flag & 0xff; 2455 2456 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2457 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2458/* 2459device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2460*/ 2461 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2462 db = db_tr->db; 2463 fp = (struct fw_pkt *)db_tr->buf; 2464 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2465 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2466 ohcifp->mode.common.spd = 0 & 0x7; 2467 ohcifp->mode.stream.len = fp->mode.stream.len; 2468 ohcifp->mode.stream.chtag = chtag; 2469 ohcifp->mode.stream.tcode = 0xa; 2470#if BYTE_ORDER == BIG_ENDIAN 2471 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2472 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2473#endif 2474 2475 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2476 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2477 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2478#if 0 /* if bulkxfer->npackets changes */ 2479 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2480 | OHCI_UPDATE 2481 | OHCI_BRANCH_ALWAYS; 2482 db[0].db.desc.depend = 2483 = db[dbch->ndesc - 1].db.desc.depend 2484 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2485#else 2486 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2487 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2488#endif 2489 bulkxfer->end = (caddr_t)db_tr; 2490 db_tr = STAILQ_NEXT(db_tr, link); 2491 } 2492 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2493 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2494 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2495#if 0 /* if bulkxfer->npackets changes */ 2496 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2497 /* OHCI 1.1 and above */ 2498 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2499#endif 2500/* 2501 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2502 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2503device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2504*/ 2505 return; 2506} 2507 2508static int 2509fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2510 int poffset) 2511{ 2512 struct fwohcidb *db = db_tr->db; 2513 struct fw_xferq *it; 2514 int err = 0; 2515 2516 it = &dbch->xferq; 2517 if(it->buf == 0){ 2518 err = EINVAL; 2519 return err; 2520 } 2521 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2522 db_tr->dbcnt = 3; 2523 2524 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2525 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2526 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2527 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2528 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2529 fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t)); 2530 2531 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2532 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2533#if 1 2534 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2535 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2536#endif 2537 return 0; 2538} 2539 2540int 2541fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2542 int poffset, struct fwdma_alloc *dummy_dma) 2543{ 2544 struct fwohcidb *db = db_tr->db; 2545 struct fw_xferq *ir; 2546 int i, ldesc; 2547 bus_addr_t dbuf[2]; 2548 int dsiz[2]; 2549 2550 ir = &dbch->xferq; 2551 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2552 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2553 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2554 if (db_tr->buf == NULL) 2555 return(ENOMEM); 2556 db_tr->dbcnt = 1; 2557 dsiz[0] = ir->psize; 2558 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2559 BUS_DMASYNC_PREREAD); 2560 } else { 2561 db_tr->dbcnt = 0; 2562 if (dummy_dma != NULL) { 2563 dsiz[db_tr->dbcnt] = sizeof(u_int32_t); 2564 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2565 } 2566 dsiz[db_tr->dbcnt] = ir->psize; 2567 if (ir->buf != NULL) { 2568 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2569 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2570 } 2571 db_tr->dbcnt++; 2572 } 2573 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2574 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2575 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2576 if (ir->flag & FWXFERQ_STREAM) { 2577 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2578 } 2579 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2580 } 2581 ldesc = db_tr->dbcnt - 1; 2582 if (ir->flag & FWXFERQ_STREAM) { 2583 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2584 } 2585 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2586 return 0; 2587} 2588 2589 2590static int 2591fwohci_arcv_swap(struct fw_pkt *fp, int len) 2592{ 2593 struct fw_pkt *fp0; 2594 u_int32_t ld0; 2595 int slen, hlen; 2596#if BYTE_ORDER == BIG_ENDIAN 2597 int i; 2598#endif 2599 2600 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2601#if 0 2602 printf("ld0: x%08x\n", ld0); 2603#endif 2604 fp0 = (struct fw_pkt *)&ld0; 2605 /* determine length to swap */ 2606 switch (fp0->mode.common.tcode) { 2607 case FWTCODE_RREQQ: 2608 case FWTCODE_WRES: 2609 case FWTCODE_WREQQ: 2610 case FWTCODE_RRESQ: 2611 case FWOHCITCODE_PHY: 2612 slen = 12; 2613 break; 2614 case FWTCODE_RREQB: 2615 case FWTCODE_WREQB: 2616 case FWTCODE_LREQ: 2617 case FWTCODE_RRESB: 2618 case FWTCODE_LRES: 2619 slen = 16; 2620 break; 2621 default: 2622 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2623 return(0); 2624 } 2625 hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2626 if (hlen > len) { 2627 if (firewire_debug) 2628 printf("splitted header\n"); 2629 return(-hlen); 2630 } 2631#if BYTE_ORDER == BIG_ENDIAN 2632 for(i = 0; i < slen/4; i ++) 2633 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2634#endif 2635 return(hlen); 2636} 2637 2638static int 2639fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2640{ 2641 struct tcode_info *info; 2642 int r; 2643 2644 info = &tinfo[fp->mode.common.tcode]; 2645 r = info->hdr_len + sizeof(u_int32_t); 2646 if ((info->flag & FWTI_BLOCK_ASY) != 0) 2647 r += roundup2(fp->mode.wreqb.len, sizeof(u_int32_t)); 2648 2649 if (r == sizeof(u_int32_t)) 2650 /* XXX */ 2651 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2652 fp->mode.common.tcode); 2653 2654 if (r > dbch->xferq.psize) { 2655 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2656 /* panic ? */ 2657 } 2658 2659 return r; 2660} 2661 2662static void 2663fwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr) 2664{ 2665 struct fwohcidb *db = &db_tr->db[0]; 2666 2667 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2668 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2669 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2670 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 2671 dbch->bottom = db_tr; 2672} 2673 2674static void 2675fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2676{ 2677 struct fwohcidb_tr *db_tr; 2678 struct iovec vec[2]; 2679 struct fw_pkt pktbuf; 2680 int nvec; 2681 struct fw_pkt *fp; 2682 u_int8_t *ld; 2683 u_int32_t stat, off, status; 2684 u_int spd; 2685 int len, plen, hlen, pcnt, offset; 2686 int s; 2687 caddr_t buf; 2688 int resCount; 2689 2690 if(&sc->arrq == dbch){ 2691 off = OHCI_ARQOFF; 2692 }else if(&sc->arrs == dbch){ 2693 off = OHCI_ARSOFF; 2694 }else{ 2695 return; 2696 } 2697 2698 s = splfw(); 2699 db_tr = dbch->top; 2700 pcnt = 0; 2701 /* XXX we cannot handle a packet which lies in more than two buf */ 2702 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 2703 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 2704 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2705 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2706#if 0 2707 printf("status 0x%04x, resCount 0x%04x\n", status, resCount); 2708#endif 2709 while (status & OHCI_CNTL_DMA_ACTIVE) { 2710 len = dbch->xferq.psize - resCount; 2711 ld = (u_int8_t *)db_tr->buf; 2712 if (dbch->pdb_tr == NULL) { 2713 len -= dbch->buf_offset; 2714 ld += dbch->buf_offset; 2715 } 2716 if (len > 0) 2717 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2718 BUS_DMASYNC_POSTREAD); 2719 while (len > 0 ) { 2720 if (count >= 0 && count-- == 0) 2721 goto out; 2722 if(dbch->pdb_tr != NULL){ 2723 /* we have a fragment in previous buffer */ 2724 int rlen; 2725 2726 offset = dbch->buf_offset; 2727 if (offset < 0) 2728 offset = - offset; 2729 buf = dbch->pdb_tr->buf + offset; 2730 rlen = dbch->xferq.psize - offset; 2731 if (firewire_debug) 2732 printf("rlen=%d, offset=%d\n", 2733 rlen, dbch->buf_offset); 2734 if (dbch->buf_offset < 0) { 2735 /* splitted in header, pull up */ 2736 char *p; 2737 2738 p = (char *)&pktbuf; 2739 bcopy(buf, p, rlen); 2740 p += rlen; 2741 /* this must be too long but harmless */ 2742 rlen = sizeof(pktbuf) - rlen; 2743 if (rlen < 0) 2744 printf("why rlen < 0\n"); 2745 bcopy(db_tr->buf, p, rlen); 2746 ld += rlen; 2747 len -= rlen; 2748 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2749 if (hlen < 0) { 2750 printf("hlen < 0 shouldn't happen"); 2751 } 2752 offset = sizeof(pktbuf); 2753 vec[0].iov_base = (char *)&pktbuf; 2754 vec[0].iov_len = offset; 2755 } else { 2756 /* splitted in payload */ 2757 offset = rlen; 2758 vec[0].iov_base = buf; 2759 vec[0].iov_len = rlen; 2760 } 2761 fp=(struct fw_pkt *)vec[0].iov_base; 2762 nvec = 1; 2763 } else { 2764 /* no fragment in previous buffer */ 2765 fp=(struct fw_pkt *)ld; 2766 hlen = fwohci_arcv_swap(fp, len); 2767 if (hlen == 0) 2768 /* XXX need reset */ 2769 goto out; 2770 if (hlen < 0) { 2771 dbch->pdb_tr = db_tr; 2772 dbch->buf_offset = - dbch->buf_offset; 2773 /* sanity check */ 2774 if (resCount != 0) 2775 printf("resCount = %d !?\n", 2776 resCount); 2777 /* XXX clear pdb_tr */ 2778 goto out; 2779 } 2780 offset = 0; 2781 nvec = 0; 2782 } 2783 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2784 if (plen < 0) { 2785 /* minimum header size + trailer 2786 = sizeof(fw_pkt) so this shouldn't happens */ 2787 printf("plen(%d) is negative! offset=%d\n", 2788 plen, offset); 2789 /* XXX clear pdb_tr */ 2790 goto out; 2791 } 2792 if (plen > 0) { 2793 len -= plen; 2794 if (len < 0) { 2795 dbch->pdb_tr = db_tr; 2796 if (firewire_debug) 2797 printf("splitted payload\n"); 2798 /* sanity check */ 2799 if (resCount != 0) 2800 printf("resCount = %d !?\n", 2801 resCount); 2802 /* XXX clear pdb_tr */ 2803 goto out; 2804 } 2805 vec[nvec].iov_base = ld; 2806 vec[nvec].iov_len = plen; 2807 nvec ++; 2808 ld += plen; 2809 } 2810 dbch->buf_offset = ld - (u_int8_t *)db_tr->buf; 2811 if (nvec == 0) 2812 printf("nvec == 0\n"); 2813 2814/* DMA result-code will be written at the tail of packet */ 2815#if BYTE_ORDER == BIG_ENDIAN 2816 stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16; 2817#else 2818 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2819#endif 2820#if 0 2821 printf("plen: %d, stat %x\n", 2822 plen ,stat); 2823#endif 2824 spd = (stat >> 5) & 0x3; 2825 stat &= 0x1f; 2826 switch(stat){ 2827 case FWOHCIEV_ACKPEND: 2828#if 0 2829 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2830#endif 2831 /* fall through */ 2832 case FWOHCIEV_ACKCOMPL: 2833 { 2834 struct fw_rcv_buf rb; 2835 2836 if ((vec[nvec-1].iov_len -= 2837 sizeof(struct fwohci_trailer)) == 0) 2838 nvec--; 2839 rb.fc = &sc->fc; 2840 rb.vec = vec; 2841 rb.nvec = nvec; 2842 rb.spd = spd; 2843 fw_rcv(&rb); 2844 break; 2845 } 2846 case FWOHCIEV_BUSRST: 2847 if (sc->fc.status != FWBUSRESET) 2848 printf("got BUSRST packet!?\n"); 2849 break; 2850 default: 2851 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2852#if 0 /* XXX */ 2853 goto out; 2854#endif 2855 break; 2856 } 2857 pcnt ++; 2858 if (dbch->pdb_tr != NULL) { 2859 fwohci_arcv_free_buf(dbch, dbch->pdb_tr); 2860 dbch->pdb_tr = NULL; 2861 } 2862 2863 } 2864out: 2865 if (resCount == 0) { 2866 /* done on this buffer */ 2867 if (dbch->pdb_tr == NULL) { 2868 fwohci_arcv_free_buf(dbch, db_tr); 2869 dbch->buf_offset = 0; 2870 } else 2871 if (dbch->pdb_tr != db_tr) 2872 printf("pdb_tr != db_tr\n"); 2873 db_tr = STAILQ_NEXT(db_tr, link); 2874 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2875 >> OHCI_STATUS_SHIFT; 2876 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2877 & OHCI_COUNT_MASK; 2878 /* XXX check buffer overrun */ 2879 dbch->top = db_tr; 2880 } else { 2881 dbch->buf_offset = dbch->xferq.psize - resCount; 2882 break; 2883 } 2884 /* XXX make sure DMA is not dead */ 2885 } 2886#if 0 2887 if (pcnt < 1) 2888 printf("fwohci_arcv: no packets\n"); 2889#endif 2890 splx(s); 2891} 2892