fwohci.c revision 119118
1103285Sikob/* 2113584Ssimokawa * Copyright (c) 2003 Hidetoshi Shimokawa 3103285Sikob * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4103285Sikob * All rights reserved. 5103285Sikob * 6103285Sikob * Redistribution and use in source and binary forms, with or without 7103285Sikob * modification, are permitted provided that the following conditions 8103285Sikob * are met: 9103285Sikob * 1. Redistributions of source code must retain the above copyright 10103285Sikob * notice, this list of conditions and the following disclaimer. 11103285Sikob * 2. Redistributions in binary form must reproduce the above copyright 12103285Sikob * notice, this list of conditions and the following disclaimer in the 13103285Sikob * documentation and/or other materials provided with the distribution. 14103285Sikob * 3. All advertising materials mentioning features or use of this software 15103285Sikob * must display the acknowledgement as bellow: 16103285Sikob * 17106802Ssimokawa * This product includes software developed by K. Kobayashi and H. Shimokawa 18103285Sikob * 19103285Sikob * 4. The name of the author may not be used to endorse or promote products 20103285Sikob * derived from this software without specific prior written permission. 21103285Sikob * 22103285Sikob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23103285Sikob * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24103285Sikob * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25103285Sikob * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26103285Sikob * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27103285Sikob * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28103285Sikob * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29103285Sikob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30103285Sikob * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31103285Sikob * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32103285Sikob * POSSIBILITY OF SUCH DAMAGE. 33103285Sikob * 34103285Sikob * $FreeBSD: head/sys/dev/firewire/fwohci.c 119118 2003-08-19 08:47:49Z simokawa $ 35103285Sikob * 36103285Sikob */ 37106802Ssimokawa 38103285Sikob#define ATRQ_CH 0 39103285Sikob#define ATRS_CH 1 40103285Sikob#define ARRQ_CH 2 41103285Sikob#define ARRS_CH 3 42103285Sikob#define ITX_CH 4 43103285Sikob#define IRX_CH 0x24 44103285Sikob 45103285Sikob#include <sys/param.h> 46103285Sikob#include <sys/systm.h> 47103285Sikob#include <sys/mbuf.h> 48103285Sikob#include <sys/malloc.h> 49103285Sikob#include <sys/sockio.h> 50103285Sikob#include <sys/bus.h> 51103285Sikob#include <sys/kernel.h> 52103285Sikob#include <sys/conf.h> 53113584Ssimokawa#include <sys/endian.h> 54103285Sikob 55103285Sikob#include <machine/bus.h> 56103285Sikob 57117067Ssimokawa#if __FreeBSD_version < 500000 58117067Ssimokawa#include <machine/clock.h> /* for DELAY() */ 59117067Ssimokawa#endif 60117067Ssimokawa 61103285Sikob#include <dev/firewire/firewire.h> 62103285Sikob#include <dev/firewire/firewirereg.h> 63113584Ssimokawa#include <dev/firewire/fwdma.h> 64103285Sikob#include <dev/firewire/fwohcireg.h> 65103285Sikob#include <dev/firewire/fwohcivar.h> 66103285Sikob#include <dev/firewire/firewire_phy.h> 67103285Sikob 68103285Sikob#undef OHCI_DEBUG 69106802Ssimokawa 70103285Sikobstatic char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 71103285Sikob "STOR","LOAD","NOP ","STOP",}; 72113584Ssimokawa 73103285Sikobstatic char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 74103285Sikob "UNDEF","REG","SYS","DEV"}; 75113584Ssimokawastatic char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 76103285Sikobchar fwohcicode[32][0x20]={ 77103285Sikob "No stat","Undef","long","miss Ack err", 78103285Sikob "underrun","overrun","desc err", "data read err", 79103285Sikob "data write err","bus reset","timeout","tcode err", 80103285Sikob "Undef","Undef","unknown event","flushed", 81103285Sikob "Undef","ack complete","ack pend","Undef", 82103285Sikob "ack busy_X","ack busy_A","ack busy_B","Undef", 83103285Sikob "Undef","Undef","Undef","ack tardy", 84103285Sikob "Undef","ack data_err","ack type_err",""}; 85113584Ssimokawa 86116376Ssimokawa#define MAX_SPEED 3 87116376Ssimokawaextern char linkspeed[][0x10]; 88103285Sikobu_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 89103285Sikob 90103285Sikobstatic struct tcode_info tinfo[] = { 91103285Sikob/* hdr_len block flag*/ 92103285Sikob/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 93103285Sikob/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 94103285Sikob/* 2 WRES */ {12, FWTI_RES}, 95103285Sikob/* 3 XXX */ { 0, 0}, 96103285Sikob/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 97103285Sikob/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 98103285Sikob/* 6 RRESQ */ {16, FWTI_RES}, 99103285Sikob/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 100103285Sikob/* 8 CYCS */ { 0, 0}, 101103285Sikob/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 102103285Sikob/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 103103285Sikob/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 104103285Sikob/* c XXX */ { 0, 0}, 105103285Sikob/* d XXX */ { 0, 0}, 106103285Sikob/* e PHY */ {12, FWTI_REQ}, 107103285Sikob/* f XXX */ { 0, 0} 108103285Sikob}; 109103285Sikob 110103285Sikob#define OHCI_WRITE_SIGMASK 0xffff0000 111103285Sikob#define OHCI_READ_SIGMASK 0xffff0000 112103285Sikob 113103285Sikob#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 114103285Sikob#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 115103285Sikob 116103285Sikobstatic void fwohci_ibr __P((struct firewire_comm *)); 117113584Ssimokawastatic void fwohci_db_init __P((struct fwohci_softc *, struct fwohci_dbch *)); 118103285Sikobstatic void fwohci_db_free __P((struct fwohci_dbch *)); 119106789Ssimokawastatic void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 120103285Sikobstatic void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 121103285Sikobstatic void fwohci_start_atq __P((struct firewire_comm *)); 122103285Sikobstatic void fwohci_start_ats __P((struct firewire_comm *)); 123103285Sikobstatic void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 124103285Sikobstatic u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 125103285Sikobstatic u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 126103285Sikobstatic int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 127103285Sikobstatic int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 128103285Sikobstatic int fwohci_irx_enable __P((struct firewire_comm *, int)); 129103285Sikobstatic int fwohci_irx_disable __P((struct firewire_comm *, int)); 130113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 131103285Sikobstatic void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 132113584Ssimokawa#endif 133103285Sikobstatic int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 134103285Sikobstatic int fwohci_itx_disable __P((struct firewire_comm *, int)); 135103285Sikobstatic void fwohci_timeout __P((void *)); 136103285Sikobstatic void fwohci_set_intr __P((struct firewire_comm *, int)); 137113584Ssimokawa 138113584Ssimokawastatic int fwohci_add_rx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *)); 139113584Ssimokawastatic int fwohci_add_tx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int)); 140103285Sikobstatic void dump_db __P((struct fwohci_softc *, u_int32_t)); 141113584Ssimokawastatic void print_db __P((struct fwohcidb_tr *, volatile struct fwohcidb *, u_int32_t , u_int32_t)); 142103285Sikobstatic void dump_dma __P((struct fwohci_softc *, u_int32_t)); 143103285Sikobstatic u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 144103285Sikobstatic void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 145103285Sikobstatic void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 146103285Sikobvoid fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 147113584Ssimokawa#if FWOHCI_TASKQUEUE 148113584Ssimokawastatic void fwohci_complete(void *, int); 149113584Ssimokawa#endif 150103285Sikob 151103285Sikob/* 152103285Sikob * memory allocated for DMA programs 153103285Sikob */ 154103285Sikob#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 155103285Sikob 156103285Sikob/* #define NDB 1024 */ 157103285Sikob#define NDB FWMAXQUEUE 158103285Sikob#define NDVDB (DVBUF * NDB) 159103285Sikob 160103285Sikob#define OHCI_VERSION 0x00 161112523Ssimokawa#define OHCI_ATRETRY 0x08 162103285Sikob#define OHCI_CROMHDR 0x18 163103285Sikob#define OHCI_BUS_OPT 0x20 164103285Sikob#define OHCI_BUSIRMC (1 << 31) 165103285Sikob#define OHCI_BUSCMC (1 << 30) 166103285Sikob#define OHCI_BUSISC (1 << 29) 167103285Sikob#define OHCI_BUSBMC (1 << 28) 168103285Sikob#define OHCI_BUSPMC (1 << 27) 169103285Sikob#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 170103285Sikob OHCI_BUSBMC | OHCI_BUSPMC 171103285Sikob 172103285Sikob#define OHCI_EUID_HI 0x24 173103285Sikob#define OHCI_EUID_LO 0x28 174103285Sikob 175103285Sikob#define OHCI_CROMPTR 0x34 176103285Sikob#define OHCI_HCCCTL 0x50 177103285Sikob#define OHCI_HCCCTLCLR 0x54 178103285Sikob#define OHCI_AREQHI 0x100 179103285Sikob#define OHCI_AREQHICLR 0x104 180103285Sikob#define OHCI_AREQLO 0x108 181103285Sikob#define OHCI_AREQLOCLR 0x10c 182103285Sikob#define OHCI_PREQHI 0x110 183103285Sikob#define OHCI_PREQHICLR 0x114 184103285Sikob#define OHCI_PREQLO 0x118 185103285Sikob#define OHCI_PREQLOCLR 0x11c 186103285Sikob#define OHCI_PREQUPPER 0x120 187103285Sikob 188103285Sikob#define OHCI_SID_BUF 0x64 189103285Sikob#define OHCI_SID_CNT 0x68 190113584Ssimokawa#define OHCI_SID_ERR (1 << 31) 191103285Sikob#define OHCI_SID_CNT_MASK 0xffc 192103285Sikob 193103285Sikob#define OHCI_IT_STAT 0x90 194103285Sikob#define OHCI_IT_STATCLR 0x94 195103285Sikob#define OHCI_IT_MASK 0x98 196103285Sikob#define OHCI_IT_MASKCLR 0x9c 197103285Sikob 198103285Sikob#define OHCI_IR_STAT 0xa0 199103285Sikob#define OHCI_IR_STATCLR 0xa4 200103285Sikob#define OHCI_IR_MASK 0xa8 201103285Sikob#define OHCI_IR_MASKCLR 0xac 202103285Sikob 203103285Sikob#define OHCI_LNKCTL 0xe0 204103285Sikob#define OHCI_LNKCTLCLR 0xe4 205103285Sikob 206103285Sikob#define OHCI_PHYACCESS 0xec 207103285Sikob#define OHCI_CYCLETIMER 0xf0 208103285Sikob 209103285Sikob#define OHCI_DMACTL(off) (off) 210103285Sikob#define OHCI_DMACTLCLR(off) (off + 4) 211103285Sikob#define OHCI_DMACMD(off) (off + 0xc) 212103285Sikob#define OHCI_DMAMATCH(off) (off + 0x10) 213103285Sikob 214103285Sikob#define OHCI_ATQOFF 0x180 215103285Sikob#define OHCI_ATQCTL OHCI_ATQOFF 216103285Sikob#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 217103285Sikob#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 218103285Sikob#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 219103285Sikob 220103285Sikob#define OHCI_ATSOFF 0x1a0 221103285Sikob#define OHCI_ATSCTL OHCI_ATSOFF 222103285Sikob#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 223103285Sikob#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 224103285Sikob#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 225103285Sikob 226103285Sikob#define OHCI_ARQOFF 0x1c0 227103285Sikob#define OHCI_ARQCTL OHCI_ARQOFF 228103285Sikob#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 229103285Sikob#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 230103285Sikob#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 231103285Sikob 232103285Sikob#define OHCI_ARSOFF 0x1e0 233103285Sikob#define OHCI_ARSCTL OHCI_ARSOFF 234103285Sikob#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 235103285Sikob#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 236103285Sikob#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 237103285Sikob 238103285Sikob#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 239103285Sikob#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 240103285Sikob#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 241103285Sikob#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 242103285Sikob 243103285Sikob#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 244103285Sikob#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 245103285Sikob#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 246103285Sikob#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 247103285Sikob#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 248103285Sikob 249103285Sikobd_ioctl_t fwohci_ioctl; 250103285Sikob 251103285Sikob/* 252103285Sikob * Communication with PHY device 253103285Sikob */ 254106790Ssimokawastatic u_int32_t 255106790Ssimokawafwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 256103285Sikob{ 257103285Sikob u_int32_t fun; 258103285Sikob 259103285Sikob addr &= 0xf; 260103285Sikob data &= 0xff; 261103285Sikob 262103285Sikob fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 263103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 264103285Sikob DELAY(100); 265103285Sikob 266103285Sikob return(fwphy_rddata( sc, addr)); 267103285Sikob} 268103285Sikob 269103285Sikobstatic u_int32_t 270103285Sikobfwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 271103285Sikob{ 272103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 273103285Sikob int i; 274103285Sikob u_int32_t bm; 275103285Sikob 276103285Sikob#define OHCI_CSR_DATA 0x0c 277103285Sikob#define OHCI_CSR_COMP 0x10 278103285Sikob#define OHCI_CSR_CONT 0x14 279103285Sikob#define OHCI_BUS_MANAGER_ID 0 280103285Sikob 281103285Sikob OWRITE(sc, OHCI_CSR_DATA, node); 282103285Sikob OWRITE(sc, OHCI_CSR_COMP, 0x3f); 283103285Sikob OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 284103285Sikob for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 285109280Ssimokawa DELAY(10); 286103285Sikob bm = OREAD(sc, OHCI_CSR_DATA); 287107653Ssimokawa if((bm & 0x3f) == 0x3f) 288103285Sikob bm = node; 289107653Ssimokawa if (bootverbose) 290107653Ssimokawa device_printf(sc->fc.dev, 291107653Ssimokawa "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 292103285Sikob 293103285Sikob return(bm); 294103285Sikob} 295103285Sikob 296106790Ssimokawastatic u_int32_t 297106790Ssimokawafwphy_rddata(struct fwohci_softc *sc, u_int addr) 298103285Sikob{ 299108500Ssimokawa u_int32_t fun, stat; 300108500Ssimokawa u_int i, retry = 0; 301103285Sikob 302103285Sikob addr &= 0xf; 303108500Ssimokawa#define MAX_RETRY 100 304108500Ssimokawaagain: 305108500Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 306103285Sikob fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 307103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 308108500Ssimokawa for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 309103285Sikob fun = OREAD(sc, OHCI_PHYACCESS); 310103285Sikob if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 311103285Sikob break; 312109280Ssimokawa DELAY(100); 313103285Sikob } 314108500Ssimokawa if(i >= MAX_RETRY) { 315109280Ssimokawa if (bootverbose) 316109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(1).\n"); 317108527Ssimokawa if (++retry < MAX_RETRY) { 318109280Ssimokawa DELAY(100); 319108527Ssimokawa goto again; 320108527Ssimokawa } 321108500Ssimokawa } 322108500Ssimokawa /* Make sure that SCLK is started */ 323108500Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 324108500Ssimokawa if ((stat & OHCI_INT_REG_FAIL) != 0 || 325108500Ssimokawa ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 326109280Ssimokawa if (bootverbose) 327109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(2).\n"); 328108500Ssimokawa if (++retry < MAX_RETRY) { 329109280Ssimokawa DELAY(100); 330108500Ssimokawa goto again; 331108500Ssimokawa } 332108500Ssimokawa } 333108500Ssimokawa if (bootverbose || retry >= MAX_RETRY) 334108500Ssimokawa device_printf(sc->fc.dev, 335119118Ssimokawa "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 336108500Ssimokawa#undef MAX_RETRY 337103285Sikob return((fun >> PHYDEV_RDDATA )& 0xff); 338103285Sikob} 339103285Sikob/* Device specific ioctl. */ 340103285Sikobint 341103285Sikobfwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 342103285Sikob{ 343103285Sikob struct firewire_softc *sc; 344103285Sikob struct fwohci_softc *fc; 345103285Sikob int unit = DEV2UNIT(dev); 346103285Sikob int err = 0; 347103285Sikob struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 348103285Sikob u_int32_t *dmach = (u_int32_t *) data; 349103285Sikob 350103285Sikob sc = devclass_get_softc(firewire_devclass, unit); 351103285Sikob if(sc == NULL){ 352103285Sikob return(EINVAL); 353103285Sikob } 354103285Sikob fc = (struct fwohci_softc *)sc->fc; 355103285Sikob 356103285Sikob if (!data) 357103285Sikob return(EINVAL); 358103285Sikob 359103285Sikob switch (cmd) { 360103285Sikob case FWOHCI_WRREG: 361103285Sikob#define OHCI_MAX_REG 0x800 362103285Sikob if(reg->addr <= OHCI_MAX_REG){ 363103285Sikob OWRITE(fc, reg->addr, reg->data); 364103285Sikob reg->data = OREAD(fc, reg->addr); 365103285Sikob }else{ 366103285Sikob err = EINVAL; 367103285Sikob } 368103285Sikob break; 369103285Sikob case FWOHCI_RDREG: 370103285Sikob if(reg->addr <= OHCI_MAX_REG){ 371103285Sikob reg->data = OREAD(fc, reg->addr); 372103285Sikob }else{ 373103285Sikob err = EINVAL; 374103285Sikob } 375103285Sikob break; 376103285Sikob/* Read DMA descriptors for debug */ 377103285Sikob case DUMPDMA: 378103285Sikob if(*dmach <= OHCI_MAX_DMA_CH ){ 379103285Sikob dump_dma(fc, *dmach); 380103285Sikob dump_db(fc, *dmach); 381103285Sikob }else{ 382103285Sikob err = EINVAL; 383103285Sikob } 384103285Sikob break; 385119118Ssimokawa/* Read/Write Phy registers */ 386119118Ssimokawa#define OHCI_MAX_PHY_REG 0xf 387119118Ssimokawa case FWOHCI_RDPHYREG: 388119118Ssimokawa if (reg->addr <= OHCI_MAX_PHY_REG) 389119118Ssimokawa reg->data = fwphy_rddata(fc, reg->addr); 390119118Ssimokawa else 391119118Ssimokawa err = EINVAL; 392119118Ssimokawa break; 393119118Ssimokawa case FWOHCI_WRPHYREG: 394119118Ssimokawa if (reg->addr <= OHCI_MAX_PHY_REG) 395119118Ssimokawa reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 396119118Ssimokawa else 397119118Ssimokawa err = EINVAL; 398119118Ssimokawa break; 399103285Sikob default: 400119118Ssimokawa err = EINVAL; 401103285Sikob break; 402103285Sikob } 403103285Sikob return err; 404103285Sikob} 405106790Ssimokawa 406108530Ssimokawastatic int 407108530Ssimokawafwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 408103285Sikob{ 409108530Ssimokawa u_int32_t reg, reg2; 410108530Ssimokawa int e1394a = 1; 411108530Ssimokawa/* 412108530Ssimokawa * probe PHY parameters 413108530Ssimokawa * 0. to prove PHY version, whether compliance of 1394a. 414108530Ssimokawa * 1. to probe maximum speed supported by the PHY and 415108530Ssimokawa * number of port supported by core-logic. 416108530Ssimokawa * It is not actually available port on your PC . 417108530Ssimokawa */ 418108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 419108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 420108530Ssimokawa 421108530Ssimokawa if((reg >> 5) != 7 ){ 422108530Ssimokawa sc->fc.mode &= ~FWPHYASYST; 423108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 424108530Ssimokawa sc->fc.speed = reg & FW_PHY_SPD >> 6; 425108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 426108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 427108530Ssimokawa sc->fc.speed, MAX_SPEED); 428108530Ssimokawa sc->fc.speed = MAX_SPEED; 429108530Ssimokawa } 430108530Ssimokawa device_printf(dev, 431108701Ssimokawa "Phy 1394 only %s, %d ports.\n", 432108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 433108530Ssimokawa }else{ 434108530Ssimokawa reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 435108530Ssimokawa sc->fc.mode |= FWPHYASYST; 436108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 437108530Ssimokawa sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 438108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 439108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 440108530Ssimokawa sc->fc.speed, MAX_SPEED); 441108530Ssimokawa sc->fc.speed = MAX_SPEED; 442108530Ssimokawa } 443108530Ssimokawa device_printf(dev, 444108701Ssimokawa "Phy 1394a available %s, %d ports.\n", 445108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 446108530Ssimokawa 447108530Ssimokawa /* check programPhyEnable */ 448108530Ssimokawa reg2 = fwphy_rddata(sc, 5); 449108530Ssimokawa#if 0 450108530Ssimokawa if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 451108530Ssimokawa#else /* XXX force to enable 1394a */ 452108530Ssimokawa if (e1394a) { 453108530Ssimokawa#endif 454108530Ssimokawa if (bootverbose) 455108530Ssimokawa device_printf(dev, 456108530Ssimokawa "Enable 1394a Enhancements\n"); 457108530Ssimokawa /* enable EAA EMC */ 458108530Ssimokawa reg2 |= 0x03; 459108530Ssimokawa /* set aPhyEnhanceEnable */ 460108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 461108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 462108530Ssimokawa } else { 463108530Ssimokawa /* for safe */ 464108530Ssimokawa reg2 &= ~0x83; 465108530Ssimokawa } 466108530Ssimokawa reg2 = fwphy_wrdata(sc, 5, reg2); 467108530Ssimokawa } 468108530Ssimokawa 469108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 470108530Ssimokawa if((reg >> 5) == 7 ){ 471108530Ssimokawa reg = fwphy_rddata(sc, 4); 472108530Ssimokawa reg |= 1 << 6; 473108530Ssimokawa fwphy_wrdata(sc, 4, reg); 474108530Ssimokawa reg = fwphy_rddata(sc, 4); 475108530Ssimokawa } 476108530Ssimokawa return 0; 477108530Ssimokawa} 478108530Ssimokawa 479108530Ssimokawa 480108530Ssimokawavoid 481108530Ssimokawafwohci_reset(struct fwohci_softc *sc, device_t dev) 482108530Ssimokawa{ 483108701Ssimokawa int i, max_rec, speed; 484103285Sikob u_int32_t reg, reg2; 485103285Sikob struct fwohcidb_tr *db_tr; 486103285Sikob 487108701Ssimokawa /* Disable interrupt */ 488108530Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 489108530Ssimokawa 490108701Ssimokawa /* Now stopping all DMA channel */ 491108530Ssimokawa OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 492108530Ssimokawa OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 493108530Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 494108530Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 495108530Ssimokawa 496108530Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, ~0); 497108530Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 498108530Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 499108530Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 500108530Ssimokawa } 501108530Ssimokawa 502108701Ssimokawa /* FLUSH FIFO and reset Transmitter/Reciever */ 503108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 504108530Ssimokawa if (bootverbose) 505108530Ssimokawa device_printf(dev, "resetting OHCI..."); 506108530Ssimokawa i = 0; 507108530Ssimokawa while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 508108530Ssimokawa if (i++ > 100) break; 509108530Ssimokawa DELAY(1000); 510108530Ssimokawa } 511108530Ssimokawa if (bootverbose) 512108530Ssimokawa printf("done (loop=%d)\n", i); 513108530Ssimokawa 514108701Ssimokawa /* Probe phy */ 515108701Ssimokawa fwohci_probe_phy(sc, dev); 516108701Ssimokawa 517108701Ssimokawa /* Probe link */ 518108530Ssimokawa reg = OREAD(sc, OHCI_BUS_OPT); 519108530Ssimokawa reg2 = reg | OHCI_BUSFNC; 520108701Ssimokawa max_rec = (reg & 0x0000f000) >> 12; 521108701Ssimokawa speed = (reg & 0x00000007); 522108701Ssimokawa device_printf(dev, "Link %s, max_rec %d bytes.\n", 523108701Ssimokawa linkspeed[speed], MAXREC(max_rec)); 524108701Ssimokawa /* XXX fix max_rec */ 525108701Ssimokawa sc->fc.maxrec = sc->fc.speed + 8; 526108701Ssimokawa if (max_rec != sc->fc.maxrec) { 527108701Ssimokawa reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 528108701Ssimokawa device_printf(dev, "max_rec %d -> %d\n", 529108701Ssimokawa MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 530108701Ssimokawa } 531108530Ssimokawa if (bootverbose) 532108530Ssimokawa device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 533108530Ssimokawa OWRITE(sc, OHCI_BUS_OPT, reg2); 534108530Ssimokawa 535108701Ssimokawa /* Initialize registers */ 536108530Ssimokawa OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 537113584Ssimokawa OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 538108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 539108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 540113584Ssimokawa OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 541108530Ssimokawa OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 542108701Ssimokawa fw_busreset(&sc->fc); 543108530Ssimokawa 544108701Ssimokawa /* Enable link */ 545108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 546108642Ssimokawa 547108701Ssimokawa /* Force to start async RX DMA */ 548108642Ssimokawa sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 549108642Ssimokawa sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 550108530Ssimokawa fwohci_rx_enable(sc, &sc->arrq); 551108530Ssimokawa fwohci_rx_enable(sc, &sc->arrs); 552108530Ssimokawa 553108701Ssimokawa /* Initialize async TX */ 554108701Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 555108701Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 556116978Ssimokawa 557108701Ssimokawa /* AT Retries */ 558108701Ssimokawa OWRITE(sc, FWOHCI_RETRY, 559108701Ssimokawa /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 560108701Ssimokawa (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 561116978Ssimokawa 562116978Ssimokawa sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 563116978Ssimokawa sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 564116978Ssimokawa sc->atrq.bottom = sc->atrq.top; 565116978Ssimokawa sc->atrs.bottom = sc->atrs.top; 566116978Ssimokawa 567108530Ssimokawa for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 568108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 569108530Ssimokawa db_tr->xfer = NULL; 570108530Ssimokawa } 571108530Ssimokawa for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 572108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 573108530Ssimokawa db_tr->xfer = NULL; 574108530Ssimokawa } 575108530Ssimokawa 576108701Ssimokawa 577108701Ssimokawa /* Enable interrupt */ 578108530Ssimokawa OWRITE(sc, FWOHCI_INTMASK, 579108530Ssimokawa OHCI_INT_ERR | OHCI_INT_PHY_SID 580108530Ssimokawa | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 581108530Ssimokawa | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 582108530Ssimokawa | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 583108530Ssimokawa fwohci_set_intr(&sc->fc, 1); 584108530Ssimokawa 585108530Ssimokawa} 586108530Ssimokawa 587108530Ssimokawaint 588108530Ssimokawafwohci_init(struct fwohci_softc *sc, device_t dev) 589108530Ssimokawa{ 590108530Ssimokawa int i; 591108530Ssimokawa u_int32_t reg; 592109814Ssimokawa u_int8_t ui[8]; 593108530Ssimokawa 594113584Ssimokawa#if FWOHCI_TASKQUEUE 595113584Ssimokawa TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 596113584Ssimokawa#endif 597113584Ssimokawa 598103285Sikob reg = OREAD(sc, OHCI_VERSION); 599103285Sikob device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 600103285Sikob (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 601103285Sikob 602118416Ssimokawa if (((reg>>16) & 0xff) < 1) { 603118416Ssimokawa device_printf(dev, "invalid OHCI version\n"); 604118416Ssimokawa return (ENXIO); 605118416Ssimokawa } 606118416Ssimokawa 607110045Ssimokawa/* Available Isochrounous DMA channel probe */ 608110045Ssimokawa OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 609110045Ssimokawa OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 610110045Ssimokawa reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 611110045Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 612110045Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 613110045Ssimokawa for (i = 0; i < 0x20; i++) 614110045Ssimokawa if ((reg & (1 << i)) == 0) 615110045Ssimokawa break; 616103285Sikob sc->fc.nisodma = i; 617103285Sikob device_printf(dev, "No. of Isochronous channel is %d.\n", i); 618118820Ssimokawa if (i == 0) 619118820Ssimokawa return (ENXIO); 620103285Sikob 621103285Sikob sc->fc.arq = &sc->arrq.xferq; 622103285Sikob sc->fc.ars = &sc->arrs.xferq; 623103285Sikob sc->fc.atq = &sc->atrq.xferq; 624103285Sikob sc->fc.ats = &sc->atrs.xferq; 625103285Sikob 626113584Ssimokawa sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 627113584Ssimokawa sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 628113584Ssimokawa sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 629113584Ssimokawa sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 630113584Ssimokawa 631103285Sikob sc->arrq.xferq.start = NULL; 632103285Sikob sc->arrs.xferq.start = NULL; 633103285Sikob sc->atrq.xferq.start = fwohci_start_atq; 634103285Sikob sc->atrs.xferq.start = fwohci_start_ats; 635103285Sikob 636113584Ssimokawa sc->arrq.xferq.buf = NULL; 637113584Ssimokawa sc->arrs.xferq.buf = NULL; 638113584Ssimokawa sc->atrq.xferq.buf = NULL; 639113584Ssimokawa sc->atrs.xferq.buf = NULL; 640103285Sikob 641118293Ssimokawa sc->arrq.xferq.dmach = -1; 642118293Ssimokawa sc->arrs.xferq.dmach = -1; 643118293Ssimokawa sc->atrq.xferq.dmach = -1; 644118293Ssimokawa sc->atrs.xferq.dmach = -1; 645118293Ssimokawa 646103285Sikob sc->arrq.ndesc = 1; 647103285Sikob sc->arrs.ndesc = 1; 648110593Ssimokawa sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 649110593Ssimokawa sc->atrs.ndesc = 2; 650103285Sikob 651103285Sikob sc->arrq.ndb = NDB; 652103285Sikob sc->arrs.ndb = NDB / 2; 653103285Sikob sc->atrq.ndb = NDB; 654103285Sikob sc->atrs.ndb = NDB / 2; 655103285Sikob 656103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 657103285Sikob sc->fc.it[i] = &sc->it[i].xferq; 658103285Sikob sc->fc.ir[i] = &sc->ir[i].xferq; 659118293Ssimokawa sc->it[i].xferq.dmach = i; 660118293Ssimokawa sc->ir[i].xferq.dmach = i; 661103285Sikob sc->it[i].ndb = 0; 662103285Sikob sc->ir[i].ndb = 0; 663103285Sikob } 664103285Sikob 665103285Sikob sc->fc.tcode = tinfo; 666113584Ssimokawa sc->fc.dev = dev; 667103285Sikob 668113584Ssimokawa sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 669113584Ssimokawa &sc->crom_dma, BUS_DMA_WAITOK); 670113584Ssimokawa if(sc->fc.config_rom == NULL){ 671113584Ssimokawa device_printf(dev, "config_rom alloc failed."); 672103285Sikob return ENOMEM; 673103285Sikob } 674103285Sikob 675116376Ssimokawa#if 0 676116376Ssimokawa bzero(&sc->fc.config_rom[0], CROMSIZE); 677103285Sikob sc->fc.config_rom[1] = 0x31333934; 678103285Sikob sc->fc.config_rom[2] = 0xf000a002; 679103285Sikob sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 680103285Sikob sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 681103285Sikob sc->fc.config_rom[5] = 0; 682103285Sikob sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 683103285Sikob 684103285Sikob sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 685113584Ssimokawa#endif 686103285Sikob 687103285Sikob 688103285Sikob/* SID recieve buffer must allign 2^11 */ 689103285Sikob#define OHCI_SIDSIZE (1 << 11) 690113584Ssimokawa sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 691113584Ssimokawa &sc->sid_dma, BUS_DMA_WAITOK); 692113584Ssimokawa if (sc->sid_buf == NULL) { 693113584Ssimokawa device_printf(dev, "sid_buf alloc failed."); 694108527Ssimokawa return ENOMEM; 695108527Ssimokawa } 696113584Ssimokawa 697113584Ssimokawa fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t), 698113584Ssimokawa &sc->dummy_dma, BUS_DMA_WAITOK); 699113584Ssimokawa 700113584Ssimokawa if (sc->dummy_dma.v_addr == NULL) { 701113584Ssimokawa device_printf(dev, "dummy_dma alloc failed."); 702109736Ssimokawa return ENOMEM; 703109736Ssimokawa } 704113584Ssimokawa 705113584Ssimokawa fwohci_db_init(sc, &sc->arrq); 706108527Ssimokawa if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 707108527Ssimokawa return ENOMEM; 708108527Ssimokawa 709113584Ssimokawa fwohci_db_init(sc, &sc->arrs); 710108527Ssimokawa if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 711108527Ssimokawa return ENOMEM; 712103285Sikob 713113584Ssimokawa fwohci_db_init(sc, &sc->atrq); 714108527Ssimokawa if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 715108527Ssimokawa return ENOMEM; 716108527Ssimokawa 717113584Ssimokawa fwohci_db_init(sc, &sc->atrs); 718108527Ssimokawa if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 719108527Ssimokawa return ENOMEM; 720103285Sikob 721109814Ssimokawa sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 722109814Ssimokawa sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 723109814Ssimokawa for( i = 0 ; i < 8 ; i ++) 724109814Ssimokawa ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 725103285Sikob device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 726109814Ssimokawa ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 727109814Ssimokawa 728103285Sikob sc->fc.ioctl = fwohci_ioctl; 729103285Sikob sc->fc.cyctimer = fwohci_cyctimer; 730103285Sikob sc->fc.set_bmr = fwohci_set_bus_manager; 731103285Sikob sc->fc.ibr = fwohci_ibr; 732103285Sikob sc->fc.irx_enable = fwohci_irx_enable; 733103285Sikob sc->fc.irx_disable = fwohci_irx_disable; 734103285Sikob 735103285Sikob sc->fc.itx_enable = fwohci_itxbuf_enable; 736103285Sikob sc->fc.itx_disable = fwohci_itx_disable; 737113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 738103285Sikob sc->fc.irx_post = fwohci_irx_post; 739113584Ssimokawa#else 740113584Ssimokawa sc->fc.irx_post = NULL; 741113584Ssimokawa#endif 742103285Sikob sc->fc.itx_post = NULL; 743103285Sikob sc->fc.timeout = fwohci_timeout; 744103285Sikob sc->fc.poll = fwohci_poll; 745103285Sikob sc->fc.set_intr = fwohci_set_intr; 746106790Ssimokawa 747113584Ssimokawa sc->intmask = sc->irstat = sc->itstat = 0; 748113584Ssimokawa 749108530Ssimokawa fw_init(&sc->fc); 750108530Ssimokawa fwohci_reset(sc, dev); 751103285Sikob 752108530Ssimokawa return 0; 753103285Sikob} 754106790Ssimokawa 755106790Ssimokawavoid 756106790Ssimokawafwohci_timeout(void *arg) 757103285Sikob{ 758103285Sikob struct fwohci_softc *sc; 759103285Sikob 760103285Sikob sc = (struct fwohci_softc *)arg; 761103285Sikob} 762106790Ssimokawa 763106790Ssimokawau_int32_t 764106790Ssimokawafwohci_cyctimer(struct firewire_comm *fc) 765103285Sikob{ 766103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 767103285Sikob return(OREAD(sc, OHCI_CYCLETIMER)); 768103285Sikob} 769103285Sikob 770108527Ssimokawaint 771108527Ssimokawafwohci_detach(struct fwohci_softc *sc, device_t dev) 772108527Ssimokawa{ 773108527Ssimokawa int i; 774108527Ssimokawa 775113584Ssimokawa if (sc->sid_buf != NULL) 776113584Ssimokawa fwdma_free(&sc->fc, &sc->sid_dma); 777113584Ssimokawa if (sc->fc.config_rom != NULL) 778113584Ssimokawa fwdma_free(&sc->fc, &sc->crom_dma); 779108527Ssimokawa 780108527Ssimokawa fwohci_db_free(&sc->arrq); 781108527Ssimokawa fwohci_db_free(&sc->arrs); 782108527Ssimokawa 783108527Ssimokawa fwohci_db_free(&sc->atrq); 784108527Ssimokawa fwohci_db_free(&sc->atrs); 785108527Ssimokawa 786108527Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 787108527Ssimokawa fwohci_db_free(&sc->it[i]); 788108527Ssimokawa fwohci_db_free(&sc->ir[i]); 789108527Ssimokawa } 790108527Ssimokawa 791108527Ssimokawa return 0; 792108527Ssimokawa} 793108527Ssimokawa 794108655Ssimokawa#define LAST_DB(dbtr, db) do { \ 795108655Ssimokawa struct fwohcidb_tr *_dbtr = (dbtr); \ 796108655Ssimokawa int _cnt = _dbtr->dbcnt; \ 797108655Ssimokawa db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 798108655Ssimokawa} while (0) 799108655Ssimokawa 800106790Ssimokawastatic void 801113584Ssimokawafwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 802113584Ssimokawa{ 803113584Ssimokawa struct fwohcidb_tr *db_tr; 804113584Ssimokawa volatile struct fwohcidb *db; 805113584Ssimokawa bus_dma_segment_t *s; 806113584Ssimokawa int i; 807113584Ssimokawa 808113584Ssimokawa db_tr = (struct fwohcidb_tr *)arg; 809113584Ssimokawa db = &db_tr->db[db_tr->dbcnt]; 810113584Ssimokawa if (error) { 811113584Ssimokawa if (firewire_debug || error != EFBIG) 812113584Ssimokawa printf("fwohci_execute_db: error=%d\n", error); 813113584Ssimokawa return; 814113584Ssimokawa } 815113584Ssimokawa for (i = 0; i < nseg; i++) { 816113584Ssimokawa s = &segs[i]; 817113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 818113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 819113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 0); 820113584Ssimokawa db++; 821113584Ssimokawa db_tr->dbcnt++; 822113584Ssimokawa } 823113584Ssimokawa} 824113584Ssimokawa 825113584Ssimokawastatic void 826113584Ssimokawafwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 827113584Ssimokawa bus_size_t size, int error) 828113584Ssimokawa{ 829113584Ssimokawa fwohci_execute_db(arg, segs, nseg, error); 830113584Ssimokawa} 831113584Ssimokawa 832113584Ssimokawastatic void 833106790Ssimokawafwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 834103285Sikob{ 835103285Sikob int i, s; 836113584Ssimokawa int tcode, hdr_len, pl_off, pl_len; 837103285Sikob int fsegment = -1; 838103285Sikob u_int32_t off; 839103285Sikob struct fw_xfer *xfer; 840103285Sikob struct fw_pkt *fp; 841103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 842103285Sikob struct fwohcidb_tr *db_tr; 843103285Sikob volatile struct fwohcidb *db; 844103285Sikob struct tcode_info *info; 845108655Ssimokawa static int maxdesc=0; 846103285Sikob 847103285Sikob if(&sc->atrq == dbch){ 848103285Sikob off = OHCI_ATQOFF; 849103285Sikob }else if(&sc->atrs == dbch){ 850103285Sikob off = OHCI_ATSOFF; 851103285Sikob }else{ 852103285Sikob return; 853103285Sikob } 854103285Sikob 855103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) 856103285Sikob return; 857103285Sikob 858103285Sikob s = splfw(); 859103285Sikob db_tr = dbch->top; 860103285Sikobtxloop: 861103285Sikob xfer = STAILQ_FIRST(&dbch->xferq.q); 862103285Sikob if(xfer == NULL){ 863103285Sikob goto kick; 864103285Sikob } 865103285Sikob if(dbch->xferq.queued == 0 ){ 866103285Sikob device_printf(sc->fc.dev, "TX queue empty\n"); 867103285Sikob } 868103285Sikob STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 869103285Sikob db_tr->xfer = xfer; 870103285Sikob xfer->state = FWXF_START; 871103285Sikob 872113584Ssimokawa fp = (struct fw_pkt *)xfer->send.buf; 873103285Sikob tcode = fp->mode.common.tcode; 874103285Sikob 875103285Sikob ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 876103285Sikob info = &tinfo[tcode]; 877113584Ssimokawa hdr_len = pl_off = info->hdr_len; 878113584Ssimokawa for( i = 0 ; i < pl_off ; i+= 4){ 879113584Ssimokawa ohcifp->mode.ld[i/4] = fp->mode.ld[i/4]; 880103285Sikob } 881103285Sikob ohcifp->mode.common.spd = xfer->spd; 882103285Sikob if (tcode == FWTCODE_STREAM ){ 883103285Sikob hdr_len = 8; 884113584Ssimokawa ohcifp->mode.stream.len = fp->mode.stream.len; 885103285Sikob } else if (tcode == FWTCODE_PHY) { 886103285Sikob hdr_len = 12; 887113584Ssimokawa ohcifp->mode.ld[1] = fp->mode.ld[1]; 888113584Ssimokawa ohcifp->mode.ld[2] = fp->mode.ld[2]; 889103285Sikob ohcifp->mode.common.spd = 0; 890103285Sikob ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 891103285Sikob } else { 892113584Ssimokawa ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 893103285Sikob ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 894103285Sikob ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 895103285Sikob } 896103285Sikob db = &db_tr->db[0]; 897113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.cmd, 898113584Ssimokawa OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 899113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 0); 900103285Sikob/* Specify bound timer of asy. responce */ 901103285Sikob if(&sc->atrs == dbch){ 902113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, 903113584Ssimokawa (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 904103285Sikob } 905113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 906113584Ssimokawa if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 907113584Ssimokawa hdr_len = 12; 908113584Ssimokawa for (i = 0; i < hdr_len/4; i ++) 909113584Ssimokawa FWOHCI_DMA_WRITE(ohcifp->mode.ld[i], ohcifp->mode.ld[i]); 910113584Ssimokawa#endif 911103285Sikob 912111942Ssimokawaagain: 913103285Sikob db_tr->dbcnt = 2; 914103285Sikob db = &db_tr->db[db_tr->dbcnt]; 915113584Ssimokawa pl_len = xfer->send.len - pl_off; 916113584Ssimokawa if (pl_len > 0) { 917113584Ssimokawa int err; 918113584Ssimokawa /* handle payload */ 919103285Sikob if (xfer->mbuf == NULL) { 920113584Ssimokawa caddr_t pl_addr; 921103285Sikob 922113584Ssimokawa pl_addr = xfer->send.buf + pl_off; 923113584Ssimokawa err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 924113584Ssimokawa pl_addr, pl_len, 925113584Ssimokawa fwohci_execute_db, db_tr, 926113584Ssimokawa /*flags*/0); 927103285Sikob } else { 928111942Ssimokawa /* XXX we can handle only 6 (=8-2) mbuf chains */ 929113584Ssimokawa err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 930113584Ssimokawa xfer->mbuf, 931113584Ssimokawa fwohci_execute_db2, db_tr, 932113584Ssimokawa /* flags */0); 933113584Ssimokawa if (err == EFBIG) { 934113584Ssimokawa struct mbuf *m0; 935113584Ssimokawa 936113584Ssimokawa if (firewire_debug) 937113584Ssimokawa device_printf(sc->fc.dev, "EFBIG.\n"); 938113584Ssimokawa m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 939113584Ssimokawa if (m0 != NULL) { 940111942Ssimokawa m_copydata(xfer->mbuf, 0, 941111942Ssimokawa xfer->mbuf->m_pkthdr.len, 942113584Ssimokawa mtod(m0, caddr_t)); 943113584Ssimokawa m0->m_len = m0->m_pkthdr.len = 944111942Ssimokawa xfer->mbuf->m_pkthdr.len; 945111942Ssimokawa m_freem(xfer->mbuf); 946113584Ssimokawa xfer->mbuf = m0; 947111942Ssimokawa goto again; 948111942Ssimokawa } 949111942Ssimokawa device_printf(sc->fc.dev, "m_getcl failed.\n"); 950111942Ssimokawa } 951103285Sikob } 952113584Ssimokawa if (err) 953113584Ssimokawa printf("dmamap_load: err=%d\n", err); 954113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 955113584Ssimokawa BUS_DMASYNC_PREWRITE); 956113584Ssimokawa#if 0 /* OHCI_OUTPUT_MODE == 0 */ 957113584Ssimokawa for (i = 2; i < db_tr->dbcnt; i++) 958113584Ssimokawa FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 959113584Ssimokawa OHCI_OUTPUT_MORE); 960113584Ssimokawa#endif 961103285Sikob } 962108655Ssimokawa if (maxdesc < db_tr->dbcnt) { 963108655Ssimokawa maxdesc = db_tr->dbcnt; 964108655Ssimokawa if (bootverbose) 965108655Ssimokawa device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 966108655Ssimokawa } 967103285Sikob /* last db */ 968103285Sikob LAST_DB(db_tr, db); 969113584Ssimokawa FWOHCI_DMA_SET(db->db.desc.cmd, 970113584Ssimokawa OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 971113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.depend, 972113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr); 973103285Sikob 974103285Sikob if(fsegment == -1 ) 975103285Sikob fsegment = db_tr->dbcnt; 976103285Sikob if (dbch->pdb_tr != NULL) { 977103285Sikob LAST_DB(dbch->pdb_tr, db); 978113584Ssimokawa FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 979103285Sikob } 980103285Sikob dbch->pdb_tr = db_tr; 981103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 982103285Sikob if(db_tr != dbch->bottom){ 983103285Sikob goto txloop; 984103285Sikob } else { 985107653Ssimokawa device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 986103285Sikob dbch->flags |= FWOHCI_DBCH_FULL; 987103285Sikob } 988103285Sikobkick: 989103285Sikob /* kick asy q */ 990113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 991113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 992103285Sikob 993103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) { 994103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 995103285Sikob } else { 996107653Ssimokawa if (bootverbose) 997107653Ssimokawa device_printf(sc->fc.dev, "start AT DMA status=%x\n", 998103285Sikob OREAD(sc, OHCI_DMACTL(off))); 999113584Ssimokawa OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1000103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1001103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1002103285Sikob } 1003106790Ssimokawa 1004103285Sikob dbch->top = db_tr; 1005103285Sikob splx(s); 1006103285Sikob return; 1007103285Sikob} 1008106790Ssimokawa 1009106790Ssimokawastatic void 1010106790Ssimokawafwohci_start_atq(struct firewire_comm *fc) 1011103285Sikob{ 1012103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1013103285Sikob fwohci_start( sc, &(sc->atrq)); 1014103285Sikob return; 1015103285Sikob} 1016106790Ssimokawa 1017106790Ssimokawastatic void 1018106790Ssimokawafwohci_start_ats(struct firewire_comm *fc) 1019103285Sikob{ 1020103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1021103285Sikob fwohci_start( sc, &(sc->atrs)); 1022103285Sikob return; 1023103285Sikob} 1024106790Ssimokawa 1025106790Ssimokawavoid 1026106790Ssimokawafwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1027103285Sikob{ 1028113584Ssimokawa int s, ch, err = 0; 1029103285Sikob struct fwohcidb_tr *tr; 1030103285Sikob volatile struct fwohcidb *db; 1031103285Sikob struct fw_xfer *xfer; 1032103285Sikob u_int32_t off; 1033113584Ssimokawa u_int stat, status; 1034103285Sikob int packets; 1035103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1036113584Ssimokawa 1037103285Sikob if(&sc->atrq == dbch){ 1038103285Sikob off = OHCI_ATQOFF; 1039113584Ssimokawa ch = ATRQ_CH; 1040103285Sikob }else if(&sc->atrs == dbch){ 1041103285Sikob off = OHCI_ATSOFF; 1042113584Ssimokawa ch = ATRS_CH; 1043103285Sikob }else{ 1044103285Sikob return; 1045103285Sikob } 1046103285Sikob s = splfw(); 1047103285Sikob tr = dbch->bottom; 1048103285Sikob packets = 0; 1049113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 1050113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 1051103285Sikob while(dbch->xferq.queued > 0){ 1052103285Sikob LAST_DB(tr, db); 1053113584Ssimokawa status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1054113584Ssimokawa if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1055103285Sikob if (fc->status != FWBUSRESET) 1056103285Sikob /* maybe out of order?? */ 1057103285Sikob goto out; 1058103285Sikob } 1059113584Ssimokawa bus_dmamap_sync(dbch->dmat, tr->dma_map, 1060113584Ssimokawa BUS_DMASYNC_POSTWRITE); 1061113584Ssimokawa bus_dmamap_unload(dbch->dmat, tr->dma_map); 1062113584Ssimokawa#if 0 1063113584Ssimokawa dump_db(sc, ch); 1064103285Sikob#endif 1065113584Ssimokawa if(status & OHCI_CNTL_DMA_DEAD) { 1066113584Ssimokawa /* Stop DMA */ 1067103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1068103285Sikob device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1069103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1070103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1071103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1072103285Sikob } 1073113584Ssimokawa stat = status & FWOHCIEV_MASK; 1074103285Sikob switch(stat){ 1075110577Ssimokawa case FWOHCIEV_ACKPEND: 1076103285Sikob case FWOHCIEV_ACKCOMPL: 1077103285Sikob err = 0; 1078103285Sikob break; 1079103285Sikob case FWOHCIEV_ACKBSA: 1080103285Sikob case FWOHCIEV_ACKBSB: 1081110577Ssimokawa case FWOHCIEV_ACKBSX: 1082103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1083103285Sikob err = EBUSY; 1084103285Sikob break; 1085103285Sikob case FWOHCIEV_FLUSHED: 1086103285Sikob case FWOHCIEV_ACKTARD: 1087103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1088103285Sikob err = EAGAIN; 1089103285Sikob break; 1090103285Sikob case FWOHCIEV_MISSACK: 1091103285Sikob case FWOHCIEV_UNDRRUN: 1092103285Sikob case FWOHCIEV_OVRRUN: 1093103285Sikob case FWOHCIEV_DESCERR: 1094103285Sikob case FWOHCIEV_DTRDERR: 1095103285Sikob case FWOHCIEV_TIMEOUT: 1096103285Sikob case FWOHCIEV_TCODERR: 1097103285Sikob case FWOHCIEV_UNKNOWN: 1098103285Sikob case FWOHCIEV_ACKDERR: 1099103285Sikob case FWOHCIEV_ACKTERR: 1100103285Sikob default: 1101103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", 1102103285Sikob stat, fwohcicode[stat]); 1103103285Sikob err = EINVAL; 1104103285Sikob break; 1105103285Sikob } 1106110577Ssimokawa if (tr->xfer != NULL) { 1107103285Sikob xfer = tr->xfer; 1108113584Ssimokawa if (xfer->state == FWXF_RCVD) { 1109113584Ssimokawa if (firewire_debug) 1110113584Ssimokawa printf("already rcvd\n"); 1111113584Ssimokawa fw_xfer_done(xfer); 1112113584Ssimokawa } else { 1113114218Ssimokawa xfer->state = FWXF_SENT; 1114114218Ssimokawa if (err == EBUSY && fc->status != FWBUSRESET) { 1115114218Ssimokawa xfer->state = FWXF_BUSY; 1116114218Ssimokawa xfer->resp = err; 1117114218Ssimokawa if (xfer->retry_req != NULL) 1118114218Ssimokawa xfer->retry_req(xfer); 1119114224Ssimokawa else { 1120114224Ssimokawa xfer->recv.len = 0; 1121114218Ssimokawa fw_xfer_done(xfer); 1122114224Ssimokawa } 1123114218Ssimokawa } else if (stat != FWOHCIEV_ACKPEND) { 1124114218Ssimokawa if (stat != FWOHCIEV_ACKCOMPL) 1125114218Ssimokawa xfer->state = FWXF_SENTERR; 1126114218Ssimokawa xfer->resp = err; 1127114224Ssimokawa xfer->recv.len = 0; 1128113584Ssimokawa fw_xfer_done(xfer); 1129114218Ssimokawa } 1130103285Sikob } 1131110577Ssimokawa /* 1132110577Ssimokawa * The watchdog timer takes care of split 1133110577Ssimokawa * transcation timeout for ACKPEND case. 1134110577Ssimokawa */ 1135113584Ssimokawa } else { 1136113584Ssimokawa printf("this shouldn't happen\n"); 1137103285Sikob } 1138110269Ssimokawa dbch->xferq.queued --; 1139103285Sikob tr->xfer = NULL; 1140103285Sikob 1141103285Sikob packets ++; 1142103285Sikob tr = STAILQ_NEXT(tr, link); 1143103285Sikob dbch->bottom = tr; 1144111956Ssimokawa if (dbch->bottom == dbch->top) { 1145111956Ssimokawa /* we reaches the end of context program */ 1146111956Ssimokawa if (firewire_debug && dbch->xferq.queued > 0) 1147111956Ssimokawa printf("queued > 0\n"); 1148111956Ssimokawa break; 1149111956Ssimokawa } 1150103285Sikob } 1151103285Sikobout: 1152103285Sikob if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1153103285Sikob printf("make free slot\n"); 1154103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1155103285Sikob fwohci_start(sc, dbch); 1156103285Sikob } 1157103285Sikob splx(s); 1158103285Sikob} 1159106790Ssimokawa 1160106790Ssimokawastatic void 1161106790Ssimokawafwohci_db_free(struct fwohci_dbch *dbch) 1162103285Sikob{ 1163103285Sikob struct fwohcidb_tr *db_tr; 1164113584Ssimokawa int idb; 1165103285Sikob 1166108527Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1167108527Ssimokawa return; 1168108527Ssimokawa 1169113584Ssimokawa for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1170103285Sikob db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1171113584Ssimokawa if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1172113584Ssimokawa db_tr->buf != NULL) { 1173113584Ssimokawa fwdma_free_size(dbch->dmat, db_tr->dma_map, 1174113584Ssimokawa db_tr->buf, dbch->xferq.psize); 1175113584Ssimokawa db_tr->buf = NULL; 1176113584Ssimokawa } else if (db_tr->dma_map != NULL) 1177113584Ssimokawa bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1178103285Sikob } 1179103285Sikob dbch->ndb = 0; 1180103285Sikob db_tr = STAILQ_FIRST(&dbch->db_trq); 1181113584Ssimokawa fwdma_free_multiseg(dbch->am); 1182110195Ssimokawa free(db_tr, M_FW); 1183103285Sikob STAILQ_INIT(&dbch->db_trq); 1184108527Ssimokawa dbch->flags &= ~FWOHCI_DBCH_INIT; 1185103285Sikob} 1186106790Ssimokawa 1187106790Ssimokawastatic void 1188113584Ssimokawafwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1189103285Sikob{ 1190103285Sikob int idb; 1191103285Sikob struct fwohcidb_tr *db_tr; 1192108642Ssimokawa 1193108642Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1194108642Ssimokawa goto out; 1195108642Ssimokawa 1196113584Ssimokawa /* create dma_tag for buffers */ 1197113584Ssimokawa#define MAX_REQCOUNT 0xffff 1198113584Ssimokawa if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1199113584Ssimokawa /*alignment*/ 1, /*boundary*/ 0, 1200113584Ssimokawa /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1201113584Ssimokawa /*highaddr*/ BUS_SPACE_MAXADDR, 1202113584Ssimokawa /*filter*/NULL, /*filterarg*/NULL, 1203113584Ssimokawa /*maxsize*/ dbch->xferq.psize, 1204113584Ssimokawa /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1205113584Ssimokawa /*maxsegsz*/ MAX_REQCOUNT, 1206117126Sscottl /*flags*/ 0, 1207117228Ssimokawa#if __FreeBSD_version >= 501102 1208117126Sscottl /*lockfunc*/busdma_lock_mutex, 1209117228Ssimokawa /*lockarg*/&Giant, 1210117228Ssimokawa#endif 1211117228Ssimokawa &dbch->dmat)) 1212113584Ssimokawa return; 1213113584Ssimokawa 1214103285Sikob /* allocate DB entries and attach one to each DMA channels */ 1215103285Sikob /* DB entry must start at 16 bytes bounary. */ 1216103285Sikob STAILQ_INIT(&dbch->db_trq); 1217103285Sikob db_tr = (struct fwohcidb_tr *) 1218103285Sikob malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1219113584Ssimokawa M_FW, M_WAITOK | M_ZERO); 1220103285Sikob if(db_tr == NULL){ 1221109379Ssimokawa printf("fwohci_db_init: malloc(1) failed\n"); 1222103285Sikob return; 1223103285Sikob } 1224109379Ssimokawa 1225113584Ssimokawa#define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1226113584Ssimokawa dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1227113584Ssimokawa DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1228113584Ssimokawa if (dbch->am == NULL) { 1229113584Ssimokawa printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1230103285Sikob return; 1231103285Sikob } 1232103285Sikob /* Attach DB to DMA ch. */ 1233103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb++){ 1234103285Sikob db_tr->dbcnt = 0; 1235113584Ssimokawa db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1236113584Ssimokawa db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1237113584Ssimokawa /* create dmamap for buffers */ 1238113584Ssimokawa /* XXX do we need 4bytes alignment tag? */ 1239113584Ssimokawa /* XXX don't alloc dma_map for AR */ 1240113584Ssimokawa if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1241113584Ssimokawa printf("bus_dmamap_create failed\n"); 1242113584Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1243113584Ssimokawa fwohci_db_free(dbch); 1244113584Ssimokawa return; 1245113584Ssimokawa } 1246103285Sikob STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1247113584Ssimokawa if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1248108530Ssimokawa if (idb % dbch->xferq.bnpacket == 0) 1249108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1250108530Ssimokawa ].start = (caddr_t)db_tr; 1251108530Ssimokawa if ((idb + 1) % dbch->xferq.bnpacket == 0) 1252108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1253108530Ssimokawa ].end = (caddr_t)db_tr; 1254103285Sikob } 1255103285Sikob db_tr++; 1256103285Sikob } 1257103285Sikob STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1258103285Sikob = STAILQ_FIRST(&dbch->db_trq); 1259108642Ssimokawaout: 1260108642Ssimokawa dbch->xferq.queued = 0; 1261108642Ssimokawa dbch->pdb_tr = NULL; 1262103285Sikob dbch->top = STAILQ_FIRST(&dbch->db_trq); 1263103285Sikob dbch->bottom = dbch->top; 1264108527Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; 1265103285Sikob} 1266106790Ssimokawa 1267106790Ssimokawastatic int 1268106790Ssimokawafwohci_itx_disable(struct firewire_comm *fc, int dmach) 1269103285Sikob{ 1270103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1271113584Ssimokawa int sleepch; 1272109890Ssimokawa 1273113584Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 1274113584Ssimokawa OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1275103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1276103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1277109890Ssimokawa /* XXX we cannot free buffers until the DMA really stops */ 1278113584Ssimokawa tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1279103285Sikob fwohci_db_free(&sc->it[dmach]); 1280103285Sikob sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1281103285Sikob return 0; 1282103285Sikob} 1283106790Ssimokawa 1284106790Ssimokawastatic int 1285106790Ssimokawafwohci_irx_disable(struct firewire_comm *fc, int dmach) 1286103285Sikob{ 1287103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1288113584Ssimokawa int sleepch; 1289103285Sikob 1290103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1291103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1292103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1293109890Ssimokawa /* XXX we cannot free buffers until the DMA really stops */ 1294113584Ssimokawa tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1295103285Sikob fwohci_db_free(&sc->ir[dmach]); 1296103285Sikob sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1297103285Sikob return 0; 1298103285Sikob} 1299106790Ssimokawa 1300113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 1301106790Ssimokawastatic void 1302106790Ssimokawafwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1303103285Sikob{ 1304113584Ssimokawa qld[0] = FWOHCI_DMA_READ(qld[0]); 1305103285Sikob return; 1306103285Sikob} 1307103285Sikob#endif 1308103285Sikob 1309106790Ssimokawastatic int 1310106790Ssimokawafwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1311103285Sikob{ 1312103285Sikob int err = 0; 1313113584Ssimokawa int idb, z, i, dmach = 0, ldesc; 1314103285Sikob u_int32_t off = NULL; 1315103285Sikob struct fwohcidb_tr *db_tr; 1316109892Ssimokawa volatile struct fwohcidb *db; 1317103285Sikob 1318103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1319103285Sikob err = EINVAL; 1320103285Sikob return err; 1321103285Sikob } 1322103285Sikob z = dbch->ndesc; 1323103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1324103285Sikob if( &sc->it[dmach] == dbch){ 1325103285Sikob off = OHCI_ITOFF(dmach); 1326103285Sikob break; 1327103285Sikob } 1328103285Sikob } 1329103285Sikob if(off == NULL){ 1330103285Sikob err = EINVAL; 1331103285Sikob return err; 1332103285Sikob } 1333103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1334103285Sikob return err; 1335103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1336103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1337103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1338103285Sikob } 1339103285Sikob db_tr = dbch->top; 1340113584Ssimokawa for (idb = 0; idb < dbch->ndb; idb ++) { 1341113584Ssimokawa fwohci_add_tx_buf(dbch, db_tr, idb); 1342103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1343103285Sikob break; 1344103285Sikob } 1345109892Ssimokawa db = db_tr->db; 1346113584Ssimokawa ldesc = db_tr->dbcnt - 1; 1347113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1348113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr | z); 1349113584Ssimokawa db[ldesc].db.desc.depend = db[0].db.desc.depend; 1350103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1351103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1352113584Ssimokawa FWOHCI_DMA_SET( 1353113584Ssimokawa db[ldesc].db.desc.cmd, 1354113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1355109280Ssimokawa /* OHCI 1.1 and above */ 1356113584Ssimokawa FWOHCI_DMA_SET( 1357113584Ssimokawa db[0].db.desc.cmd, 1358113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1359103285Sikob } 1360103285Sikob } 1361103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1362103285Sikob } 1363113584Ssimokawa FWOHCI_DMA_CLEAR( 1364113584Ssimokawa dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1365103285Sikob return err; 1366103285Sikob} 1367106790Ssimokawa 1368106790Ssimokawastatic int 1369106790Ssimokawafwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1370103285Sikob{ 1371103285Sikob int err = 0; 1372109892Ssimokawa int idb, z, i, dmach = 0, ldesc; 1373103285Sikob u_int32_t off = NULL; 1374103285Sikob struct fwohcidb_tr *db_tr; 1375109892Ssimokawa volatile struct fwohcidb *db; 1376103285Sikob 1377103285Sikob z = dbch->ndesc; 1378103285Sikob if(&sc->arrq == dbch){ 1379103285Sikob off = OHCI_ARQOFF; 1380103285Sikob }else if(&sc->arrs == dbch){ 1381103285Sikob off = OHCI_ARSOFF; 1382103285Sikob }else{ 1383103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1384103285Sikob if( &sc->ir[dmach] == dbch){ 1385103285Sikob off = OHCI_IROFF(dmach); 1386103285Sikob break; 1387103285Sikob } 1388103285Sikob } 1389103285Sikob } 1390103285Sikob if(off == NULL){ 1391103285Sikob err = EINVAL; 1392103285Sikob return err; 1393103285Sikob } 1394103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1395103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1396103285Sikob return err; 1397103285Sikob }else{ 1398103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1399103285Sikob err = EBUSY; 1400103285Sikob return err; 1401103285Sikob } 1402103285Sikob } 1403103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1404108642Ssimokawa dbch->top = STAILQ_FIRST(&dbch->db_trq); 1405103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1406103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1407103285Sikob } 1408103285Sikob db_tr = dbch->top; 1409113584Ssimokawa for (idb = 0; idb < dbch->ndb; idb ++) { 1410113584Ssimokawa fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1411113584Ssimokawa if (STAILQ_NEXT(db_tr, link) == NULL) 1412103285Sikob break; 1413109892Ssimokawa db = db_tr->db; 1414109892Ssimokawa ldesc = db_tr->dbcnt - 1; 1415113584Ssimokawa FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1416113584Ssimokawa STAILQ_NEXT(db_tr, link)->bus_addr | z); 1417103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1418103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1419113584Ssimokawa FWOHCI_DMA_SET( 1420113584Ssimokawa db[ldesc].db.desc.cmd, 1421113584Ssimokawa OHCI_INTERRUPT_ALWAYS); 1422113584Ssimokawa FWOHCI_DMA_CLEAR( 1423113584Ssimokawa db[ldesc].db.desc.depend, 1424113584Ssimokawa 0xf); 1425103285Sikob } 1426103285Sikob } 1427103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1428103285Sikob } 1429113584Ssimokawa FWOHCI_DMA_CLEAR( 1430113584Ssimokawa dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1431103285Sikob dbch->buf_offset = 0; 1432113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1433113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1434103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1435103285Sikob return err; 1436103285Sikob }else{ 1437113584Ssimokawa OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1438103285Sikob } 1439103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1440103285Sikob return err; 1441103285Sikob} 1442106790Ssimokawa 1443106790Ssimokawastatic int 1444113584Ssimokawafwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1445109890Ssimokawa{ 1446109890Ssimokawa int sec, cycle, cycle_match; 1447109890Ssimokawa 1448109890Ssimokawa cycle = cycle_now & 0x1fff; 1449109890Ssimokawa sec = cycle_now >> 13; 1450109890Ssimokawa#define CYCLE_MOD 0x10 1451113584Ssimokawa#if 1 1452109890Ssimokawa#define CYCLE_DELAY 8 /* min delay to start DMA */ 1453113584Ssimokawa#else 1454113584Ssimokawa#define CYCLE_DELAY 7000 /* min delay to start DMA */ 1455113584Ssimokawa#endif 1456109890Ssimokawa cycle = cycle + CYCLE_DELAY; 1457109890Ssimokawa if (cycle >= 8000) { 1458109890Ssimokawa sec ++; 1459109890Ssimokawa cycle -= 8000; 1460109890Ssimokawa } 1461113584Ssimokawa cycle = roundup2(cycle, CYCLE_MOD); 1462109890Ssimokawa if (cycle >= 8000) { 1463109890Ssimokawa sec ++; 1464109890Ssimokawa if (cycle == 8000) 1465109890Ssimokawa cycle = 0; 1466109890Ssimokawa else 1467109890Ssimokawa cycle = CYCLE_MOD; 1468109890Ssimokawa } 1469109890Ssimokawa cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1470109890Ssimokawa 1471109890Ssimokawa return(cycle_match); 1472109890Ssimokawa} 1473109890Ssimokawa 1474109890Ssimokawastatic int 1475106790Ssimokawafwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1476103285Sikob{ 1477103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1478103285Sikob int err = 0; 1479103285Sikob unsigned short tag, ich; 1480103285Sikob struct fwohci_dbch *dbch; 1481109890Ssimokawa int cycle_match, cycle_now, s, ldesc; 1482109356Ssimokawa u_int32_t stat; 1483109890Ssimokawa struct fw_bulkxfer *first, *chunk, *prev; 1484109890Ssimokawa struct fw_xferq *it; 1485103285Sikob 1486103285Sikob dbch = &sc->it[dmach]; 1487109890Ssimokawa it = &dbch->xferq; 1488109890Ssimokawa 1489109890Ssimokawa tag = (it->flag >> 6) & 3; 1490109890Ssimokawa ich = it->flag & 0x3f; 1491109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1492109890Ssimokawa dbch->ndb = it->bnpacket * it->bnchunk; 1493103285Sikob dbch->ndesc = 3; 1494113584Ssimokawa fwohci_db_init(sc, dbch); 1495109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1496109179Ssimokawa return ENOMEM; 1497103285Sikob err = fwohci_tx_enable(sc, dbch); 1498103285Sikob } 1499103285Sikob if(err) 1500103285Sikob return err; 1501109890Ssimokawa 1502109892Ssimokawa ldesc = dbch->ndesc - 1; 1503109890Ssimokawa s = splfw(); 1504109890Ssimokawa prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1505109890Ssimokawa while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1506109890Ssimokawa volatile struct fwohcidb *db; 1507109890Ssimokawa 1508113584Ssimokawa fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1509113584Ssimokawa BUS_DMASYNC_PREWRITE); 1510109890Ssimokawa fwohci_txbufdb(sc, dmach, chunk); 1511109890Ssimokawa if (prev != NULL) { 1512109890Ssimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 1513113584Ssimokawa#if 0 /* XXX necessary? */ 1514113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1515113584Ssimokawa OHCI_BRANCH_ALWAYS); 1516113584Ssimokawa#endif 1517109892Ssimokawa#if 0 /* if bulkxfer->npacket changes */ 1518109890Ssimokawa db[ldesc].db.desc.depend = db[0].db.desc.depend = 1519113584Ssimokawa ((struct fwohcidb_tr *) 1520113584Ssimokawa (chunk->start))->bus_addr | dbch->ndesc; 1521109892Ssimokawa#else 1522113584Ssimokawa FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1523113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1524109892Ssimokawa#endif 1525103285Sikob } 1526109890Ssimokawa STAILQ_REMOVE_HEAD(&it->stvalid, link); 1527109890Ssimokawa STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1528109890Ssimokawa prev = chunk; 1529109403Ssimokawa } 1530113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1531113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1532109890Ssimokawa splx(s); 1533109890Ssimokawa stat = OREAD(sc, OHCI_ITCTL(dmach)); 1534113584Ssimokawa if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1535113584Ssimokawa printf("stat 0x%x\n", stat); 1536113584Ssimokawa 1537109890Ssimokawa if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1538109890Ssimokawa return 0; 1539109890Ssimokawa 1540113584Ssimokawa#if 0 1541109890Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1542113584Ssimokawa#endif 1543109403Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1544109403Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1545109403Ssimokawa OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1546113584Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1547109890Ssimokawa 1548109890Ssimokawa first = STAILQ_FIRST(&it->stdma); 1549113584Ssimokawa OWRITE(sc, OHCI_ITCMD(dmach), 1550113584Ssimokawa ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1551113584Ssimokawa if (firewire_debug) { 1552109890Ssimokawa printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1553113584Ssimokawa#if 1 1554113584Ssimokawa dump_dma(sc, ITX_CH + dmach); 1555113584Ssimokawa#endif 1556113584Ssimokawa } 1557109403Ssimokawa if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1558109890Ssimokawa#if 1 1559109890Ssimokawa /* Don't start until all chunks are buffered */ 1560109890Ssimokawa if (STAILQ_FIRST(&it->stfree) != NULL) 1561109890Ssimokawa goto out; 1562109890Ssimokawa#endif 1563113584Ssimokawa#if 1 1564109890Ssimokawa /* Clear cycle match counter bits */ 1565109890Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1566109890Ssimokawa 1567109356Ssimokawa /* 2bit second + 13bit cycle */ 1568109356Ssimokawa cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1569113584Ssimokawa cycle_match = fwohci_next_cycle(fc, cycle_now); 1570109890Ssimokawa 1571109356Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), 1572109356Ssimokawa OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1573109356Ssimokawa | OHCI_CNTL_DMA_RUN); 1574113584Ssimokawa#else 1575113584Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1576113584Ssimokawa#endif 1577113584Ssimokawa if (firewire_debug) { 1578109403Ssimokawa printf("cycle_match: 0x%04x->0x%04x\n", 1579109403Ssimokawa cycle_now, cycle_match); 1580113584Ssimokawa dump_dma(sc, ITX_CH + dmach); 1581113584Ssimokawa dump_db(sc, ITX_CH + dmach); 1582113584Ssimokawa } 1583109403Ssimokawa } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1584109890Ssimokawa device_printf(sc->fc.dev, 1585109890Ssimokawa "IT DMA underrun (0x%08x)\n", stat); 1586113584Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1587103285Sikob } 1588109890Ssimokawaout: 1589103285Sikob return err; 1590103285Sikob} 1591106790Ssimokawa 1592106790Ssimokawastatic int 1593113584Ssimokawafwohci_irx_enable(struct firewire_comm *fc, int dmach) 1594103285Sikob{ 1595103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1596109890Ssimokawa int err = 0, s, ldesc; 1597103285Sikob unsigned short tag, ich; 1598109736Ssimokawa u_int32_t stat; 1599109890Ssimokawa struct fwohci_dbch *dbch; 1600113584Ssimokawa struct fwohcidb_tr *db_tr; 1601109890Ssimokawa struct fw_bulkxfer *first, *prev, *chunk; 1602109890Ssimokawa struct fw_xferq *ir; 1603103285Sikob 1604109890Ssimokawa dbch = &sc->ir[dmach]; 1605109890Ssimokawa ir = &dbch->xferq; 1606109890Ssimokawa 1607109890Ssimokawa if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1608109890Ssimokawa tag = (ir->flag >> 6) & 3; 1609109890Ssimokawa ich = ir->flag & 0x3f; 1610108995Ssimokawa OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1611108995Ssimokawa 1612109890Ssimokawa ir->queued = 0; 1613109890Ssimokawa dbch->ndb = ir->bnpacket * ir->bnchunk; 1614109890Ssimokawa dbch->ndesc = 2; 1615113584Ssimokawa fwohci_db_init(sc, dbch); 1616109890Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1617109179Ssimokawa return ENOMEM; 1618109890Ssimokawa err = fwohci_rx_enable(sc, dbch); 1619103285Sikob } 1620103285Sikob if(err) 1621103285Sikob return err; 1622103285Sikob 1623109890Ssimokawa first = STAILQ_FIRST(&ir->stfree); 1624109890Ssimokawa if (first == NULL) { 1625109890Ssimokawa device_printf(fc->dev, "IR DMA no free chunk\n"); 1626109890Ssimokawa return 0; 1627109890Ssimokawa } 1628109890Ssimokawa 1629111892Ssimokawa ldesc = dbch->ndesc - 1; 1630111892Ssimokawa s = splfw(); 1631109890Ssimokawa prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1632109890Ssimokawa while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1633109890Ssimokawa volatile struct fwohcidb *db; 1634109890Ssimokawa 1635111942Ssimokawa#if 1 /* XXX for if_fwe */ 1636113584Ssimokawa if (chunk->mbuf != NULL) { 1637113584Ssimokawa db_tr = (struct fwohcidb_tr *)(chunk->start); 1638113584Ssimokawa db_tr->dbcnt = 1; 1639113584Ssimokawa err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 1640113584Ssimokawa chunk->mbuf, fwohci_execute_db2, db_tr, 1641113584Ssimokawa /* flags */0); 1642113584Ssimokawa FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1643113584Ssimokawa OHCI_UPDATE | OHCI_INPUT_LAST | 1644113584Ssimokawa OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1645113584Ssimokawa } 1646111942Ssimokawa#endif 1647109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 1648113584Ssimokawa FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1649113584Ssimokawa FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1650109890Ssimokawa if (prev != NULL) { 1651109890Ssimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 1652113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1653103285Sikob } 1654109890Ssimokawa STAILQ_REMOVE_HEAD(&ir->stfree, link); 1655109890Ssimokawa STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1656109890Ssimokawa prev = chunk; 1657103285Sikob } 1658113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1659113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1660109890Ssimokawa splx(s); 1661109890Ssimokawa stat = OREAD(sc, OHCI_IRCTL(dmach)); 1662109890Ssimokawa if (stat & OHCI_CNTL_DMA_ACTIVE) 1663109890Ssimokawa return 0; 1664109890Ssimokawa if (stat & OHCI_CNTL_DMA_RUN) { 1665109890Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1666109890Ssimokawa device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1667109890Ssimokawa } 1668109890Ssimokawa 1669113584Ssimokawa if (firewire_debug) 1670113584Ssimokawa printf("start IR DMA 0x%x\n", stat); 1671109890Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1672109890Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1673109890Ssimokawa OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1674109890Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1675109890Ssimokawa OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1676109890Ssimokawa OWRITE(sc, OHCI_IRCMD(dmach), 1677113584Ssimokawa ((struct fwohcidb_tr *)(first->start))->bus_addr 1678109890Ssimokawa | dbch->ndesc); 1679109890Ssimokawa OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1680109890Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1681113584Ssimokawa#if 0 1682113584Ssimokawa dump_db(sc, IRX_CH + dmach); 1683113584Ssimokawa#endif 1684103285Sikob return err; 1685103285Sikob} 1686106790Ssimokawa 1687106790Ssimokawaint 1688110145Ssimokawafwohci_stop(struct fwohci_softc *sc, device_t dev) 1689103285Sikob{ 1690103285Sikob u_int i; 1691103285Sikob 1692103285Sikob/* Now stopping all DMA channel */ 1693103285Sikob OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1694103285Sikob OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1695103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1696103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1697103285Sikob 1698103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1699103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1700103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1701103285Sikob } 1702103285Sikob 1703103285Sikob/* FLUSH FIFO and reset Transmitter/Reciever */ 1704103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1705103285Sikob 1706103285Sikob/* Stop interrupt */ 1707103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, 1708103285Sikob OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1709103285Sikob | OHCI_INT_PHY_INT 1710103285Sikob | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1711103285Sikob | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1712103285Sikob | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1713103285Sikob | OHCI_INT_PHY_BUS_R); 1714116978Ssimokawa 1715118416Ssimokawa if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1716118416Ssimokawa fw_drain_txq(&sc->fc); 1717116978Ssimokawa 1718108642Ssimokawa/* XXX Link down? Bus reset? */ 1719103285Sikob return 0; 1720103285Sikob} 1721103285Sikob 1722108642Ssimokawaint 1723108642Ssimokawafwohci_resume(struct fwohci_softc *sc, device_t dev) 1724108642Ssimokawa{ 1725108642Ssimokawa int i; 1726116978Ssimokawa struct fw_xferq *ir; 1727116978Ssimokawa struct fw_bulkxfer *chunk; 1728108642Ssimokawa 1729108642Ssimokawa fwohci_reset(sc, dev); 1730108642Ssimokawa /* XXX resume isochronus receive automatically. (how about TX?) */ 1731108642Ssimokawa for(i = 0; i < sc->fc.nisodma; i ++) { 1732116978Ssimokawa ir = &sc->ir[i].xferq; 1733116978Ssimokawa if((ir->flag & FWXFERQ_RUNNING) != 0) { 1734108642Ssimokawa device_printf(sc->fc.dev, 1735108642Ssimokawa "resume iso receive ch: %d\n", i); 1736116978Ssimokawa ir->flag &= ~FWXFERQ_RUNNING; 1737116978Ssimokawa /* requeue stdma to stfree */ 1738116978Ssimokawa while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1739116978Ssimokawa STAILQ_REMOVE_HEAD(&ir->stdma, link); 1740116978Ssimokawa STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1741116978Ssimokawa } 1742108642Ssimokawa sc->fc.irx_enable(&sc->fc, i); 1743108642Ssimokawa } 1744108642Ssimokawa } 1745108642Ssimokawa 1746108642Ssimokawa bus_generic_resume(dev); 1747108642Ssimokawa sc->fc.ibr(&sc->fc); 1748108642Ssimokawa return 0; 1749108642Ssimokawa} 1750108642Ssimokawa 1751103285Sikob#define ACK_ALL 1752103285Sikobstatic void 1753106789Ssimokawafwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1754103285Sikob{ 1755103285Sikob u_int32_t irstat, itstat; 1756103285Sikob u_int i; 1757103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1758103285Sikob 1759103285Sikob#ifdef OHCI_DEBUG 1760103285Sikob if(stat & OREAD(sc, FWOHCI_INTMASK)) 1761103285Sikob device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1762103285Sikob stat & OHCI_INT_EN ? "DMA_EN ":"", 1763103285Sikob stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1764103285Sikob stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1765103285Sikob stat & OHCI_INT_ERR ? "INT_ERR ":"", 1766103285Sikob stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1767103285Sikob stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1768103285Sikob stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1769103285Sikob stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1770103285Sikob stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1771103285Sikob stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1772103285Sikob stat & OHCI_INT_PHY_SID ? "SID ":"", 1773103285Sikob stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1774103285Sikob stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1775103285Sikob stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1776103285Sikob stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1777103285Sikob stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1778103285Sikob stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1779103285Sikob stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1780103285Sikob stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1781103285Sikob stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1782103285Sikob stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1783103285Sikob stat, OREAD(sc, FWOHCI_INTMASK) 1784103285Sikob ); 1785103285Sikob#endif 1786103285Sikob/* Bus reset */ 1787103285Sikob if(stat & OHCI_INT_PHY_BUS_R ){ 1788111074Ssimokawa if (fc->status == FWBUSRESET) 1789111074Ssimokawa goto busresetout; 1790111074Ssimokawa /* Disable bus reset interrupt until sid recv. */ 1791111074Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1792111074Ssimokawa 1793103285Sikob device_printf(fc->dev, "BUS reset\n"); 1794103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1795103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1796103285Sikob 1797103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1798103285Sikob sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1799103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1800103285Sikob sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1801103285Sikob 1802103285Sikob#ifndef ACK_ALL 1803103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1804103285Sikob#endif 1805110798Ssimokawa fw_busreset(fc); 1806116376Ssimokawa OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1807116376Ssimokawa OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1808103285Sikob } 1809111074Ssimokawabusresetout: 1810103285Sikob if((stat & OHCI_INT_DMA_IR )){ 1811103285Sikob#ifndef ACK_ALL 1812103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1813103285Sikob#endif 1814113584Ssimokawa#if __FreeBSD_version >= 500000 1815113584Ssimokawa irstat = atomic_readandclear_int(&sc->irstat); 1816113584Ssimokawa#else 1817113584Ssimokawa irstat = sc->irstat; 1818113584Ssimokawa sc->irstat = 0; 1819113584Ssimokawa#endif 1820103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1821109644Ssimokawa struct fwohci_dbch *dbch; 1822109644Ssimokawa 1823103285Sikob if((irstat & (1 << i)) != 0){ 1824109644Ssimokawa dbch = &sc->ir[i]; 1825109644Ssimokawa if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1826109644Ssimokawa device_printf(sc->fc.dev, 1827109644Ssimokawa "dma(%d) not active\n", i); 1828109644Ssimokawa continue; 1829109644Ssimokawa } 1830113584Ssimokawa fwohci_rbuf_update(sc, i); 1831103285Sikob } 1832103285Sikob } 1833103285Sikob } 1834103285Sikob if((stat & OHCI_INT_DMA_IT )){ 1835103285Sikob#ifndef ACK_ALL 1836103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1837103285Sikob#endif 1838113584Ssimokawa#if __FreeBSD_version >= 500000 1839113584Ssimokawa itstat = atomic_readandclear_int(&sc->itstat); 1840113584Ssimokawa#else 1841113584Ssimokawa itstat = sc->itstat; 1842113584Ssimokawa sc->itstat = 0; 1843113584Ssimokawa#endif 1844103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1845103285Sikob if((itstat & (1 << i)) != 0){ 1846103285Sikob fwohci_tbuf_update(sc, i); 1847103285Sikob } 1848103285Sikob } 1849103285Sikob } 1850103285Sikob if((stat & OHCI_INT_DMA_PRRS )){ 1851103285Sikob#ifndef ACK_ALL 1852103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1853103285Sikob#endif 1854103285Sikob#if 0 1855103285Sikob dump_dma(sc, ARRS_CH); 1856103285Sikob dump_db(sc, ARRS_CH); 1857103285Sikob#endif 1858106789Ssimokawa fwohci_arcv(sc, &sc->arrs, count); 1859103285Sikob } 1860103285Sikob if((stat & OHCI_INT_DMA_PRRQ )){ 1861103285Sikob#ifndef ACK_ALL 1862103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1863103285Sikob#endif 1864103285Sikob#if 0 1865103285Sikob dump_dma(sc, ARRQ_CH); 1866103285Sikob dump_db(sc, ARRQ_CH); 1867103285Sikob#endif 1868106789Ssimokawa fwohci_arcv(sc, &sc->arrq, count); 1869103285Sikob } 1870103285Sikob if(stat & OHCI_INT_PHY_SID){ 1871113584Ssimokawa u_int32_t *buf, node_id; 1872103285Sikob int plen; 1873103285Sikob 1874103285Sikob#ifndef ACK_ALL 1875103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1876103285Sikob#endif 1877111074Ssimokawa /* Enable bus reset interrupt */ 1878111074Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1879111787Ssimokawa /* Allow async. request to us */ 1880111787Ssimokawa OWRITE(sc, OHCI_AREQHI, 1 << 31); 1881111787Ssimokawa /* XXX insecure ?? */ 1882111787Ssimokawa OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1883111787Ssimokawa OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1884111787Ssimokawa OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1885112523Ssimokawa /* Set ATRetries register */ 1886112523Ssimokawa OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1887103285Sikob/* 1888103285Sikob** Checking whether the node is root or not. If root, turn on 1889103285Sikob** cycle master. 1890103285Sikob*/ 1891113584Ssimokawa node_id = OREAD(sc, FWOHCI_NODEID); 1892113584Ssimokawa plen = OREAD(sc, OHCI_SID_CNT); 1893113584Ssimokawa 1894113584Ssimokawa device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 1895113584Ssimokawa node_id, (plen >> 16) & 0xff); 1896113584Ssimokawa if (!(node_id & OHCI_NODE_VALID)) { 1897103285Sikob printf("Bus reset failure\n"); 1898103285Sikob goto sidout; 1899103285Sikob } 1900113584Ssimokawa if (node_id & OHCI_NODE_ROOT) { 1901103285Sikob printf("CYCLEMASTER mode\n"); 1902103285Sikob OWRITE(sc, OHCI_LNKCTL, 1903103285Sikob OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1904113584Ssimokawa } else { 1905103285Sikob printf("non CYCLEMASTER mode\n"); 1906103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1907103285Sikob OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1908103285Sikob } 1909113584Ssimokawa fc->nodeid = node_id & 0x3f; 1910103285Sikob 1911113584Ssimokawa if (plen & OHCI_SID_ERR) { 1912113584Ssimokawa device_printf(fc->dev, "SID Error\n"); 1913113584Ssimokawa goto sidout; 1914113584Ssimokawa } 1915113584Ssimokawa plen &= OHCI_SID_CNT_MASK; 1916109736Ssimokawa if (plen < 4 || plen > OHCI_SIDSIZE) { 1917109736Ssimokawa device_printf(fc->dev, "invalid SID len = %d\n", plen); 1918109736Ssimokawa goto sidout; 1919109736Ssimokawa } 1920103285Sikob plen -= 4; /* chop control info */ 1921113584Ssimokawa buf = (u_int32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1922113584Ssimokawa if (buf == NULL) { 1923113584Ssimokawa device_printf(fc->dev, "malloc failed\n"); 1924113584Ssimokawa goto sidout; 1925113584Ssimokawa } 1926113584Ssimokawa for (i = 0; i < plen / 4; i ++) 1927113584Ssimokawa buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 1928110269Ssimokawa#if 1 1929110269Ssimokawa /* pending all pre-bus_reset packets */ 1930110269Ssimokawa fwohci_txd(sc, &sc->atrq); 1931110269Ssimokawa fwohci_txd(sc, &sc->atrs); 1932110269Ssimokawa fwohci_arcv(sc, &sc->arrs, -1); 1933110269Ssimokawa fwohci_arcv(sc, &sc->arrq, -1); 1934110798Ssimokawa fw_drain_txq(fc); 1935110269Ssimokawa#endif 1936113584Ssimokawa fw_sidrcv(fc, buf, plen); 1937113584Ssimokawa free(buf, M_FW); 1938103285Sikob } 1939103285Sikobsidout: 1940103285Sikob if((stat & OHCI_INT_DMA_ATRQ )){ 1941103285Sikob#ifndef ACK_ALL 1942103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1943103285Sikob#endif 1944103285Sikob fwohci_txd(sc, &(sc->atrq)); 1945103285Sikob } 1946103285Sikob if((stat & OHCI_INT_DMA_ATRS )){ 1947103285Sikob#ifndef ACK_ALL 1948103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1949103285Sikob#endif 1950103285Sikob fwohci_txd(sc, &(sc->atrs)); 1951103285Sikob } 1952103285Sikob if((stat & OHCI_INT_PW_ERR )){ 1953103285Sikob#ifndef ACK_ALL 1954103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1955103285Sikob#endif 1956103285Sikob device_printf(fc->dev, "posted write error\n"); 1957103285Sikob } 1958103285Sikob if((stat & OHCI_INT_ERR )){ 1959103285Sikob#ifndef ACK_ALL 1960103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1961103285Sikob#endif 1962103285Sikob device_printf(fc->dev, "unrecoverable error\n"); 1963103285Sikob } 1964103285Sikob if((stat & OHCI_INT_PHY_INT)) { 1965103285Sikob#ifndef ACK_ALL 1966103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1967103285Sikob#endif 1968103285Sikob device_printf(fc->dev, "phy int\n"); 1969103285Sikob } 1970103285Sikob 1971103285Sikob return; 1972103285Sikob} 1973103285Sikob 1974113584Ssimokawa#if FWOHCI_TASKQUEUE 1975113584Ssimokawastatic void 1976113584Ssimokawafwohci_complete(void *arg, int pending) 1977113584Ssimokawa{ 1978113584Ssimokawa struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1979113584Ssimokawa u_int32_t stat; 1980113584Ssimokawa 1981113584Ssimokawaagain: 1982113584Ssimokawa stat = atomic_readandclear_int(&sc->intstat); 1983113584Ssimokawa if (stat) 1984113584Ssimokawa fwohci_intr_body(sc, stat, -1); 1985113584Ssimokawa else 1986113584Ssimokawa return; 1987113584Ssimokawa goto again; 1988113584Ssimokawa} 1989113584Ssimokawa#endif 1990113584Ssimokawa 1991113584Ssimokawastatic u_int32_t 1992113584Ssimokawafwochi_check_stat(struct fwohci_softc *sc) 1993113584Ssimokawa{ 1994113584Ssimokawa u_int32_t stat, irstat, itstat; 1995113584Ssimokawa 1996113584Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 1997113584Ssimokawa if (stat == 0xffffffff) { 1998113584Ssimokawa device_printf(sc->fc.dev, 1999113584Ssimokawa "device physically ejected?\n"); 2000113584Ssimokawa return(stat); 2001113584Ssimokawa } 2002113584Ssimokawa#ifdef ACK_ALL 2003113584Ssimokawa if (stat) 2004113584Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2005113584Ssimokawa#endif 2006113584Ssimokawa if (stat & OHCI_INT_DMA_IR) { 2007113584Ssimokawa irstat = OREAD(sc, OHCI_IR_STAT); 2008113584Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, irstat); 2009113584Ssimokawa atomic_set_int(&sc->irstat, irstat); 2010113584Ssimokawa } 2011113584Ssimokawa if (stat & OHCI_INT_DMA_IT) { 2012113584Ssimokawa itstat = OREAD(sc, OHCI_IT_STAT); 2013113584Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, itstat); 2014113584Ssimokawa atomic_set_int(&sc->itstat, itstat); 2015113584Ssimokawa } 2016113584Ssimokawa return(stat); 2017113584Ssimokawa} 2018113584Ssimokawa 2019103285Sikobvoid 2020103285Sikobfwohci_intr(void *arg) 2021103285Sikob{ 2022103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2023113584Ssimokawa u_int32_t stat; 2024113584Ssimokawa#if !FWOHCI_TASKQUEUE 2025113584Ssimokawa u_int32_t bus_reset = 0; 2026113584Ssimokawa#endif 2027103285Sikob 2028103285Sikob if (!(sc->intmask & OHCI_INT_EN)) { 2029103285Sikob /* polling mode */ 2030103285Sikob return; 2031103285Sikob } 2032103285Sikob 2033113584Ssimokawa#if !FWOHCI_TASKQUEUE 2034113584Ssimokawaagain: 2035103285Sikob#endif 2036113584Ssimokawa stat = fwochi_check_stat(sc); 2037113584Ssimokawa if (stat == 0 || stat == 0xffffffff) 2038113584Ssimokawa return; 2039113584Ssimokawa#if FWOHCI_TASKQUEUE 2040113584Ssimokawa atomic_set_int(&sc->intstat, stat); 2041113584Ssimokawa /* XXX mask bus reset intr. during bus reset phase */ 2042113584Ssimokawa if (stat) 2043113584Ssimokawa taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete); 2044113584Ssimokawa#else 2045113584Ssimokawa /* We cannot clear bus reset event during bus reset phase */ 2046113584Ssimokawa if ((stat & ~bus_reset) == 0) 2047113584Ssimokawa return; 2048113584Ssimokawa bus_reset = stat & OHCI_INT_PHY_BUS_R; 2049113584Ssimokawa fwohci_intr_body(sc, stat, -1); 2050113584Ssimokawa goto again; 2051113584Ssimokawa#endif 2052103285Sikob} 2053103285Sikob 2054116897Ssimokawavoid 2055103285Sikobfwohci_poll(struct firewire_comm *fc, int quick, int count) 2056103285Sikob{ 2057103285Sikob int s; 2058103285Sikob u_int32_t stat; 2059103285Sikob struct fwohci_softc *sc; 2060103285Sikob 2061103285Sikob 2062103285Sikob sc = (struct fwohci_softc *)fc; 2063103285Sikob stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2064103285Sikob OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2065103285Sikob OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2066103285Sikob#if 0 2067103285Sikob if (!quick) { 2068103285Sikob#else 2069103285Sikob if (1) { 2070103285Sikob#endif 2071113584Ssimokawa stat = fwochi_check_stat(sc); 2072113584Ssimokawa if (stat == 0 || stat == 0xffffffff) 2073103285Sikob return; 2074103285Sikob } 2075103285Sikob s = splfw(); 2076106789Ssimokawa fwohci_intr_body(sc, stat, count); 2077103285Sikob splx(s); 2078103285Sikob} 2079103285Sikob 2080103285Sikobstatic void 2081103285Sikobfwohci_set_intr(struct firewire_comm *fc, int enable) 2082103285Sikob{ 2083103285Sikob struct fwohci_softc *sc; 2084103285Sikob 2085103285Sikob sc = (struct fwohci_softc *)fc; 2086107653Ssimokawa if (bootverbose) 2087108642Ssimokawa device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2088103285Sikob if (enable) { 2089103285Sikob sc->intmask |= OHCI_INT_EN; 2090103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2091103285Sikob } else { 2092103285Sikob sc->intmask &= ~OHCI_INT_EN; 2093103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2094103285Sikob } 2095103285Sikob} 2096103285Sikob 2097106790Ssimokawastatic void 2098106790Ssimokawafwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2099103285Sikob{ 2100103285Sikob struct firewire_comm *fc = &sc->fc; 2101109890Ssimokawa volatile struct fwohcidb *db; 2102109890Ssimokawa struct fw_bulkxfer *chunk; 2103109890Ssimokawa struct fw_xferq *it; 2104109890Ssimokawa u_int32_t stat, count; 2105113584Ssimokawa int s, w=0, ldesc; 2106103285Sikob 2107109890Ssimokawa it = fc->it[dmach]; 2108113584Ssimokawa ldesc = sc->it[dmach].ndesc - 1; 2109109890Ssimokawa s = splfw(); /* unnecessary ? */ 2110113584Ssimokawa fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2111109890Ssimokawa while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2112109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 2113113584Ssimokawa stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2114113584Ssimokawa >> OHCI_STATUS_SHIFT; 2115109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->start))->db; 2116113584Ssimokawa count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2117113584Ssimokawa & OHCI_COUNT_MASK; 2118109890Ssimokawa if (stat == 0) 2119109890Ssimokawa break; 2120109890Ssimokawa STAILQ_REMOVE_HEAD(&it->stdma, link); 2121109890Ssimokawa switch (stat & FWOHCIEV_MASK){ 2122109890Ssimokawa case FWOHCIEV_ACKCOMPL: 2123109890Ssimokawa#if 0 2124109890Ssimokawa device_printf(fc->dev, "0x%08x\n", count); 2125109179Ssimokawa#endif 2126109890Ssimokawa break; 2127109890Ssimokawa default: 2128109423Ssimokawa device_printf(fc->dev, 2129113584Ssimokawa "Isochronous transmit err %02x(%s)\n", 2130113584Ssimokawa stat, fwohcicode[stat & 0x1f]); 2131109890Ssimokawa } 2132109890Ssimokawa STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2133109890Ssimokawa w++; 2134109403Ssimokawa } 2135109890Ssimokawa splx(s); 2136109890Ssimokawa if (w) 2137109890Ssimokawa wakeup(it); 2138103285Sikob} 2139106790Ssimokawa 2140106790Ssimokawastatic void 2141106790Ssimokawafwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2142103285Sikob{ 2143109179Ssimokawa struct firewire_comm *fc = &sc->fc; 2144113584Ssimokawa volatile struct fwohcidb_tr *db_tr; 2145109890Ssimokawa struct fw_bulkxfer *chunk; 2146109890Ssimokawa struct fw_xferq *ir; 2147109890Ssimokawa u_int32_t stat; 2148113584Ssimokawa int s, w=0, ldesc; 2149109179Ssimokawa 2150109890Ssimokawa ir = fc->ir[dmach]; 2151113584Ssimokawa ldesc = sc->ir[dmach].ndesc - 1; 2152113584Ssimokawa#if 0 2153113584Ssimokawa dump_db(sc, dmach); 2154113584Ssimokawa#endif 2155109890Ssimokawa s = splfw(); 2156113584Ssimokawa fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2157109890Ssimokawa while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2158113584Ssimokawa db_tr = (struct fwohcidb_tr *)chunk->end; 2159113584Ssimokawa stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2160113584Ssimokawa >> OHCI_STATUS_SHIFT; 2161109890Ssimokawa if (stat == 0) 2162109890Ssimokawa break; 2163113584Ssimokawa 2164113584Ssimokawa if (chunk->mbuf != NULL) { 2165113584Ssimokawa bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2166113584Ssimokawa BUS_DMASYNC_POSTREAD); 2167113584Ssimokawa bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 2168113584Ssimokawa } else if (ir->buf != NULL) { 2169113584Ssimokawa fwdma_sync_multiseg(ir->buf, chunk->poffset, 2170113584Ssimokawa ir->bnpacket, BUS_DMASYNC_POSTREAD); 2171113584Ssimokawa } else { 2172113584Ssimokawa /* XXX */ 2173113584Ssimokawa printf("fwohci_rbuf_update: this shouldn't happend\n"); 2174113584Ssimokawa } 2175113584Ssimokawa 2176109890Ssimokawa STAILQ_REMOVE_HEAD(&ir->stdma, link); 2177109890Ssimokawa STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2178109890Ssimokawa switch (stat & FWOHCIEV_MASK) { 2179109890Ssimokawa case FWOHCIEV_ACKCOMPL: 2180111942Ssimokawa chunk->resp = 0; 2181109890Ssimokawa break; 2182109890Ssimokawa default: 2183111942Ssimokawa chunk->resp = EINVAL; 2184109890Ssimokawa device_printf(fc->dev, 2185113584Ssimokawa "Isochronous receive err %02x(%s)\n", 2186113584Ssimokawa stat, fwohcicode[stat & 0x1f]); 2187109890Ssimokawa } 2188109890Ssimokawa w++; 2189103285Sikob } 2190109890Ssimokawa splx(s); 2191111942Ssimokawa if (w) { 2192111942Ssimokawa if (ir->flag & FWXFERQ_HANDLER) 2193111942Ssimokawa ir->hand(ir); 2194111942Ssimokawa else 2195111942Ssimokawa wakeup(ir); 2196111942Ssimokawa } 2197103285Sikob} 2198106790Ssimokawa 2199106790Ssimokawavoid 2200106790Ssimokawadump_dma(struct fwohci_softc *sc, u_int32_t ch) 2201106790Ssimokawa{ 2202103285Sikob u_int32_t off, cntl, stat, cmd, match; 2203103285Sikob 2204103285Sikob if(ch == 0){ 2205103285Sikob off = OHCI_ATQOFF; 2206103285Sikob }else if(ch == 1){ 2207103285Sikob off = OHCI_ATSOFF; 2208103285Sikob }else if(ch == 2){ 2209103285Sikob off = OHCI_ARQOFF; 2210103285Sikob }else if(ch == 3){ 2211103285Sikob off = OHCI_ARSOFF; 2212103285Sikob }else if(ch < IRX_CH){ 2213103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2214103285Sikob }else{ 2215103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2216103285Sikob } 2217103285Sikob cntl = stat = OREAD(sc, off); 2218103285Sikob cmd = OREAD(sc, off + 0xc); 2219103285Sikob match = OREAD(sc, off + 0x10); 2220103285Sikob 2221113584Ssimokawa device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2222103285Sikob ch, 2223103285Sikob cntl, 2224103285Sikob cmd, 2225103285Sikob match); 2226103285Sikob stat &= 0xffff ; 2227113584Ssimokawa if (stat) { 2228103285Sikob device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2229103285Sikob ch, 2230103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2231103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2232103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2233103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2234103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2235103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2236103285Sikob fwohcicode[stat & 0x1f], 2237103285Sikob stat & 0x1f 2238103285Sikob ); 2239103285Sikob }else{ 2240103285Sikob device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2241103285Sikob } 2242103285Sikob} 2243106790Ssimokawa 2244106790Ssimokawavoid 2245106790Ssimokawadump_db(struct fwohci_softc *sc, u_int32_t ch) 2246106790Ssimokawa{ 2247103285Sikob struct fwohci_dbch *dbch; 2248113584Ssimokawa struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2249103285Sikob volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2250103285Sikob int idb, jdb; 2251103285Sikob u_int32_t cmd, off; 2252103285Sikob if(ch == 0){ 2253103285Sikob off = OHCI_ATQOFF; 2254103285Sikob dbch = &sc->atrq; 2255103285Sikob }else if(ch == 1){ 2256103285Sikob off = OHCI_ATSOFF; 2257103285Sikob dbch = &sc->atrs; 2258103285Sikob }else if(ch == 2){ 2259103285Sikob off = OHCI_ARQOFF; 2260103285Sikob dbch = &sc->arrq; 2261103285Sikob }else if(ch == 3){ 2262103285Sikob off = OHCI_ARSOFF; 2263103285Sikob dbch = &sc->arrs; 2264103285Sikob }else if(ch < IRX_CH){ 2265103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2266103285Sikob dbch = &sc->it[ch - ITX_CH]; 2267103285Sikob }else { 2268103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2269103285Sikob dbch = &sc->ir[ch - IRX_CH]; 2270103285Sikob } 2271103285Sikob cmd = OREAD(sc, off + 0xc); 2272103285Sikob 2273103285Sikob if( dbch->ndb == 0 ){ 2274103285Sikob device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2275103285Sikob return; 2276103285Sikob } 2277103285Sikob pp = dbch->top; 2278103285Sikob prev = pp->db; 2279103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2280103285Sikob if(pp == NULL){ 2281103285Sikob curr = NULL; 2282103285Sikob goto outdb; 2283103285Sikob } 2284103285Sikob cp = STAILQ_NEXT(pp, link); 2285103285Sikob if(cp == NULL){ 2286103285Sikob curr = NULL; 2287103285Sikob goto outdb; 2288103285Sikob } 2289103285Sikob np = STAILQ_NEXT(cp, link); 2290103285Sikob for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2291113584Ssimokawa if ((cmd & 0xfffffff0) == cp->bus_addr) { 2292103285Sikob curr = cp->db; 2293103285Sikob if(np != NULL){ 2294103285Sikob next = np->db; 2295103285Sikob }else{ 2296103285Sikob next = NULL; 2297103285Sikob } 2298103285Sikob goto outdb; 2299103285Sikob } 2300103285Sikob } 2301103285Sikob pp = STAILQ_NEXT(pp, link); 2302103285Sikob prev = pp->db; 2303103285Sikob } 2304103285Sikoboutdb: 2305103285Sikob if( curr != NULL){ 2306113584Ssimokawa#if 0 2307103285Sikob printf("Prev DB %d\n", ch); 2308113584Ssimokawa print_db(pp, prev, ch, dbch->ndesc); 2309113584Ssimokawa#endif 2310103285Sikob printf("Current DB %d\n", ch); 2311113584Ssimokawa print_db(cp, curr, ch, dbch->ndesc); 2312113584Ssimokawa#if 0 2313103285Sikob printf("Next DB %d\n", ch); 2314113584Ssimokawa print_db(np, next, ch, dbch->ndesc); 2315113584Ssimokawa#endif 2316103285Sikob }else{ 2317103285Sikob printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2318103285Sikob } 2319103285Sikob return; 2320103285Sikob} 2321106790Ssimokawa 2322106790Ssimokawavoid 2323113584Ssimokawaprint_db(struct fwohcidb_tr *db_tr, volatile struct fwohcidb *db, 2324113584Ssimokawa u_int32_t ch, u_int32_t max) 2325106790Ssimokawa{ 2326103285Sikob fwohcireg_t stat; 2327103285Sikob int i, key; 2328113584Ssimokawa u_int32_t cmd, res; 2329103285Sikob 2330103285Sikob if(db == NULL){ 2331103285Sikob printf("No Descriptor is found\n"); 2332103285Sikob return; 2333103285Sikob } 2334103285Sikob 2335103285Sikob printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2336103285Sikob ch, 2337103285Sikob "Current", 2338103285Sikob "OP ", 2339103285Sikob "KEY", 2340103285Sikob "INT", 2341103285Sikob "BR ", 2342103285Sikob "len", 2343103285Sikob "Addr", 2344103285Sikob "Depend", 2345103285Sikob "Stat", 2346103285Sikob "Cnt"); 2347103285Sikob for( i = 0 ; i <= max ; i ++){ 2348113584Ssimokawa cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2349113584Ssimokawa res = FWOHCI_DMA_READ(db[i].db.desc.res); 2350113584Ssimokawa key = cmd & OHCI_KEY_MASK; 2351113584Ssimokawa stat = res >> OHCI_STATUS_SHIFT; 2352108712Ssimokawa#if __FreeBSD_version >= 500000 2353113972Ssimokawa printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2354114142Ssimokawa (uintmax_t)db_tr->bus_addr, 2355108712Ssimokawa#else 2356108712Ssimokawa printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2357114142Ssimokawa db_tr->bus_addr, 2358108712Ssimokawa#endif 2359113584Ssimokawa dbcode[(cmd >> 28) & 0xf], 2360113584Ssimokawa dbkey[(cmd >> 24) & 0x7], 2361113584Ssimokawa dbcond[(cmd >> 20) & 0x3], 2362113584Ssimokawa dbcond[(cmd >> 18) & 0x3], 2363113584Ssimokawa cmd & OHCI_COUNT_MASK, 2364113584Ssimokawa FWOHCI_DMA_READ(db[i].db.desc.addr), 2365113584Ssimokawa FWOHCI_DMA_READ(db[i].db.desc.depend), 2366113584Ssimokawa stat, 2367113584Ssimokawa res & OHCI_COUNT_MASK); 2368103285Sikob if(stat & 0xff00){ 2369103285Sikob printf(" %s%s%s%s%s%s %s(%x)\n", 2370103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2371103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2372103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2373103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2374103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2375103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2376103285Sikob fwohcicode[stat & 0x1f], 2377103285Sikob stat & 0x1f 2378103285Sikob ); 2379103285Sikob }else{ 2380103285Sikob printf(" Nostat\n"); 2381103285Sikob } 2382103285Sikob if(key == OHCI_KEY_ST2 ){ 2383103285Sikob printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2384113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2385113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2386113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2387113584Ssimokawa FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2388103285Sikob } 2389103285Sikob if(key == OHCI_KEY_DEVICE){ 2390103285Sikob return; 2391103285Sikob } 2392113584Ssimokawa if((cmd & OHCI_BRANCH_MASK) 2393103285Sikob == OHCI_BRANCH_ALWAYS){ 2394103285Sikob return; 2395103285Sikob } 2396113584Ssimokawa if((cmd & OHCI_CMD_MASK) 2397103285Sikob == OHCI_OUTPUT_LAST){ 2398103285Sikob return; 2399103285Sikob } 2400113584Ssimokawa if((cmd & OHCI_CMD_MASK) 2401103285Sikob == OHCI_INPUT_LAST){ 2402103285Sikob return; 2403103285Sikob } 2404103285Sikob if(key == OHCI_KEY_ST2 ){ 2405103285Sikob i++; 2406103285Sikob } 2407103285Sikob } 2408103285Sikob return; 2409103285Sikob} 2410106790Ssimokawa 2411106790Ssimokawavoid 2412106790Ssimokawafwohci_ibr(struct firewire_comm *fc) 2413103285Sikob{ 2414103285Sikob struct fwohci_softc *sc; 2415103285Sikob u_int32_t fun; 2416103285Sikob 2417110577Ssimokawa device_printf(fc->dev, "Initiate bus reset\n"); 2418103285Sikob sc = (struct fwohci_softc *)fc; 2419108276Ssimokawa 2420108276Ssimokawa /* 2421108276Ssimokawa * Set root hold-off bit so that non cyclemaster capable node 2422108276Ssimokawa * shouldn't became the root node. 2423108276Ssimokawa */ 2424103285Sikob#if 1 2425103285Sikob fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2426109280Ssimokawa fun |= FW_PHY_IBR | FW_PHY_RHB; 2427103285Sikob fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2428109280Ssimokawa#else /* Short bus reset */ 2429103285Sikob fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2430109280Ssimokawa fun |= FW_PHY_ISBR | FW_PHY_RHB; 2431103285Sikob fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2432103285Sikob#endif 2433103285Sikob} 2434106790Ssimokawa 2435106790Ssimokawavoid 2436106790Ssimokawafwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2437103285Sikob{ 2438103285Sikob struct fwohcidb_tr *db_tr, *fdb_tr; 2439103285Sikob struct fwohci_dbch *dbch; 2440109892Ssimokawa volatile struct fwohcidb *db; 2441103285Sikob struct fw_pkt *fp; 2442103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 2443103285Sikob unsigned short chtag; 2444103285Sikob int idb; 2445103285Sikob 2446103285Sikob dbch = &sc->it[dmach]; 2447103285Sikob chtag = sc->it[dmach].xferq.flag & 0xff; 2448103285Sikob 2449103285Sikob db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2450103285Sikob fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2451103285Sikob/* 2452113584Ssimokawadevice_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2453103285Sikob*/ 2454113584Ssimokawa for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2455109892Ssimokawa db = db_tr->db; 2456103285Sikob fp = (struct fw_pkt *)db_tr->buf; 2457109892Ssimokawa ohcifp = (volatile struct fwohci_txpkthdr *) db[1].db.immed; 2458113584Ssimokawa ohcifp->mode.ld[0] = fp->mode.ld[0]; 2459113584Ssimokawa ohcifp->mode.stream.len = fp->mode.stream.len; 2460103285Sikob ohcifp->mode.stream.chtag = chtag; 2461103285Sikob ohcifp->mode.stream.tcode = 0xa; 2462109890Ssimokawa ohcifp->mode.stream.spd = 0; 2463113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2464113584Ssimokawa FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2465113584Ssimokawa FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2466113584Ssimokawa#endif 2467103285Sikob 2468113584Ssimokawa FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2469113584Ssimokawa FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2470113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2471109892Ssimokawa#if 0 /* if bulkxfer->npackets changes */ 2472113584Ssimokawa db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2473103285Sikob | OHCI_UPDATE 2474109892Ssimokawa | OHCI_BRANCH_ALWAYS; 2475109892Ssimokawa db[0].db.desc.depend = 2476109892Ssimokawa = db[dbch->ndesc - 1].db.desc.depend 2477113584Ssimokawa = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2478109892Ssimokawa#else 2479113584Ssimokawa FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2480113584Ssimokawa FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2481109892Ssimokawa#endif 2482103285Sikob bulkxfer->end = (caddr_t)db_tr; 2483103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2484103285Sikob } 2485109892Ssimokawa db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2486113584Ssimokawa FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2487113584Ssimokawa FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2488109892Ssimokawa#if 0 /* if bulkxfer->npackets changes */ 2489109892Ssimokawa db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2490109280Ssimokawa /* OHCI 1.1 and above */ 2491109892Ssimokawa db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2492109892Ssimokawa#endif 2493109892Ssimokawa/* 2494103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2495103285Sikob fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2496113584Ssimokawadevice_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2497103285Sikob*/ 2498103285Sikob return; 2499103285Sikob} 2500106790Ssimokawa 2501106790Ssimokawastatic int 2502113584Ssimokawafwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2503113584Ssimokawa int poffset) 2504103285Sikob{ 2505103285Sikob volatile struct fwohcidb *db = db_tr->db; 2506113584Ssimokawa struct fw_xferq *it; 2507103285Sikob int err = 0; 2508113584Ssimokawa 2509113584Ssimokawa it = &dbch->xferq; 2510113584Ssimokawa if(it->buf == 0){ 2511103285Sikob err = EINVAL; 2512103285Sikob return err; 2513103285Sikob } 2514113584Ssimokawa db_tr->buf = fwdma_v_addr(it->buf, poffset); 2515103285Sikob db_tr->dbcnt = 3; 2516103285Sikob 2517113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2518113584Ssimokawa OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2519113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2520113584Ssimokawa fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t)); 2521113584Ssimokawa 2522113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2523113584Ssimokawa OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2524109892Ssimokawa#if 1 2525113584Ssimokawa FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2526113584Ssimokawa FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2527109892Ssimokawa#endif 2528113584Ssimokawa return 0; 2529103285Sikob} 2530106790Ssimokawa 2531106790Ssimokawaint 2532113584Ssimokawafwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2533113584Ssimokawa int poffset, struct fwdma_alloc *dummy_dma) 2534103285Sikob{ 2535103285Sikob volatile struct fwohcidb *db = db_tr->db; 2536113584Ssimokawa struct fw_xferq *ir; 2537113584Ssimokawa int i, ldesc; 2538113584Ssimokawa bus_addr_t dbuf[2]; 2539103285Sikob int dsiz[2]; 2540103285Sikob 2541113584Ssimokawa ir = &dbch->xferq; 2542113584Ssimokawa if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2543113584Ssimokawa db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2544113584Ssimokawa ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2545113584Ssimokawa if (db_tr->buf == NULL) 2546113584Ssimokawa return(ENOMEM); 2547103285Sikob db_tr->dbcnt = 1; 2548113584Ssimokawa dsiz[0] = ir->psize; 2549113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2550113584Ssimokawa BUS_DMASYNC_PREREAD); 2551113584Ssimokawa } else { 2552113584Ssimokawa db_tr->dbcnt = 0; 2553113584Ssimokawa if (dummy_dma != NULL) { 2554113584Ssimokawa dsiz[db_tr->dbcnt] = sizeof(u_int32_t); 2555113584Ssimokawa dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2556113584Ssimokawa } 2557113584Ssimokawa dsiz[db_tr->dbcnt] = ir->psize; 2558113584Ssimokawa if (ir->buf != NULL) { 2559113584Ssimokawa db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2560113584Ssimokawa dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2561113584Ssimokawa } 2562113584Ssimokawa db_tr->dbcnt++; 2563103285Sikob } 2564103285Sikob for(i = 0 ; i < db_tr->dbcnt ; i++){ 2565113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2566113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2567113584Ssimokawa if (ir->flag & FWXFERQ_STREAM) { 2568113584Ssimokawa FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2569103285Sikob } 2570113584Ssimokawa FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2571103285Sikob } 2572113584Ssimokawa ldesc = db_tr->dbcnt - 1; 2573113584Ssimokawa if (ir->flag & FWXFERQ_STREAM) { 2574113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2575103285Sikob } 2576113584Ssimokawa FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2577113584Ssimokawa return 0; 2578103285Sikob} 2579106790Ssimokawa 2580113584Ssimokawa 2581113584Ssimokawastatic int 2582113584Ssimokawafwohci_arcv_swap(struct fw_pkt *fp, int len) 2583103285Sikob{ 2584113584Ssimokawa struct fw_pkt *fp0; 2585113584Ssimokawa u_int32_t ld0; 2586113584Ssimokawa int slen; 2587113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2588113584Ssimokawa int i; 2589113584Ssimokawa#endif 2590103285Sikob 2591113584Ssimokawa ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2592113584Ssimokawa#if 0 2593113584Ssimokawa printf("ld0: x%08x\n", ld0); 2594113584Ssimokawa#endif 2595113584Ssimokawa fp0 = (struct fw_pkt *)&ld0; 2596113584Ssimokawa switch (fp0->mode.common.tcode) { 2597113584Ssimokawa case FWTCODE_RREQQ: 2598113584Ssimokawa case FWTCODE_WRES: 2599113584Ssimokawa case FWTCODE_WREQQ: 2600113584Ssimokawa case FWTCODE_RRESQ: 2601113584Ssimokawa case FWOHCITCODE_PHY: 2602113584Ssimokawa slen = 12; 2603113584Ssimokawa break; 2604113584Ssimokawa case FWTCODE_RREQB: 2605113584Ssimokawa case FWTCODE_WREQB: 2606113584Ssimokawa case FWTCODE_LREQ: 2607113584Ssimokawa case FWTCODE_RRESB: 2608113584Ssimokawa case FWTCODE_LRES: 2609113584Ssimokawa slen = 16; 2610113584Ssimokawa break; 2611113584Ssimokawa default: 2612113584Ssimokawa printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2613113584Ssimokawa return(0); 2614103285Sikob } 2615113584Ssimokawa if (slen > len) { 2616113584Ssimokawa if (firewire_debug) 2617113584Ssimokawa printf("splitted header\n"); 2618113584Ssimokawa return(-slen); 2619103285Sikob } 2620113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2621113584Ssimokawa for(i = 0; i < slen/4; i ++) 2622113584Ssimokawa fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2623113584Ssimokawa#endif 2624113584Ssimokawa return(slen); 2625103285Sikob} 2626103285Sikob 2627113584Ssimokawa#define PLEN(x) roundup2(x, sizeof(u_int32_t)) 2628103285Sikobstatic int 2629113584Ssimokawafwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2630103285Sikob{ 2631113584Ssimokawa int r; 2632103285Sikob 2633103285Sikob switch(fp->mode.common.tcode){ 2634103285Sikob case FWTCODE_RREQQ: 2635110798Ssimokawa r = sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2636110798Ssimokawa break; 2637103285Sikob case FWTCODE_WRES: 2638110798Ssimokawa r = sizeof(fp->mode.wres) + sizeof(u_int32_t); 2639110798Ssimokawa break; 2640103285Sikob case FWTCODE_WREQQ: 2641110798Ssimokawa r = sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2642110798Ssimokawa break; 2643103285Sikob case FWTCODE_RREQB: 2644110798Ssimokawa r = sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2645110798Ssimokawa break; 2646103285Sikob case FWTCODE_RRESQ: 2647110798Ssimokawa r = sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2648110798Ssimokawa break; 2649103285Sikob case FWTCODE_WREQB: 2650110798Ssimokawa r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2651103285Sikob + sizeof(u_int32_t); 2652110798Ssimokawa break; 2653103285Sikob case FWTCODE_LREQ: 2654110798Ssimokawa r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2655103285Sikob + sizeof(u_int32_t); 2656110798Ssimokawa break; 2657103285Sikob case FWTCODE_RRESB: 2658110798Ssimokawa r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2659103285Sikob + sizeof(u_int32_t); 2660110798Ssimokawa break; 2661103285Sikob case FWTCODE_LRES: 2662110798Ssimokawa r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2663103285Sikob + sizeof(u_int32_t); 2664110798Ssimokawa break; 2665103285Sikob case FWOHCITCODE_PHY: 2666110798Ssimokawa r = 16; 2667110798Ssimokawa break; 2668110798Ssimokawa default: 2669110798Ssimokawa device_printf(sc->fc.dev, "Unknown tcode %d\n", 2670110798Ssimokawa fp->mode.common.tcode); 2671110798Ssimokawa r = 0; 2672103285Sikob } 2673110798Ssimokawa if (r > dbch->xferq.psize) { 2674110798Ssimokawa device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2675110798Ssimokawa /* panic ? */ 2676110798Ssimokawa } 2677110798Ssimokawa return r; 2678103285Sikob} 2679103285Sikob 2680106790Ssimokawastatic void 2681113584Ssimokawafwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr) 2682113584Ssimokawa{ 2683113584Ssimokawa volatile struct fwohcidb *db = &db_tr->db[0]; 2684113584Ssimokawa 2685113584Ssimokawa FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2686113584Ssimokawa FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2687113584Ssimokawa FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2688113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 2689113584Ssimokawa dbch->bottom = db_tr; 2690113584Ssimokawa} 2691113584Ssimokawa 2692113584Ssimokawastatic void 2693106790Ssimokawafwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2694103285Sikob{ 2695103285Sikob struct fwohcidb_tr *db_tr; 2696113584Ssimokawa struct iovec vec[2]; 2697113584Ssimokawa struct fw_pkt pktbuf; 2698113584Ssimokawa int nvec; 2699103285Sikob struct fw_pkt *fp; 2700103285Sikob u_int8_t *ld; 2701113584Ssimokawa u_int32_t stat, off, status; 2702103285Sikob u_int spd; 2703113584Ssimokawa int len, plen, hlen, pcnt, offset; 2704103285Sikob int s; 2705103285Sikob caddr_t buf; 2706103285Sikob int resCount; 2707103285Sikob 2708103285Sikob if(&sc->arrq == dbch){ 2709103285Sikob off = OHCI_ARQOFF; 2710103285Sikob }else if(&sc->arrs == dbch){ 2711103285Sikob off = OHCI_ARSOFF; 2712103285Sikob }else{ 2713103285Sikob return; 2714103285Sikob } 2715103285Sikob 2716103285Sikob s = splfw(); 2717103285Sikob db_tr = dbch->top; 2718103285Sikob pcnt = 0; 2719103285Sikob /* XXX we cannot handle a packet which lies in more than two buf */ 2720113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 2721113584Ssimokawa fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 2722113584Ssimokawa status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2723113584Ssimokawa resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2724113584Ssimokawa#if 0 2725113584Ssimokawa printf("status 0x%04x, resCount 0x%04x\n", status, resCount); 2726113584Ssimokawa#endif 2727113584Ssimokawa while (status & OHCI_CNTL_DMA_ACTIVE) { 2728113584Ssimokawa len = dbch->xferq.psize - resCount; 2729113584Ssimokawa ld = (u_int8_t *)db_tr->buf; 2730113584Ssimokawa if (dbch->pdb_tr == NULL) { 2731113584Ssimokawa len -= dbch->buf_offset; 2732113584Ssimokawa ld += dbch->buf_offset; 2733113584Ssimokawa } 2734113584Ssimokawa if (len > 0) 2735113584Ssimokawa bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2736113584Ssimokawa BUS_DMASYNC_POSTREAD); 2737103285Sikob while (len > 0 ) { 2738106789Ssimokawa if (count >= 0 && count-- == 0) 2739106789Ssimokawa goto out; 2740113584Ssimokawa if(dbch->pdb_tr != NULL){ 2741113584Ssimokawa /* we have a fragment in previous buffer */ 2742113584Ssimokawa int rlen; 2743103285Sikob 2744113584Ssimokawa offset = dbch->buf_offset; 2745113584Ssimokawa if (offset < 0) 2746113584Ssimokawa offset = - offset; 2747113584Ssimokawa buf = dbch->pdb_tr->buf + offset; 2748113584Ssimokawa rlen = dbch->xferq.psize - offset; 2749113584Ssimokawa if (firewire_debug) 2750113584Ssimokawa printf("rlen=%d, offset=%d\n", 2751113584Ssimokawa rlen, dbch->buf_offset); 2752113584Ssimokawa if (dbch->buf_offset < 0) { 2753113584Ssimokawa /* splitted in header, pull up */ 2754113584Ssimokawa char *p; 2755113584Ssimokawa 2756113584Ssimokawa p = (char *)&pktbuf; 2757113584Ssimokawa bcopy(buf, p, rlen); 2758113584Ssimokawa p += rlen; 2759113584Ssimokawa /* this must be too long but harmless */ 2760113584Ssimokawa rlen = sizeof(pktbuf) - rlen; 2761113584Ssimokawa if (rlen < 0) 2762113584Ssimokawa printf("why rlen < 0\n"); 2763113584Ssimokawa bcopy(db_tr->buf, p, rlen); 2764103285Sikob ld += rlen; 2765103285Sikob len -= rlen; 2766113584Ssimokawa hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2767113584Ssimokawa if (hlen < 0) { 2768113584Ssimokawa printf("hlen < 0 shouldn't happen"); 2769113584Ssimokawa } 2770113584Ssimokawa offset = sizeof(pktbuf); 2771113584Ssimokawa vec[0].iov_base = (char *)&pktbuf; 2772113584Ssimokawa vec[0].iov_len = offset; 2773113584Ssimokawa } else { 2774113584Ssimokawa /* splitted in payload */ 2775113584Ssimokawa offset = rlen; 2776113584Ssimokawa vec[0].iov_base = buf; 2777113584Ssimokawa vec[0].iov_len = rlen; 2778103285Sikob } 2779113584Ssimokawa fp=(struct fw_pkt *)vec[0].iov_base; 2780113584Ssimokawa nvec = 1; 2781113584Ssimokawa } else { 2782113584Ssimokawa /* no fragment in previous buffer */ 2783103285Sikob fp=(struct fw_pkt *)ld; 2784113584Ssimokawa hlen = fwohci_arcv_swap(fp, len); 2785113584Ssimokawa if (hlen == 0) 2786113584Ssimokawa /* XXX need reset */ 2787103285Sikob goto out; 2788113584Ssimokawa if (hlen < 0) { 2789113584Ssimokawa dbch->pdb_tr = db_tr; 2790113584Ssimokawa dbch->buf_offset = - dbch->buf_offset; 2791113584Ssimokawa /* sanity check */ 2792113584Ssimokawa if (resCount != 0) 2793113584Ssimokawa printf("resCount != 0 !?\n"); 2794113584Ssimokawa goto out; 2795103285Sikob } 2796113584Ssimokawa offset = 0; 2797113584Ssimokawa nvec = 0; 2798113584Ssimokawa } 2799113584Ssimokawa plen = fwohci_get_plen(sc, dbch, fp) - offset; 2800113584Ssimokawa if (plen < 0) { 2801113584Ssimokawa /* minimum header size + trailer 2802113584Ssimokawa = sizeof(fw_pkt) so this shouldn't happens */ 2803113584Ssimokawa printf("plen is negative! offset=%d\n", offset); 2804113584Ssimokawa goto out; 2805113584Ssimokawa } 2806113584Ssimokawa if (plen > 0) { 2807113584Ssimokawa len -= plen; 2808113584Ssimokawa if (len < 0) { 2809113584Ssimokawa dbch->pdb_tr = db_tr; 2810113584Ssimokawa if (firewire_debug) 2811113584Ssimokawa printf("splitted payload\n"); 2812113584Ssimokawa /* sanity check */ 2813113584Ssimokawa if (resCount != 0) 2814113584Ssimokawa printf("resCount != 0 !?\n"); 2815113584Ssimokawa goto out; 2816103285Sikob } 2817113584Ssimokawa vec[nvec].iov_base = ld; 2818113584Ssimokawa vec[nvec].iov_len = plen; 2819113584Ssimokawa nvec ++; 2820103285Sikob ld += plen; 2821103285Sikob } 2822113584Ssimokawa dbch->buf_offset = ld - (u_int8_t *)db_tr->buf; 2823113584Ssimokawa if (nvec == 0) 2824113584Ssimokawa printf("nvec == 0\n"); 2825113584Ssimokawa 2826103285Sikob/* DMA result-code will be written at the tail of packet */ 2827113584Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 2828113584Ssimokawa stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16; 2829113584Ssimokawa#else 2830113584Ssimokawa stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2831113584Ssimokawa#endif 2832110577Ssimokawa#if 0 2833113584Ssimokawa printf("plen: %d, stat %x\n", plen ,stat); 2834103285Sikob#endif 2835113584Ssimokawa spd = (stat >> 5) & 0x3; 2836113584Ssimokawa stat &= 0x1f; 2837113584Ssimokawa switch(stat){ 2838113584Ssimokawa case FWOHCIEV_ACKPEND: 2839113584Ssimokawa#if 0 2840113584Ssimokawa printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2841113584Ssimokawa#endif 2842113584Ssimokawa /* fall through */ 2843113584Ssimokawa case FWOHCIEV_ACKCOMPL: 2844113584Ssimokawa if ((vec[nvec-1].iov_len -= 2845113584Ssimokawa sizeof(struct fwohci_trailer)) == 0) 2846113584Ssimokawa nvec--; 2847113584Ssimokawa fw_rcv(&sc->fc, vec, nvec, 0, spd); 2848103285Sikob break; 2849113584Ssimokawa case FWOHCIEV_BUSRST: 2850113584Ssimokawa if (sc->fc.status != FWBUSRESET) 2851113584Ssimokawa printf("got BUSRST packet!?\n"); 2852113584Ssimokawa break; 2853113584Ssimokawa default: 2854113584Ssimokawa device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2855103285Sikob#if 0 /* XXX */ 2856113584Ssimokawa goto out; 2857103285Sikob#endif 2858113584Ssimokawa break; 2859103285Sikob } 2860103285Sikob pcnt ++; 2861113584Ssimokawa if (dbch->pdb_tr != NULL) { 2862113584Ssimokawa fwohci_arcv_free_buf(dbch, dbch->pdb_tr); 2863113584Ssimokawa dbch->pdb_tr = NULL; 2864113584Ssimokawa } 2865113584Ssimokawa 2866113584Ssimokawa } 2867103285Sikobout: 2868103285Sikob if (resCount == 0) { 2869103285Sikob /* done on this buffer */ 2870113584Ssimokawa if (dbch->pdb_tr == NULL) { 2871113584Ssimokawa fwohci_arcv_free_buf(dbch, db_tr); 2872113584Ssimokawa dbch->buf_offset = 0; 2873113584Ssimokawa } else 2874113584Ssimokawa if (dbch->pdb_tr != db_tr) 2875113584Ssimokawa printf("pdb_tr != db_tr\n"); 2876103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2877113584Ssimokawa status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2878113584Ssimokawa >> OHCI_STATUS_SHIFT; 2879113584Ssimokawa resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2880113584Ssimokawa & OHCI_COUNT_MASK; 2881113584Ssimokawa /* XXX check buffer overrun */ 2882103285Sikob dbch->top = db_tr; 2883103285Sikob } else { 2884103285Sikob dbch->buf_offset = dbch->xferq.psize - resCount; 2885103285Sikob break; 2886103285Sikob } 2887103285Sikob /* XXX make sure DMA is not dead */ 2888103285Sikob } 2889103285Sikob#if 0 2890103285Sikob if (pcnt < 1) 2891103285Sikob printf("fwohci_arcv: no packets\n"); 2892103285Sikob#endif 2893103285Sikob splx(s); 2894103285Sikob} 2895