fwohci.c revision 119118
1/* 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the acknowledgement as bellow: 16 * 17 * This product includes software developed by K. Kobayashi and H. Shimokawa 18 * 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: head/sys/dev/firewire/fwohci.c 119118 2003-08-19 08:47:49Z simokawa $ 35 * 36 */ 37 38#define ATRQ_CH 0 39#define ATRS_CH 1 40#define ARRQ_CH 2 41#define ARRS_CH 3 42#define ITX_CH 4 43#define IRX_CH 0x24 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/mbuf.h> 48#include <sys/malloc.h> 49#include <sys/sockio.h> 50#include <sys/bus.h> 51#include <sys/kernel.h> 52#include <sys/conf.h> 53#include <sys/endian.h> 54 55#include <machine/bus.h> 56 57#if __FreeBSD_version < 500000 58#include <machine/clock.h> /* for DELAY() */ 59#endif 60 61#include <dev/firewire/firewire.h> 62#include <dev/firewire/firewirereg.h> 63#include <dev/firewire/fwdma.h> 64#include <dev/firewire/fwohcireg.h> 65#include <dev/firewire/fwohcivar.h> 66#include <dev/firewire/firewire_phy.h> 67 68#undef OHCI_DEBUG 69 70static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 71 "STOR","LOAD","NOP ","STOP",}; 72 73static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 74 "UNDEF","REG","SYS","DEV"}; 75static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 76char fwohcicode[32][0x20]={ 77 "No stat","Undef","long","miss Ack err", 78 "underrun","overrun","desc err", "data read err", 79 "data write err","bus reset","timeout","tcode err", 80 "Undef","Undef","unknown event","flushed", 81 "Undef","ack complete","ack pend","Undef", 82 "ack busy_X","ack busy_A","ack busy_B","Undef", 83 "Undef","Undef","Undef","ack tardy", 84 "Undef","ack data_err","ack type_err",""}; 85 86#define MAX_SPEED 3 87extern char linkspeed[][0x10]; 88u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 89 90static struct tcode_info tinfo[] = { 91/* hdr_len block flag*/ 92/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 93/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 94/* 2 WRES */ {12, FWTI_RES}, 95/* 3 XXX */ { 0, 0}, 96/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 97/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 98/* 6 RRESQ */ {16, FWTI_RES}, 99/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 100/* 8 CYCS */ { 0, 0}, 101/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 102/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 103/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 104/* c XXX */ { 0, 0}, 105/* d XXX */ { 0, 0}, 106/* e PHY */ {12, FWTI_REQ}, 107/* f XXX */ { 0, 0} 108}; 109 110#define OHCI_WRITE_SIGMASK 0xffff0000 111#define OHCI_READ_SIGMASK 0xffff0000 112 113#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 114#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 115 116static void fwohci_ibr __P((struct firewire_comm *)); 117static void fwohci_db_init __P((struct fwohci_softc *, struct fwohci_dbch *)); 118static void fwohci_db_free __P((struct fwohci_dbch *)); 119static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 120static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 121static void fwohci_start_atq __P((struct firewire_comm *)); 122static void fwohci_start_ats __P((struct firewire_comm *)); 123static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 124static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 125static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 126static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 127static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 128static int fwohci_irx_enable __P((struct firewire_comm *, int)); 129static int fwohci_irx_disable __P((struct firewire_comm *, int)); 130#if BYTE_ORDER == BIG_ENDIAN 131static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 132#endif 133static int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 134static int fwohci_itx_disable __P((struct firewire_comm *, int)); 135static void fwohci_timeout __P((void *)); 136static void fwohci_set_intr __P((struct firewire_comm *, int)); 137 138static int fwohci_add_rx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *)); 139static int fwohci_add_tx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int)); 140static void dump_db __P((struct fwohci_softc *, u_int32_t)); 141static void print_db __P((struct fwohcidb_tr *, volatile struct fwohcidb *, u_int32_t , u_int32_t)); 142static void dump_dma __P((struct fwohci_softc *, u_int32_t)); 143static u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 144static void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 145static void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 146void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 147#if FWOHCI_TASKQUEUE 148static void fwohci_complete(void *, int); 149#endif 150 151/* 152 * memory allocated for DMA programs 153 */ 154#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 155 156/* #define NDB 1024 */ 157#define NDB FWMAXQUEUE 158#define NDVDB (DVBUF * NDB) 159 160#define OHCI_VERSION 0x00 161#define OHCI_ATRETRY 0x08 162#define OHCI_CROMHDR 0x18 163#define OHCI_BUS_OPT 0x20 164#define OHCI_BUSIRMC (1 << 31) 165#define OHCI_BUSCMC (1 << 30) 166#define OHCI_BUSISC (1 << 29) 167#define OHCI_BUSBMC (1 << 28) 168#define OHCI_BUSPMC (1 << 27) 169#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 170 OHCI_BUSBMC | OHCI_BUSPMC 171 172#define OHCI_EUID_HI 0x24 173#define OHCI_EUID_LO 0x28 174 175#define OHCI_CROMPTR 0x34 176#define OHCI_HCCCTL 0x50 177#define OHCI_HCCCTLCLR 0x54 178#define OHCI_AREQHI 0x100 179#define OHCI_AREQHICLR 0x104 180#define OHCI_AREQLO 0x108 181#define OHCI_AREQLOCLR 0x10c 182#define OHCI_PREQHI 0x110 183#define OHCI_PREQHICLR 0x114 184#define OHCI_PREQLO 0x118 185#define OHCI_PREQLOCLR 0x11c 186#define OHCI_PREQUPPER 0x120 187 188#define OHCI_SID_BUF 0x64 189#define OHCI_SID_CNT 0x68 190#define OHCI_SID_ERR (1 << 31) 191#define OHCI_SID_CNT_MASK 0xffc 192 193#define OHCI_IT_STAT 0x90 194#define OHCI_IT_STATCLR 0x94 195#define OHCI_IT_MASK 0x98 196#define OHCI_IT_MASKCLR 0x9c 197 198#define OHCI_IR_STAT 0xa0 199#define OHCI_IR_STATCLR 0xa4 200#define OHCI_IR_MASK 0xa8 201#define OHCI_IR_MASKCLR 0xac 202 203#define OHCI_LNKCTL 0xe0 204#define OHCI_LNKCTLCLR 0xe4 205 206#define OHCI_PHYACCESS 0xec 207#define OHCI_CYCLETIMER 0xf0 208 209#define OHCI_DMACTL(off) (off) 210#define OHCI_DMACTLCLR(off) (off + 4) 211#define OHCI_DMACMD(off) (off + 0xc) 212#define OHCI_DMAMATCH(off) (off + 0x10) 213 214#define OHCI_ATQOFF 0x180 215#define OHCI_ATQCTL OHCI_ATQOFF 216#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 217#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 218#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 219 220#define OHCI_ATSOFF 0x1a0 221#define OHCI_ATSCTL OHCI_ATSOFF 222#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 223#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 224#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 225 226#define OHCI_ARQOFF 0x1c0 227#define OHCI_ARQCTL OHCI_ARQOFF 228#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 229#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 230#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 231 232#define OHCI_ARSOFF 0x1e0 233#define OHCI_ARSCTL OHCI_ARSOFF 234#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 235#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 236#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 237 238#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 239#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 240#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 241#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 242 243#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 244#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 245#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 246#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 247#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 248 249d_ioctl_t fwohci_ioctl; 250 251/* 252 * Communication with PHY device 253 */ 254static u_int32_t 255fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 256{ 257 u_int32_t fun; 258 259 addr &= 0xf; 260 data &= 0xff; 261 262 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 263 OWRITE(sc, OHCI_PHYACCESS, fun); 264 DELAY(100); 265 266 return(fwphy_rddata( sc, addr)); 267} 268 269static u_int32_t 270fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 271{ 272 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 273 int i; 274 u_int32_t bm; 275 276#define OHCI_CSR_DATA 0x0c 277#define OHCI_CSR_COMP 0x10 278#define OHCI_CSR_CONT 0x14 279#define OHCI_BUS_MANAGER_ID 0 280 281 OWRITE(sc, OHCI_CSR_DATA, node); 282 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 283 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 284 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 285 DELAY(10); 286 bm = OREAD(sc, OHCI_CSR_DATA); 287 if((bm & 0x3f) == 0x3f) 288 bm = node; 289 if (bootverbose) 290 device_printf(sc->fc.dev, 291 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 292 293 return(bm); 294} 295 296static u_int32_t 297fwphy_rddata(struct fwohci_softc *sc, u_int addr) 298{ 299 u_int32_t fun, stat; 300 u_int i, retry = 0; 301 302 addr &= 0xf; 303#define MAX_RETRY 100 304again: 305 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 306 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 307 OWRITE(sc, OHCI_PHYACCESS, fun); 308 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 309 fun = OREAD(sc, OHCI_PHYACCESS); 310 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 311 break; 312 DELAY(100); 313 } 314 if(i >= MAX_RETRY) { 315 if (bootverbose) 316 device_printf(sc->fc.dev, "phy read failed(1).\n"); 317 if (++retry < MAX_RETRY) { 318 DELAY(100); 319 goto again; 320 } 321 } 322 /* Make sure that SCLK is started */ 323 stat = OREAD(sc, FWOHCI_INTSTAT); 324 if ((stat & OHCI_INT_REG_FAIL) != 0 || 325 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 326 if (bootverbose) 327 device_printf(sc->fc.dev, "phy read failed(2).\n"); 328 if (++retry < MAX_RETRY) { 329 DELAY(100); 330 goto again; 331 } 332 } 333 if (bootverbose || retry >= MAX_RETRY) 334 device_printf(sc->fc.dev, 335 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 336#undef MAX_RETRY 337 return((fun >> PHYDEV_RDDATA )& 0xff); 338} 339/* Device specific ioctl. */ 340int 341fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 342{ 343 struct firewire_softc *sc; 344 struct fwohci_softc *fc; 345 int unit = DEV2UNIT(dev); 346 int err = 0; 347 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 348 u_int32_t *dmach = (u_int32_t *) data; 349 350 sc = devclass_get_softc(firewire_devclass, unit); 351 if(sc == NULL){ 352 return(EINVAL); 353 } 354 fc = (struct fwohci_softc *)sc->fc; 355 356 if (!data) 357 return(EINVAL); 358 359 switch (cmd) { 360 case FWOHCI_WRREG: 361#define OHCI_MAX_REG 0x800 362 if(reg->addr <= OHCI_MAX_REG){ 363 OWRITE(fc, reg->addr, reg->data); 364 reg->data = OREAD(fc, reg->addr); 365 }else{ 366 err = EINVAL; 367 } 368 break; 369 case FWOHCI_RDREG: 370 if(reg->addr <= OHCI_MAX_REG){ 371 reg->data = OREAD(fc, reg->addr); 372 }else{ 373 err = EINVAL; 374 } 375 break; 376/* Read DMA descriptors for debug */ 377 case DUMPDMA: 378 if(*dmach <= OHCI_MAX_DMA_CH ){ 379 dump_dma(fc, *dmach); 380 dump_db(fc, *dmach); 381 }else{ 382 err = EINVAL; 383 } 384 break; 385/* Read/Write Phy registers */ 386#define OHCI_MAX_PHY_REG 0xf 387 case FWOHCI_RDPHYREG: 388 if (reg->addr <= OHCI_MAX_PHY_REG) 389 reg->data = fwphy_rddata(fc, reg->addr); 390 else 391 err = EINVAL; 392 break; 393 case FWOHCI_WRPHYREG: 394 if (reg->addr <= OHCI_MAX_PHY_REG) 395 reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 396 else 397 err = EINVAL; 398 break; 399 default: 400 err = EINVAL; 401 break; 402 } 403 return err; 404} 405 406static int 407fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 408{ 409 u_int32_t reg, reg2; 410 int e1394a = 1; 411/* 412 * probe PHY parameters 413 * 0. to prove PHY version, whether compliance of 1394a. 414 * 1. to probe maximum speed supported by the PHY and 415 * number of port supported by core-logic. 416 * It is not actually available port on your PC . 417 */ 418 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 419 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 420 421 if((reg >> 5) != 7 ){ 422 sc->fc.mode &= ~FWPHYASYST; 423 sc->fc.nport = reg & FW_PHY_NP; 424 sc->fc.speed = reg & FW_PHY_SPD >> 6; 425 if (sc->fc.speed > MAX_SPEED) { 426 device_printf(dev, "invalid speed %d (fixed to %d).\n", 427 sc->fc.speed, MAX_SPEED); 428 sc->fc.speed = MAX_SPEED; 429 } 430 device_printf(dev, 431 "Phy 1394 only %s, %d ports.\n", 432 linkspeed[sc->fc.speed], sc->fc.nport); 433 }else{ 434 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 435 sc->fc.mode |= FWPHYASYST; 436 sc->fc.nport = reg & FW_PHY_NP; 437 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 438 if (sc->fc.speed > MAX_SPEED) { 439 device_printf(dev, "invalid speed %d (fixed to %d).\n", 440 sc->fc.speed, MAX_SPEED); 441 sc->fc.speed = MAX_SPEED; 442 } 443 device_printf(dev, 444 "Phy 1394a available %s, %d ports.\n", 445 linkspeed[sc->fc.speed], sc->fc.nport); 446 447 /* check programPhyEnable */ 448 reg2 = fwphy_rddata(sc, 5); 449#if 0 450 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 451#else /* XXX force to enable 1394a */ 452 if (e1394a) { 453#endif 454 if (bootverbose) 455 device_printf(dev, 456 "Enable 1394a Enhancements\n"); 457 /* enable EAA EMC */ 458 reg2 |= 0x03; 459 /* set aPhyEnhanceEnable */ 460 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 461 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 462 } else { 463 /* for safe */ 464 reg2 &= ~0x83; 465 } 466 reg2 = fwphy_wrdata(sc, 5, reg2); 467 } 468 469 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 470 if((reg >> 5) == 7 ){ 471 reg = fwphy_rddata(sc, 4); 472 reg |= 1 << 6; 473 fwphy_wrdata(sc, 4, reg); 474 reg = fwphy_rddata(sc, 4); 475 } 476 return 0; 477} 478 479 480void 481fwohci_reset(struct fwohci_softc *sc, device_t dev) 482{ 483 int i, max_rec, speed; 484 u_int32_t reg, reg2; 485 struct fwohcidb_tr *db_tr; 486 487 /* Disable interrupt */ 488 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 489 490 /* Now stopping all DMA channel */ 491 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 492 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 493 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 494 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 495 496 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 497 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 498 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 499 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 500 } 501 502 /* FLUSH FIFO and reset Transmitter/Reciever */ 503 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 504 if (bootverbose) 505 device_printf(dev, "resetting OHCI..."); 506 i = 0; 507 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 508 if (i++ > 100) break; 509 DELAY(1000); 510 } 511 if (bootverbose) 512 printf("done (loop=%d)\n", i); 513 514 /* Probe phy */ 515 fwohci_probe_phy(sc, dev); 516 517 /* Probe link */ 518 reg = OREAD(sc, OHCI_BUS_OPT); 519 reg2 = reg | OHCI_BUSFNC; 520 max_rec = (reg & 0x0000f000) >> 12; 521 speed = (reg & 0x00000007); 522 device_printf(dev, "Link %s, max_rec %d bytes.\n", 523 linkspeed[speed], MAXREC(max_rec)); 524 /* XXX fix max_rec */ 525 sc->fc.maxrec = sc->fc.speed + 8; 526 if (max_rec != sc->fc.maxrec) { 527 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 528 device_printf(dev, "max_rec %d -> %d\n", 529 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 530 } 531 if (bootverbose) 532 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 533 OWRITE(sc, OHCI_BUS_OPT, reg2); 534 535 /* Initialize registers */ 536 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 537 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 538 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 539 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 540 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 541 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 542 fw_busreset(&sc->fc); 543 544 /* Enable link */ 545 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 546 547 /* Force to start async RX DMA */ 548 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 549 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 550 fwohci_rx_enable(sc, &sc->arrq); 551 fwohci_rx_enable(sc, &sc->arrs); 552 553 /* Initialize async TX */ 554 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 555 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 556 557 /* AT Retries */ 558 OWRITE(sc, FWOHCI_RETRY, 559 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 560 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 561 562 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 563 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 564 sc->atrq.bottom = sc->atrq.top; 565 sc->atrs.bottom = sc->atrs.top; 566 567 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 568 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 569 db_tr->xfer = NULL; 570 } 571 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 572 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 573 db_tr->xfer = NULL; 574 } 575 576 577 /* Enable interrupt */ 578 OWRITE(sc, FWOHCI_INTMASK, 579 OHCI_INT_ERR | OHCI_INT_PHY_SID 580 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 581 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 582 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 583 fwohci_set_intr(&sc->fc, 1); 584 585} 586 587int 588fwohci_init(struct fwohci_softc *sc, device_t dev) 589{ 590 int i; 591 u_int32_t reg; 592 u_int8_t ui[8]; 593 594#if FWOHCI_TASKQUEUE 595 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 596#endif 597 598 reg = OREAD(sc, OHCI_VERSION); 599 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 600 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 601 602 if (((reg>>16) & 0xff) < 1) { 603 device_printf(dev, "invalid OHCI version\n"); 604 return (ENXIO); 605 } 606 607/* Available Isochrounous DMA channel probe */ 608 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 609 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 610 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 611 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 612 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 613 for (i = 0; i < 0x20; i++) 614 if ((reg & (1 << i)) == 0) 615 break; 616 sc->fc.nisodma = i; 617 device_printf(dev, "No. of Isochronous channel is %d.\n", i); 618 if (i == 0) 619 return (ENXIO); 620 621 sc->fc.arq = &sc->arrq.xferq; 622 sc->fc.ars = &sc->arrs.xferq; 623 sc->fc.atq = &sc->atrq.xferq; 624 sc->fc.ats = &sc->atrs.xferq; 625 626 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 627 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 628 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 629 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 630 631 sc->arrq.xferq.start = NULL; 632 sc->arrs.xferq.start = NULL; 633 sc->atrq.xferq.start = fwohci_start_atq; 634 sc->atrs.xferq.start = fwohci_start_ats; 635 636 sc->arrq.xferq.buf = NULL; 637 sc->arrs.xferq.buf = NULL; 638 sc->atrq.xferq.buf = NULL; 639 sc->atrs.xferq.buf = NULL; 640 641 sc->arrq.xferq.dmach = -1; 642 sc->arrs.xferq.dmach = -1; 643 sc->atrq.xferq.dmach = -1; 644 sc->atrs.xferq.dmach = -1; 645 646 sc->arrq.ndesc = 1; 647 sc->arrs.ndesc = 1; 648 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 649 sc->atrs.ndesc = 2; 650 651 sc->arrq.ndb = NDB; 652 sc->arrs.ndb = NDB / 2; 653 sc->atrq.ndb = NDB; 654 sc->atrs.ndb = NDB / 2; 655 656 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 657 sc->fc.it[i] = &sc->it[i].xferq; 658 sc->fc.ir[i] = &sc->ir[i].xferq; 659 sc->it[i].xferq.dmach = i; 660 sc->ir[i].xferq.dmach = i; 661 sc->it[i].ndb = 0; 662 sc->ir[i].ndb = 0; 663 } 664 665 sc->fc.tcode = tinfo; 666 sc->fc.dev = dev; 667 668 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 669 &sc->crom_dma, BUS_DMA_WAITOK); 670 if(sc->fc.config_rom == NULL){ 671 device_printf(dev, "config_rom alloc failed."); 672 return ENOMEM; 673 } 674 675#if 0 676 bzero(&sc->fc.config_rom[0], CROMSIZE); 677 sc->fc.config_rom[1] = 0x31333934; 678 sc->fc.config_rom[2] = 0xf000a002; 679 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 680 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 681 sc->fc.config_rom[5] = 0; 682 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 683 684 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 685#endif 686 687 688/* SID recieve buffer must allign 2^11 */ 689#define OHCI_SIDSIZE (1 << 11) 690 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 691 &sc->sid_dma, BUS_DMA_WAITOK); 692 if (sc->sid_buf == NULL) { 693 device_printf(dev, "sid_buf alloc failed."); 694 return ENOMEM; 695 } 696 697 fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t), 698 &sc->dummy_dma, BUS_DMA_WAITOK); 699 700 if (sc->dummy_dma.v_addr == NULL) { 701 device_printf(dev, "dummy_dma alloc failed."); 702 return ENOMEM; 703 } 704 705 fwohci_db_init(sc, &sc->arrq); 706 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 707 return ENOMEM; 708 709 fwohci_db_init(sc, &sc->arrs); 710 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 711 return ENOMEM; 712 713 fwohci_db_init(sc, &sc->atrq); 714 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 715 return ENOMEM; 716 717 fwohci_db_init(sc, &sc->atrs); 718 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 719 return ENOMEM; 720 721 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 722 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 723 for( i = 0 ; i < 8 ; i ++) 724 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 725 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 726 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 727 728 sc->fc.ioctl = fwohci_ioctl; 729 sc->fc.cyctimer = fwohci_cyctimer; 730 sc->fc.set_bmr = fwohci_set_bus_manager; 731 sc->fc.ibr = fwohci_ibr; 732 sc->fc.irx_enable = fwohci_irx_enable; 733 sc->fc.irx_disable = fwohci_irx_disable; 734 735 sc->fc.itx_enable = fwohci_itxbuf_enable; 736 sc->fc.itx_disable = fwohci_itx_disable; 737#if BYTE_ORDER == BIG_ENDIAN 738 sc->fc.irx_post = fwohci_irx_post; 739#else 740 sc->fc.irx_post = NULL; 741#endif 742 sc->fc.itx_post = NULL; 743 sc->fc.timeout = fwohci_timeout; 744 sc->fc.poll = fwohci_poll; 745 sc->fc.set_intr = fwohci_set_intr; 746 747 sc->intmask = sc->irstat = sc->itstat = 0; 748 749 fw_init(&sc->fc); 750 fwohci_reset(sc, dev); 751 752 return 0; 753} 754 755void 756fwohci_timeout(void *arg) 757{ 758 struct fwohci_softc *sc; 759 760 sc = (struct fwohci_softc *)arg; 761} 762 763u_int32_t 764fwohci_cyctimer(struct firewire_comm *fc) 765{ 766 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 767 return(OREAD(sc, OHCI_CYCLETIMER)); 768} 769 770int 771fwohci_detach(struct fwohci_softc *sc, device_t dev) 772{ 773 int i; 774 775 if (sc->sid_buf != NULL) 776 fwdma_free(&sc->fc, &sc->sid_dma); 777 if (sc->fc.config_rom != NULL) 778 fwdma_free(&sc->fc, &sc->crom_dma); 779 780 fwohci_db_free(&sc->arrq); 781 fwohci_db_free(&sc->arrs); 782 783 fwohci_db_free(&sc->atrq); 784 fwohci_db_free(&sc->atrs); 785 786 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 787 fwohci_db_free(&sc->it[i]); 788 fwohci_db_free(&sc->ir[i]); 789 } 790 791 return 0; 792} 793 794#define LAST_DB(dbtr, db) do { \ 795 struct fwohcidb_tr *_dbtr = (dbtr); \ 796 int _cnt = _dbtr->dbcnt; \ 797 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 798} while (0) 799 800static void 801fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 802{ 803 struct fwohcidb_tr *db_tr; 804 volatile struct fwohcidb *db; 805 bus_dma_segment_t *s; 806 int i; 807 808 db_tr = (struct fwohcidb_tr *)arg; 809 db = &db_tr->db[db_tr->dbcnt]; 810 if (error) { 811 if (firewire_debug || error != EFBIG) 812 printf("fwohci_execute_db: error=%d\n", error); 813 return; 814 } 815 for (i = 0; i < nseg; i++) { 816 s = &segs[i]; 817 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 818 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 819 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 820 db++; 821 db_tr->dbcnt++; 822 } 823} 824 825static void 826fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 827 bus_size_t size, int error) 828{ 829 fwohci_execute_db(arg, segs, nseg, error); 830} 831 832static void 833fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 834{ 835 int i, s; 836 int tcode, hdr_len, pl_off, pl_len; 837 int fsegment = -1; 838 u_int32_t off; 839 struct fw_xfer *xfer; 840 struct fw_pkt *fp; 841 volatile struct fwohci_txpkthdr *ohcifp; 842 struct fwohcidb_tr *db_tr; 843 volatile struct fwohcidb *db; 844 struct tcode_info *info; 845 static int maxdesc=0; 846 847 if(&sc->atrq == dbch){ 848 off = OHCI_ATQOFF; 849 }else if(&sc->atrs == dbch){ 850 off = OHCI_ATSOFF; 851 }else{ 852 return; 853 } 854 855 if (dbch->flags & FWOHCI_DBCH_FULL) 856 return; 857 858 s = splfw(); 859 db_tr = dbch->top; 860txloop: 861 xfer = STAILQ_FIRST(&dbch->xferq.q); 862 if(xfer == NULL){ 863 goto kick; 864 } 865 if(dbch->xferq.queued == 0 ){ 866 device_printf(sc->fc.dev, "TX queue empty\n"); 867 } 868 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 869 db_tr->xfer = xfer; 870 xfer->state = FWXF_START; 871 872 fp = (struct fw_pkt *)xfer->send.buf; 873 tcode = fp->mode.common.tcode; 874 875 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 876 info = &tinfo[tcode]; 877 hdr_len = pl_off = info->hdr_len; 878 for( i = 0 ; i < pl_off ; i+= 4){ 879 ohcifp->mode.ld[i/4] = fp->mode.ld[i/4]; 880 } 881 ohcifp->mode.common.spd = xfer->spd; 882 if (tcode == FWTCODE_STREAM ){ 883 hdr_len = 8; 884 ohcifp->mode.stream.len = fp->mode.stream.len; 885 } else if (tcode == FWTCODE_PHY) { 886 hdr_len = 12; 887 ohcifp->mode.ld[1] = fp->mode.ld[1]; 888 ohcifp->mode.ld[2] = fp->mode.ld[2]; 889 ohcifp->mode.common.spd = 0; 890 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 891 } else { 892 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 893 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 894 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 895 } 896 db = &db_tr->db[0]; 897 FWOHCI_DMA_WRITE(db->db.desc.cmd, 898 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 899 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 900/* Specify bound timer of asy. responce */ 901 if(&sc->atrs == dbch){ 902 FWOHCI_DMA_WRITE(db->db.desc.res, 903 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 904 } 905#if BYTE_ORDER == BIG_ENDIAN 906 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 907 hdr_len = 12; 908 for (i = 0; i < hdr_len/4; i ++) 909 FWOHCI_DMA_WRITE(ohcifp->mode.ld[i], ohcifp->mode.ld[i]); 910#endif 911 912again: 913 db_tr->dbcnt = 2; 914 db = &db_tr->db[db_tr->dbcnt]; 915 pl_len = xfer->send.len - pl_off; 916 if (pl_len > 0) { 917 int err; 918 /* handle payload */ 919 if (xfer->mbuf == NULL) { 920 caddr_t pl_addr; 921 922 pl_addr = xfer->send.buf + pl_off; 923 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 924 pl_addr, pl_len, 925 fwohci_execute_db, db_tr, 926 /*flags*/0); 927 } else { 928 /* XXX we can handle only 6 (=8-2) mbuf chains */ 929 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 930 xfer->mbuf, 931 fwohci_execute_db2, db_tr, 932 /* flags */0); 933 if (err == EFBIG) { 934 struct mbuf *m0; 935 936 if (firewire_debug) 937 device_printf(sc->fc.dev, "EFBIG.\n"); 938 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 939 if (m0 != NULL) { 940 m_copydata(xfer->mbuf, 0, 941 xfer->mbuf->m_pkthdr.len, 942 mtod(m0, caddr_t)); 943 m0->m_len = m0->m_pkthdr.len = 944 xfer->mbuf->m_pkthdr.len; 945 m_freem(xfer->mbuf); 946 xfer->mbuf = m0; 947 goto again; 948 } 949 device_printf(sc->fc.dev, "m_getcl failed.\n"); 950 } 951 } 952 if (err) 953 printf("dmamap_load: err=%d\n", err); 954 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 955 BUS_DMASYNC_PREWRITE); 956#if 0 /* OHCI_OUTPUT_MODE == 0 */ 957 for (i = 2; i < db_tr->dbcnt; i++) 958 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 959 OHCI_OUTPUT_MORE); 960#endif 961 } 962 if (maxdesc < db_tr->dbcnt) { 963 maxdesc = db_tr->dbcnt; 964 if (bootverbose) 965 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 966 } 967 /* last db */ 968 LAST_DB(db_tr, db); 969 FWOHCI_DMA_SET(db->db.desc.cmd, 970 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 971 FWOHCI_DMA_WRITE(db->db.desc.depend, 972 STAILQ_NEXT(db_tr, link)->bus_addr); 973 974 if(fsegment == -1 ) 975 fsegment = db_tr->dbcnt; 976 if (dbch->pdb_tr != NULL) { 977 LAST_DB(dbch->pdb_tr, db); 978 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 979 } 980 dbch->pdb_tr = db_tr; 981 db_tr = STAILQ_NEXT(db_tr, link); 982 if(db_tr != dbch->bottom){ 983 goto txloop; 984 } else { 985 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 986 dbch->flags |= FWOHCI_DBCH_FULL; 987 } 988kick: 989 /* kick asy q */ 990 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 991 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 992 993 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 994 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 995 } else { 996 if (bootverbose) 997 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 998 OREAD(sc, OHCI_DMACTL(off))); 999 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1000 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1001 dbch->xferq.flag |= FWXFERQ_RUNNING; 1002 } 1003 1004 dbch->top = db_tr; 1005 splx(s); 1006 return; 1007} 1008 1009static void 1010fwohci_start_atq(struct firewire_comm *fc) 1011{ 1012 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1013 fwohci_start( sc, &(sc->atrq)); 1014 return; 1015} 1016 1017static void 1018fwohci_start_ats(struct firewire_comm *fc) 1019{ 1020 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1021 fwohci_start( sc, &(sc->atrs)); 1022 return; 1023} 1024 1025void 1026fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1027{ 1028 int s, ch, err = 0; 1029 struct fwohcidb_tr *tr; 1030 volatile struct fwohcidb *db; 1031 struct fw_xfer *xfer; 1032 u_int32_t off; 1033 u_int stat, status; 1034 int packets; 1035 struct firewire_comm *fc = (struct firewire_comm *)sc; 1036 1037 if(&sc->atrq == dbch){ 1038 off = OHCI_ATQOFF; 1039 ch = ATRQ_CH; 1040 }else if(&sc->atrs == dbch){ 1041 off = OHCI_ATSOFF; 1042 ch = ATRS_CH; 1043 }else{ 1044 return; 1045 } 1046 s = splfw(); 1047 tr = dbch->bottom; 1048 packets = 0; 1049 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 1050 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 1051 while(dbch->xferq.queued > 0){ 1052 LAST_DB(tr, db); 1053 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1054 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1055 if (fc->status != FWBUSRESET) 1056 /* maybe out of order?? */ 1057 goto out; 1058 } 1059 bus_dmamap_sync(dbch->dmat, tr->dma_map, 1060 BUS_DMASYNC_POSTWRITE); 1061 bus_dmamap_unload(dbch->dmat, tr->dma_map); 1062#if 0 1063 dump_db(sc, ch); 1064#endif 1065 if(status & OHCI_CNTL_DMA_DEAD) { 1066 /* Stop DMA */ 1067 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1068 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1069 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1070 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1071 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1072 } 1073 stat = status & FWOHCIEV_MASK; 1074 switch(stat){ 1075 case FWOHCIEV_ACKPEND: 1076 case FWOHCIEV_ACKCOMPL: 1077 err = 0; 1078 break; 1079 case FWOHCIEV_ACKBSA: 1080 case FWOHCIEV_ACKBSB: 1081 case FWOHCIEV_ACKBSX: 1082 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1083 err = EBUSY; 1084 break; 1085 case FWOHCIEV_FLUSHED: 1086 case FWOHCIEV_ACKTARD: 1087 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1088 err = EAGAIN; 1089 break; 1090 case FWOHCIEV_MISSACK: 1091 case FWOHCIEV_UNDRRUN: 1092 case FWOHCIEV_OVRRUN: 1093 case FWOHCIEV_DESCERR: 1094 case FWOHCIEV_DTRDERR: 1095 case FWOHCIEV_TIMEOUT: 1096 case FWOHCIEV_TCODERR: 1097 case FWOHCIEV_UNKNOWN: 1098 case FWOHCIEV_ACKDERR: 1099 case FWOHCIEV_ACKTERR: 1100 default: 1101 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1102 stat, fwohcicode[stat]); 1103 err = EINVAL; 1104 break; 1105 } 1106 if (tr->xfer != NULL) { 1107 xfer = tr->xfer; 1108 if (xfer->state == FWXF_RCVD) { 1109 if (firewire_debug) 1110 printf("already rcvd\n"); 1111 fw_xfer_done(xfer); 1112 } else { 1113 xfer->state = FWXF_SENT; 1114 if (err == EBUSY && fc->status != FWBUSRESET) { 1115 xfer->state = FWXF_BUSY; 1116 xfer->resp = err; 1117 if (xfer->retry_req != NULL) 1118 xfer->retry_req(xfer); 1119 else { 1120 xfer->recv.len = 0; 1121 fw_xfer_done(xfer); 1122 } 1123 } else if (stat != FWOHCIEV_ACKPEND) { 1124 if (stat != FWOHCIEV_ACKCOMPL) 1125 xfer->state = FWXF_SENTERR; 1126 xfer->resp = err; 1127 xfer->recv.len = 0; 1128 fw_xfer_done(xfer); 1129 } 1130 } 1131 /* 1132 * The watchdog timer takes care of split 1133 * transcation timeout for ACKPEND case. 1134 */ 1135 } else { 1136 printf("this shouldn't happen\n"); 1137 } 1138 dbch->xferq.queued --; 1139 tr->xfer = NULL; 1140 1141 packets ++; 1142 tr = STAILQ_NEXT(tr, link); 1143 dbch->bottom = tr; 1144 if (dbch->bottom == dbch->top) { 1145 /* we reaches the end of context program */ 1146 if (firewire_debug && dbch->xferq.queued > 0) 1147 printf("queued > 0\n"); 1148 break; 1149 } 1150 } 1151out: 1152 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1153 printf("make free slot\n"); 1154 dbch->flags &= ~FWOHCI_DBCH_FULL; 1155 fwohci_start(sc, dbch); 1156 } 1157 splx(s); 1158} 1159 1160static void 1161fwohci_db_free(struct fwohci_dbch *dbch) 1162{ 1163 struct fwohcidb_tr *db_tr; 1164 int idb; 1165 1166 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1167 return; 1168 1169 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1170 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1171 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1172 db_tr->buf != NULL) { 1173 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1174 db_tr->buf, dbch->xferq.psize); 1175 db_tr->buf = NULL; 1176 } else if (db_tr->dma_map != NULL) 1177 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1178 } 1179 dbch->ndb = 0; 1180 db_tr = STAILQ_FIRST(&dbch->db_trq); 1181 fwdma_free_multiseg(dbch->am); 1182 free(db_tr, M_FW); 1183 STAILQ_INIT(&dbch->db_trq); 1184 dbch->flags &= ~FWOHCI_DBCH_INIT; 1185} 1186 1187static void 1188fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1189{ 1190 int idb; 1191 struct fwohcidb_tr *db_tr; 1192 1193 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1194 goto out; 1195 1196 /* create dma_tag for buffers */ 1197#define MAX_REQCOUNT 0xffff 1198 if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1199 /*alignment*/ 1, /*boundary*/ 0, 1200 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1201 /*highaddr*/ BUS_SPACE_MAXADDR, 1202 /*filter*/NULL, /*filterarg*/NULL, 1203 /*maxsize*/ dbch->xferq.psize, 1204 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1205 /*maxsegsz*/ MAX_REQCOUNT, 1206 /*flags*/ 0, 1207#if __FreeBSD_version >= 501102 1208 /*lockfunc*/busdma_lock_mutex, 1209 /*lockarg*/&Giant, 1210#endif 1211 &dbch->dmat)) 1212 return; 1213 1214 /* allocate DB entries and attach one to each DMA channels */ 1215 /* DB entry must start at 16 bytes bounary. */ 1216 STAILQ_INIT(&dbch->db_trq); 1217 db_tr = (struct fwohcidb_tr *) 1218 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1219 M_FW, M_WAITOK | M_ZERO); 1220 if(db_tr == NULL){ 1221 printf("fwohci_db_init: malloc(1) failed\n"); 1222 return; 1223 } 1224 1225#define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1226 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1227 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1228 if (dbch->am == NULL) { 1229 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1230 return; 1231 } 1232 /* Attach DB to DMA ch. */ 1233 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1234 db_tr->dbcnt = 0; 1235 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1236 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1237 /* create dmamap for buffers */ 1238 /* XXX do we need 4bytes alignment tag? */ 1239 /* XXX don't alloc dma_map for AR */ 1240 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1241 printf("bus_dmamap_create failed\n"); 1242 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1243 fwohci_db_free(dbch); 1244 return; 1245 } 1246 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1247 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1248 if (idb % dbch->xferq.bnpacket == 0) 1249 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1250 ].start = (caddr_t)db_tr; 1251 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1252 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1253 ].end = (caddr_t)db_tr; 1254 } 1255 db_tr++; 1256 } 1257 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1258 = STAILQ_FIRST(&dbch->db_trq); 1259out: 1260 dbch->xferq.queued = 0; 1261 dbch->pdb_tr = NULL; 1262 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1263 dbch->bottom = dbch->top; 1264 dbch->flags = FWOHCI_DBCH_INIT; 1265} 1266 1267static int 1268fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1269{ 1270 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1271 int sleepch; 1272 1273 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1274 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1275 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1276 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1277 /* XXX we cannot free buffers until the DMA really stops */ 1278 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1279 fwohci_db_free(&sc->it[dmach]); 1280 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1281 return 0; 1282} 1283 1284static int 1285fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1286{ 1287 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1288 int sleepch; 1289 1290 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1291 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1292 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1293 /* XXX we cannot free buffers until the DMA really stops */ 1294 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1295 fwohci_db_free(&sc->ir[dmach]); 1296 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1297 return 0; 1298} 1299 1300#if BYTE_ORDER == BIG_ENDIAN 1301static void 1302fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1303{ 1304 qld[0] = FWOHCI_DMA_READ(qld[0]); 1305 return; 1306} 1307#endif 1308 1309static int 1310fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1311{ 1312 int err = 0; 1313 int idb, z, i, dmach = 0, ldesc; 1314 u_int32_t off = NULL; 1315 struct fwohcidb_tr *db_tr; 1316 volatile struct fwohcidb *db; 1317 1318 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1319 err = EINVAL; 1320 return err; 1321 } 1322 z = dbch->ndesc; 1323 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1324 if( &sc->it[dmach] == dbch){ 1325 off = OHCI_ITOFF(dmach); 1326 break; 1327 } 1328 } 1329 if(off == NULL){ 1330 err = EINVAL; 1331 return err; 1332 } 1333 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1334 return err; 1335 dbch->xferq.flag |= FWXFERQ_RUNNING; 1336 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1337 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1338 } 1339 db_tr = dbch->top; 1340 for (idb = 0; idb < dbch->ndb; idb ++) { 1341 fwohci_add_tx_buf(dbch, db_tr, idb); 1342 if(STAILQ_NEXT(db_tr, link) == NULL){ 1343 break; 1344 } 1345 db = db_tr->db; 1346 ldesc = db_tr->dbcnt - 1; 1347 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1348 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1349 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1350 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1351 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1352 FWOHCI_DMA_SET( 1353 db[ldesc].db.desc.cmd, 1354 OHCI_INTERRUPT_ALWAYS); 1355 /* OHCI 1.1 and above */ 1356 FWOHCI_DMA_SET( 1357 db[0].db.desc.cmd, 1358 OHCI_INTERRUPT_ALWAYS); 1359 } 1360 } 1361 db_tr = STAILQ_NEXT(db_tr, link); 1362 } 1363 FWOHCI_DMA_CLEAR( 1364 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1365 return err; 1366} 1367 1368static int 1369fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1370{ 1371 int err = 0; 1372 int idb, z, i, dmach = 0, ldesc; 1373 u_int32_t off = NULL; 1374 struct fwohcidb_tr *db_tr; 1375 volatile struct fwohcidb *db; 1376 1377 z = dbch->ndesc; 1378 if(&sc->arrq == dbch){ 1379 off = OHCI_ARQOFF; 1380 }else if(&sc->arrs == dbch){ 1381 off = OHCI_ARSOFF; 1382 }else{ 1383 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1384 if( &sc->ir[dmach] == dbch){ 1385 off = OHCI_IROFF(dmach); 1386 break; 1387 } 1388 } 1389 } 1390 if(off == NULL){ 1391 err = EINVAL; 1392 return err; 1393 } 1394 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1395 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1396 return err; 1397 }else{ 1398 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1399 err = EBUSY; 1400 return err; 1401 } 1402 } 1403 dbch->xferq.flag |= FWXFERQ_RUNNING; 1404 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1405 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1406 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1407 } 1408 db_tr = dbch->top; 1409 for (idb = 0; idb < dbch->ndb; idb ++) { 1410 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1411 if (STAILQ_NEXT(db_tr, link) == NULL) 1412 break; 1413 db = db_tr->db; 1414 ldesc = db_tr->dbcnt - 1; 1415 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1416 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1417 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1418 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1419 FWOHCI_DMA_SET( 1420 db[ldesc].db.desc.cmd, 1421 OHCI_INTERRUPT_ALWAYS); 1422 FWOHCI_DMA_CLEAR( 1423 db[ldesc].db.desc.depend, 1424 0xf); 1425 } 1426 } 1427 db_tr = STAILQ_NEXT(db_tr, link); 1428 } 1429 FWOHCI_DMA_CLEAR( 1430 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1431 dbch->buf_offset = 0; 1432 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1433 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1434 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1435 return err; 1436 }else{ 1437 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1438 } 1439 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1440 return err; 1441} 1442 1443static int 1444fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1445{ 1446 int sec, cycle, cycle_match; 1447 1448 cycle = cycle_now & 0x1fff; 1449 sec = cycle_now >> 13; 1450#define CYCLE_MOD 0x10 1451#if 1 1452#define CYCLE_DELAY 8 /* min delay to start DMA */ 1453#else 1454#define CYCLE_DELAY 7000 /* min delay to start DMA */ 1455#endif 1456 cycle = cycle + CYCLE_DELAY; 1457 if (cycle >= 8000) { 1458 sec ++; 1459 cycle -= 8000; 1460 } 1461 cycle = roundup2(cycle, CYCLE_MOD); 1462 if (cycle >= 8000) { 1463 sec ++; 1464 if (cycle == 8000) 1465 cycle = 0; 1466 else 1467 cycle = CYCLE_MOD; 1468 } 1469 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1470 1471 return(cycle_match); 1472} 1473 1474static int 1475fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1476{ 1477 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1478 int err = 0; 1479 unsigned short tag, ich; 1480 struct fwohci_dbch *dbch; 1481 int cycle_match, cycle_now, s, ldesc; 1482 u_int32_t stat; 1483 struct fw_bulkxfer *first, *chunk, *prev; 1484 struct fw_xferq *it; 1485 1486 dbch = &sc->it[dmach]; 1487 it = &dbch->xferq; 1488 1489 tag = (it->flag >> 6) & 3; 1490 ich = it->flag & 0x3f; 1491 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1492 dbch->ndb = it->bnpacket * it->bnchunk; 1493 dbch->ndesc = 3; 1494 fwohci_db_init(sc, dbch); 1495 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1496 return ENOMEM; 1497 err = fwohci_tx_enable(sc, dbch); 1498 } 1499 if(err) 1500 return err; 1501 1502 ldesc = dbch->ndesc - 1; 1503 s = splfw(); 1504 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1505 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1506 volatile struct fwohcidb *db; 1507 1508 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1509 BUS_DMASYNC_PREWRITE); 1510 fwohci_txbufdb(sc, dmach, chunk); 1511 if (prev != NULL) { 1512 db = ((struct fwohcidb_tr *)(prev->end))->db; 1513#if 0 /* XXX necessary? */ 1514 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1515 OHCI_BRANCH_ALWAYS); 1516#endif 1517#if 0 /* if bulkxfer->npacket changes */ 1518 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1519 ((struct fwohcidb_tr *) 1520 (chunk->start))->bus_addr | dbch->ndesc; 1521#else 1522 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1523 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1524#endif 1525 } 1526 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1527 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1528 prev = chunk; 1529 } 1530 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1531 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1532 splx(s); 1533 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1534 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1535 printf("stat 0x%x\n", stat); 1536 1537 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1538 return 0; 1539 1540#if 0 1541 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1542#endif 1543 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1544 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1545 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1546 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1547 1548 first = STAILQ_FIRST(&it->stdma); 1549 OWRITE(sc, OHCI_ITCMD(dmach), 1550 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1551 if (firewire_debug) { 1552 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1553#if 1 1554 dump_dma(sc, ITX_CH + dmach); 1555#endif 1556 } 1557 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1558#if 1 1559 /* Don't start until all chunks are buffered */ 1560 if (STAILQ_FIRST(&it->stfree) != NULL) 1561 goto out; 1562#endif 1563#if 1 1564 /* Clear cycle match counter bits */ 1565 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1566 1567 /* 2bit second + 13bit cycle */ 1568 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1569 cycle_match = fwohci_next_cycle(fc, cycle_now); 1570 1571 OWRITE(sc, OHCI_ITCTL(dmach), 1572 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1573 | OHCI_CNTL_DMA_RUN); 1574#else 1575 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1576#endif 1577 if (firewire_debug) { 1578 printf("cycle_match: 0x%04x->0x%04x\n", 1579 cycle_now, cycle_match); 1580 dump_dma(sc, ITX_CH + dmach); 1581 dump_db(sc, ITX_CH + dmach); 1582 } 1583 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1584 device_printf(sc->fc.dev, 1585 "IT DMA underrun (0x%08x)\n", stat); 1586 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1587 } 1588out: 1589 return err; 1590} 1591 1592static int 1593fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1594{ 1595 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1596 int err = 0, s, ldesc; 1597 unsigned short tag, ich; 1598 u_int32_t stat; 1599 struct fwohci_dbch *dbch; 1600 struct fwohcidb_tr *db_tr; 1601 struct fw_bulkxfer *first, *prev, *chunk; 1602 struct fw_xferq *ir; 1603 1604 dbch = &sc->ir[dmach]; 1605 ir = &dbch->xferq; 1606 1607 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1608 tag = (ir->flag >> 6) & 3; 1609 ich = ir->flag & 0x3f; 1610 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1611 1612 ir->queued = 0; 1613 dbch->ndb = ir->bnpacket * ir->bnchunk; 1614 dbch->ndesc = 2; 1615 fwohci_db_init(sc, dbch); 1616 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1617 return ENOMEM; 1618 err = fwohci_rx_enable(sc, dbch); 1619 } 1620 if(err) 1621 return err; 1622 1623 first = STAILQ_FIRST(&ir->stfree); 1624 if (first == NULL) { 1625 device_printf(fc->dev, "IR DMA no free chunk\n"); 1626 return 0; 1627 } 1628 1629 ldesc = dbch->ndesc - 1; 1630 s = splfw(); 1631 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1632 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1633 volatile struct fwohcidb *db; 1634 1635#if 1 /* XXX for if_fwe */ 1636 if (chunk->mbuf != NULL) { 1637 db_tr = (struct fwohcidb_tr *)(chunk->start); 1638 db_tr->dbcnt = 1; 1639 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 1640 chunk->mbuf, fwohci_execute_db2, db_tr, 1641 /* flags */0); 1642 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1643 OHCI_UPDATE | OHCI_INPUT_LAST | 1644 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1645 } 1646#endif 1647 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1648 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1649 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1650 if (prev != NULL) { 1651 db = ((struct fwohcidb_tr *)(prev->end))->db; 1652 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1653 } 1654 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1655 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1656 prev = chunk; 1657 } 1658 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1659 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1660 splx(s); 1661 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1662 if (stat & OHCI_CNTL_DMA_ACTIVE) 1663 return 0; 1664 if (stat & OHCI_CNTL_DMA_RUN) { 1665 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1666 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1667 } 1668 1669 if (firewire_debug) 1670 printf("start IR DMA 0x%x\n", stat); 1671 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1672 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1673 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1674 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1675 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1676 OWRITE(sc, OHCI_IRCMD(dmach), 1677 ((struct fwohcidb_tr *)(first->start))->bus_addr 1678 | dbch->ndesc); 1679 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1680 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1681#if 0 1682 dump_db(sc, IRX_CH + dmach); 1683#endif 1684 return err; 1685} 1686 1687int 1688fwohci_stop(struct fwohci_softc *sc, device_t dev) 1689{ 1690 u_int i; 1691 1692/* Now stopping all DMA channel */ 1693 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1694 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1695 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1696 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1697 1698 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1699 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1700 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1701 } 1702 1703/* FLUSH FIFO and reset Transmitter/Reciever */ 1704 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1705 1706/* Stop interrupt */ 1707 OWRITE(sc, FWOHCI_INTMASKCLR, 1708 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1709 | OHCI_INT_PHY_INT 1710 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1711 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1712 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1713 | OHCI_INT_PHY_BUS_R); 1714 1715 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1716 fw_drain_txq(&sc->fc); 1717 1718/* XXX Link down? Bus reset? */ 1719 return 0; 1720} 1721 1722int 1723fwohci_resume(struct fwohci_softc *sc, device_t dev) 1724{ 1725 int i; 1726 struct fw_xferq *ir; 1727 struct fw_bulkxfer *chunk; 1728 1729 fwohci_reset(sc, dev); 1730 /* XXX resume isochronus receive automatically. (how about TX?) */ 1731 for(i = 0; i < sc->fc.nisodma; i ++) { 1732 ir = &sc->ir[i].xferq; 1733 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1734 device_printf(sc->fc.dev, 1735 "resume iso receive ch: %d\n", i); 1736 ir->flag &= ~FWXFERQ_RUNNING; 1737 /* requeue stdma to stfree */ 1738 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1739 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1740 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1741 } 1742 sc->fc.irx_enable(&sc->fc, i); 1743 } 1744 } 1745 1746 bus_generic_resume(dev); 1747 sc->fc.ibr(&sc->fc); 1748 return 0; 1749} 1750 1751#define ACK_ALL 1752static void 1753fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1754{ 1755 u_int32_t irstat, itstat; 1756 u_int i; 1757 struct firewire_comm *fc = (struct firewire_comm *)sc; 1758 1759#ifdef OHCI_DEBUG 1760 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1761 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1762 stat & OHCI_INT_EN ? "DMA_EN ":"", 1763 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1764 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1765 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1766 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1767 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1768 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1769 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1770 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1771 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1772 stat & OHCI_INT_PHY_SID ? "SID ":"", 1773 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1774 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1775 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1776 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1777 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1778 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1779 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1780 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1781 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1782 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1783 stat, OREAD(sc, FWOHCI_INTMASK) 1784 ); 1785#endif 1786/* Bus reset */ 1787 if(stat & OHCI_INT_PHY_BUS_R ){ 1788 if (fc->status == FWBUSRESET) 1789 goto busresetout; 1790 /* Disable bus reset interrupt until sid recv. */ 1791 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1792 1793 device_printf(fc->dev, "BUS reset\n"); 1794 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1795 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1796 1797 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1798 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1799 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1800 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1801 1802#ifndef ACK_ALL 1803 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1804#endif 1805 fw_busreset(fc); 1806 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1807 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1808 } 1809busresetout: 1810 if((stat & OHCI_INT_DMA_IR )){ 1811#ifndef ACK_ALL 1812 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1813#endif 1814#if __FreeBSD_version >= 500000 1815 irstat = atomic_readandclear_int(&sc->irstat); 1816#else 1817 irstat = sc->irstat; 1818 sc->irstat = 0; 1819#endif 1820 for(i = 0; i < fc->nisodma ; i++){ 1821 struct fwohci_dbch *dbch; 1822 1823 if((irstat & (1 << i)) != 0){ 1824 dbch = &sc->ir[i]; 1825 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1826 device_printf(sc->fc.dev, 1827 "dma(%d) not active\n", i); 1828 continue; 1829 } 1830 fwohci_rbuf_update(sc, i); 1831 } 1832 } 1833 } 1834 if((stat & OHCI_INT_DMA_IT )){ 1835#ifndef ACK_ALL 1836 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1837#endif 1838#if __FreeBSD_version >= 500000 1839 itstat = atomic_readandclear_int(&sc->itstat); 1840#else 1841 itstat = sc->itstat; 1842 sc->itstat = 0; 1843#endif 1844 for(i = 0; i < fc->nisodma ; i++){ 1845 if((itstat & (1 << i)) != 0){ 1846 fwohci_tbuf_update(sc, i); 1847 } 1848 } 1849 } 1850 if((stat & OHCI_INT_DMA_PRRS )){ 1851#ifndef ACK_ALL 1852 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1853#endif 1854#if 0 1855 dump_dma(sc, ARRS_CH); 1856 dump_db(sc, ARRS_CH); 1857#endif 1858 fwohci_arcv(sc, &sc->arrs, count); 1859 } 1860 if((stat & OHCI_INT_DMA_PRRQ )){ 1861#ifndef ACK_ALL 1862 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1863#endif 1864#if 0 1865 dump_dma(sc, ARRQ_CH); 1866 dump_db(sc, ARRQ_CH); 1867#endif 1868 fwohci_arcv(sc, &sc->arrq, count); 1869 } 1870 if(stat & OHCI_INT_PHY_SID){ 1871 u_int32_t *buf, node_id; 1872 int plen; 1873 1874#ifndef ACK_ALL 1875 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1876#endif 1877 /* Enable bus reset interrupt */ 1878 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1879 /* Allow async. request to us */ 1880 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1881 /* XXX insecure ?? */ 1882 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1883 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1884 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1885 /* Set ATRetries register */ 1886 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1887/* 1888** Checking whether the node is root or not. If root, turn on 1889** cycle master. 1890*/ 1891 node_id = OREAD(sc, FWOHCI_NODEID); 1892 plen = OREAD(sc, OHCI_SID_CNT); 1893 1894 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 1895 node_id, (plen >> 16) & 0xff); 1896 if (!(node_id & OHCI_NODE_VALID)) { 1897 printf("Bus reset failure\n"); 1898 goto sidout; 1899 } 1900 if (node_id & OHCI_NODE_ROOT) { 1901 printf("CYCLEMASTER mode\n"); 1902 OWRITE(sc, OHCI_LNKCTL, 1903 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1904 } else { 1905 printf("non CYCLEMASTER mode\n"); 1906 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1907 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1908 } 1909 fc->nodeid = node_id & 0x3f; 1910 1911 if (plen & OHCI_SID_ERR) { 1912 device_printf(fc->dev, "SID Error\n"); 1913 goto sidout; 1914 } 1915 plen &= OHCI_SID_CNT_MASK; 1916 if (plen < 4 || plen > OHCI_SIDSIZE) { 1917 device_printf(fc->dev, "invalid SID len = %d\n", plen); 1918 goto sidout; 1919 } 1920 plen -= 4; /* chop control info */ 1921 buf = (u_int32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1922 if (buf == NULL) { 1923 device_printf(fc->dev, "malloc failed\n"); 1924 goto sidout; 1925 } 1926 for (i = 0; i < plen / 4; i ++) 1927 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 1928#if 1 1929 /* pending all pre-bus_reset packets */ 1930 fwohci_txd(sc, &sc->atrq); 1931 fwohci_txd(sc, &sc->atrs); 1932 fwohci_arcv(sc, &sc->arrs, -1); 1933 fwohci_arcv(sc, &sc->arrq, -1); 1934 fw_drain_txq(fc); 1935#endif 1936 fw_sidrcv(fc, buf, plen); 1937 free(buf, M_FW); 1938 } 1939sidout: 1940 if((stat & OHCI_INT_DMA_ATRQ )){ 1941#ifndef ACK_ALL 1942 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1943#endif 1944 fwohci_txd(sc, &(sc->atrq)); 1945 } 1946 if((stat & OHCI_INT_DMA_ATRS )){ 1947#ifndef ACK_ALL 1948 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1949#endif 1950 fwohci_txd(sc, &(sc->atrs)); 1951 } 1952 if((stat & OHCI_INT_PW_ERR )){ 1953#ifndef ACK_ALL 1954 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1955#endif 1956 device_printf(fc->dev, "posted write error\n"); 1957 } 1958 if((stat & OHCI_INT_ERR )){ 1959#ifndef ACK_ALL 1960 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1961#endif 1962 device_printf(fc->dev, "unrecoverable error\n"); 1963 } 1964 if((stat & OHCI_INT_PHY_INT)) { 1965#ifndef ACK_ALL 1966 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1967#endif 1968 device_printf(fc->dev, "phy int\n"); 1969 } 1970 1971 return; 1972} 1973 1974#if FWOHCI_TASKQUEUE 1975static void 1976fwohci_complete(void *arg, int pending) 1977{ 1978 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1979 u_int32_t stat; 1980 1981again: 1982 stat = atomic_readandclear_int(&sc->intstat); 1983 if (stat) 1984 fwohci_intr_body(sc, stat, -1); 1985 else 1986 return; 1987 goto again; 1988} 1989#endif 1990 1991static u_int32_t 1992fwochi_check_stat(struct fwohci_softc *sc) 1993{ 1994 u_int32_t stat, irstat, itstat; 1995 1996 stat = OREAD(sc, FWOHCI_INTSTAT); 1997 if (stat == 0xffffffff) { 1998 device_printf(sc->fc.dev, 1999 "device physically ejected?\n"); 2000 return(stat); 2001 } 2002#ifdef ACK_ALL 2003 if (stat) 2004 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2005#endif 2006 if (stat & OHCI_INT_DMA_IR) { 2007 irstat = OREAD(sc, OHCI_IR_STAT); 2008 OWRITE(sc, OHCI_IR_STATCLR, irstat); 2009 atomic_set_int(&sc->irstat, irstat); 2010 } 2011 if (stat & OHCI_INT_DMA_IT) { 2012 itstat = OREAD(sc, OHCI_IT_STAT); 2013 OWRITE(sc, OHCI_IT_STATCLR, itstat); 2014 atomic_set_int(&sc->itstat, itstat); 2015 } 2016 return(stat); 2017} 2018 2019void 2020fwohci_intr(void *arg) 2021{ 2022 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2023 u_int32_t stat; 2024#if !FWOHCI_TASKQUEUE 2025 u_int32_t bus_reset = 0; 2026#endif 2027 2028 if (!(sc->intmask & OHCI_INT_EN)) { 2029 /* polling mode */ 2030 return; 2031 } 2032 2033#if !FWOHCI_TASKQUEUE 2034again: 2035#endif 2036 stat = fwochi_check_stat(sc); 2037 if (stat == 0 || stat == 0xffffffff) 2038 return; 2039#if FWOHCI_TASKQUEUE 2040 atomic_set_int(&sc->intstat, stat); 2041 /* XXX mask bus reset intr. during bus reset phase */ 2042 if (stat) 2043 taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete); 2044#else 2045 /* We cannot clear bus reset event during bus reset phase */ 2046 if ((stat & ~bus_reset) == 0) 2047 return; 2048 bus_reset = stat & OHCI_INT_PHY_BUS_R; 2049 fwohci_intr_body(sc, stat, -1); 2050 goto again; 2051#endif 2052} 2053 2054void 2055fwohci_poll(struct firewire_comm *fc, int quick, int count) 2056{ 2057 int s; 2058 u_int32_t stat; 2059 struct fwohci_softc *sc; 2060 2061 2062 sc = (struct fwohci_softc *)fc; 2063 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2064 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2065 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2066#if 0 2067 if (!quick) { 2068#else 2069 if (1) { 2070#endif 2071 stat = fwochi_check_stat(sc); 2072 if (stat == 0 || stat == 0xffffffff) 2073 return; 2074 } 2075 s = splfw(); 2076 fwohci_intr_body(sc, stat, count); 2077 splx(s); 2078} 2079 2080static void 2081fwohci_set_intr(struct firewire_comm *fc, int enable) 2082{ 2083 struct fwohci_softc *sc; 2084 2085 sc = (struct fwohci_softc *)fc; 2086 if (bootverbose) 2087 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2088 if (enable) { 2089 sc->intmask |= OHCI_INT_EN; 2090 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2091 } else { 2092 sc->intmask &= ~OHCI_INT_EN; 2093 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2094 } 2095} 2096 2097static void 2098fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2099{ 2100 struct firewire_comm *fc = &sc->fc; 2101 volatile struct fwohcidb *db; 2102 struct fw_bulkxfer *chunk; 2103 struct fw_xferq *it; 2104 u_int32_t stat, count; 2105 int s, w=0, ldesc; 2106 2107 it = fc->it[dmach]; 2108 ldesc = sc->it[dmach].ndesc - 1; 2109 s = splfw(); /* unnecessary ? */ 2110 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2111 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2112 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2113 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2114 >> OHCI_STATUS_SHIFT; 2115 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2116 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2117 & OHCI_COUNT_MASK; 2118 if (stat == 0) 2119 break; 2120 STAILQ_REMOVE_HEAD(&it->stdma, link); 2121 switch (stat & FWOHCIEV_MASK){ 2122 case FWOHCIEV_ACKCOMPL: 2123#if 0 2124 device_printf(fc->dev, "0x%08x\n", count); 2125#endif 2126 break; 2127 default: 2128 device_printf(fc->dev, 2129 "Isochronous transmit err %02x(%s)\n", 2130 stat, fwohcicode[stat & 0x1f]); 2131 } 2132 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2133 w++; 2134 } 2135 splx(s); 2136 if (w) 2137 wakeup(it); 2138} 2139 2140static void 2141fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2142{ 2143 struct firewire_comm *fc = &sc->fc; 2144 volatile struct fwohcidb_tr *db_tr; 2145 struct fw_bulkxfer *chunk; 2146 struct fw_xferq *ir; 2147 u_int32_t stat; 2148 int s, w=0, ldesc; 2149 2150 ir = fc->ir[dmach]; 2151 ldesc = sc->ir[dmach].ndesc - 1; 2152#if 0 2153 dump_db(sc, dmach); 2154#endif 2155 s = splfw(); 2156 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2157 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2158 db_tr = (struct fwohcidb_tr *)chunk->end; 2159 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2160 >> OHCI_STATUS_SHIFT; 2161 if (stat == 0) 2162 break; 2163 2164 if (chunk->mbuf != NULL) { 2165 bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2166 BUS_DMASYNC_POSTREAD); 2167 bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 2168 } else if (ir->buf != NULL) { 2169 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2170 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2171 } else { 2172 /* XXX */ 2173 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2174 } 2175 2176 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2177 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2178 switch (stat & FWOHCIEV_MASK) { 2179 case FWOHCIEV_ACKCOMPL: 2180 chunk->resp = 0; 2181 break; 2182 default: 2183 chunk->resp = EINVAL; 2184 device_printf(fc->dev, 2185 "Isochronous receive err %02x(%s)\n", 2186 stat, fwohcicode[stat & 0x1f]); 2187 } 2188 w++; 2189 } 2190 splx(s); 2191 if (w) { 2192 if (ir->flag & FWXFERQ_HANDLER) 2193 ir->hand(ir); 2194 else 2195 wakeup(ir); 2196 } 2197} 2198 2199void 2200dump_dma(struct fwohci_softc *sc, u_int32_t ch) 2201{ 2202 u_int32_t off, cntl, stat, cmd, match; 2203 2204 if(ch == 0){ 2205 off = OHCI_ATQOFF; 2206 }else if(ch == 1){ 2207 off = OHCI_ATSOFF; 2208 }else if(ch == 2){ 2209 off = OHCI_ARQOFF; 2210 }else if(ch == 3){ 2211 off = OHCI_ARSOFF; 2212 }else if(ch < IRX_CH){ 2213 off = OHCI_ITCTL(ch - ITX_CH); 2214 }else{ 2215 off = OHCI_IRCTL(ch - IRX_CH); 2216 } 2217 cntl = stat = OREAD(sc, off); 2218 cmd = OREAD(sc, off + 0xc); 2219 match = OREAD(sc, off + 0x10); 2220 2221 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2222 ch, 2223 cntl, 2224 cmd, 2225 match); 2226 stat &= 0xffff ; 2227 if (stat) { 2228 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2229 ch, 2230 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2231 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2232 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2233 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2234 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2235 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2236 fwohcicode[stat & 0x1f], 2237 stat & 0x1f 2238 ); 2239 }else{ 2240 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2241 } 2242} 2243 2244void 2245dump_db(struct fwohci_softc *sc, u_int32_t ch) 2246{ 2247 struct fwohci_dbch *dbch; 2248 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2249 volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2250 int idb, jdb; 2251 u_int32_t cmd, off; 2252 if(ch == 0){ 2253 off = OHCI_ATQOFF; 2254 dbch = &sc->atrq; 2255 }else if(ch == 1){ 2256 off = OHCI_ATSOFF; 2257 dbch = &sc->atrs; 2258 }else if(ch == 2){ 2259 off = OHCI_ARQOFF; 2260 dbch = &sc->arrq; 2261 }else if(ch == 3){ 2262 off = OHCI_ARSOFF; 2263 dbch = &sc->arrs; 2264 }else if(ch < IRX_CH){ 2265 off = OHCI_ITCTL(ch - ITX_CH); 2266 dbch = &sc->it[ch - ITX_CH]; 2267 }else { 2268 off = OHCI_IRCTL(ch - IRX_CH); 2269 dbch = &sc->ir[ch - IRX_CH]; 2270 } 2271 cmd = OREAD(sc, off + 0xc); 2272 2273 if( dbch->ndb == 0 ){ 2274 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2275 return; 2276 } 2277 pp = dbch->top; 2278 prev = pp->db; 2279 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2280 if(pp == NULL){ 2281 curr = NULL; 2282 goto outdb; 2283 } 2284 cp = STAILQ_NEXT(pp, link); 2285 if(cp == NULL){ 2286 curr = NULL; 2287 goto outdb; 2288 } 2289 np = STAILQ_NEXT(cp, link); 2290 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2291 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2292 curr = cp->db; 2293 if(np != NULL){ 2294 next = np->db; 2295 }else{ 2296 next = NULL; 2297 } 2298 goto outdb; 2299 } 2300 } 2301 pp = STAILQ_NEXT(pp, link); 2302 prev = pp->db; 2303 } 2304outdb: 2305 if( curr != NULL){ 2306#if 0 2307 printf("Prev DB %d\n", ch); 2308 print_db(pp, prev, ch, dbch->ndesc); 2309#endif 2310 printf("Current DB %d\n", ch); 2311 print_db(cp, curr, ch, dbch->ndesc); 2312#if 0 2313 printf("Next DB %d\n", ch); 2314 print_db(np, next, ch, dbch->ndesc); 2315#endif 2316 }else{ 2317 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2318 } 2319 return; 2320} 2321 2322void 2323print_db(struct fwohcidb_tr *db_tr, volatile struct fwohcidb *db, 2324 u_int32_t ch, u_int32_t max) 2325{ 2326 fwohcireg_t stat; 2327 int i, key; 2328 u_int32_t cmd, res; 2329 2330 if(db == NULL){ 2331 printf("No Descriptor is found\n"); 2332 return; 2333 } 2334 2335 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2336 ch, 2337 "Current", 2338 "OP ", 2339 "KEY", 2340 "INT", 2341 "BR ", 2342 "len", 2343 "Addr", 2344 "Depend", 2345 "Stat", 2346 "Cnt"); 2347 for( i = 0 ; i <= max ; i ++){ 2348 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2349 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2350 key = cmd & OHCI_KEY_MASK; 2351 stat = res >> OHCI_STATUS_SHIFT; 2352#if __FreeBSD_version >= 500000 2353 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2354 (uintmax_t)db_tr->bus_addr, 2355#else 2356 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2357 db_tr->bus_addr, 2358#endif 2359 dbcode[(cmd >> 28) & 0xf], 2360 dbkey[(cmd >> 24) & 0x7], 2361 dbcond[(cmd >> 20) & 0x3], 2362 dbcond[(cmd >> 18) & 0x3], 2363 cmd & OHCI_COUNT_MASK, 2364 FWOHCI_DMA_READ(db[i].db.desc.addr), 2365 FWOHCI_DMA_READ(db[i].db.desc.depend), 2366 stat, 2367 res & OHCI_COUNT_MASK); 2368 if(stat & 0xff00){ 2369 printf(" %s%s%s%s%s%s %s(%x)\n", 2370 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2371 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2372 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2373 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2374 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2375 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2376 fwohcicode[stat & 0x1f], 2377 stat & 0x1f 2378 ); 2379 }else{ 2380 printf(" Nostat\n"); 2381 } 2382 if(key == OHCI_KEY_ST2 ){ 2383 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2384 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2385 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2386 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2387 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2388 } 2389 if(key == OHCI_KEY_DEVICE){ 2390 return; 2391 } 2392 if((cmd & OHCI_BRANCH_MASK) 2393 == OHCI_BRANCH_ALWAYS){ 2394 return; 2395 } 2396 if((cmd & OHCI_CMD_MASK) 2397 == OHCI_OUTPUT_LAST){ 2398 return; 2399 } 2400 if((cmd & OHCI_CMD_MASK) 2401 == OHCI_INPUT_LAST){ 2402 return; 2403 } 2404 if(key == OHCI_KEY_ST2 ){ 2405 i++; 2406 } 2407 } 2408 return; 2409} 2410 2411void 2412fwohci_ibr(struct firewire_comm *fc) 2413{ 2414 struct fwohci_softc *sc; 2415 u_int32_t fun; 2416 2417 device_printf(fc->dev, "Initiate bus reset\n"); 2418 sc = (struct fwohci_softc *)fc; 2419 2420 /* 2421 * Set root hold-off bit so that non cyclemaster capable node 2422 * shouldn't became the root node. 2423 */ 2424#if 1 2425 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2426 fun |= FW_PHY_IBR | FW_PHY_RHB; 2427 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2428#else /* Short bus reset */ 2429 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2430 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2431 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2432#endif 2433} 2434 2435void 2436fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2437{ 2438 struct fwohcidb_tr *db_tr, *fdb_tr; 2439 struct fwohci_dbch *dbch; 2440 volatile struct fwohcidb *db; 2441 struct fw_pkt *fp; 2442 volatile struct fwohci_txpkthdr *ohcifp; 2443 unsigned short chtag; 2444 int idb; 2445 2446 dbch = &sc->it[dmach]; 2447 chtag = sc->it[dmach].xferq.flag & 0xff; 2448 2449 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2450 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2451/* 2452device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2453*/ 2454 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2455 db = db_tr->db; 2456 fp = (struct fw_pkt *)db_tr->buf; 2457 ohcifp = (volatile struct fwohci_txpkthdr *) db[1].db.immed; 2458 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2459 ohcifp->mode.stream.len = fp->mode.stream.len; 2460 ohcifp->mode.stream.chtag = chtag; 2461 ohcifp->mode.stream.tcode = 0xa; 2462 ohcifp->mode.stream.spd = 0; 2463#if BYTE_ORDER == BIG_ENDIAN 2464 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2465 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2466#endif 2467 2468 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2469 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2470 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2471#if 0 /* if bulkxfer->npackets changes */ 2472 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2473 | OHCI_UPDATE 2474 | OHCI_BRANCH_ALWAYS; 2475 db[0].db.desc.depend = 2476 = db[dbch->ndesc - 1].db.desc.depend 2477 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2478#else 2479 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2480 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2481#endif 2482 bulkxfer->end = (caddr_t)db_tr; 2483 db_tr = STAILQ_NEXT(db_tr, link); 2484 } 2485 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2486 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2487 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2488#if 0 /* if bulkxfer->npackets changes */ 2489 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2490 /* OHCI 1.1 and above */ 2491 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2492#endif 2493/* 2494 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2495 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2496device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2497*/ 2498 return; 2499} 2500 2501static int 2502fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2503 int poffset) 2504{ 2505 volatile struct fwohcidb *db = db_tr->db; 2506 struct fw_xferq *it; 2507 int err = 0; 2508 2509 it = &dbch->xferq; 2510 if(it->buf == 0){ 2511 err = EINVAL; 2512 return err; 2513 } 2514 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2515 db_tr->dbcnt = 3; 2516 2517 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2518 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2519 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2520 fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t)); 2521 2522 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2523 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2524#if 1 2525 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2526 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2527#endif 2528 return 0; 2529} 2530 2531int 2532fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2533 int poffset, struct fwdma_alloc *dummy_dma) 2534{ 2535 volatile struct fwohcidb *db = db_tr->db; 2536 struct fw_xferq *ir; 2537 int i, ldesc; 2538 bus_addr_t dbuf[2]; 2539 int dsiz[2]; 2540 2541 ir = &dbch->xferq; 2542 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2543 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2544 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2545 if (db_tr->buf == NULL) 2546 return(ENOMEM); 2547 db_tr->dbcnt = 1; 2548 dsiz[0] = ir->psize; 2549 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2550 BUS_DMASYNC_PREREAD); 2551 } else { 2552 db_tr->dbcnt = 0; 2553 if (dummy_dma != NULL) { 2554 dsiz[db_tr->dbcnt] = sizeof(u_int32_t); 2555 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2556 } 2557 dsiz[db_tr->dbcnt] = ir->psize; 2558 if (ir->buf != NULL) { 2559 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2560 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2561 } 2562 db_tr->dbcnt++; 2563 } 2564 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2565 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2566 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2567 if (ir->flag & FWXFERQ_STREAM) { 2568 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2569 } 2570 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2571 } 2572 ldesc = db_tr->dbcnt - 1; 2573 if (ir->flag & FWXFERQ_STREAM) { 2574 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2575 } 2576 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2577 return 0; 2578} 2579 2580 2581static int 2582fwohci_arcv_swap(struct fw_pkt *fp, int len) 2583{ 2584 struct fw_pkt *fp0; 2585 u_int32_t ld0; 2586 int slen; 2587#if BYTE_ORDER == BIG_ENDIAN 2588 int i; 2589#endif 2590 2591 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2592#if 0 2593 printf("ld0: x%08x\n", ld0); 2594#endif 2595 fp0 = (struct fw_pkt *)&ld0; 2596 switch (fp0->mode.common.tcode) { 2597 case FWTCODE_RREQQ: 2598 case FWTCODE_WRES: 2599 case FWTCODE_WREQQ: 2600 case FWTCODE_RRESQ: 2601 case FWOHCITCODE_PHY: 2602 slen = 12; 2603 break; 2604 case FWTCODE_RREQB: 2605 case FWTCODE_WREQB: 2606 case FWTCODE_LREQ: 2607 case FWTCODE_RRESB: 2608 case FWTCODE_LRES: 2609 slen = 16; 2610 break; 2611 default: 2612 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2613 return(0); 2614 } 2615 if (slen > len) { 2616 if (firewire_debug) 2617 printf("splitted header\n"); 2618 return(-slen); 2619 } 2620#if BYTE_ORDER == BIG_ENDIAN 2621 for(i = 0; i < slen/4; i ++) 2622 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2623#endif 2624 return(slen); 2625} 2626 2627#define PLEN(x) roundup2(x, sizeof(u_int32_t)) 2628static int 2629fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2630{ 2631 int r; 2632 2633 switch(fp->mode.common.tcode){ 2634 case FWTCODE_RREQQ: 2635 r = sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2636 break; 2637 case FWTCODE_WRES: 2638 r = sizeof(fp->mode.wres) + sizeof(u_int32_t); 2639 break; 2640 case FWTCODE_WREQQ: 2641 r = sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2642 break; 2643 case FWTCODE_RREQB: 2644 r = sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2645 break; 2646 case FWTCODE_RRESQ: 2647 r = sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2648 break; 2649 case FWTCODE_WREQB: 2650 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2651 + sizeof(u_int32_t); 2652 break; 2653 case FWTCODE_LREQ: 2654 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2655 + sizeof(u_int32_t); 2656 break; 2657 case FWTCODE_RRESB: 2658 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2659 + sizeof(u_int32_t); 2660 break; 2661 case FWTCODE_LRES: 2662 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2663 + sizeof(u_int32_t); 2664 break; 2665 case FWOHCITCODE_PHY: 2666 r = 16; 2667 break; 2668 default: 2669 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2670 fp->mode.common.tcode); 2671 r = 0; 2672 } 2673 if (r > dbch->xferq.psize) { 2674 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2675 /* panic ? */ 2676 } 2677 return r; 2678} 2679 2680static void 2681fwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr) 2682{ 2683 volatile struct fwohcidb *db = &db_tr->db[0]; 2684 2685 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2686 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2687 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2688 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 2689 dbch->bottom = db_tr; 2690} 2691 2692static void 2693fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2694{ 2695 struct fwohcidb_tr *db_tr; 2696 struct iovec vec[2]; 2697 struct fw_pkt pktbuf; 2698 int nvec; 2699 struct fw_pkt *fp; 2700 u_int8_t *ld; 2701 u_int32_t stat, off, status; 2702 u_int spd; 2703 int len, plen, hlen, pcnt, offset; 2704 int s; 2705 caddr_t buf; 2706 int resCount; 2707 2708 if(&sc->arrq == dbch){ 2709 off = OHCI_ARQOFF; 2710 }else if(&sc->arrs == dbch){ 2711 off = OHCI_ARSOFF; 2712 }else{ 2713 return; 2714 } 2715 2716 s = splfw(); 2717 db_tr = dbch->top; 2718 pcnt = 0; 2719 /* XXX we cannot handle a packet which lies in more than two buf */ 2720 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 2721 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 2722 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2723 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2724#if 0 2725 printf("status 0x%04x, resCount 0x%04x\n", status, resCount); 2726#endif 2727 while (status & OHCI_CNTL_DMA_ACTIVE) { 2728 len = dbch->xferq.psize - resCount; 2729 ld = (u_int8_t *)db_tr->buf; 2730 if (dbch->pdb_tr == NULL) { 2731 len -= dbch->buf_offset; 2732 ld += dbch->buf_offset; 2733 } 2734 if (len > 0) 2735 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2736 BUS_DMASYNC_POSTREAD); 2737 while (len > 0 ) { 2738 if (count >= 0 && count-- == 0) 2739 goto out; 2740 if(dbch->pdb_tr != NULL){ 2741 /* we have a fragment in previous buffer */ 2742 int rlen; 2743 2744 offset = dbch->buf_offset; 2745 if (offset < 0) 2746 offset = - offset; 2747 buf = dbch->pdb_tr->buf + offset; 2748 rlen = dbch->xferq.psize - offset; 2749 if (firewire_debug) 2750 printf("rlen=%d, offset=%d\n", 2751 rlen, dbch->buf_offset); 2752 if (dbch->buf_offset < 0) { 2753 /* splitted in header, pull up */ 2754 char *p; 2755 2756 p = (char *)&pktbuf; 2757 bcopy(buf, p, rlen); 2758 p += rlen; 2759 /* this must be too long but harmless */ 2760 rlen = sizeof(pktbuf) - rlen; 2761 if (rlen < 0) 2762 printf("why rlen < 0\n"); 2763 bcopy(db_tr->buf, p, rlen); 2764 ld += rlen; 2765 len -= rlen; 2766 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2767 if (hlen < 0) { 2768 printf("hlen < 0 shouldn't happen"); 2769 } 2770 offset = sizeof(pktbuf); 2771 vec[0].iov_base = (char *)&pktbuf; 2772 vec[0].iov_len = offset; 2773 } else { 2774 /* splitted in payload */ 2775 offset = rlen; 2776 vec[0].iov_base = buf; 2777 vec[0].iov_len = rlen; 2778 } 2779 fp=(struct fw_pkt *)vec[0].iov_base; 2780 nvec = 1; 2781 } else { 2782 /* no fragment in previous buffer */ 2783 fp=(struct fw_pkt *)ld; 2784 hlen = fwohci_arcv_swap(fp, len); 2785 if (hlen == 0) 2786 /* XXX need reset */ 2787 goto out; 2788 if (hlen < 0) { 2789 dbch->pdb_tr = db_tr; 2790 dbch->buf_offset = - dbch->buf_offset; 2791 /* sanity check */ 2792 if (resCount != 0) 2793 printf("resCount != 0 !?\n"); 2794 goto out; 2795 } 2796 offset = 0; 2797 nvec = 0; 2798 } 2799 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2800 if (plen < 0) { 2801 /* minimum header size + trailer 2802 = sizeof(fw_pkt) so this shouldn't happens */ 2803 printf("plen is negative! offset=%d\n", offset); 2804 goto out; 2805 } 2806 if (plen > 0) { 2807 len -= plen; 2808 if (len < 0) { 2809 dbch->pdb_tr = db_tr; 2810 if (firewire_debug) 2811 printf("splitted payload\n"); 2812 /* sanity check */ 2813 if (resCount != 0) 2814 printf("resCount != 0 !?\n"); 2815 goto out; 2816 } 2817 vec[nvec].iov_base = ld; 2818 vec[nvec].iov_len = plen; 2819 nvec ++; 2820 ld += plen; 2821 } 2822 dbch->buf_offset = ld - (u_int8_t *)db_tr->buf; 2823 if (nvec == 0) 2824 printf("nvec == 0\n"); 2825 2826/* DMA result-code will be written at the tail of packet */ 2827#if BYTE_ORDER == BIG_ENDIAN 2828 stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16; 2829#else 2830 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2831#endif 2832#if 0 2833 printf("plen: %d, stat %x\n", plen ,stat); 2834#endif 2835 spd = (stat >> 5) & 0x3; 2836 stat &= 0x1f; 2837 switch(stat){ 2838 case FWOHCIEV_ACKPEND: 2839#if 0 2840 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2841#endif 2842 /* fall through */ 2843 case FWOHCIEV_ACKCOMPL: 2844 if ((vec[nvec-1].iov_len -= 2845 sizeof(struct fwohci_trailer)) == 0) 2846 nvec--; 2847 fw_rcv(&sc->fc, vec, nvec, 0, spd); 2848 break; 2849 case FWOHCIEV_BUSRST: 2850 if (sc->fc.status != FWBUSRESET) 2851 printf("got BUSRST packet!?\n"); 2852 break; 2853 default: 2854 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2855#if 0 /* XXX */ 2856 goto out; 2857#endif 2858 break; 2859 } 2860 pcnt ++; 2861 if (dbch->pdb_tr != NULL) { 2862 fwohci_arcv_free_buf(dbch, dbch->pdb_tr); 2863 dbch->pdb_tr = NULL; 2864 } 2865 2866 } 2867out: 2868 if (resCount == 0) { 2869 /* done on this buffer */ 2870 if (dbch->pdb_tr == NULL) { 2871 fwohci_arcv_free_buf(dbch, db_tr); 2872 dbch->buf_offset = 0; 2873 } else 2874 if (dbch->pdb_tr != db_tr) 2875 printf("pdb_tr != db_tr\n"); 2876 db_tr = STAILQ_NEXT(db_tr, link); 2877 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2878 >> OHCI_STATUS_SHIFT; 2879 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2880 & OHCI_COUNT_MASK; 2881 /* XXX check buffer overrun */ 2882 dbch->top = db_tr; 2883 } else { 2884 dbch->buf_offset = dbch->xferq.psize - resCount; 2885 break; 2886 } 2887 /* XXX make sure DMA is not dead */ 2888 } 2889#if 0 2890 if (pcnt < 1) 2891 printf("fwohci_arcv: no packets\n"); 2892#endif 2893 splx(s); 2894} 2895