fwohci.c revision 109179
1103285Sikob/* 2103285Sikob * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 3103285Sikob * All rights reserved. 4103285Sikob * 5103285Sikob * Redistribution and use in source and binary forms, with or without 6103285Sikob * modification, are permitted provided that the following conditions 7103285Sikob * are met: 8103285Sikob * 1. Redistributions of source code must retain the above copyright 9103285Sikob * notice, this list of conditions and the following disclaimer. 10103285Sikob * 2. Redistributions in binary form must reproduce the above copyright 11103285Sikob * notice, this list of conditions and the following disclaimer in the 12103285Sikob * documentation and/or other materials provided with the distribution. 13103285Sikob * 3. All advertising materials mentioning features or use of this software 14103285Sikob * must display the acknowledgement as bellow: 15103285Sikob * 16106802Ssimokawa * This product includes software developed by K. Kobayashi and H. Shimokawa 17103285Sikob * 18103285Sikob * 4. The name of the author may not be used to endorse or promote products 19103285Sikob * derived from this software without specific prior written permission. 20103285Sikob * 21103285Sikob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22103285Sikob * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23103285Sikob * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24103285Sikob * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25103285Sikob * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26103285Sikob * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27103285Sikob * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28103285Sikob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29103285Sikob * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30103285Sikob * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31103285Sikob * POSSIBILITY OF SUCH DAMAGE. 32103285Sikob * 33103285Sikob * $FreeBSD: head/sys/dev/firewire/fwohci.c 109179 2003-01-13 16:08:09Z simokawa $ 34103285Sikob * 35103285Sikob */ 36106802Ssimokawa 37103285Sikob#define ATRQ_CH 0 38103285Sikob#define ATRS_CH 1 39103285Sikob#define ARRQ_CH 2 40103285Sikob#define ARRS_CH 3 41103285Sikob#define ITX_CH 4 42103285Sikob#define IRX_CH 0x24 43103285Sikob 44103285Sikob#include <sys/param.h> 45103285Sikob#include <sys/systm.h> 46103285Sikob#include <sys/types.h> 47103285Sikob#include <sys/mbuf.h> 48103285Sikob#include <sys/mman.h> 49103285Sikob#include <sys/socket.h> 50103285Sikob#include <sys/socketvar.h> 51103285Sikob#include <sys/signalvar.h> 52103285Sikob#include <sys/malloc.h> 53103285Sikob#include <sys/uio.h> 54103285Sikob#include <sys/sockio.h> 55103285Sikob#include <sys/bus.h> 56103285Sikob#include <sys/kernel.h> 57103285Sikob#include <sys/conf.h> 58103285Sikob 59103285Sikob#include <machine/bus.h> 60103285Sikob#include <machine/resource.h> 61103285Sikob#include <sys/rman.h> 62103285Sikob 63103285Sikob#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 64103285Sikob#include <machine/clock.h> 65103285Sikob#include <pci/pcivar.h> 66103285Sikob#include <pci/pcireg.h> 67103285Sikob#include <vm/vm.h> 68103285Sikob#include <vm/vm_extern.h> 69103285Sikob#include <vm/pmap.h> /* for vtophys proto */ 70103285Sikob 71103285Sikob#include <dev/firewire/firewire.h> 72103285Sikob#include <dev/firewire/firewirereg.h> 73103285Sikob#include <dev/firewire/fwohcireg.h> 74103285Sikob#include <dev/firewire/fwohcivar.h> 75103285Sikob#include <dev/firewire/firewire_phy.h> 76103285Sikob 77109179Ssimokawa#include <dev/firewire/iec68113.h> 78109179Ssimokawa 79103285Sikob#undef OHCI_DEBUG 80106802Ssimokawa 81103285Sikobstatic char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 82103285Sikob "STOR","LOAD","NOP ","STOP",}; 83103285Sikobstatic char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 84103285Sikob "UNDEF","REG","SYS","DEV"}; 85103285Sikobchar fwohcicode[32][0x20]={ 86103285Sikob "No stat","Undef","long","miss Ack err", 87103285Sikob "underrun","overrun","desc err", "data read err", 88103285Sikob "data write err","bus reset","timeout","tcode err", 89103285Sikob "Undef","Undef","unknown event","flushed", 90103285Sikob "Undef","ack complete","ack pend","Undef", 91103285Sikob "ack busy_X","ack busy_A","ack busy_B","Undef", 92103285Sikob "Undef","Undef","Undef","ack tardy", 93103285Sikob "Undef","ack data_err","ack type_err",""}; 94103285Sikob#define MAX_SPEED 2 95103285Sikobextern char linkspeed[MAX_SPEED+1][0x10]; 96103285Sikobstatic char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 97103285Sikobu_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 98103285Sikob 99103285Sikobstatic struct tcode_info tinfo[] = { 100103285Sikob/* hdr_len block flag*/ 101103285Sikob/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 102103285Sikob/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 103103285Sikob/* 2 WRES */ {12, FWTI_RES}, 104103285Sikob/* 3 XXX */ { 0, 0}, 105103285Sikob/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 106103285Sikob/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 107103285Sikob/* 6 RRESQ */ {16, FWTI_RES}, 108103285Sikob/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 109103285Sikob/* 8 CYCS */ { 0, 0}, 110103285Sikob/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 111103285Sikob/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 112103285Sikob/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 113103285Sikob/* c XXX */ { 0, 0}, 114103285Sikob/* d XXX */ { 0, 0}, 115103285Sikob/* e PHY */ {12, FWTI_REQ}, 116103285Sikob/* f XXX */ { 0, 0} 117103285Sikob}; 118103285Sikob 119103285Sikob#define OHCI_WRITE_SIGMASK 0xffff0000 120103285Sikob#define OHCI_READ_SIGMASK 0xffff0000 121103285Sikob 122103285Sikob#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 123103285Sikob#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 124103285Sikob 125103285Sikobstatic void fwohci_ibr __P((struct firewire_comm *)); 126103285Sikobstatic void fwohci_db_init __P((struct fwohci_dbch *)); 127103285Sikobstatic void fwohci_db_free __P((struct fwohci_dbch *)); 128106789Ssimokawastatic void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 129106789Ssimokawastatic void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 130103285Sikobstatic void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 131103285Sikobstatic void fwohci_start_atq __P((struct firewire_comm *)); 132103285Sikobstatic void fwohci_start_ats __P((struct firewire_comm *)); 133103285Sikobstatic void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 134103285Sikobstatic void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *)); 135103285Sikobstatic void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *)); 136103285Sikobstatic void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *)); 137103285Sikobstatic u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 138103285Sikobstatic u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 139103285Sikobstatic int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 140103285Sikobstatic int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 141103285Sikobstatic int fwohci_irx_enable __P((struct firewire_comm *, int)); 142103285Sikobstatic int fwohci_irxpp_enable __P((struct firewire_comm *, int)); 143103285Sikobstatic int fwohci_irxbuf_enable __P((struct firewire_comm *, int)); 144103285Sikobstatic int fwohci_irx_disable __P((struct firewire_comm *, int)); 145103285Sikobstatic void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 146103285Sikobstatic int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 147103285Sikobstatic int fwohci_itx_disable __P((struct firewire_comm *, int)); 148103285Sikobstatic void fwohci_timeout __P((void *)); 149103285Sikobstatic void fwohci_poll __P((struct firewire_comm *, int, int)); 150103285Sikobstatic void fwohci_set_intr __P((struct firewire_comm *, int)); 151103285Sikobstatic int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *)); 152103285Sikobstatic int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *)); 153103285Sikobstatic void dump_db __P((struct fwohci_softc *, u_int32_t)); 154103285Sikobstatic void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t)); 155103285Sikobstatic void dump_dma __P((struct fwohci_softc *, u_int32_t)); 156103285Sikobstatic u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 157103285Sikobstatic void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 158103285Sikobstatic void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 159103285Sikobvoid fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 160103285Sikob 161103285Sikob/* 162103285Sikob * memory allocated for DMA programs 163103285Sikob */ 164103285Sikob#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 165103285Sikob 166103285Sikob/* #define NDB 1024 */ 167103285Sikob#define NDB FWMAXQUEUE 168103285Sikob#define NDVDB (DVBUF * NDB) 169103285Sikob 170103285Sikob#define OHCI_VERSION 0x00 171103285Sikob#define OHCI_CROMHDR 0x18 172103285Sikob#define OHCI_BUS_OPT 0x20 173103285Sikob#define OHCI_BUSIRMC (1 << 31) 174103285Sikob#define OHCI_BUSCMC (1 << 30) 175103285Sikob#define OHCI_BUSISC (1 << 29) 176103285Sikob#define OHCI_BUSBMC (1 << 28) 177103285Sikob#define OHCI_BUSPMC (1 << 27) 178103285Sikob#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 179103285Sikob OHCI_BUSBMC | OHCI_BUSPMC 180103285Sikob 181103285Sikob#define OHCI_EUID_HI 0x24 182103285Sikob#define OHCI_EUID_LO 0x28 183103285Sikob 184103285Sikob#define OHCI_CROMPTR 0x34 185103285Sikob#define OHCI_HCCCTL 0x50 186103285Sikob#define OHCI_HCCCTLCLR 0x54 187103285Sikob#define OHCI_AREQHI 0x100 188103285Sikob#define OHCI_AREQHICLR 0x104 189103285Sikob#define OHCI_AREQLO 0x108 190103285Sikob#define OHCI_AREQLOCLR 0x10c 191103285Sikob#define OHCI_PREQHI 0x110 192103285Sikob#define OHCI_PREQHICLR 0x114 193103285Sikob#define OHCI_PREQLO 0x118 194103285Sikob#define OHCI_PREQLOCLR 0x11c 195103285Sikob#define OHCI_PREQUPPER 0x120 196103285Sikob 197103285Sikob#define OHCI_SID_BUF 0x64 198103285Sikob#define OHCI_SID_CNT 0x68 199103285Sikob#define OHCI_SID_CNT_MASK 0xffc 200103285Sikob 201103285Sikob#define OHCI_IT_STAT 0x90 202103285Sikob#define OHCI_IT_STATCLR 0x94 203103285Sikob#define OHCI_IT_MASK 0x98 204103285Sikob#define OHCI_IT_MASKCLR 0x9c 205103285Sikob 206103285Sikob#define OHCI_IR_STAT 0xa0 207103285Sikob#define OHCI_IR_STATCLR 0xa4 208103285Sikob#define OHCI_IR_MASK 0xa8 209103285Sikob#define OHCI_IR_MASKCLR 0xac 210103285Sikob 211103285Sikob#define OHCI_LNKCTL 0xe0 212103285Sikob#define OHCI_LNKCTLCLR 0xe4 213103285Sikob 214103285Sikob#define OHCI_PHYACCESS 0xec 215103285Sikob#define OHCI_CYCLETIMER 0xf0 216103285Sikob 217103285Sikob#define OHCI_DMACTL(off) (off) 218103285Sikob#define OHCI_DMACTLCLR(off) (off + 4) 219103285Sikob#define OHCI_DMACMD(off) (off + 0xc) 220103285Sikob#define OHCI_DMAMATCH(off) (off + 0x10) 221103285Sikob 222103285Sikob#define OHCI_ATQOFF 0x180 223103285Sikob#define OHCI_ATQCTL OHCI_ATQOFF 224103285Sikob#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 225103285Sikob#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 226103285Sikob#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 227103285Sikob 228103285Sikob#define OHCI_ATSOFF 0x1a0 229103285Sikob#define OHCI_ATSCTL OHCI_ATSOFF 230103285Sikob#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 231103285Sikob#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 232103285Sikob#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 233103285Sikob 234103285Sikob#define OHCI_ARQOFF 0x1c0 235103285Sikob#define OHCI_ARQCTL OHCI_ARQOFF 236103285Sikob#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 237103285Sikob#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 238103285Sikob#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 239103285Sikob 240103285Sikob#define OHCI_ARSOFF 0x1e0 241103285Sikob#define OHCI_ARSCTL OHCI_ARSOFF 242103285Sikob#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 243103285Sikob#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 244103285Sikob#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 245103285Sikob 246103285Sikob#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 247103285Sikob#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 248103285Sikob#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 249103285Sikob#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 250103285Sikob 251103285Sikob#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 252103285Sikob#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 253103285Sikob#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 254103285Sikob#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 255103285Sikob#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 256103285Sikob 257103285Sikobd_ioctl_t fwohci_ioctl; 258103285Sikob 259103285Sikob/* 260103285Sikob * Communication with PHY device 261103285Sikob */ 262106790Ssimokawastatic u_int32_t 263106790Ssimokawafwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 264103285Sikob{ 265103285Sikob u_int32_t fun; 266103285Sikob 267103285Sikob addr &= 0xf; 268103285Sikob data &= 0xff; 269103285Sikob 270103285Sikob fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 271103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 272103285Sikob DELAY(100); 273103285Sikob 274103285Sikob return(fwphy_rddata( sc, addr)); 275103285Sikob} 276103285Sikob 277103285Sikobstatic u_int32_t 278103285Sikobfwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 279103285Sikob{ 280103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 281103285Sikob int i; 282103285Sikob u_int32_t bm; 283103285Sikob 284103285Sikob#define OHCI_CSR_DATA 0x0c 285103285Sikob#define OHCI_CSR_COMP 0x10 286103285Sikob#define OHCI_CSR_CONT 0x14 287103285Sikob#define OHCI_BUS_MANAGER_ID 0 288103285Sikob 289103285Sikob OWRITE(sc, OHCI_CSR_DATA, node); 290103285Sikob OWRITE(sc, OHCI_CSR_COMP, 0x3f); 291103285Sikob OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 292103285Sikob for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 293103285Sikob DELAY(100); 294103285Sikob bm = OREAD(sc, OHCI_CSR_DATA); 295107653Ssimokawa if((bm & 0x3f) == 0x3f) 296103285Sikob bm = node; 297107653Ssimokawa if (bootverbose) 298107653Ssimokawa device_printf(sc->fc.dev, 299107653Ssimokawa "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 300103285Sikob 301103285Sikob return(bm); 302103285Sikob} 303103285Sikob 304106790Ssimokawastatic u_int32_t 305106790Ssimokawafwphy_rddata(struct fwohci_softc *sc, u_int addr) 306103285Sikob{ 307108500Ssimokawa u_int32_t fun, stat; 308108500Ssimokawa u_int i, retry = 0; 309103285Sikob 310103285Sikob addr &= 0xf; 311108500Ssimokawa#define MAX_RETRY 100 312108500Ssimokawaagain: 313108500Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 314103285Sikob fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 315103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 316108500Ssimokawa for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 317103285Sikob fun = OREAD(sc, OHCI_PHYACCESS); 318103285Sikob if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 319103285Sikob break; 320103285Sikob DELAY(1000); 321103285Sikob } 322108500Ssimokawa if(i >= MAX_RETRY) { 323103285Sikob device_printf(sc->fc.dev, "cannot read phy\n"); 324108527Ssimokawa#if 0 325108500Ssimokawa return 0; /* XXX */ 326108527Ssimokawa#else 327108527Ssimokawa if (++retry < MAX_RETRY) { 328108527Ssimokawa DELAY(1000); 329108527Ssimokawa goto again; 330108527Ssimokawa } 331108527Ssimokawa#endif 332108500Ssimokawa } 333108500Ssimokawa /* Make sure that SCLK is started */ 334108500Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 335108500Ssimokawa if ((stat & OHCI_INT_REG_FAIL) != 0 || 336108500Ssimokawa ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 337108500Ssimokawa if (++retry < MAX_RETRY) { 338108500Ssimokawa DELAY(1000); 339108500Ssimokawa goto again; 340108500Ssimokawa } 341108500Ssimokawa } 342108500Ssimokawa if (bootverbose || retry >= MAX_RETRY) 343108500Ssimokawa device_printf(sc->fc.dev, 344108500Ssimokawa "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 345108500Ssimokawa#undef MAX_RETRY 346103285Sikob return((fun >> PHYDEV_RDDATA )& 0xff); 347103285Sikob} 348103285Sikob/* Device specific ioctl. */ 349103285Sikobint 350103285Sikobfwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 351103285Sikob{ 352103285Sikob struct firewire_softc *sc; 353103285Sikob struct fwohci_softc *fc; 354103285Sikob int unit = DEV2UNIT(dev); 355103285Sikob int err = 0; 356103285Sikob struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 357103285Sikob u_int32_t *dmach = (u_int32_t *) data; 358103285Sikob 359103285Sikob sc = devclass_get_softc(firewire_devclass, unit); 360103285Sikob if(sc == NULL){ 361103285Sikob return(EINVAL); 362103285Sikob } 363103285Sikob fc = (struct fwohci_softc *)sc->fc; 364103285Sikob 365103285Sikob if (!data) 366103285Sikob return(EINVAL); 367103285Sikob 368103285Sikob switch (cmd) { 369103285Sikob case FWOHCI_WRREG: 370103285Sikob#define OHCI_MAX_REG 0x800 371103285Sikob if(reg->addr <= OHCI_MAX_REG){ 372103285Sikob OWRITE(fc, reg->addr, reg->data); 373103285Sikob reg->data = OREAD(fc, reg->addr); 374103285Sikob }else{ 375103285Sikob err = EINVAL; 376103285Sikob } 377103285Sikob break; 378103285Sikob case FWOHCI_RDREG: 379103285Sikob if(reg->addr <= OHCI_MAX_REG){ 380103285Sikob reg->data = OREAD(fc, reg->addr); 381103285Sikob }else{ 382103285Sikob err = EINVAL; 383103285Sikob } 384103285Sikob break; 385103285Sikob/* Read DMA descriptors for debug */ 386103285Sikob case DUMPDMA: 387103285Sikob if(*dmach <= OHCI_MAX_DMA_CH ){ 388103285Sikob dump_dma(fc, *dmach); 389103285Sikob dump_db(fc, *dmach); 390103285Sikob }else{ 391103285Sikob err = EINVAL; 392103285Sikob } 393103285Sikob break; 394103285Sikob default: 395103285Sikob break; 396103285Sikob } 397103285Sikob return err; 398103285Sikob} 399106790Ssimokawa 400108530Ssimokawastatic int 401108530Ssimokawafwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 402103285Sikob{ 403108530Ssimokawa u_int32_t reg, reg2; 404108530Ssimokawa int e1394a = 1; 405108530Ssimokawa/* 406108530Ssimokawa * probe PHY parameters 407108530Ssimokawa * 0. to prove PHY version, whether compliance of 1394a. 408108530Ssimokawa * 1. to probe maximum speed supported by the PHY and 409108530Ssimokawa * number of port supported by core-logic. 410108530Ssimokawa * It is not actually available port on your PC . 411108530Ssimokawa */ 412108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 413108530Ssimokawa#if 0 414108530Ssimokawa /* XXX wait for SCLK. */ 415108530Ssimokawa DELAY(100000); 416108530Ssimokawa#endif 417108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 418108530Ssimokawa 419108530Ssimokawa if((reg >> 5) != 7 ){ 420108530Ssimokawa sc->fc.mode &= ~FWPHYASYST; 421108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 422108530Ssimokawa sc->fc.speed = reg & FW_PHY_SPD >> 6; 423108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 424108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 425108530Ssimokawa sc->fc.speed, MAX_SPEED); 426108530Ssimokawa sc->fc.speed = MAX_SPEED; 427108530Ssimokawa } 428108530Ssimokawa device_printf(dev, 429108701Ssimokawa "Phy 1394 only %s, %d ports.\n", 430108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 431108530Ssimokawa }else{ 432108530Ssimokawa reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 433108530Ssimokawa sc->fc.mode |= FWPHYASYST; 434108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 435108530Ssimokawa sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 436108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 437108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 438108530Ssimokawa sc->fc.speed, MAX_SPEED); 439108530Ssimokawa sc->fc.speed = MAX_SPEED; 440108530Ssimokawa } 441108530Ssimokawa device_printf(dev, 442108701Ssimokawa "Phy 1394a available %s, %d ports.\n", 443108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 444108530Ssimokawa 445108530Ssimokawa /* check programPhyEnable */ 446108530Ssimokawa reg2 = fwphy_rddata(sc, 5); 447108530Ssimokawa#if 0 448108530Ssimokawa if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 449108530Ssimokawa#else /* XXX force to enable 1394a */ 450108530Ssimokawa if (e1394a) { 451108530Ssimokawa#endif 452108530Ssimokawa if (bootverbose) 453108530Ssimokawa device_printf(dev, 454108530Ssimokawa "Enable 1394a Enhancements\n"); 455108530Ssimokawa /* enable EAA EMC */ 456108530Ssimokawa reg2 |= 0x03; 457108530Ssimokawa /* set aPhyEnhanceEnable */ 458108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 459108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 460108530Ssimokawa } else { 461108530Ssimokawa /* for safe */ 462108530Ssimokawa reg2 &= ~0x83; 463108530Ssimokawa } 464108530Ssimokawa reg2 = fwphy_wrdata(sc, 5, reg2); 465108530Ssimokawa } 466108530Ssimokawa 467108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 468108530Ssimokawa if((reg >> 5) == 7 ){ 469108530Ssimokawa reg = fwphy_rddata(sc, 4); 470108530Ssimokawa reg |= 1 << 6; 471108530Ssimokawa fwphy_wrdata(sc, 4, reg); 472108530Ssimokawa reg = fwphy_rddata(sc, 4); 473108530Ssimokawa } 474108530Ssimokawa return 0; 475108530Ssimokawa} 476108530Ssimokawa 477108530Ssimokawa 478108530Ssimokawavoid 479108530Ssimokawafwohci_reset(struct fwohci_softc *sc, device_t dev) 480108530Ssimokawa{ 481108701Ssimokawa int i, max_rec, speed; 482103285Sikob u_int32_t reg, reg2; 483103285Sikob struct fwohcidb_tr *db_tr; 484103285Sikob 485108701Ssimokawa /* Disable interrupt */ 486108530Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 487108530Ssimokawa 488108701Ssimokawa /* Now stopping all DMA channel */ 489108530Ssimokawa OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 490108530Ssimokawa OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 491108530Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 492108530Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 493108530Ssimokawa 494108530Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, ~0); 495108530Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 496108530Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 497108530Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 498108530Ssimokawa } 499108530Ssimokawa 500108701Ssimokawa /* FLUSH FIFO and reset Transmitter/Reciever */ 501108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 502108530Ssimokawa if (bootverbose) 503108530Ssimokawa device_printf(dev, "resetting OHCI..."); 504108530Ssimokawa i = 0; 505108530Ssimokawa while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 506108530Ssimokawa if (i++ > 100) break; 507108530Ssimokawa DELAY(1000); 508108530Ssimokawa } 509108530Ssimokawa if (bootverbose) 510108530Ssimokawa printf("done (loop=%d)\n", i); 511108530Ssimokawa 512108701Ssimokawa /* Probe phy */ 513108701Ssimokawa fwohci_probe_phy(sc, dev); 514108701Ssimokawa 515108701Ssimokawa /* Probe link */ 516108530Ssimokawa reg = OREAD(sc, OHCI_BUS_OPT); 517108530Ssimokawa reg2 = reg | OHCI_BUSFNC; 518108701Ssimokawa max_rec = (reg & 0x0000f000) >> 12; 519108701Ssimokawa speed = (reg & 0x00000007); 520108701Ssimokawa device_printf(dev, "Link %s, max_rec %d bytes.\n", 521108701Ssimokawa linkspeed[speed], MAXREC(max_rec)); 522108701Ssimokawa /* XXX fix max_rec */ 523108701Ssimokawa sc->fc.maxrec = sc->fc.speed + 8; 524108701Ssimokawa if (max_rec != sc->fc.maxrec) { 525108701Ssimokawa reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 526108701Ssimokawa device_printf(dev, "max_rec %d -> %d\n", 527108701Ssimokawa MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 528108701Ssimokawa } 529108530Ssimokawa if (bootverbose) 530108530Ssimokawa device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 531108530Ssimokawa OWRITE(sc, OHCI_BUS_OPT, reg2); 532108530Ssimokawa 533108701Ssimokawa /* Initialize registers */ 534108530Ssimokawa OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 535108530Ssimokawa OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0])); 536108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 537108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 538108642Ssimokawa OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf)); 539108530Ssimokawa OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 540108701Ssimokawa fw_busreset(&sc->fc); 541108530Ssimokawa 542108701Ssimokawa /* Enable link */ 543108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 544108642Ssimokawa 545108701Ssimokawa /* Force to start async RX DMA */ 546108642Ssimokawa sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 547108642Ssimokawa sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 548108530Ssimokawa fwohci_rx_enable(sc, &sc->arrq); 549108530Ssimokawa fwohci_rx_enable(sc, &sc->arrs); 550108530Ssimokawa 551108701Ssimokawa /* Initialize async TX */ 552108701Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 553108701Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 554108701Ssimokawa /* AT Retries */ 555108701Ssimokawa OWRITE(sc, FWOHCI_RETRY, 556108701Ssimokawa /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 557108701Ssimokawa (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 558108530Ssimokawa for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 559108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 560108530Ssimokawa db_tr->xfer = NULL; 561108530Ssimokawa } 562108530Ssimokawa for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 563108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 564108530Ssimokawa db_tr->xfer = NULL; 565108530Ssimokawa } 566108530Ssimokawa 567108701Ssimokawa 568108701Ssimokawa /* Enable interrupt */ 569108530Ssimokawa OWRITE(sc, FWOHCI_INTMASK, 570108530Ssimokawa OHCI_INT_ERR | OHCI_INT_PHY_SID 571108530Ssimokawa | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 572108530Ssimokawa | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 573108530Ssimokawa | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 574108530Ssimokawa fwohci_set_intr(&sc->fc, 1); 575108530Ssimokawa 576108530Ssimokawa} 577108530Ssimokawa 578108530Ssimokawaint 579108530Ssimokawafwohci_init(struct fwohci_softc *sc, device_t dev) 580108530Ssimokawa{ 581108530Ssimokawa int i; 582108530Ssimokawa u_int32_t reg; 583108530Ssimokawa 584103285Sikob reg = OREAD(sc, OHCI_VERSION); 585103285Sikob device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 586103285Sikob (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 587103285Sikob 588103285Sikob/* XXX: Available Isochrounous DMA channel probe */ 589103285Sikob for( i = 0 ; i < 0x20 ; i ++ ){ 590103285Sikob OWRITE(sc, OHCI_IRCTL(i), OHCI_CNTL_DMA_RUN); 591103285Sikob reg = OREAD(sc, OHCI_IRCTL(i)); 592103285Sikob if(!(reg & OHCI_CNTL_DMA_RUN)) break; 593103285Sikob OWRITE(sc, OHCI_ITCTL(i), OHCI_CNTL_DMA_RUN); 594103285Sikob reg = OREAD(sc, OHCI_ITCTL(i)); 595103285Sikob if(!(reg & OHCI_CNTL_DMA_RUN)) break; 596103285Sikob } 597103285Sikob sc->fc.nisodma = i; 598103285Sikob device_printf(dev, "No. of Isochronous channel is %d.\n", i); 599103285Sikob 600103285Sikob sc->fc.arq = &sc->arrq.xferq; 601103285Sikob sc->fc.ars = &sc->arrs.xferq; 602103285Sikob sc->fc.atq = &sc->atrq.xferq; 603103285Sikob sc->fc.ats = &sc->atrs.xferq; 604103285Sikob 605103285Sikob sc->arrq.xferq.start = NULL; 606103285Sikob sc->arrs.xferq.start = NULL; 607103285Sikob sc->atrq.xferq.start = fwohci_start_atq; 608103285Sikob sc->atrs.xferq.start = fwohci_start_ats; 609103285Sikob 610103285Sikob sc->arrq.xferq.drain = NULL; 611103285Sikob sc->arrs.xferq.drain = NULL; 612103285Sikob sc->atrq.xferq.drain = fwohci_drain_atq; 613103285Sikob sc->atrs.xferq.drain = fwohci_drain_ats; 614103285Sikob 615103285Sikob sc->arrq.ndesc = 1; 616103285Sikob sc->arrs.ndesc = 1; 617108655Ssimokawa sc->atrq.ndesc = 6; /* equal to maximum of mbuf chains */ 618108655Ssimokawa sc->atrs.ndesc = 6 / 2; 619103285Sikob 620103285Sikob sc->arrq.ndb = NDB; 621103285Sikob sc->arrs.ndb = NDB / 2; 622103285Sikob sc->atrq.ndb = NDB; 623103285Sikob sc->atrs.ndb = NDB / 2; 624103285Sikob 625103285Sikob sc->arrq.dummy = NULL; 626103285Sikob sc->arrs.dummy = NULL; 627103285Sikob sc->atrq.dummy = NULL; 628103285Sikob sc->atrs.dummy = NULL; 629103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 630103285Sikob sc->fc.it[i] = &sc->it[i].xferq; 631103285Sikob sc->fc.ir[i] = &sc->ir[i].xferq; 632103285Sikob sc->it[i].ndb = 0; 633103285Sikob sc->ir[i].ndb = 0; 634103285Sikob } 635103285Sikob 636103285Sikob sc->fc.tcode = tinfo; 637103285Sikob 638103285Sikob sc->cromptr = (u_int32_t *) 639103285Sikob contigmalloc(CROMSIZE * 2, M_DEVBUF, M_NOWAIT, 0, ~0, 1<<10, 0); 640103285Sikob 641103285Sikob if(sc->cromptr == NULL){ 642108527Ssimokawa device_printf(dev, "cromptr alloc failed."); 643103285Sikob return ENOMEM; 644103285Sikob } 645103285Sikob sc->fc.dev = dev; 646103285Sikob sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]); 647103285Sikob 648103285Sikob sc->fc.config_rom[1] = 0x31333934; 649103285Sikob sc->fc.config_rom[2] = 0xf000a002; 650103285Sikob sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 651103285Sikob sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 652103285Sikob sc->fc.config_rom[5] = 0; 653103285Sikob sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 654103285Sikob 655103285Sikob sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 656103285Sikob 657103285Sikob 658103285Sikob/* SID recieve buffer must allign 2^11 */ 659103285Sikob#define OHCI_SIDSIZE (1 << 11) 660103285Sikob sc->fc.sid_buf = (u_int32_t *) vm_page_alloc_contig( OHCI_SIDSIZE, 661103285Sikob 0x10000, 0xffffffff, OHCI_SIDSIZE); 662108527Ssimokawa if (sc->fc.sid_buf == NULL) { 663108527Ssimokawa device_printf(dev, "sid_buf alloc failed.\n"); 664108527Ssimokawa return ENOMEM; 665108527Ssimokawa } 666108527Ssimokawa 667108530Ssimokawa 668103285Sikob fwohci_db_init(&sc->arrq); 669108527Ssimokawa if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 670108527Ssimokawa return ENOMEM; 671108527Ssimokawa 672103285Sikob fwohci_db_init(&sc->arrs); 673108527Ssimokawa if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 674108527Ssimokawa return ENOMEM; 675103285Sikob 676103285Sikob fwohci_db_init(&sc->atrq); 677108527Ssimokawa if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 678108527Ssimokawa return ENOMEM; 679108527Ssimokawa 680103285Sikob fwohci_db_init(&sc->atrs); 681108527Ssimokawa if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 682108527Ssimokawa return ENOMEM; 683103285Sikob 684103285Sikob reg = OREAD(sc, FWOHCIGUID_H); 685103285Sikob for( i = 0 ; i < 4 ; i ++){ 686103285Sikob sc->fc.eui[3 - i] = reg & 0xff; 687103285Sikob reg = reg >> 8; 688103285Sikob } 689103285Sikob reg = OREAD(sc, FWOHCIGUID_L); 690103285Sikob for( i = 0 ; i < 4 ; i ++){ 691103285Sikob sc->fc.eui[7 - i] = reg & 0xff; 692103285Sikob reg = reg >> 8; 693103285Sikob } 694103285Sikob device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 695103285Sikob sc->fc.eui[0], sc->fc.eui[1], sc->fc.eui[2], sc->fc.eui[3], 696103285Sikob sc->fc.eui[4], sc->fc.eui[5], sc->fc.eui[6], sc->fc.eui[7]); 697103285Sikob sc->fc.ioctl = fwohci_ioctl; 698103285Sikob sc->fc.cyctimer = fwohci_cyctimer; 699103285Sikob sc->fc.set_bmr = fwohci_set_bus_manager; 700103285Sikob sc->fc.ibr = fwohci_ibr; 701103285Sikob sc->fc.irx_enable = fwohci_irx_enable; 702103285Sikob sc->fc.irx_disable = fwohci_irx_disable; 703103285Sikob 704103285Sikob sc->fc.itx_enable = fwohci_itxbuf_enable; 705103285Sikob sc->fc.itx_disable = fwohci_itx_disable; 706103285Sikob sc->fc.irx_post = fwohci_irx_post; 707103285Sikob sc->fc.itx_post = NULL; 708103285Sikob sc->fc.timeout = fwohci_timeout; 709103285Sikob sc->fc.poll = fwohci_poll; 710103285Sikob sc->fc.set_intr = fwohci_set_intr; 711106790Ssimokawa 712108530Ssimokawa fw_init(&sc->fc); 713108530Ssimokawa fwohci_reset(sc, dev); 714103285Sikob 715108530Ssimokawa return 0; 716103285Sikob} 717106790Ssimokawa 718106790Ssimokawavoid 719106790Ssimokawafwohci_timeout(void *arg) 720103285Sikob{ 721103285Sikob struct fwohci_softc *sc; 722103285Sikob 723103285Sikob sc = (struct fwohci_softc *)arg; 724103285Sikob sc->fc.timeouthandle = timeout(fwohci_timeout, 725103285Sikob (void *)sc, FW_XFERTIMEOUT * hz * 10); 726103285Sikob} 727106790Ssimokawa 728106790Ssimokawau_int32_t 729106790Ssimokawafwohci_cyctimer(struct firewire_comm *fc) 730103285Sikob{ 731103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 732103285Sikob return(OREAD(sc, OHCI_CYCLETIMER)); 733103285Sikob} 734103285Sikob 735108527Ssimokawaint 736108527Ssimokawafwohci_detach(struct fwohci_softc *sc, device_t dev) 737108527Ssimokawa{ 738108527Ssimokawa int i; 739108527Ssimokawa 740108527Ssimokawa if (sc->fc.sid_buf != NULL) 741108527Ssimokawa contigfree((void *)(uintptr_t)sc->fc.sid_buf, 742108527Ssimokawa OHCI_SIDSIZE, M_DEVBUF); 743108527Ssimokawa if (sc->cromptr != NULL) 744108527Ssimokawa contigfree((void *)sc->cromptr, CROMSIZE * 2, M_DEVBUF); 745108527Ssimokawa 746108527Ssimokawa fwohci_db_free(&sc->arrq); 747108527Ssimokawa fwohci_db_free(&sc->arrs); 748108527Ssimokawa 749108527Ssimokawa fwohci_db_free(&sc->atrq); 750108527Ssimokawa fwohci_db_free(&sc->atrs); 751108527Ssimokawa 752108527Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 753108527Ssimokawa fwohci_db_free(&sc->it[i]); 754108527Ssimokawa fwohci_db_free(&sc->ir[i]); 755108527Ssimokawa } 756108527Ssimokawa 757108527Ssimokawa return 0; 758108527Ssimokawa} 759108527Ssimokawa 760108655Ssimokawa#define LAST_DB(dbtr, db) do { \ 761108655Ssimokawa struct fwohcidb_tr *_dbtr = (dbtr); \ 762108655Ssimokawa int _cnt = _dbtr->dbcnt; \ 763108655Ssimokawa db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 764108655Ssimokawa} while (0) 765108655Ssimokawa 766106790Ssimokawastatic void 767106790Ssimokawafwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 768103285Sikob{ 769103285Sikob int i, s; 770103285Sikob int tcode, hdr_len, hdr_off, len; 771103285Sikob int fsegment = -1; 772103285Sikob u_int32_t off; 773103285Sikob struct fw_xfer *xfer; 774103285Sikob struct fw_pkt *fp; 775103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 776103285Sikob struct fwohcidb_tr *db_tr; 777103285Sikob volatile struct fwohcidb *db; 778103285Sikob struct mbuf *m; 779103285Sikob struct tcode_info *info; 780108655Ssimokawa static int maxdesc=0; 781103285Sikob 782103285Sikob if(&sc->atrq == dbch){ 783103285Sikob off = OHCI_ATQOFF; 784103285Sikob }else if(&sc->atrs == dbch){ 785103285Sikob off = OHCI_ATSOFF; 786103285Sikob }else{ 787103285Sikob return; 788103285Sikob } 789103285Sikob 790103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) 791103285Sikob return; 792103285Sikob 793103285Sikob s = splfw(); 794103285Sikob db_tr = dbch->top; 795103285Sikobtxloop: 796103285Sikob xfer = STAILQ_FIRST(&dbch->xferq.q); 797103285Sikob if(xfer == NULL){ 798103285Sikob goto kick; 799103285Sikob } 800103285Sikob if(dbch->xferq.queued == 0 ){ 801103285Sikob device_printf(sc->fc.dev, "TX queue empty\n"); 802103285Sikob } 803103285Sikob STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 804103285Sikob db_tr->xfer = xfer; 805103285Sikob xfer->state = FWXF_START; 806103285Sikob dbch->xferq.packets++; 807103285Sikob 808103285Sikob fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off); 809103285Sikob tcode = fp->mode.common.tcode; 810103285Sikob 811103285Sikob ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 812103285Sikob info = &tinfo[tcode]; 813103285Sikob hdr_len = hdr_off = info->hdr_len; 814103285Sikob /* fw_asyreq must pass valid send.len */ 815103285Sikob len = xfer->send.len; 816103285Sikob for( i = 0 ; i < hdr_off ; i+= 4){ 817103285Sikob ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]); 818103285Sikob } 819103285Sikob ohcifp->mode.common.spd = xfer->spd; 820103285Sikob if (tcode == FWTCODE_STREAM ){ 821103285Sikob hdr_len = 8; 822103285Sikob ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 823103285Sikob } else if (tcode == FWTCODE_PHY) { 824103285Sikob hdr_len = 12; 825103285Sikob ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]); 826103285Sikob ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]); 827103285Sikob ohcifp->mode.common.spd = 0; 828103285Sikob ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 829103285Sikob } else { 830103285Sikob ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst); 831103285Sikob ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 832103285Sikob ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 833103285Sikob } 834103285Sikob db = &db_tr->db[0]; 835103285Sikob db->db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len; 836103285Sikob db->db.desc.status = 0; 837103285Sikob/* Specify bound timer of asy. responce */ 838103285Sikob if(&sc->atrs == dbch){ 839103285Sikob db->db.desc.count 840103285Sikob = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13); 841103285Sikob } 842103285Sikob 843103285Sikob db_tr->dbcnt = 2; 844103285Sikob db = &db_tr->db[db_tr->dbcnt]; 845103285Sikob if(len > hdr_off){ 846103285Sikob if (xfer->mbuf == NULL) { 847103285Sikob db->db.desc.addr 848103285Sikob = vtophys(xfer->send.buf + xfer->send.off) + hdr_off; 849103285Sikob db->db.desc.cmd 850103285Sikob = OHCI_OUTPUT_MORE | ((len - hdr_off) & 0xffff); 851103285Sikob db->db.desc.status = 0; 852103285Sikob 853103285Sikob db_tr->dbcnt++; 854103285Sikob } else { 855103285Sikob /* XXX we assume mbuf chain is shorter than ndesc */ 856108655Ssimokawa for (m = xfer->mbuf; m != NULL; m = m->m_next) { 857108655Ssimokawa if (m->m_len == 0) 858108655Ssimokawa /* unrecoverable error could ocurre. */ 859108655Ssimokawa continue; 860108655Ssimokawa if (db_tr->dbcnt >= dbch->ndesc) { 861108655Ssimokawa device_printf(sc->fc.dev, 862108655Ssimokawa "dbch->ndesc is too small" 863108655Ssimokawa ", trancated.\n"); 864108655Ssimokawa break; 865108655Ssimokawa } 866103285Sikob db->db.desc.addr 867103285Sikob = vtophys(mtod(m, caddr_t)); 868103285Sikob db->db.desc.cmd = OHCI_OUTPUT_MORE | m->m_len; 869103285Sikob db->db.desc.status = 0; 870103285Sikob db++; 871103285Sikob db_tr->dbcnt++; 872108655Ssimokawa } 873103285Sikob } 874103285Sikob } 875108655Ssimokawa if (maxdesc < db_tr->dbcnt) { 876108655Ssimokawa maxdesc = db_tr->dbcnt; 877108655Ssimokawa if (bootverbose) 878108655Ssimokawa device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 879108655Ssimokawa } 880103285Sikob /* last db */ 881103285Sikob LAST_DB(db_tr, db); 882103285Sikob db->db.desc.cmd |= OHCI_OUTPUT_LAST 883103285Sikob | OHCI_INTERRUPT_ALWAYS 884103285Sikob | OHCI_BRANCH_ALWAYS; 885103285Sikob db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db); 886103285Sikob 887103285Sikob if(fsegment == -1 ) 888103285Sikob fsegment = db_tr->dbcnt; 889103285Sikob if (dbch->pdb_tr != NULL) { 890103285Sikob LAST_DB(dbch->pdb_tr, db); 891103285Sikob db->db.desc.depend |= db_tr->dbcnt; 892103285Sikob } 893103285Sikob dbch->pdb_tr = db_tr; 894103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 895103285Sikob if(db_tr != dbch->bottom){ 896103285Sikob goto txloop; 897103285Sikob } else { 898107653Ssimokawa device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 899103285Sikob dbch->flags |= FWOHCI_DBCH_FULL; 900103285Sikob } 901103285Sikobkick: 902103285Sikob if (firewire_debug) printf("kick\n"); 903103285Sikob /* kick asy q */ 904103285Sikob 905103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) { 906103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 907103285Sikob } else { 908107653Ssimokawa if (bootverbose) 909107653Ssimokawa device_printf(sc->fc.dev, "start AT DMA status=%x\n", 910103285Sikob OREAD(sc, OHCI_DMACTL(off))); 911103285Sikob OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment); 912103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 913103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 914103285Sikob } 915106790Ssimokawa 916103285Sikob dbch->top = db_tr; 917103285Sikob splx(s); 918103285Sikob return; 919103285Sikob} 920106790Ssimokawa 921106790Ssimokawastatic void 922106790Ssimokawafwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer) 923103285Sikob{ 924103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 925103285Sikob fwohci_drain(&sc->fc, xfer, &(sc->atrq)); 926103285Sikob return; 927103285Sikob} 928106790Ssimokawa 929106790Ssimokawastatic void 930106790Ssimokawafwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer) 931103285Sikob{ 932103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 933103285Sikob fwohci_drain(&sc->fc, xfer, &(sc->atrs)); 934103285Sikob return; 935103285Sikob} 936106790Ssimokawa 937106790Ssimokawastatic void 938106790Ssimokawafwohci_start_atq(struct firewire_comm *fc) 939103285Sikob{ 940103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 941103285Sikob fwohci_start( sc, &(sc->atrq)); 942103285Sikob return; 943103285Sikob} 944106790Ssimokawa 945106790Ssimokawastatic void 946106790Ssimokawafwohci_start_ats(struct firewire_comm *fc) 947103285Sikob{ 948103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 949103285Sikob fwohci_start( sc, &(sc->atrs)); 950103285Sikob return; 951103285Sikob} 952106790Ssimokawa 953106790Ssimokawavoid 954106790Ssimokawafwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 955103285Sikob{ 956103285Sikob int s, err = 0; 957103285Sikob struct fwohcidb_tr *tr; 958103285Sikob volatile struct fwohcidb *db; 959103285Sikob struct fw_xfer *xfer; 960103285Sikob u_int32_t off; 961103285Sikob u_int stat; 962103285Sikob int packets; 963103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 964103285Sikob if(&sc->atrq == dbch){ 965103285Sikob off = OHCI_ATQOFF; 966103285Sikob }else if(&sc->atrs == dbch){ 967103285Sikob off = OHCI_ATSOFF; 968103285Sikob }else{ 969103285Sikob return; 970103285Sikob } 971103285Sikob s = splfw(); 972103285Sikob tr = dbch->bottom; 973103285Sikob packets = 0; 974103285Sikob while(dbch->xferq.queued > 0){ 975103285Sikob LAST_DB(tr, db); 976103285Sikob if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){ 977103285Sikob if (fc->status != FWBUSRESET) 978103285Sikob /* maybe out of order?? */ 979103285Sikob goto out; 980103285Sikob } 981103285Sikob if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) { 982103285Sikob#ifdef OHCI_DEBUG 983103285Sikob dump_dma(sc, ch); 984103285Sikob dump_db(sc, ch); 985103285Sikob#endif 986103285Sikob/* Stop DMA */ 987103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 988103285Sikob device_printf(sc->fc.dev, "force reset AT FIFO\n"); 989103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 990103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 991103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 992103285Sikob } 993103285Sikob stat = db->db.desc.status & FWOHCIEV_MASK; 994103285Sikob switch(stat){ 995103285Sikob case FWOHCIEV_ACKCOMPL: 996103285Sikob case FWOHCIEV_ACKPEND: 997103285Sikob err = 0; 998103285Sikob break; 999103285Sikob case FWOHCIEV_ACKBSA: 1000103285Sikob case FWOHCIEV_ACKBSB: 1001103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1002103285Sikob case FWOHCIEV_ACKBSX: 1003103285Sikob err = EBUSY; 1004103285Sikob break; 1005103285Sikob case FWOHCIEV_FLUSHED: 1006103285Sikob case FWOHCIEV_ACKTARD: 1007103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1008103285Sikob err = EAGAIN; 1009103285Sikob break; 1010103285Sikob case FWOHCIEV_MISSACK: 1011103285Sikob case FWOHCIEV_UNDRRUN: 1012103285Sikob case FWOHCIEV_OVRRUN: 1013103285Sikob case FWOHCIEV_DESCERR: 1014103285Sikob case FWOHCIEV_DTRDERR: 1015103285Sikob case FWOHCIEV_TIMEOUT: 1016103285Sikob case FWOHCIEV_TCODERR: 1017103285Sikob case FWOHCIEV_UNKNOWN: 1018103285Sikob case FWOHCIEV_ACKDERR: 1019103285Sikob case FWOHCIEV_ACKTERR: 1020103285Sikob default: 1021103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", 1022103285Sikob stat, fwohcicode[stat]); 1023103285Sikob err = EINVAL; 1024103285Sikob break; 1025103285Sikob } 1026103285Sikob if(tr->xfer != NULL){ 1027103285Sikob xfer = tr->xfer; 1028103285Sikob xfer->state = FWXF_SENT; 1029103285Sikob if(err == EBUSY && fc->status != FWBUSRESET){ 1030103285Sikob xfer->state = FWXF_BUSY; 1031103285Sikob switch(xfer->act_type){ 1032103285Sikob case FWACT_XFER: 1033103285Sikob xfer->resp = err; 1034103285Sikob if(xfer->retry_req != NULL){ 1035103285Sikob xfer->retry_req(xfer); 1036103285Sikob } 1037103285Sikob break; 1038103285Sikob default: 1039103285Sikob break; 1040103285Sikob } 1041103285Sikob } else if( stat != FWOHCIEV_ACKPEND){ 1042103285Sikob if (stat != FWOHCIEV_ACKCOMPL) 1043103285Sikob xfer->state = FWXF_SENTERR; 1044103285Sikob xfer->resp = err; 1045103285Sikob switch(xfer->act_type){ 1046103285Sikob case FWACT_XFER: 1047103285Sikob fw_xfer_done(xfer); 1048103285Sikob break; 1049103285Sikob default: 1050103285Sikob break; 1051103285Sikob } 1052103285Sikob } 1053103285Sikob dbch->xferq.queued --; 1054103285Sikob } 1055103285Sikob tr->xfer = NULL; 1056103285Sikob 1057103285Sikob packets ++; 1058103285Sikob tr = STAILQ_NEXT(tr, link); 1059103285Sikob dbch->bottom = tr; 1060103285Sikob } 1061103285Sikobout: 1062103285Sikob if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1063103285Sikob printf("make free slot\n"); 1064103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1065103285Sikob fwohci_start(sc, dbch); 1066103285Sikob } 1067103285Sikob splx(s); 1068103285Sikob} 1069106790Ssimokawa 1070106790Ssimokawastatic void 1071106790Ssimokawafwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch) 1072103285Sikob{ 1073103285Sikob int i, s; 1074103285Sikob struct fwohcidb_tr *tr; 1075103285Sikob 1076103285Sikob if(xfer->state != FWXF_START) return; 1077103285Sikob 1078103285Sikob s = splfw(); 1079103285Sikob tr = dbch->bottom; 1080103285Sikob for( i = 0 ; i <= dbch->xferq.queued ; i ++){ 1081103285Sikob if(tr->xfer == xfer){ 1082103285Sikob s = splfw(); 1083103285Sikob tr->xfer = NULL; 1084103285Sikob dbch->xferq.queued --; 1085103285Sikob#if 1 1086103285Sikob /* XXX */ 1087103285Sikob if (tr == dbch->bottom) 1088103285Sikob dbch->bottom = STAILQ_NEXT(tr, link); 1089103285Sikob#endif 1090103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) { 1091103285Sikob printf("fwohci_drain: make slot\n"); 1092103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1093103285Sikob fwohci_start((struct fwohci_softc *)fc, dbch); 1094103285Sikob } 1095103285Sikob 1096103285Sikob splx(s); 1097103285Sikob break; 1098103285Sikob } 1099103285Sikob tr = STAILQ_NEXT(tr, link); 1100103285Sikob } 1101103285Sikob splx(s); 1102103285Sikob return; 1103103285Sikob} 1104103285Sikob 1105106790Ssimokawastatic void 1106106790Ssimokawafwohci_db_free(struct fwohci_dbch *dbch) 1107103285Sikob{ 1108103285Sikob struct fwohcidb_tr *db_tr; 1109103285Sikob int idb; 1110103285Sikob 1111108527Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1112108527Ssimokawa return; 1113108527Ssimokawa 1114103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1115103285Sikob for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; 1116103285Sikob idb < dbch->ndb; 1117103285Sikob db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1118108527Ssimokawa if (db_tr->buf != NULL) { 1119108527Ssimokawa free(db_tr->buf, M_DEVBUF); 1120108527Ssimokawa db_tr->buf = NULL; 1121108527Ssimokawa } 1122103285Sikob } 1123103285Sikob } 1124103285Sikob dbch->ndb = 0; 1125103285Sikob db_tr = STAILQ_FIRST(&dbch->db_trq); 1126103285Sikob contigfree((void *)(uintptr_t)(volatile void *)db_tr->db, 1127103285Sikob sizeof(struct fwohcidb) * dbch->ndesc * dbch->ndb, M_DEVBUF); 1128103285Sikob free(db_tr, M_DEVBUF); 1129103285Sikob STAILQ_INIT(&dbch->db_trq); 1130108527Ssimokawa dbch->flags &= ~FWOHCI_DBCH_INIT; 1131103285Sikob} 1132106790Ssimokawa 1133106790Ssimokawastatic void 1134106790Ssimokawafwohci_db_init(struct fwohci_dbch *dbch) 1135103285Sikob{ 1136103285Sikob int idb; 1137103285Sikob struct fwohcidb *db; 1138103285Sikob struct fwohcidb_tr *db_tr; 1139108642Ssimokawa 1140108642Ssimokawa 1141108642Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1142108642Ssimokawa goto out; 1143108642Ssimokawa 1144103285Sikob /* allocate DB entries and attach one to each DMA channels */ 1145103285Sikob /* DB entry must start at 16 bytes bounary. */ 1146103285Sikob STAILQ_INIT(&dbch->db_trq); 1147103285Sikob db_tr = (struct fwohcidb_tr *) 1148103285Sikob malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1149108527Ssimokawa M_DEVBUF, M_DONTWAIT | M_ZERO); 1150103285Sikob if(db_tr == NULL){ 1151108642Ssimokawa printf("fwohci_db_init: malloc failed\n"); 1152103285Sikob return; 1153103285Sikob } 1154103285Sikob db = (struct fwohcidb *) 1155103285Sikob contigmalloc(sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb, 1156103285Sikob M_DEVBUF, M_DONTWAIT, 0x10000, 0xffffffff, PAGE_SIZE, 0ul); 1157103285Sikob if(db == NULL){ 1158108642Ssimokawa printf("fwohci_db_init: contigmalloc failed\n"); 1159108527Ssimokawa free(db_tr, M_DEVBUF); 1160103285Sikob return; 1161103285Sikob } 1162103285Sikob bzero(db, sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb); 1163103285Sikob /* Attach DB to DMA ch. */ 1164103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb++){ 1165103285Sikob db_tr->dbcnt = 0; 1166103285Sikob db_tr->db = &db[idb * dbch->ndesc]; 1167103285Sikob STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1168108530Ssimokawa if (!(dbch->xferq.flag & FWXFERQ_PACKET) && 1169108530Ssimokawa dbch->xferq.bnpacket != 0) { 1170108701Ssimokawa /* XXX what those for? */ 1171108530Ssimokawa if (idb % dbch->xferq.bnpacket == 0) 1172108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1173108530Ssimokawa ].start = (caddr_t)db_tr; 1174108530Ssimokawa if ((idb + 1) % dbch->xferq.bnpacket == 0) 1175108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1176108530Ssimokawa ].end = (caddr_t)db_tr; 1177103285Sikob } 1178103285Sikob db_tr++; 1179103285Sikob } 1180103285Sikob STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1181103285Sikob = STAILQ_FIRST(&dbch->db_trq); 1182108642Ssimokawaout: 1183108642Ssimokawa dbch->frag.buf = NULL; 1184108642Ssimokawa dbch->frag.len = 0; 1185108642Ssimokawa dbch->frag.plen = 0; 1186108642Ssimokawa dbch->xferq.queued = 0; 1187108642Ssimokawa dbch->pdb_tr = NULL; 1188103285Sikob dbch->top = STAILQ_FIRST(&dbch->db_trq); 1189103285Sikob dbch->bottom = dbch->top; 1190108527Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; 1191103285Sikob} 1192106790Ssimokawa 1193106790Ssimokawastatic int 1194106790Ssimokawafwohci_itx_disable(struct firewire_comm *fc, int dmach) 1195103285Sikob{ 1196103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1197103285Sikob OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1198103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1199103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1200103285Sikob fwohci_db_free(&sc->it[dmach]); 1201103285Sikob sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1202103285Sikob return 0; 1203103285Sikob} 1204106790Ssimokawa 1205106790Ssimokawastatic int 1206106790Ssimokawafwohci_irx_disable(struct firewire_comm *fc, int dmach) 1207103285Sikob{ 1208103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1209103285Sikob 1210103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1211103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1212103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1213103285Sikob if(sc->ir[dmach].dummy != NULL){ 1214103285Sikob free(sc->ir[dmach].dummy, M_DEVBUF); 1215103285Sikob } 1216103285Sikob sc->ir[dmach].dummy = NULL; 1217103285Sikob fwohci_db_free(&sc->ir[dmach]); 1218103285Sikob sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1219103285Sikob return 0; 1220103285Sikob} 1221106790Ssimokawa 1222106790Ssimokawastatic void 1223106790Ssimokawafwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1224103285Sikob{ 1225103285Sikob qld[0] = ntohl(qld[0]); 1226103285Sikob return; 1227103285Sikob} 1228106790Ssimokawa 1229106790Ssimokawastatic int 1230106790Ssimokawafwohci_irxpp_enable(struct firewire_comm *fc, int dmach) 1231103285Sikob{ 1232103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1233103285Sikob int err = 0; 1234103285Sikob unsigned short tag, ich; 1235103285Sikob 1236103285Sikob tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1237103285Sikob ich = sc->ir[dmach].xferq.flag & 0x3f; 1238103285Sikob 1239103285Sikob#if 0 1240103285Sikob if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){ 1241103285Sikob wakeup(fc->ir[dmach]); 1242103285Sikob return err; 1243103285Sikob } 1244103285Sikob#endif 1245103285Sikob 1246103285Sikob OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1247103285Sikob if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1248103285Sikob sc->ir[dmach].xferq.queued = 0; 1249103285Sikob sc->ir[dmach].ndb = NDB; 1250103285Sikob sc->ir[dmach].xferq.psize = FWPMAX_S400; 1251103285Sikob sc->ir[dmach].ndesc = 1; 1252103285Sikob fwohci_db_init(&sc->ir[dmach]); 1253109179Ssimokawa if ((sc->ir[dmach].flags & FWOHCI_DBCH_INIT) == 0) 1254109179Ssimokawa return ENOMEM; 1255103285Sikob err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1256103285Sikob } 1257103285Sikob if(err){ 1258103285Sikob device_printf(sc->fc.dev, "err in IRX setting\n"); 1259103285Sikob return err; 1260103285Sikob } 1261103285Sikob if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1262103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1263103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1264103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1265103285Sikob OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1266103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000); 1267103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1268103285Sikob OWRITE(sc, OHCI_IRCMD(dmach), 1269103285Sikob vtophys(sc->ir[dmach].top->db) | 1); 1270103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1271103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1272103285Sikob } 1273103285Sikob return err; 1274103285Sikob} 1275106790Ssimokawa 1276106790Ssimokawastatic int 1277106790Ssimokawafwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1278103285Sikob{ 1279103285Sikob int err = 0; 1280103285Sikob int idb, z, i, dmach = 0; 1281103285Sikob u_int32_t off = NULL; 1282103285Sikob struct fwohcidb_tr *db_tr; 1283103285Sikob 1284103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1285103285Sikob err = EINVAL; 1286103285Sikob return err; 1287103285Sikob } 1288103285Sikob z = dbch->ndesc; 1289103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1290103285Sikob if( &sc->it[dmach] == dbch){ 1291103285Sikob off = OHCI_ITOFF(dmach); 1292103285Sikob break; 1293103285Sikob } 1294103285Sikob } 1295103285Sikob if(off == NULL){ 1296103285Sikob err = EINVAL; 1297103285Sikob return err; 1298103285Sikob } 1299103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1300103285Sikob return err; 1301103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1302103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1303103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1304103285Sikob } 1305103285Sikob db_tr = dbch->top; 1306103285Sikob for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1307103285Sikob fwohci_add_tx_buf(db_tr, 1308103285Sikob dbch->xferq.psize, dbch->xferq.flag, 1309103285Sikob dbch->xferq.buf + dbch->xferq.psize * idb); 1310103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1311103285Sikob break; 1312103285Sikob } 1313103285Sikob db_tr->db[0].db.desc.depend 1314103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1315103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1316103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1317103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1318103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1319103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1320103285Sikob |= OHCI_INTERRUPT_ALWAYS; 1321103285Sikob db_tr->db[0].db.desc.depend &= ~0xf; 1322103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1323103285Sikob ~0xf; 1324103285Sikob } 1325103285Sikob } 1326103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1327103285Sikob } 1328103285Sikob dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1329103285Sikob return err; 1330103285Sikob} 1331106790Ssimokawa 1332106790Ssimokawastatic int 1333106790Ssimokawafwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1334103285Sikob{ 1335103285Sikob int err = 0; 1336103285Sikob int idb, z, i, dmach = 0; 1337103285Sikob u_int32_t off = NULL; 1338103285Sikob struct fwohcidb_tr *db_tr; 1339103285Sikob 1340103285Sikob z = dbch->ndesc; 1341103285Sikob if(&sc->arrq == dbch){ 1342103285Sikob off = OHCI_ARQOFF; 1343103285Sikob }else if(&sc->arrs == dbch){ 1344103285Sikob off = OHCI_ARSOFF; 1345103285Sikob }else{ 1346103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1347103285Sikob if( &sc->ir[dmach] == dbch){ 1348103285Sikob off = OHCI_IROFF(dmach); 1349103285Sikob break; 1350103285Sikob } 1351103285Sikob } 1352103285Sikob } 1353103285Sikob if(off == NULL){ 1354103285Sikob err = EINVAL; 1355103285Sikob return err; 1356103285Sikob } 1357103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1358103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1359103285Sikob return err; 1360103285Sikob }else{ 1361103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1362103285Sikob err = EBUSY; 1363103285Sikob return err; 1364103285Sikob } 1365103285Sikob } 1366103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1367108642Ssimokawa dbch->top = STAILQ_FIRST(&dbch->db_trq); 1368103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1369103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1370103285Sikob } 1371103285Sikob db_tr = dbch->top; 1372103285Sikob for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1373103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1374103285Sikob fwohci_add_rx_buf(db_tr, 1375103285Sikob dbch->xferq.psize, dbch->xferq.flag, 0, NULL); 1376103285Sikob }else{ 1377103285Sikob fwohci_add_rx_buf(db_tr, 1378103285Sikob dbch->xferq.psize, dbch->xferq.flag, 1379103285Sikob dbch->xferq.buf + dbch->xferq.psize * idb, 1380103285Sikob dbch->dummy + sizeof(u_int32_t) * idb); 1381103285Sikob } 1382103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1383103285Sikob break; 1384103285Sikob } 1385103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1386103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1387103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1388103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1389103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1390103285Sikob |= OHCI_INTERRUPT_ALWAYS; 1391103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1392103285Sikob ~0xf; 1393103285Sikob } 1394103285Sikob } 1395103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1396103285Sikob } 1397103285Sikob dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1398103285Sikob dbch->buf_offset = 0; 1399103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1400103285Sikob return err; 1401103285Sikob }else{ 1402103285Sikob OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z); 1403103285Sikob } 1404103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1405103285Sikob return err; 1406103285Sikob} 1407106790Ssimokawa 1408106790Ssimokawastatic int 1409106790Ssimokawafwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1410103285Sikob{ 1411103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1412103285Sikob int err = 0; 1413103285Sikob unsigned short tag, ich; 1414103285Sikob struct fwohci_dbch *dbch; 1415103285Sikob struct fw_pkt *fp; 1416103285Sikob struct fwohcidb_tr *db_tr; 1417103285Sikob 1418103285Sikob tag = (sc->it[dmach].xferq.flag >> 6) & 3; 1419103285Sikob ich = sc->it[dmach].xferq.flag & 0x3f; 1420103285Sikob dbch = &sc->it[dmach]; 1421109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1422103285Sikob dbch->xferq.queued = 0; 1423103285Sikob dbch->ndb = dbch->xferq.bnpacket * dbch->xferq.bnchunk; 1424103285Sikob dbch->ndesc = 3; 1425103285Sikob fwohci_db_init(dbch); 1426109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1427109179Ssimokawa return ENOMEM; 1428103285Sikob err = fwohci_tx_enable(sc, dbch); 1429103285Sikob } 1430103285Sikob if(err) 1431103285Sikob return err; 1432103285Sikob if(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){ 1433103285Sikob if(dbch->xferq.stdma2 != NULL){ 1434103285Sikob fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1435103285Sikob ((struct fwohcidb_tr *) 1436103285Sikob (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1437103285Sikob |= OHCI_BRANCH_ALWAYS; 1438103285Sikob ((struct fwohcidb_tr *) 1439103285Sikob (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1440103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1441103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1442103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1443103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1444103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1445103285Sikob } 1446103285Sikob }else if(!(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1447103285Sikob fw_tbuf_update(&sc->fc, dmach, 0); 1448103285Sikob if(dbch->xferq.stdma == NULL){ 1449103285Sikob return err; 1450103285Sikob } 1451103285Sikob OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1452103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1453103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1454103285Sikob OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1455103285Sikob OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xf0000000); 1456103285Sikob fwohci_txbufdb(sc, dmach, dbch->xferq.stdma); 1457103285Sikob if(dbch->xferq.stdma2 != NULL){ 1458103285Sikob fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1459103285Sikob ((struct fwohcidb_tr *) 1460103285Sikob (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1461103285Sikob |= OHCI_BRANCH_ALWAYS; 1462103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1463103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1464103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1465103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1466103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1467103285Sikob ((struct fwohcidb_tr *) (dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1468103285Sikob }else{ 1469103285Sikob ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1470103285Sikob ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1471103285Sikob } 1472103285Sikob OWRITE(sc, OHCI_ITCMD(dmach), 1473103285Sikob vtophys(((struct fwohcidb_tr *) 1474103285Sikob (dbch->xferq.stdma->start))->db) | dbch->ndesc); 1475103285Sikob if(dbch->xferq.flag & FWXFERQ_DV){ 1476103285Sikob db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1477103285Sikob fp = (struct fw_pkt *)db_tr->buf; 1478109179Ssimokawa dbch->xferq.dvoffset = 1479109179Ssimokawa ((fc->cyctimer(fc) >> 12) + 4) & 0xf; 1480109179Ssimokawa#if 0 1481109179Ssimokawa printf("dvoffset: %d\n", dbch->xferq.dvoffset); 1482109179Ssimokawa#endif 1483109179Ssimokawa fp->mode.ld[2] |= htonl(dbch->xferq.dvoffset << 12); 1484103285Sikob } 1485103285Sikob 1486103285Sikob OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1487103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1488103285Sikob } 1489103285Sikob return err; 1490103285Sikob} 1491106790Ssimokawa 1492106790Ssimokawastatic int 1493106790Ssimokawafwohci_irxbuf_enable(struct firewire_comm *fc, int dmach) 1494103285Sikob{ 1495103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1496103285Sikob int err = 0; 1497103285Sikob unsigned short tag, ich; 1498103285Sikob 1499103285Sikob if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1500108995Ssimokawa tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1501108995Ssimokawa ich = sc->ir[dmach].xferq.flag & 0x3f; 1502108995Ssimokawa OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1503108995Ssimokawa 1504103285Sikob sc->ir[dmach].xferq.queued = 0; 1505103285Sikob sc->ir[dmach].ndb = sc->ir[dmach].xferq.bnpacket * 1506103285Sikob sc->ir[dmach].xferq.bnchunk; 1507103285Sikob sc->ir[dmach].dummy = 1508103285Sikob malloc(sizeof(u_int32_t) * sc->ir[dmach].ndb, 1509103285Sikob M_DEVBUF, M_DONTWAIT); 1510103285Sikob if(sc->ir[dmach].dummy == NULL){ 1511103285Sikob err = ENOMEM; 1512103285Sikob return err; 1513103285Sikob } 1514103285Sikob sc->ir[dmach].ndesc = 2; 1515103285Sikob fwohci_db_init(&sc->ir[dmach]); 1516109179Ssimokawa if ((sc->ir[dmach].flags & FWOHCI_DBCH_INIT) == 0) 1517109179Ssimokawa return ENOMEM; 1518103285Sikob err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1519103285Sikob } 1520103285Sikob if(err) 1521103285Sikob return err; 1522103285Sikob 1523103285Sikob if(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){ 1524103285Sikob if(sc->ir[dmach].xferq.stdma2 != NULL){ 1525103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1526103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1527103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1528103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1529103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1530103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1531103285Sikob } 1532103285Sikob }else if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE) 1533103285Sikob && !(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET)){ 1534103285Sikob fw_rbuf_update(&sc->fc, dmach, 0); 1535103285Sikob 1536103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1537103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1538103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1539103285Sikob OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1540103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1541103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1542103285Sikob if(sc->ir[dmach].xferq.stdma2 != NULL){ 1543103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1544103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1545103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1546103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1547103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1548103285Sikob }else{ 1549103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1550103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1551103285Sikob } 1552103285Sikob OWRITE(sc, OHCI_IRCMD(dmach), 1553103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->start))->db) | sc->ir[dmach].ndesc); 1554103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1555108995Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1556103285Sikob } 1557103285Sikob return err; 1558103285Sikob} 1559106790Ssimokawa 1560106790Ssimokawastatic int 1561106790Ssimokawafwohci_irx_enable(struct firewire_comm *fc, int dmach) 1562103285Sikob{ 1563103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1564103285Sikob int err = 0; 1565103285Sikob 1566103285Sikob if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){ 1567103285Sikob err = fwohci_irxpp_enable(fc, dmach); 1568103285Sikob return err; 1569103285Sikob }else{ 1570103285Sikob err = fwohci_irxbuf_enable(fc, dmach); 1571103285Sikob return err; 1572103285Sikob } 1573103285Sikob} 1574106790Ssimokawa 1575106790Ssimokawaint 1576108642Ssimokawafwohci_shutdown(struct fwohci_softc *sc, device_t dev) 1577103285Sikob{ 1578103285Sikob u_int i; 1579103285Sikob 1580103285Sikob/* Now stopping all DMA channel */ 1581103285Sikob OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1582103285Sikob OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1583103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1584103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1585103285Sikob 1586103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1587103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1588103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1589103285Sikob } 1590103285Sikob 1591103285Sikob/* FLUSH FIFO and reset Transmitter/Reciever */ 1592103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1593103285Sikob 1594103285Sikob/* Stop interrupt */ 1595103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, 1596103285Sikob OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1597103285Sikob | OHCI_INT_PHY_INT 1598103285Sikob | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1599103285Sikob | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1600103285Sikob | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1601103285Sikob | OHCI_INT_PHY_BUS_R); 1602108642Ssimokawa/* XXX Link down? Bus reset? */ 1603103285Sikob return 0; 1604103285Sikob} 1605103285Sikob 1606108642Ssimokawaint 1607108642Ssimokawafwohci_resume(struct fwohci_softc *sc, device_t dev) 1608108642Ssimokawa{ 1609108642Ssimokawa int i; 1610108642Ssimokawa 1611108642Ssimokawa fwohci_reset(sc, dev); 1612108642Ssimokawa /* XXX resume isochronus receive automatically. (how about TX?) */ 1613108642Ssimokawa for(i = 0; i < sc->fc.nisodma; i ++) { 1614108642Ssimokawa if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) { 1615108642Ssimokawa device_printf(sc->fc.dev, 1616108642Ssimokawa "resume iso receive ch: %d\n", i); 1617108642Ssimokawa sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING; 1618108642Ssimokawa sc->fc.irx_enable(&sc->fc, i); 1619108642Ssimokawa } 1620108642Ssimokawa } 1621108642Ssimokawa 1622108642Ssimokawa bus_generic_resume(dev); 1623108642Ssimokawa sc->fc.ibr(&sc->fc); 1624108642Ssimokawa return 0; 1625108642Ssimokawa} 1626108642Ssimokawa 1627103285Sikob#define ACK_ALL 1628103285Sikobstatic void 1629106789Ssimokawafwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1630103285Sikob{ 1631103285Sikob u_int32_t irstat, itstat; 1632103285Sikob u_int i; 1633103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1634103285Sikob 1635103285Sikob#ifdef OHCI_DEBUG 1636103285Sikob if(stat & OREAD(sc, FWOHCI_INTMASK)) 1637103285Sikob device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1638103285Sikob stat & OHCI_INT_EN ? "DMA_EN ":"", 1639103285Sikob stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1640103285Sikob stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1641103285Sikob stat & OHCI_INT_ERR ? "INT_ERR ":"", 1642103285Sikob stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1643103285Sikob stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1644103285Sikob stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1645103285Sikob stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1646103285Sikob stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1647103285Sikob stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1648103285Sikob stat & OHCI_INT_PHY_SID ? "SID ":"", 1649103285Sikob stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1650103285Sikob stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1651103285Sikob stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1652103285Sikob stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1653103285Sikob stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1654103285Sikob stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1655103285Sikob stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1656103285Sikob stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1657103285Sikob stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1658103285Sikob stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1659103285Sikob stat, OREAD(sc, FWOHCI_INTMASK) 1660103285Sikob ); 1661103285Sikob#endif 1662103285Sikob/* Bus reset */ 1663103285Sikob if(stat & OHCI_INT_PHY_BUS_R ){ 1664103285Sikob device_printf(fc->dev, "BUS reset\n"); 1665103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1666103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1667103285Sikob 1668103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1669103285Sikob sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1670103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1671103285Sikob sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1672103285Sikob 1673103285Sikob#if 0 1674103285Sikob for( i = 0 ; i < fc->nisodma ; i ++ ){ 1675103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1676103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1677103285Sikob } 1678103285Sikob 1679103285Sikob#endif 1680103285Sikob fw_busreset(fc); 1681103285Sikob 1682103285Sikob /* XXX need to wait DMA to stop */ 1683103285Sikob#ifndef ACK_ALL 1684103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1685103285Sikob#endif 1686103285Sikob#if 1 1687103285Sikob /* pending all pre-bus_reset packets */ 1688103285Sikob fwohci_txd(sc, &sc->atrq); 1689103285Sikob fwohci_txd(sc, &sc->atrs); 1690106789Ssimokawa fwohci_arcv(sc, &sc->arrs, -1); 1691106789Ssimokawa fwohci_arcv(sc, &sc->arrq, -1); 1692103285Sikob#endif 1693103285Sikob 1694103285Sikob 1695103285Sikob OWRITE(sc, OHCI_AREQHI, 1 << 31); 1696103285Sikob /* XXX insecure ?? */ 1697103285Sikob OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1698103285Sikob OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1699103285Sikob OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1700103285Sikob 1701103285Sikob } 1702103285Sikob if((stat & OHCI_INT_DMA_IR )){ 1703103285Sikob#ifndef ACK_ALL 1704103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1705103285Sikob#endif 1706103285Sikob irstat = OREAD(sc, OHCI_IR_STAT); 1707103285Sikob OWRITE(sc, OHCI_IR_STATCLR, ~0); 1708103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1709103285Sikob if((irstat & (1 << i)) != 0){ 1710103285Sikob if(sc->ir[i].xferq.flag & FWXFERQ_PACKET){ 1711106789Ssimokawa fwohci_ircv(sc, &sc->ir[i], count); 1712103285Sikob }else{ 1713103285Sikob fwohci_rbuf_update(sc, i); 1714103285Sikob } 1715103285Sikob } 1716103285Sikob } 1717103285Sikob } 1718103285Sikob if((stat & OHCI_INT_DMA_IT )){ 1719103285Sikob#ifndef ACK_ALL 1720103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1721103285Sikob#endif 1722103285Sikob itstat = OREAD(sc, OHCI_IT_STAT); 1723103285Sikob OWRITE(sc, OHCI_IT_STATCLR, ~0); 1724103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1725103285Sikob if((itstat & (1 << i)) != 0){ 1726103285Sikob fwohci_tbuf_update(sc, i); 1727103285Sikob } 1728103285Sikob } 1729103285Sikob } 1730103285Sikob if((stat & OHCI_INT_DMA_PRRS )){ 1731103285Sikob#ifndef ACK_ALL 1732103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1733103285Sikob#endif 1734103285Sikob#if 0 1735103285Sikob dump_dma(sc, ARRS_CH); 1736103285Sikob dump_db(sc, ARRS_CH); 1737103285Sikob#endif 1738106789Ssimokawa fwohci_arcv(sc, &sc->arrs, count); 1739103285Sikob } 1740103285Sikob if((stat & OHCI_INT_DMA_PRRQ )){ 1741103285Sikob#ifndef ACK_ALL 1742103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1743103285Sikob#endif 1744103285Sikob#if 0 1745103285Sikob dump_dma(sc, ARRQ_CH); 1746103285Sikob dump_db(sc, ARRQ_CH); 1747103285Sikob#endif 1748106789Ssimokawa fwohci_arcv(sc, &sc->arrq, count); 1749103285Sikob } 1750103285Sikob if(stat & OHCI_INT_PHY_SID){ 1751103285Sikob caddr_t buf; 1752103285Sikob int plen; 1753103285Sikob 1754103285Sikob#ifndef ACK_ALL 1755103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1756103285Sikob#endif 1757103285Sikob/* 1758103285Sikob** Checking whether the node is root or not. If root, turn on 1759103285Sikob** cycle master. 1760103285Sikob*/ 1761103285Sikob device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID)); 1762103285Sikob if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){ 1763103285Sikob printf("Bus reset failure\n"); 1764103285Sikob goto sidout; 1765103285Sikob } 1766103285Sikob if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){ 1767103285Sikob printf("CYCLEMASTER mode\n"); 1768103285Sikob OWRITE(sc, OHCI_LNKCTL, 1769103285Sikob OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1770103285Sikob }else{ 1771103285Sikob printf("non CYCLEMASTER mode\n"); 1772103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1773103285Sikob OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1774103285Sikob } 1775103285Sikob fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f; 1776103285Sikob 1777103285Sikob plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK; 1778103285Sikob plen -= 4; /* chop control info */ 1779103285Sikob buf = malloc( FWPMAX_S400, M_DEVBUF, M_NOWAIT); 1780103285Sikob if(buf == NULL) goto sidout; 1781108530Ssimokawa bcopy((void *)(uintptr_t)(volatile void *)(fc->sid_buf + 1), 1782103285Sikob buf, plen); 1783103285Sikob fw_sidrcv(fc, buf, plen, 0); 1784103285Sikob } 1785103285Sikobsidout: 1786103285Sikob if((stat & OHCI_INT_DMA_ATRQ )){ 1787103285Sikob#ifndef ACK_ALL 1788103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1789103285Sikob#endif 1790103285Sikob fwohci_txd(sc, &(sc->atrq)); 1791103285Sikob } 1792103285Sikob if((stat & OHCI_INT_DMA_ATRS )){ 1793103285Sikob#ifndef ACK_ALL 1794103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1795103285Sikob#endif 1796103285Sikob fwohci_txd(sc, &(sc->atrs)); 1797103285Sikob } 1798103285Sikob if((stat & OHCI_INT_PW_ERR )){ 1799103285Sikob#ifndef ACK_ALL 1800103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1801103285Sikob#endif 1802103285Sikob device_printf(fc->dev, "posted write error\n"); 1803103285Sikob } 1804103285Sikob if((stat & OHCI_INT_ERR )){ 1805103285Sikob#ifndef ACK_ALL 1806103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1807103285Sikob#endif 1808103285Sikob device_printf(fc->dev, "unrecoverable error\n"); 1809103285Sikob } 1810103285Sikob if((stat & OHCI_INT_PHY_INT)) { 1811103285Sikob#ifndef ACK_ALL 1812103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1813103285Sikob#endif 1814103285Sikob device_printf(fc->dev, "phy int\n"); 1815103285Sikob } 1816103285Sikob 1817103285Sikob return; 1818103285Sikob} 1819103285Sikob 1820103285Sikobvoid 1821103285Sikobfwohci_intr(void *arg) 1822103285Sikob{ 1823103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1824103285Sikob u_int32_t stat; 1825103285Sikob 1826103285Sikob if (!(sc->intmask & OHCI_INT_EN)) { 1827103285Sikob /* polling mode */ 1828103285Sikob return; 1829103285Sikob } 1830103285Sikob 1831103285Sikob while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) { 1832103285Sikob if (stat == 0xffffffff) { 1833103285Sikob device_printf(sc->fc.dev, 1834103285Sikob "device physically ejected?\n"); 1835103285Sikob return; 1836103285Sikob } 1837103285Sikob#ifdef ACK_ALL 1838103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1839103285Sikob#endif 1840106789Ssimokawa fwohci_intr_body(sc, stat, -1); 1841103285Sikob } 1842103285Sikob} 1843103285Sikob 1844103285Sikobstatic void 1845103285Sikobfwohci_poll(struct firewire_comm *fc, int quick, int count) 1846103285Sikob{ 1847103285Sikob int s; 1848103285Sikob u_int32_t stat; 1849103285Sikob struct fwohci_softc *sc; 1850103285Sikob 1851103285Sikob 1852103285Sikob sc = (struct fwohci_softc *)fc; 1853103285Sikob stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 1854103285Sikob OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 1855103285Sikob OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 1856103285Sikob#if 0 1857103285Sikob if (!quick) { 1858103285Sikob#else 1859103285Sikob if (1) { 1860103285Sikob#endif 1861103285Sikob stat = OREAD(sc, FWOHCI_INTSTAT); 1862103285Sikob if (stat == 0) 1863103285Sikob return; 1864103285Sikob if (stat == 0xffffffff) { 1865103285Sikob device_printf(sc->fc.dev, 1866103285Sikob "device physically ejected?\n"); 1867103285Sikob return; 1868103285Sikob } 1869103285Sikob#ifdef ACK_ALL 1870103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1871103285Sikob#endif 1872103285Sikob } 1873103285Sikob s = splfw(); 1874106789Ssimokawa fwohci_intr_body(sc, stat, count); 1875103285Sikob splx(s); 1876103285Sikob} 1877103285Sikob 1878103285Sikobstatic void 1879103285Sikobfwohci_set_intr(struct firewire_comm *fc, int enable) 1880103285Sikob{ 1881103285Sikob struct fwohci_softc *sc; 1882103285Sikob 1883103285Sikob sc = (struct fwohci_softc *)fc; 1884107653Ssimokawa if (bootverbose) 1885108642Ssimokawa device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 1886103285Sikob if (enable) { 1887103285Sikob sc->intmask |= OHCI_INT_EN; 1888103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 1889103285Sikob } else { 1890103285Sikob sc->intmask &= ~OHCI_INT_EN; 1891103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 1892103285Sikob } 1893103285Sikob} 1894103285Sikob 1895106790Ssimokawastatic void 1896106790Ssimokawafwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 1897103285Sikob{ 1898103285Sikob int stat; 1899103285Sikob struct firewire_comm *fc = &sc->fc; 1900103285Sikob struct fw_pkt *fp; 1901103285Sikob struct fwohci_dbch *dbch; 1902103285Sikob struct fwohcidb_tr *db_tr; 1903103285Sikob 1904103285Sikob dbch = &sc->it[dmach]; 1905109179Ssimokawa#if 0 /* XXX OHCI interrupt before the last packet is really on the wire */ 1906103285Sikob if((dbch->xferq.flag & FWXFERQ_DV) && (dbch->xferq.stdma2 != NULL)){ 1907103285Sikob db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma2->start; 1908103285Sikob/* 1909103285Sikob * Overwrite highest significant 4 bits timestamp information 1910103285Sikob */ 1911103285Sikob fp = (struct fw_pkt *)db_tr->buf; 1912109179Ssimokawa fp->mode.ld[2] &= htonl(0xffff0fff); 1913109179Ssimokawa fp->mode.ld[2] |= htonl((fc->cyctimer(fc) + 0x4000) & 0xf000); 1914103285Sikob } 1915109179Ssimokawa#endif 1916103285Sikob stat = OREAD(sc, OHCI_ITCTL(dmach)) & 0x1f; 1917103285Sikob switch(stat){ 1918103285Sikob case FWOHCIEV_ACKCOMPL: 1919109179Ssimokawa#if 1 1920109179Ssimokawa if (dbch->xferq.flag & FWXFERQ_DV) { 1921109179Ssimokawa struct ciphdr *ciph; 1922109179Ssimokawa int timer, timestamp, cycl, diff; 1923109179Ssimokawa static int last_timer=0; 1924109179Ssimokawa 1925109179Ssimokawa timer = (fc->cyctimer(fc) >> 12) & 0xffff; 1926109179Ssimokawa db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1927109179Ssimokawa fp = (struct fw_pkt *)db_tr->buf; 1928109179Ssimokawa ciph = (struct ciphdr *) &fp->mode.ld[1]; 1929109179Ssimokawa timestamp = db_tr->db[2].db.desc.count & 0xffff; 1930109179Ssimokawa cycl = ntohs(ciph->fdf.dv.cyc) >> 12; 1931109179Ssimokawa diff = cycl - (timestamp & 0xf) - 1; 1932109179Ssimokawa if (diff < 0) 1933109179Ssimokawa diff += 16; 1934109179Ssimokawa if (diff > 8) 1935109179Ssimokawa diff -= 16; 1936109179Ssimokawa if (firewire_debug) 1937109179Ssimokawa printf("dbc: %3d timer: 0x%04x packet: 0x%04x" 1938109179Ssimokawa " cyc: 0x%x diff: %+1d\n", 1939109179Ssimokawa ciph->dbc, last_timer, timestamp, cycl, diff); 1940109179Ssimokawa last_timer = timer; 1941109179Ssimokawa /* XXX adjust dbch->xferq.dvoffset if diff != 0 or 1 */ 1942109179Ssimokawa } 1943109179Ssimokawa#endif 1944103285Sikob fw_tbuf_update(fc, dmach, 1); 1945103285Sikob break; 1946103285Sikob default: 1947109179Ssimokawa device_printf(fc->dev, "Isochronous transmit err %02x\n", stat); 1948103285Sikob fw_tbuf_update(fc, dmach, 0); 1949103285Sikob break; 1950103285Sikob } 1951109179Ssimokawa fwohci_itxbuf_enable(fc, dmach); 1952103285Sikob} 1953106790Ssimokawa 1954106790Ssimokawastatic void 1955106790Ssimokawafwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 1956103285Sikob{ 1957109179Ssimokawa struct firewire_comm *fc = &sc->fc; 1958103285Sikob int stat; 1959109179Ssimokawa 1960103285Sikob stat = OREAD(sc, OHCI_IRCTL(dmach)) & 0x1f; 1961103285Sikob switch(stat){ 1962103285Sikob case FWOHCIEV_ACKCOMPL: 1963109179Ssimokawa fw_rbuf_update(fc, dmach, 1); 1964109179Ssimokawa wakeup(fc->ir[dmach]); 1965109179Ssimokawa fwohci_irx_enable(fc, dmach); 1966103285Sikob break; 1967103285Sikob default: 1968109179Ssimokawa device_printf(fc->dev, "Isochronous receive err %02x\n", 1969109179Ssimokawa stat); 1970103285Sikob break; 1971103285Sikob } 1972103285Sikob} 1973106790Ssimokawa 1974106790Ssimokawavoid 1975106790Ssimokawadump_dma(struct fwohci_softc *sc, u_int32_t ch) 1976106790Ssimokawa{ 1977103285Sikob u_int32_t off, cntl, stat, cmd, match; 1978103285Sikob 1979103285Sikob if(ch == 0){ 1980103285Sikob off = OHCI_ATQOFF; 1981103285Sikob }else if(ch == 1){ 1982103285Sikob off = OHCI_ATSOFF; 1983103285Sikob }else if(ch == 2){ 1984103285Sikob off = OHCI_ARQOFF; 1985103285Sikob }else if(ch == 3){ 1986103285Sikob off = OHCI_ARSOFF; 1987103285Sikob }else if(ch < IRX_CH){ 1988103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 1989103285Sikob }else{ 1990103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 1991103285Sikob } 1992103285Sikob cntl = stat = OREAD(sc, off); 1993103285Sikob cmd = OREAD(sc, off + 0xc); 1994103285Sikob match = OREAD(sc, off + 0x10); 1995103285Sikob 1996103285Sikob device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n", 1997103285Sikob ch, 1998103285Sikob cntl, 1999103285Sikob stat, 2000103285Sikob cmd, 2001103285Sikob match); 2002103285Sikob stat &= 0xffff ; 2003103285Sikob if(stat & 0xff00){ 2004103285Sikob device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2005103285Sikob ch, 2006103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2007103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2008103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2009103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2010103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2011103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2012103285Sikob fwohcicode[stat & 0x1f], 2013103285Sikob stat & 0x1f 2014103285Sikob ); 2015103285Sikob }else{ 2016103285Sikob device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2017103285Sikob } 2018103285Sikob} 2019106790Ssimokawa 2020106790Ssimokawavoid 2021106790Ssimokawadump_db(struct fwohci_softc *sc, u_int32_t ch) 2022106790Ssimokawa{ 2023103285Sikob struct fwohci_dbch *dbch; 2024103285Sikob struct fwohcidb_tr *cp = NULL, *pp, *np; 2025103285Sikob volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2026103285Sikob int idb, jdb; 2027103285Sikob u_int32_t cmd, off; 2028103285Sikob if(ch == 0){ 2029103285Sikob off = OHCI_ATQOFF; 2030103285Sikob dbch = &sc->atrq; 2031103285Sikob }else if(ch == 1){ 2032103285Sikob off = OHCI_ATSOFF; 2033103285Sikob dbch = &sc->atrs; 2034103285Sikob }else if(ch == 2){ 2035103285Sikob off = OHCI_ARQOFF; 2036103285Sikob dbch = &sc->arrq; 2037103285Sikob }else if(ch == 3){ 2038103285Sikob off = OHCI_ARSOFF; 2039103285Sikob dbch = &sc->arrs; 2040103285Sikob }else if(ch < IRX_CH){ 2041103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2042103285Sikob dbch = &sc->it[ch - ITX_CH]; 2043103285Sikob }else { 2044103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2045103285Sikob dbch = &sc->ir[ch - IRX_CH]; 2046103285Sikob } 2047103285Sikob cmd = OREAD(sc, off + 0xc); 2048103285Sikob 2049103285Sikob if( dbch->ndb == 0 ){ 2050103285Sikob device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2051103285Sikob return; 2052103285Sikob } 2053103285Sikob pp = dbch->top; 2054103285Sikob prev = pp->db; 2055103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2056103285Sikob if(pp == NULL){ 2057103285Sikob curr = NULL; 2058103285Sikob goto outdb; 2059103285Sikob } 2060103285Sikob cp = STAILQ_NEXT(pp, link); 2061103285Sikob if(cp == NULL){ 2062103285Sikob curr = NULL; 2063103285Sikob goto outdb; 2064103285Sikob } 2065103285Sikob np = STAILQ_NEXT(cp, link); 2066103285Sikob if(cp == NULL) break; 2067103285Sikob for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2068103285Sikob if((cmd & 0xfffffff0) 2069103285Sikob == vtophys(&(cp->db[jdb]))){ 2070103285Sikob curr = cp->db; 2071103285Sikob if(np != NULL){ 2072103285Sikob next = np->db; 2073103285Sikob }else{ 2074103285Sikob next = NULL; 2075103285Sikob } 2076103285Sikob goto outdb; 2077103285Sikob } 2078103285Sikob } 2079103285Sikob pp = STAILQ_NEXT(pp, link); 2080103285Sikob prev = pp->db; 2081103285Sikob } 2082103285Sikoboutdb: 2083103285Sikob if( curr != NULL){ 2084103285Sikob printf("Prev DB %d\n", ch); 2085103285Sikob print_db(prev, ch, dbch->ndesc); 2086103285Sikob printf("Current DB %d\n", ch); 2087103285Sikob print_db(curr, ch, dbch->ndesc); 2088103285Sikob printf("Next DB %d\n", ch); 2089103285Sikob print_db(next, ch, dbch->ndesc); 2090103285Sikob }else{ 2091103285Sikob printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2092103285Sikob } 2093103285Sikob return; 2094103285Sikob} 2095106790Ssimokawa 2096106790Ssimokawavoid 2097106790Ssimokawaprint_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max) 2098106790Ssimokawa{ 2099103285Sikob fwohcireg_t stat; 2100103285Sikob int i, key; 2101103285Sikob 2102103285Sikob if(db == NULL){ 2103103285Sikob printf("No Descriptor is found\n"); 2104103285Sikob return; 2105103285Sikob } 2106103285Sikob 2107103285Sikob printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2108103285Sikob ch, 2109103285Sikob "Current", 2110103285Sikob "OP ", 2111103285Sikob "KEY", 2112103285Sikob "INT", 2113103285Sikob "BR ", 2114103285Sikob "len", 2115103285Sikob "Addr", 2116103285Sikob "Depend", 2117103285Sikob "Stat", 2118103285Sikob "Cnt"); 2119103285Sikob for( i = 0 ; i <= max ; i ++){ 2120103285Sikob key = db[i].db.desc.cmd & OHCI_KEY_MASK; 2121108712Ssimokawa#if __FreeBSD_version >= 500000 2122106543Ssimokawa printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x", 2123108712Ssimokawa#else 2124108712Ssimokawa printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2125108712Ssimokawa#endif 2126103285Sikob vtophys(&db[i]), 2127103285Sikob dbcode[(db[i].db.desc.cmd >> 28) & 0xf], 2128103285Sikob dbkey[(db[i].db.desc.cmd >> 24) & 0x7], 2129103285Sikob dbcond[(db[i].db.desc.cmd >> 20) & 0x3], 2130103285Sikob dbcond[(db[i].db.desc.cmd >> 18) & 0x3], 2131103285Sikob db[i].db.desc.cmd & 0xffff, 2132103285Sikob db[i].db.desc.addr, 2133103285Sikob db[i].db.desc.depend, 2134103285Sikob db[i].db.desc.status, 2135103285Sikob db[i].db.desc.count); 2136103285Sikob stat = db[i].db.desc.status; 2137103285Sikob if(stat & 0xff00){ 2138103285Sikob printf(" %s%s%s%s%s%s %s(%x)\n", 2139103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2140103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2141103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2142103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2143103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2144103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2145103285Sikob fwohcicode[stat & 0x1f], 2146103285Sikob stat & 0x1f 2147103285Sikob ); 2148103285Sikob }else{ 2149103285Sikob printf(" Nostat\n"); 2150103285Sikob } 2151103285Sikob if(key == OHCI_KEY_ST2 ){ 2152103285Sikob printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2153103285Sikob db[i+1].db.immed[0], 2154103285Sikob db[i+1].db.immed[1], 2155103285Sikob db[i+1].db.immed[2], 2156103285Sikob db[i+1].db.immed[3]); 2157103285Sikob } 2158103285Sikob if(key == OHCI_KEY_DEVICE){ 2159103285Sikob return; 2160103285Sikob } 2161103285Sikob if((db[i].db.desc.cmd & OHCI_BRANCH_MASK) 2162103285Sikob == OHCI_BRANCH_ALWAYS){ 2163103285Sikob return; 2164103285Sikob } 2165103285Sikob if((db[i].db.desc.cmd & OHCI_CMD_MASK) 2166103285Sikob == OHCI_OUTPUT_LAST){ 2167103285Sikob return; 2168103285Sikob } 2169103285Sikob if((db[i].db.desc.cmd & OHCI_CMD_MASK) 2170103285Sikob == OHCI_INPUT_LAST){ 2171103285Sikob return; 2172103285Sikob } 2173103285Sikob if(key == OHCI_KEY_ST2 ){ 2174103285Sikob i++; 2175103285Sikob } 2176103285Sikob } 2177103285Sikob return; 2178103285Sikob} 2179106790Ssimokawa 2180106790Ssimokawavoid 2181106790Ssimokawafwohci_ibr(struct firewire_comm *fc) 2182103285Sikob{ 2183103285Sikob struct fwohci_softc *sc; 2184103285Sikob u_int32_t fun; 2185103285Sikob 2186103285Sikob sc = (struct fwohci_softc *)fc; 2187108276Ssimokawa 2188108276Ssimokawa /* 2189108276Ssimokawa * Set root hold-off bit so that non cyclemaster capable node 2190108276Ssimokawa * shouldn't became the root node. 2191108276Ssimokawa */ 2192108276Ssimokawa fun = fwphy_rddata(sc, FW_PHY_RHB_REG); 2193108276Ssimokawa fun |= FW_PHY_RHB; 2194108276Ssimokawa fun = fwphy_wrdata(sc, FW_PHY_RHB_REG, fun); 2195103285Sikob#if 1 2196103285Sikob fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2197103285Sikob fun |= FW_PHY_IBR; 2198103285Sikob fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2199103285Sikob#else 2200103285Sikob fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2201103285Sikob fun |= FW_PHY_ISBR; 2202103285Sikob fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2203103285Sikob#endif 2204103285Sikob} 2205106790Ssimokawa 2206106790Ssimokawavoid 2207106790Ssimokawafwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2208103285Sikob{ 2209103285Sikob struct fwohcidb_tr *db_tr, *fdb_tr; 2210103285Sikob struct fwohci_dbch *dbch; 2211103285Sikob struct fw_pkt *fp; 2212103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 2213103285Sikob unsigned short chtag; 2214103285Sikob int idb; 2215103285Sikob 2216103285Sikob dbch = &sc->it[dmach]; 2217103285Sikob chtag = sc->it[dmach].xferq.flag & 0xff; 2218103285Sikob 2219103285Sikob db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2220103285Sikob fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2221103285Sikob/* 2222103285Sikobdevice_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2223103285Sikob*/ 2224103285Sikob if(bulkxfer->flag != 0){ 2225103285Sikob return; 2226103285Sikob } 2227103285Sikob bulkxfer->flag = 1; 2228103285Sikob for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){ 2229103285Sikob db_tr->db[0].db.desc.cmd 2230103285Sikob = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2231103285Sikob fp = (struct fw_pkt *)db_tr->buf; 2232103285Sikob ohcifp = (volatile struct fwohci_txpkthdr *) 2233103285Sikob db_tr->db[1].db.immed; 2234103285Sikob ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]); 2235103285Sikob ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 2236103285Sikob ohcifp->mode.stream.chtag = chtag; 2237103285Sikob ohcifp->mode.stream.tcode = 0xa; 2238103285Sikob ohcifp->mode.stream.spd = 4; 2239103285Sikob ohcifp->mode.ld[2] = ntohl(fp->mode.ld[1]); 2240103285Sikob ohcifp->mode.ld[3] = ntohl(fp->mode.ld[2]); 2241103285Sikob 2242103285Sikob db_tr->db[2].db.desc.cmd 2243103285Sikob = OHCI_OUTPUT_LAST 2244103285Sikob | OHCI_UPDATE 2245103285Sikob | OHCI_BRANCH_ALWAYS 2246103285Sikob | ((ntohs(fp->mode.stream.len) ) & 0xffff); 2247103285Sikob db_tr->db[2].db.desc.status = 0; 2248103285Sikob db_tr->db[2].db.desc.count = 0; 2249103285Sikob if(dbch->xferq.flag & FWXFERQ_DV){ 2250103285Sikob db_tr->db[0].db.desc.depend 2251103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2252103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.depend 2253103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2254103285Sikob }else{ 2255103285Sikob db_tr->db[0].db.desc.depend 2256103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2257103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.depend 2258103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2259103285Sikob } 2260103285Sikob bulkxfer->end = (caddr_t)db_tr; 2261103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2262103285Sikob } 2263103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->end; 2264103285Sikob db_tr->db[0].db.desc.depend &= ~0xf; 2265103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 2266103285Sikob/**/ 2267103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.cmd &= ~OHCI_BRANCH_ALWAYS; 2268103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_BRANCH_NEVER; 2269103285Sikob/**/ 2270103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS; 2271103285Sikob 2272103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2273103285Sikob fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2274103285Sikob/* 2275103285Sikobdevice_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2276103285Sikob*/ 2277103285Sikob return; 2278103285Sikob} 2279106790Ssimokawa 2280106790Ssimokawastatic int 2281106790Ssimokawafwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size, 2282106790Ssimokawa int mode, void *buf) 2283103285Sikob{ 2284103285Sikob volatile struct fwohcidb *db = db_tr->db; 2285103285Sikob int err = 0; 2286103285Sikob if(buf == 0){ 2287103285Sikob err = EINVAL; 2288103285Sikob return err; 2289103285Sikob } 2290103285Sikob db_tr->buf = buf; 2291103285Sikob db_tr->dbcnt = 3; 2292103285Sikob db_tr->dummy = NULL; 2293103285Sikob 2294103285Sikob db[0].db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2295103285Sikob 2296103285Sikob db[2].db.desc.depend = 0; 2297103285Sikob db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t); 2298103285Sikob db[2].db.desc.cmd = OHCI_OUTPUT_MORE; 2299103285Sikob 2300103285Sikob db[0].db.desc.status = 0; 2301103285Sikob db[0].db.desc.count = 0; 2302103285Sikob 2303103285Sikob db[2].db.desc.status = 0; 2304103285Sikob db[2].db.desc.count = 0; 2305103285Sikob if( mode & FWXFERQ_STREAM ){ 2306103285Sikob db[2].db.desc.cmd |= OHCI_OUTPUT_LAST; 2307103285Sikob if(mode & FWXFERQ_PACKET ){ 2308103285Sikob db[2].db.desc.cmd 2309103285Sikob |= OHCI_INTERRUPT_ALWAYS; 2310103285Sikob } 2311103285Sikob } 2312103285Sikob db[2].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2313103285Sikob return 1; 2314103285Sikob} 2315106790Ssimokawa 2316106790Ssimokawaint 2317106790Ssimokawafwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode, 2318106790Ssimokawa void *buf, void *dummy) 2319103285Sikob{ 2320103285Sikob volatile struct fwohcidb *db = db_tr->db; 2321103285Sikob int i; 2322103285Sikob void *dbuf[2]; 2323103285Sikob int dsiz[2]; 2324103285Sikob 2325103285Sikob if(buf == 0){ 2326103285Sikob buf = malloc(size, M_DEVBUF, M_NOWAIT); 2327103285Sikob if(buf == NULL) return 0; 2328103285Sikob db_tr->buf = buf; 2329103285Sikob db_tr->dbcnt = 1; 2330103285Sikob db_tr->dummy = NULL; 2331103285Sikob dsiz[0] = size; 2332103285Sikob dbuf[0] = buf; 2333103285Sikob }else if(dummy == NULL){ 2334103285Sikob db_tr->buf = buf; 2335103285Sikob db_tr->dbcnt = 1; 2336103285Sikob db_tr->dummy = NULL; 2337103285Sikob dsiz[0] = size; 2338103285Sikob dbuf[0] = buf; 2339103285Sikob }else{ 2340103285Sikob db_tr->buf = buf; 2341103285Sikob db_tr->dbcnt = 2; 2342103285Sikob db_tr->dummy = dummy; 2343103285Sikob dsiz[0] = sizeof(u_int32_t); 2344103285Sikob dsiz[1] = size; 2345103285Sikob dbuf[0] = dummy; 2346103285Sikob dbuf[1] = buf; 2347103285Sikob } 2348103285Sikob for(i = 0 ; i < db_tr->dbcnt ; i++){ 2349103285Sikob db[i].db.desc.addr = vtophys(dbuf[i]) ; 2350103285Sikob db[i].db.desc.cmd = OHCI_INPUT_MORE | dsiz[i]; 2351103285Sikob if( mode & FWXFERQ_STREAM ){ 2352103285Sikob db[i].db.desc.cmd |= OHCI_UPDATE; 2353103285Sikob } 2354103285Sikob db[i].db.desc.status = 0; 2355103285Sikob db[i].db.desc.count = dsiz[i]; 2356103285Sikob } 2357103285Sikob if( mode & FWXFERQ_STREAM ){ 2358103285Sikob db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_INPUT_LAST; 2359103285Sikob if(mode & FWXFERQ_PACKET ){ 2360103285Sikob db[db_tr->dbcnt - 1].db.desc.cmd 2361103285Sikob |= OHCI_INTERRUPT_ALWAYS; 2362103285Sikob } 2363103285Sikob } 2364103285Sikob db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2365103285Sikob return 1; 2366103285Sikob} 2367106790Ssimokawa 2368106790Ssimokawastatic void 2369106790Ssimokawafwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2370103285Sikob{ 2371103285Sikob struct fwohcidb_tr *db_tr = dbch->top, *odb_tr; 2372103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 2373103285Sikob int z = 1; 2374103285Sikob struct fw_pkt *fp; 2375103285Sikob u_int8_t *ld; 2376103285Sikob u_int32_t off = NULL; 2377103285Sikob u_int32_t stat; 2378103285Sikob u_int32_t *qld; 2379103285Sikob u_int32_t reg; 2380103285Sikob u_int spd; 2381103285Sikob u_int dmach; 2382103285Sikob int len, i, plen; 2383103285Sikob caddr_t buf; 2384103285Sikob 2385103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 2386103285Sikob if( &sc->ir[dmach] == dbch){ 2387103285Sikob off = OHCI_IROFF(dmach); 2388103285Sikob break; 2389103285Sikob } 2390103285Sikob } 2391103285Sikob if(off == NULL){ 2392103285Sikob return; 2393103285Sikob } 2394103285Sikob if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){ 2395103285Sikob fwohci_irx_disable(&sc->fc, dmach); 2396103285Sikob return; 2397103285Sikob } 2398103285Sikob 2399103285Sikob odb_tr = NULL; 2400103285Sikob db_tr = dbch->top; 2401103285Sikob i = 0; 2402103285Sikob while ((reg = db_tr->db[0].db.desc.status) & 0x1f) { 2403106789Ssimokawa if (count >= 0 && count-- == 0) 2404106789Ssimokawa break; 2405103285Sikob ld = (u_int8_t *)db_tr->buf; 2406103285Sikob if (dbch->xferq.flag & FWXFERQ_PACKET) { 2407103285Sikob /* skip timeStamp */ 2408103285Sikob ld += sizeof(struct fwohci_trailer); 2409103285Sikob } 2410103285Sikob qld = (u_int32_t *)ld; 2411103285Sikob len = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2412103285Sikob/* 2413103285Sikob{ 2414103285Sikobdevice_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len, 2415103285Sikob db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]); 2416103285Sikob} 2417103285Sikob*/ 2418103285Sikob fp=(struct fw_pkt *)ld; 2419103285Sikob qld[0] = htonl(qld[0]); 2420103285Sikob plen = sizeof(struct fw_isohdr) 2421103285Sikob + ntohs(fp->mode.stream.len) + sizeof(u_int32_t); 2422103285Sikob ld += plen; 2423103285Sikob len -= plen; 2424103285Sikob buf = db_tr->buf; 2425103285Sikob db_tr->buf = NULL; 2426103285Sikob stat = reg & 0x1f; 2427103285Sikob spd = reg & 0x3; 2428103285Sikob switch(stat){ 2429103285Sikob case FWOHCIEV_ACKCOMPL: 2430103285Sikob case FWOHCIEV_ACKPEND: 2431103285Sikob fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd); 2432103285Sikob break; 2433103285Sikob default: 2434103285Sikob free(buf, M_DEVBUF); 2435103285Sikob device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat); 2436103285Sikob break; 2437103285Sikob } 2438103285Sikob i++; 2439103285Sikob fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2440103285Sikob dbch->xferq.flag, 0, NULL); 2441103285Sikob db_tr->db[0].db.desc.depend &= ~0xf; 2442103285Sikob if(dbch->pdb_tr != NULL){ 2443103285Sikob dbch->pdb_tr->db[0].db.desc.depend |= z; 2444103285Sikob } else { 2445103285Sikob /* XXX should be rewritten in better way */ 2446103285Sikob dbch->bottom->db[0].db.desc.depend |= z; 2447103285Sikob } 2448103285Sikob dbch->pdb_tr = db_tr; 2449103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2450103285Sikob } 2451103285Sikob dbch->top = db_tr; 2452103285Sikob reg = OREAD(sc, OHCI_DMACTL(off)); 2453103285Sikob if (reg & OHCI_CNTL_DMA_ACTIVE) 2454103285Sikob return; 2455103285Sikob device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n", 2456103285Sikob dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i); 2457103285Sikob dbch->top = db_tr; 2458103285Sikob fwohci_irx_enable(fc, dmach); 2459103285Sikob} 2460103285Sikob 2461103285Sikob#define PLEN(x) (((ntohs(x))+0x3) & ~0x3) 2462103285Sikobstatic int 2463103285Sikobfwohci_get_plen(struct fwohci_softc *sc, struct fw_pkt *fp, int hlen) 2464103285Sikob{ 2465103285Sikob int i; 2466103285Sikob 2467103285Sikob for( i = 4; i < hlen ; i+=4){ 2468103285Sikob fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]); 2469103285Sikob } 2470103285Sikob 2471103285Sikob switch(fp->mode.common.tcode){ 2472103285Sikob case FWTCODE_RREQQ: 2473103285Sikob return sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2474103285Sikob case FWTCODE_WRES: 2475103285Sikob return sizeof(fp->mode.wres) + sizeof(u_int32_t); 2476103285Sikob case FWTCODE_WREQQ: 2477103285Sikob return sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2478103285Sikob case FWTCODE_RREQB: 2479103285Sikob return sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2480103285Sikob case FWTCODE_RRESQ: 2481103285Sikob return sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2482103285Sikob case FWTCODE_WREQB: 2483103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2484103285Sikob + sizeof(u_int32_t); 2485103285Sikob case FWTCODE_LREQ: 2486103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2487103285Sikob + sizeof(u_int32_t); 2488103285Sikob case FWTCODE_RRESB: 2489103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2490103285Sikob + sizeof(u_int32_t); 2491103285Sikob case FWTCODE_LRES: 2492103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2493103285Sikob + sizeof(u_int32_t); 2494103285Sikob case FWOHCITCODE_PHY: 2495103285Sikob return 16; 2496103285Sikob } 2497103285Sikob device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2498103285Sikob return 0; 2499103285Sikob} 2500103285Sikob 2501106790Ssimokawastatic void 2502106790Ssimokawafwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2503103285Sikob{ 2504103285Sikob struct fwohcidb_tr *db_tr; 2505103285Sikob int z = 1; 2506103285Sikob struct fw_pkt *fp; 2507103285Sikob u_int8_t *ld; 2508103285Sikob u_int32_t stat, off; 2509103285Sikob u_int spd; 2510103285Sikob int len, plen, hlen, pcnt, poff = 0, rlen; 2511103285Sikob int s; 2512103285Sikob caddr_t buf; 2513103285Sikob int resCount; 2514103285Sikob 2515103285Sikob if(&sc->arrq == dbch){ 2516103285Sikob off = OHCI_ARQOFF; 2517103285Sikob }else if(&sc->arrs == dbch){ 2518103285Sikob off = OHCI_ARSOFF; 2519103285Sikob }else{ 2520103285Sikob return; 2521103285Sikob } 2522103285Sikob 2523103285Sikob s = splfw(); 2524103285Sikob db_tr = dbch->top; 2525103285Sikob pcnt = 0; 2526103285Sikob /* XXX we cannot handle a packet which lies in more than two buf */ 2527103285Sikob while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) { 2528103285Sikob ld = (u_int8_t *)db_tr->buf + dbch->buf_offset; 2529103285Sikob resCount = db_tr->db[0].db.desc.count; 2530103285Sikob len = dbch->xferq.psize - resCount 2531103285Sikob - dbch->buf_offset; 2532103285Sikob while (len > 0 ) { 2533106789Ssimokawa if (count >= 0 && count-- == 0) 2534106789Ssimokawa goto out; 2535103285Sikob if(dbch->frag.buf != NULL){ 2536103285Sikob buf = dbch->frag.buf; 2537103285Sikob if (dbch->frag.plen < 0) { 2538103285Sikob /* incomplete header */ 2539103285Sikob int hlen; 2540103285Sikob 2541103285Sikob hlen = - dbch->frag.plen; 2542103285Sikob rlen = hlen - dbch->frag.len; 2543103285Sikob bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen); 2544103285Sikob ld += rlen; 2545103285Sikob len -= rlen; 2546103285Sikob dbch->frag.len += rlen; 2547103285Sikob#if 0 2548103285Sikob printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2549103285Sikob#endif 2550103285Sikob fp=(struct fw_pkt *)dbch->frag.buf; 2551103285Sikob dbch->frag.plen 2552103285Sikob = fwohci_get_plen(sc, fp, hlen); 2553103285Sikob if (dbch->frag.plen == 0) 2554103285Sikob goto out; 2555103285Sikob } 2556103285Sikob rlen = dbch->frag.plen - dbch->frag.len; 2557103285Sikob#if 0 2558103285Sikob printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2559103285Sikob#endif 2560103285Sikob bcopy(ld, dbch->frag.buf + dbch->frag.len, 2561103285Sikob rlen); 2562103285Sikob ld += rlen; 2563103285Sikob len -= rlen; 2564103285Sikob plen = dbch->frag.plen; 2565103285Sikob dbch->frag.buf = NULL; 2566103285Sikob dbch->frag.plen = 0; 2567103285Sikob dbch->frag.len = 0; 2568103285Sikob poff = 0; 2569103285Sikob }else{ 2570103285Sikob fp=(struct fw_pkt *)ld; 2571103285Sikob fp->mode.ld[0] = htonl(fp->mode.ld[0]); 2572103285Sikob switch(fp->mode.common.tcode){ 2573103285Sikob case FWTCODE_RREQQ: 2574103285Sikob case FWTCODE_WRES: 2575103285Sikob case FWTCODE_WREQQ: 2576103285Sikob case FWTCODE_RRESQ: 2577103285Sikob case FWOHCITCODE_PHY: 2578103285Sikob hlen = 12; 2579103285Sikob break; 2580103285Sikob case FWTCODE_RREQB: 2581103285Sikob case FWTCODE_WREQB: 2582103285Sikob case FWTCODE_LREQ: 2583103285Sikob case FWTCODE_RRESB: 2584103285Sikob case FWTCODE_LRES: 2585103285Sikob hlen = 16; 2586103285Sikob break; 2587103285Sikob default: 2588103285Sikob device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2589103285Sikob goto out; 2590103285Sikob } 2591103285Sikob if (len >= hlen) { 2592103285Sikob plen = fwohci_get_plen(sc, fp, hlen); 2593103285Sikob if (plen == 0) 2594103285Sikob goto out; 2595103285Sikob plen = (plen + 3) & ~3; 2596103285Sikob len -= plen; 2597103285Sikob } else { 2598103285Sikob plen = -hlen; 2599103285Sikob len -= hlen; 2600103285Sikob } 2601103285Sikob if(resCount > 0 || len > 0){ 2602103285Sikob buf = malloc( dbch->xferq.psize, 2603103285Sikob M_DEVBUF, M_NOWAIT); 2604103285Sikob if(buf == NULL){ 2605103285Sikob printf("cannot malloc!\n"); 2606103285Sikob free(db_tr->buf, M_DEVBUF); 2607103285Sikob goto out; 2608103285Sikob } 2609103285Sikob bcopy(ld, buf, plen); 2610103285Sikob poff = 0; 2611103285Sikob dbch->frag.buf = NULL; 2612103285Sikob dbch->frag.plen = 0; 2613103285Sikob dbch->frag.len = 0; 2614103285Sikob }else if(len < 0){ 2615103285Sikob dbch->frag.buf = db_tr->buf; 2616103285Sikob if (plen < 0) { 2617103285Sikob#if 0 2618103285Sikob printf("plen < 0:" 2619103285Sikob "hlen: %d len: %d\n", 2620103285Sikob hlen, len); 2621103285Sikob#endif 2622103285Sikob dbch->frag.len = hlen + len; 2623103285Sikob dbch->frag.plen = -hlen; 2624103285Sikob } else { 2625103285Sikob dbch->frag.len = plen + len; 2626103285Sikob dbch->frag.plen = plen; 2627103285Sikob } 2628103285Sikob bcopy(ld, db_tr->buf, dbch->frag.len); 2629103285Sikob buf = NULL; 2630103285Sikob }else{ 2631103285Sikob buf = db_tr->buf; 2632103285Sikob poff = ld - (u_int8_t *)buf; 2633103285Sikob dbch->frag.buf = NULL; 2634103285Sikob dbch->frag.plen = 0; 2635103285Sikob dbch->frag.len = 0; 2636103285Sikob } 2637103285Sikob ld += plen; 2638103285Sikob } 2639103285Sikob if( buf != NULL){ 2640103285Sikob/* DMA result-code will be written at the tail of packet */ 2641103285Sikob stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2642103285Sikob spd = (stat >> 5) & 0x3; 2643103285Sikob stat &= 0x1f; 2644103285Sikob switch(stat){ 2645103285Sikob case FWOHCIEV_ACKPEND: 2646103285Sikob#if 0 2647103285Sikob printf("fwohci_arcv: ack pending..\n"); 2648103285Sikob#endif 2649103285Sikob /* fall through */ 2650103285Sikob case FWOHCIEV_ACKCOMPL: 2651103285Sikob if( poff != 0 ) 2652103285Sikob bcopy(buf+poff, buf, plen - 4); 2653103285Sikob fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd); 2654103285Sikob break; 2655103285Sikob case FWOHCIEV_BUSRST: 2656103285Sikob free(buf, M_DEVBUF); 2657103285Sikob if (sc->fc.status != FWBUSRESET) 2658103285Sikob printf("got BUSRST packet!?\n"); 2659103285Sikob break; 2660103285Sikob default: 2661103285Sikob device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2662103285Sikob#if 0 /* XXX */ 2663103285Sikob goto out; 2664103285Sikob#endif 2665103285Sikob break; 2666103285Sikob } 2667103285Sikob } 2668103285Sikob pcnt ++; 2669103285Sikob }; 2670103285Sikobout: 2671103285Sikob if (resCount == 0) { 2672103285Sikob /* done on this buffer */ 2673103285Sikob fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2674103285Sikob dbch->xferq.flag, 0, NULL); 2675103285Sikob dbch->bottom->db[0].db.desc.depend |= z; 2676103285Sikob dbch->bottom = db_tr; 2677103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2678103285Sikob dbch->top = db_tr; 2679103285Sikob dbch->buf_offset = 0; 2680103285Sikob } else { 2681103285Sikob dbch->buf_offset = dbch->xferq.psize - resCount; 2682103285Sikob break; 2683103285Sikob } 2684103285Sikob /* XXX make sure DMA is not dead */ 2685103285Sikob } 2686103285Sikob#if 0 2687103285Sikob if (pcnt < 1) 2688103285Sikob printf("fwohci_arcv: no packets\n"); 2689103285Sikob#endif 2690103285Sikob splx(s); 2691103285Sikob} 2692