fwohci.c revision 109179
1/* 2 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the acknowledgement as bellow: 15 * 16 * This product includes software developed by K. Kobayashi and H. Shimokawa 17 * 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/firewire/fwohci.c 109179 2003-01-13 16:08:09Z simokawa $ 34 * 35 */ 36 37#define ATRQ_CH 0 38#define ATRS_CH 1 39#define ARRQ_CH 2 40#define ARRS_CH 3 41#define ITX_CH 4 42#define IRX_CH 0x24 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/types.h> 47#include <sys/mbuf.h> 48#include <sys/mman.h> 49#include <sys/socket.h> 50#include <sys/socketvar.h> 51#include <sys/signalvar.h> 52#include <sys/malloc.h> 53#include <sys/uio.h> 54#include <sys/sockio.h> 55#include <sys/bus.h> 56#include <sys/kernel.h> 57#include <sys/conf.h> 58 59#include <machine/bus.h> 60#include <machine/resource.h> 61#include <sys/rman.h> 62 63#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 64#include <machine/clock.h> 65#include <pci/pcivar.h> 66#include <pci/pcireg.h> 67#include <vm/vm.h> 68#include <vm/vm_extern.h> 69#include <vm/pmap.h> /* for vtophys proto */ 70 71#include <dev/firewire/firewire.h> 72#include <dev/firewire/firewirereg.h> 73#include <dev/firewire/fwohcireg.h> 74#include <dev/firewire/fwohcivar.h> 75#include <dev/firewire/firewire_phy.h> 76 77#include <dev/firewire/iec68113.h> 78 79#undef OHCI_DEBUG 80 81static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 82 "STOR","LOAD","NOP ","STOP",}; 83static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 84 "UNDEF","REG","SYS","DEV"}; 85char fwohcicode[32][0x20]={ 86 "No stat","Undef","long","miss Ack err", 87 "underrun","overrun","desc err", "data read err", 88 "data write err","bus reset","timeout","tcode err", 89 "Undef","Undef","unknown event","flushed", 90 "Undef","ack complete","ack pend","Undef", 91 "ack busy_X","ack busy_A","ack busy_B","Undef", 92 "Undef","Undef","Undef","ack tardy", 93 "Undef","ack data_err","ack type_err",""}; 94#define MAX_SPEED 2 95extern char linkspeed[MAX_SPEED+1][0x10]; 96static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 97u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 98 99static struct tcode_info tinfo[] = { 100/* hdr_len block flag*/ 101/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 102/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 103/* 2 WRES */ {12, FWTI_RES}, 104/* 3 XXX */ { 0, 0}, 105/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 106/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 107/* 6 RRESQ */ {16, FWTI_RES}, 108/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 109/* 8 CYCS */ { 0, 0}, 110/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 111/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 112/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 113/* c XXX */ { 0, 0}, 114/* d XXX */ { 0, 0}, 115/* e PHY */ {12, FWTI_REQ}, 116/* f XXX */ { 0, 0} 117}; 118 119#define OHCI_WRITE_SIGMASK 0xffff0000 120#define OHCI_READ_SIGMASK 0xffff0000 121 122#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 123#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 124 125static void fwohci_ibr __P((struct firewire_comm *)); 126static void fwohci_db_init __P((struct fwohci_dbch *)); 127static void fwohci_db_free __P((struct fwohci_dbch *)); 128static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 129static void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 130static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 131static void fwohci_start_atq __P((struct firewire_comm *)); 132static void fwohci_start_ats __P((struct firewire_comm *)); 133static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 134static void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *)); 135static void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *)); 136static void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *)); 137static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 138static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 139static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 140static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 141static int fwohci_irx_enable __P((struct firewire_comm *, int)); 142static int fwohci_irxpp_enable __P((struct firewire_comm *, int)); 143static int fwohci_irxbuf_enable __P((struct firewire_comm *, int)); 144static int fwohci_irx_disable __P((struct firewire_comm *, int)); 145static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 146static int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 147static int fwohci_itx_disable __P((struct firewire_comm *, int)); 148static void fwohci_timeout __P((void *)); 149static void fwohci_poll __P((struct firewire_comm *, int, int)); 150static void fwohci_set_intr __P((struct firewire_comm *, int)); 151static int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *)); 152static int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *)); 153static void dump_db __P((struct fwohci_softc *, u_int32_t)); 154static void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t)); 155static void dump_dma __P((struct fwohci_softc *, u_int32_t)); 156static u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 157static void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 158static void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 159void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 160 161/* 162 * memory allocated for DMA programs 163 */ 164#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 165 166/* #define NDB 1024 */ 167#define NDB FWMAXQUEUE 168#define NDVDB (DVBUF * NDB) 169 170#define OHCI_VERSION 0x00 171#define OHCI_CROMHDR 0x18 172#define OHCI_BUS_OPT 0x20 173#define OHCI_BUSIRMC (1 << 31) 174#define OHCI_BUSCMC (1 << 30) 175#define OHCI_BUSISC (1 << 29) 176#define OHCI_BUSBMC (1 << 28) 177#define OHCI_BUSPMC (1 << 27) 178#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 179 OHCI_BUSBMC | OHCI_BUSPMC 180 181#define OHCI_EUID_HI 0x24 182#define OHCI_EUID_LO 0x28 183 184#define OHCI_CROMPTR 0x34 185#define OHCI_HCCCTL 0x50 186#define OHCI_HCCCTLCLR 0x54 187#define OHCI_AREQHI 0x100 188#define OHCI_AREQHICLR 0x104 189#define OHCI_AREQLO 0x108 190#define OHCI_AREQLOCLR 0x10c 191#define OHCI_PREQHI 0x110 192#define OHCI_PREQHICLR 0x114 193#define OHCI_PREQLO 0x118 194#define OHCI_PREQLOCLR 0x11c 195#define OHCI_PREQUPPER 0x120 196 197#define OHCI_SID_BUF 0x64 198#define OHCI_SID_CNT 0x68 199#define OHCI_SID_CNT_MASK 0xffc 200 201#define OHCI_IT_STAT 0x90 202#define OHCI_IT_STATCLR 0x94 203#define OHCI_IT_MASK 0x98 204#define OHCI_IT_MASKCLR 0x9c 205 206#define OHCI_IR_STAT 0xa0 207#define OHCI_IR_STATCLR 0xa4 208#define OHCI_IR_MASK 0xa8 209#define OHCI_IR_MASKCLR 0xac 210 211#define OHCI_LNKCTL 0xe0 212#define OHCI_LNKCTLCLR 0xe4 213 214#define OHCI_PHYACCESS 0xec 215#define OHCI_CYCLETIMER 0xf0 216 217#define OHCI_DMACTL(off) (off) 218#define OHCI_DMACTLCLR(off) (off + 4) 219#define OHCI_DMACMD(off) (off + 0xc) 220#define OHCI_DMAMATCH(off) (off + 0x10) 221 222#define OHCI_ATQOFF 0x180 223#define OHCI_ATQCTL OHCI_ATQOFF 224#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 225#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 226#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 227 228#define OHCI_ATSOFF 0x1a0 229#define OHCI_ATSCTL OHCI_ATSOFF 230#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 231#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 232#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 233 234#define OHCI_ARQOFF 0x1c0 235#define OHCI_ARQCTL OHCI_ARQOFF 236#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 237#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 238#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 239 240#define OHCI_ARSOFF 0x1e0 241#define OHCI_ARSCTL OHCI_ARSOFF 242#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 243#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 244#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 245 246#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 247#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 248#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 249#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 250 251#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 252#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 253#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 254#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 255#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 256 257d_ioctl_t fwohci_ioctl; 258 259/* 260 * Communication with PHY device 261 */ 262static u_int32_t 263fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 264{ 265 u_int32_t fun; 266 267 addr &= 0xf; 268 data &= 0xff; 269 270 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 271 OWRITE(sc, OHCI_PHYACCESS, fun); 272 DELAY(100); 273 274 return(fwphy_rddata( sc, addr)); 275} 276 277static u_int32_t 278fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 279{ 280 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 281 int i; 282 u_int32_t bm; 283 284#define OHCI_CSR_DATA 0x0c 285#define OHCI_CSR_COMP 0x10 286#define OHCI_CSR_CONT 0x14 287#define OHCI_BUS_MANAGER_ID 0 288 289 OWRITE(sc, OHCI_CSR_DATA, node); 290 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 291 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 292 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 293 DELAY(100); 294 bm = OREAD(sc, OHCI_CSR_DATA); 295 if((bm & 0x3f) == 0x3f) 296 bm = node; 297 if (bootverbose) 298 device_printf(sc->fc.dev, 299 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 300 301 return(bm); 302} 303 304static u_int32_t 305fwphy_rddata(struct fwohci_softc *sc, u_int addr) 306{ 307 u_int32_t fun, stat; 308 u_int i, retry = 0; 309 310 addr &= 0xf; 311#define MAX_RETRY 100 312again: 313 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 314 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 315 OWRITE(sc, OHCI_PHYACCESS, fun); 316 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 317 fun = OREAD(sc, OHCI_PHYACCESS); 318 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 319 break; 320 DELAY(1000); 321 } 322 if(i >= MAX_RETRY) { 323 device_printf(sc->fc.dev, "cannot read phy\n"); 324#if 0 325 return 0; /* XXX */ 326#else 327 if (++retry < MAX_RETRY) { 328 DELAY(1000); 329 goto again; 330 } 331#endif 332 } 333 /* Make sure that SCLK is started */ 334 stat = OREAD(sc, FWOHCI_INTSTAT); 335 if ((stat & OHCI_INT_REG_FAIL) != 0 || 336 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 337 if (++retry < MAX_RETRY) { 338 DELAY(1000); 339 goto again; 340 } 341 } 342 if (bootverbose || retry >= MAX_RETRY) 343 device_printf(sc->fc.dev, 344 "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 345#undef MAX_RETRY 346 return((fun >> PHYDEV_RDDATA )& 0xff); 347} 348/* Device specific ioctl. */ 349int 350fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 351{ 352 struct firewire_softc *sc; 353 struct fwohci_softc *fc; 354 int unit = DEV2UNIT(dev); 355 int err = 0; 356 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 357 u_int32_t *dmach = (u_int32_t *) data; 358 359 sc = devclass_get_softc(firewire_devclass, unit); 360 if(sc == NULL){ 361 return(EINVAL); 362 } 363 fc = (struct fwohci_softc *)sc->fc; 364 365 if (!data) 366 return(EINVAL); 367 368 switch (cmd) { 369 case FWOHCI_WRREG: 370#define OHCI_MAX_REG 0x800 371 if(reg->addr <= OHCI_MAX_REG){ 372 OWRITE(fc, reg->addr, reg->data); 373 reg->data = OREAD(fc, reg->addr); 374 }else{ 375 err = EINVAL; 376 } 377 break; 378 case FWOHCI_RDREG: 379 if(reg->addr <= OHCI_MAX_REG){ 380 reg->data = OREAD(fc, reg->addr); 381 }else{ 382 err = EINVAL; 383 } 384 break; 385/* Read DMA descriptors for debug */ 386 case DUMPDMA: 387 if(*dmach <= OHCI_MAX_DMA_CH ){ 388 dump_dma(fc, *dmach); 389 dump_db(fc, *dmach); 390 }else{ 391 err = EINVAL; 392 } 393 break; 394 default: 395 break; 396 } 397 return err; 398} 399 400static int 401fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 402{ 403 u_int32_t reg, reg2; 404 int e1394a = 1; 405/* 406 * probe PHY parameters 407 * 0. to prove PHY version, whether compliance of 1394a. 408 * 1. to probe maximum speed supported by the PHY and 409 * number of port supported by core-logic. 410 * It is not actually available port on your PC . 411 */ 412 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 413#if 0 414 /* XXX wait for SCLK. */ 415 DELAY(100000); 416#endif 417 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 418 419 if((reg >> 5) != 7 ){ 420 sc->fc.mode &= ~FWPHYASYST; 421 sc->fc.nport = reg & FW_PHY_NP; 422 sc->fc.speed = reg & FW_PHY_SPD >> 6; 423 if (sc->fc.speed > MAX_SPEED) { 424 device_printf(dev, "invalid speed %d (fixed to %d).\n", 425 sc->fc.speed, MAX_SPEED); 426 sc->fc.speed = MAX_SPEED; 427 } 428 device_printf(dev, 429 "Phy 1394 only %s, %d ports.\n", 430 linkspeed[sc->fc.speed], sc->fc.nport); 431 }else{ 432 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 433 sc->fc.mode |= FWPHYASYST; 434 sc->fc.nport = reg & FW_PHY_NP; 435 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 436 if (sc->fc.speed > MAX_SPEED) { 437 device_printf(dev, "invalid speed %d (fixed to %d).\n", 438 sc->fc.speed, MAX_SPEED); 439 sc->fc.speed = MAX_SPEED; 440 } 441 device_printf(dev, 442 "Phy 1394a available %s, %d ports.\n", 443 linkspeed[sc->fc.speed], sc->fc.nport); 444 445 /* check programPhyEnable */ 446 reg2 = fwphy_rddata(sc, 5); 447#if 0 448 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 449#else /* XXX force to enable 1394a */ 450 if (e1394a) { 451#endif 452 if (bootverbose) 453 device_printf(dev, 454 "Enable 1394a Enhancements\n"); 455 /* enable EAA EMC */ 456 reg2 |= 0x03; 457 /* set aPhyEnhanceEnable */ 458 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 459 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 460 } else { 461 /* for safe */ 462 reg2 &= ~0x83; 463 } 464 reg2 = fwphy_wrdata(sc, 5, reg2); 465 } 466 467 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 468 if((reg >> 5) == 7 ){ 469 reg = fwphy_rddata(sc, 4); 470 reg |= 1 << 6; 471 fwphy_wrdata(sc, 4, reg); 472 reg = fwphy_rddata(sc, 4); 473 } 474 return 0; 475} 476 477 478void 479fwohci_reset(struct fwohci_softc *sc, device_t dev) 480{ 481 int i, max_rec, speed; 482 u_int32_t reg, reg2; 483 struct fwohcidb_tr *db_tr; 484 485 /* Disable interrupt */ 486 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 487 488 /* Now stopping all DMA channel */ 489 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 490 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 491 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 492 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 493 494 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 495 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 496 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 497 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 498 } 499 500 /* FLUSH FIFO and reset Transmitter/Reciever */ 501 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 502 if (bootverbose) 503 device_printf(dev, "resetting OHCI..."); 504 i = 0; 505 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 506 if (i++ > 100) break; 507 DELAY(1000); 508 } 509 if (bootverbose) 510 printf("done (loop=%d)\n", i); 511 512 /* Probe phy */ 513 fwohci_probe_phy(sc, dev); 514 515 /* Probe link */ 516 reg = OREAD(sc, OHCI_BUS_OPT); 517 reg2 = reg | OHCI_BUSFNC; 518 max_rec = (reg & 0x0000f000) >> 12; 519 speed = (reg & 0x00000007); 520 device_printf(dev, "Link %s, max_rec %d bytes.\n", 521 linkspeed[speed], MAXREC(max_rec)); 522 /* XXX fix max_rec */ 523 sc->fc.maxrec = sc->fc.speed + 8; 524 if (max_rec != sc->fc.maxrec) { 525 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 526 device_printf(dev, "max_rec %d -> %d\n", 527 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 528 } 529 if (bootverbose) 530 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 531 OWRITE(sc, OHCI_BUS_OPT, reg2); 532 533 /* Initialize registers */ 534 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 535 OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0])); 536 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 537 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 538 OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf)); 539 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 540 fw_busreset(&sc->fc); 541 542 /* Enable link */ 543 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 544 545 /* Force to start async RX DMA */ 546 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 547 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 548 fwohci_rx_enable(sc, &sc->arrq); 549 fwohci_rx_enable(sc, &sc->arrs); 550 551 /* Initialize async TX */ 552 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 553 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 554 /* AT Retries */ 555 OWRITE(sc, FWOHCI_RETRY, 556 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 557 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 558 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 559 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 560 db_tr->xfer = NULL; 561 } 562 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 563 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 564 db_tr->xfer = NULL; 565 } 566 567 568 /* Enable interrupt */ 569 OWRITE(sc, FWOHCI_INTMASK, 570 OHCI_INT_ERR | OHCI_INT_PHY_SID 571 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 572 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 573 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 574 fwohci_set_intr(&sc->fc, 1); 575 576} 577 578int 579fwohci_init(struct fwohci_softc *sc, device_t dev) 580{ 581 int i; 582 u_int32_t reg; 583 584 reg = OREAD(sc, OHCI_VERSION); 585 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 586 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 587 588/* XXX: Available Isochrounous DMA channel probe */ 589 for( i = 0 ; i < 0x20 ; i ++ ){ 590 OWRITE(sc, OHCI_IRCTL(i), OHCI_CNTL_DMA_RUN); 591 reg = OREAD(sc, OHCI_IRCTL(i)); 592 if(!(reg & OHCI_CNTL_DMA_RUN)) break; 593 OWRITE(sc, OHCI_ITCTL(i), OHCI_CNTL_DMA_RUN); 594 reg = OREAD(sc, OHCI_ITCTL(i)); 595 if(!(reg & OHCI_CNTL_DMA_RUN)) break; 596 } 597 sc->fc.nisodma = i; 598 device_printf(dev, "No. of Isochronous channel is %d.\n", i); 599 600 sc->fc.arq = &sc->arrq.xferq; 601 sc->fc.ars = &sc->arrs.xferq; 602 sc->fc.atq = &sc->atrq.xferq; 603 sc->fc.ats = &sc->atrs.xferq; 604 605 sc->arrq.xferq.start = NULL; 606 sc->arrs.xferq.start = NULL; 607 sc->atrq.xferq.start = fwohci_start_atq; 608 sc->atrs.xferq.start = fwohci_start_ats; 609 610 sc->arrq.xferq.drain = NULL; 611 sc->arrs.xferq.drain = NULL; 612 sc->atrq.xferq.drain = fwohci_drain_atq; 613 sc->atrs.xferq.drain = fwohci_drain_ats; 614 615 sc->arrq.ndesc = 1; 616 sc->arrs.ndesc = 1; 617 sc->atrq.ndesc = 6; /* equal to maximum of mbuf chains */ 618 sc->atrs.ndesc = 6 / 2; 619 620 sc->arrq.ndb = NDB; 621 sc->arrs.ndb = NDB / 2; 622 sc->atrq.ndb = NDB; 623 sc->atrs.ndb = NDB / 2; 624 625 sc->arrq.dummy = NULL; 626 sc->arrs.dummy = NULL; 627 sc->atrq.dummy = NULL; 628 sc->atrs.dummy = NULL; 629 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 630 sc->fc.it[i] = &sc->it[i].xferq; 631 sc->fc.ir[i] = &sc->ir[i].xferq; 632 sc->it[i].ndb = 0; 633 sc->ir[i].ndb = 0; 634 } 635 636 sc->fc.tcode = tinfo; 637 638 sc->cromptr = (u_int32_t *) 639 contigmalloc(CROMSIZE * 2, M_DEVBUF, M_NOWAIT, 0, ~0, 1<<10, 0); 640 641 if(sc->cromptr == NULL){ 642 device_printf(dev, "cromptr alloc failed."); 643 return ENOMEM; 644 } 645 sc->fc.dev = dev; 646 sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]); 647 648 sc->fc.config_rom[1] = 0x31333934; 649 sc->fc.config_rom[2] = 0xf000a002; 650 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 651 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 652 sc->fc.config_rom[5] = 0; 653 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 654 655 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 656 657 658/* SID recieve buffer must allign 2^11 */ 659#define OHCI_SIDSIZE (1 << 11) 660 sc->fc.sid_buf = (u_int32_t *) vm_page_alloc_contig( OHCI_SIDSIZE, 661 0x10000, 0xffffffff, OHCI_SIDSIZE); 662 if (sc->fc.sid_buf == NULL) { 663 device_printf(dev, "sid_buf alloc failed.\n"); 664 return ENOMEM; 665 } 666 667 668 fwohci_db_init(&sc->arrq); 669 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 670 return ENOMEM; 671 672 fwohci_db_init(&sc->arrs); 673 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 674 return ENOMEM; 675 676 fwohci_db_init(&sc->atrq); 677 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 678 return ENOMEM; 679 680 fwohci_db_init(&sc->atrs); 681 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 682 return ENOMEM; 683 684 reg = OREAD(sc, FWOHCIGUID_H); 685 for( i = 0 ; i < 4 ; i ++){ 686 sc->fc.eui[3 - i] = reg & 0xff; 687 reg = reg >> 8; 688 } 689 reg = OREAD(sc, FWOHCIGUID_L); 690 for( i = 0 ; i < 4 ; i ++){ 691 sc->fc.eui[7 - i] = reg & 0xff; 692 reg = reg >> 8; 693 } 694 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 695 sc->fc.eui[0], sc->fc.eui[1], sc->fc.eui[2], sc->fc.eui[3], 696 sc->fc.eui[4], sc->fc.eui[5], sc->fc.eui[6], sc->fc.eui[7]); 697 sc->fc.ioctl = fwohci_ioctl; 698 sc->fc.cyctimer = fwohci_cyctimer; 699 sc->fc.set_bmr = fwohci_set_bus_manager; 700 sc->fc.ibr = fwohci_ibr; 701 sc->fc.irx_enable = fwohci_irx_enable; 702 sc->fc.irx_disable = fwohci_irx_disable; 703 704 sc->fc.itx_enable = fwohci_itxbuf_enable; 705 sc->fc.itx_disable = fwohci_itx_disable; 706 sc->fc.irx_post = fwohci_irx_post; 707 sc->fc.itx_post = NULL; 708 sc->fc.timeout = fwohci_timeout; 709 sc->fc.poll = fwohci_poll; 710 sc->fc.set_intr = fwohci_set_intr; 711 712 fw_init(&sc->fc); 713 fwohci_reset(sc, dev); 714 715 return 0; 716} 717 718void 719fwohci_timeout(void *arg) 720{ 721 struct fwohci_softc *sc; 722 723 sc = (struct fwohci_softc *)arg; 724 sc->fc.timeouthandle = timeout(fwohci_timeout, 725 (void *)sc, FW_XFERTIMEOUT * hz * 10); 726} 727 728u_int32_t 729fwohci_cyctimer(struct firewire_comm *fc) 730{ 731 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 732 return(OREAD(sc, OHCI_CYCLETIMER)); 733} 734 735int 736fwohci_detach(struct fwohci_softc *sc, device_t dev) 737{ 738 int i; 739 740 if (sc->fc.sid_buf != NULL) 741 contigfree((void *)(uintptr_t)sc->fc.sid_buf, 742 OHCI_SIDSIZE, M_DEVBUF); 743 if (sc->cromptr != NULL) 744 contigfree((void *)sc->cromptr, CROMSIZE * 2, M_DEVBUF); 745 746 fwohci_db_free(&sc->arrq); 747 fwohci_db_free(&sc->arrs); 748 749 fwohci_db_free(&sc->atrq); 750 fwohci_db_free(&sc->atrs); 751 752 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 753 fwohci_db_free(&sc->it[i]); 754 fwohci_db_free(&sc->ir[i]); 755 } 756 757 return 0; 758} 759 760#define LAST_DB(dbtr, db) do { \ 761 struct fwohcidb_tr *_dbtr = (dbtr); \ 762 int _cnt = _dbtr->dbcnt; \ 763 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 764} while (0) 765 766static void 767fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 768{ 769 int i, s; 770 int tcode, hdr_len, hdr_off, len; 771 int fsegment = -1; 772 u_int32_t off; 773 struct fw_xfer *xfer; 774 struct fw_pkt *fp; 775 volatile struct fwohci_txpkthdr *ohcifp; 776 struct fwohcidb_tr *db_tr; 777 volatile struct fwohcidb *db; 778 struct mbuf *m; 779 struct tcode_info *info; 780 static int maxdesc=0; 781 782 if(&sc->atrq == dbch){ 783 off = OHCI_ATQOFF; 784 }else if(&sc->atrs == dbch){ 785 off = OHCI_ATSOFF; 786 }else{ 787 return; 788 } 789 790 if (dbch->flags & FWOHCI_DBCH_FULL) 791 return; 792 793 s = splfw(); 794 db_tr = dbch->top; 795txloop: 796 xfer = STAILQ_FIRST(&dbch->xferq.q); 797 if(xfer == NULL){ 798 goto kick; 799 } 800 if(dbch->xferq.queued == 0 ){ 801 device_printf(sc->fc.dev, "TX queue empty\n"); 802 } 803 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 804 db_tr->xfer = xfer; 805 xfer->state = FWXF_START; 806 dbch->xferq.packets++; 807 808 fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off); 809 tcode = fp->mode.common.tcode; 810 811 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 812 info = &tinfo[tcode]; 813 hdr_len = hdr_off = info->hdr_len; 814 /* fw_asyreq must pass valid send.len */ 815 len = xfer->send.len; 816 for( i = 0 ; i < hdr_off ; i+= 4){ 817 ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]); 818 } 819 ohcifp->mode.common.spd = xfer->spd; 820 if (tcode == FWTCODE_STREAM ){ 821 hdr_len = 8; 822 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 823 } else if (tcode == FWTCODE_PHY) { 824 hdr_len = 12; 825 ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]); 826 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]); 827 ohcifp->mode.common.spd = 0; 828 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 829 } else { 830 ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst); 831 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 832 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 833 } 834 db = &db_tr->db[0]; 835 db->db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len; 836 db->db.desc.status = 0; 837/* Specify bound timer of asy. responce */ 838 if(&sc->atrs == dbch){ 839 db->db.desc.count 840 = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13); 841 } 842 843 db_tr->dbcnt = 2; 844 db = &db_tr->db[db_tr->dbcnt]; 845 if(len > hdr_off){ 846 if (xfer->mbuf == NULL) { 847 db->db.desc.addr 848 = vtophys(xfer->send.buf + xfer->send.off) + hdr_off; 849 db->db.desc.cmd 850 = OHCI_OUTPUT_MORE | ((len - hdr_off) & 0xffff); 851 db->db.desc.status = 0; 852 853 db_tr->dbcnt++; 854 } else { 855 /* XXX we assume mbuf chain is shorter than ndesc */ 856 for (m = xfer->mbuf; m != NULL; m = m->m_next) { 857 if (m->m_len == 0) 858 /* unrecoverable error could ocurre. */ 859 continue; 860 if (db_tr->dbcnt >= dbch->ndesc) { 861 device_printf(sc->fc.dev, 862 "dbch->ndesc is too small" 863 ", trancated.\n"); 864 break; 865 } 866 db->db.desc.addr 867 = vtophys(mtod(m, caddr_t)); 868 db->db.desc.cmd = OHCI_OUTPUT_MORE | m->m_len; 869 db->db.desc.status = 0; 870 db++; 871 db_tr->dbcnt++; 872 } 873 } 874 } 875 if (maxdesc < db_tr->dbcnt) { 876 maxdesc = db_tr->dbcnt; 877 if (bootverbose) 878 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 879 } 880 /* last db */ 881 LAST_DB(db_tr, db); 882 db->db.desc.cmd |= OHCI_OUTPUT_LAST 883 | OHCI_INTERRUPT_ALWAYS 884 | OHCI_BRANCH_ALWAYS; 885 db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db); 886 887 if(fsegment == -1 ) 888 fsegment = db_tr->dbcnt; 889 if (dbch->pdb_tr != NULL) { 890 LAST_DB(dbch->pdb_tr, db); 891 db->db.desc.depend |= db_tr->dbcnt; 892 } 893 dbch->pdb_tr = db_tr; 894 db_tr = STAILQ_NEXT(db_tr, link); 895 if(db_tr != dbch->bottom){ 896 goto txloop; 897 } else { 898 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 899 dbch->flags |= FWOHCI_DBCH_FULL; 900 } 901kick: 902 if (firewire_debug) printf("kick\n"); 903 /* kick asy q */ 904 905 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 906 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 907 } else { 908 if (bootverbose) 909 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 910 OREAD(sc, OHCI_DMACTL(off))); 911 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment); 912 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 913 dbch->xferq.flag |= FWXFERQ_RUNNING; 914 } 915 916 dbch->top = db_tr; 917 splx(s); 918 return; 919} 920 921static void 922fwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer) 923{ 924 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 925 fwohci_drain(&sc->fc, xfer, &(sc->atrq)); 926 return; 927} 928 929static void 930fwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer) 931{ 932 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 933 fwohci_drain(&sc->fc, xfer, &(sc->atrs)); 934 return; 935} 936 937static void 938fwohci_start_atq(struct firewire_comm *fc) 939{ 940 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 941 fwohci_start( sc, &(sc->atrq)); 942 return; 943} 944 945static void 946fwohci_start_ats(struct firewire_comm *fc) 947{ 948 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 949 fwohci_start( sc, &(sc->atrs)); 950 return; 951} 952 953void 954fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 955{ 956 int s, err = 0; 957 struct fwohcidb_tr *tr; 958 volatile struct fwohcidb *db; 959 struct fw_xfer *xfer; 960 u_int32_t off; 961 u_int stat; 962 int packets; 963 struct firewire_comm *fc = (struct firewire_comm *)sc; 964 if(&sc->atrq == dbch){ 965 off = OHCI_ATQOFF; 966 }else if(&sc->atrs == dbch){ 967 off = OHCI_ATSOFF; 968 }else{ 969 return; 970 } 971 s = splfw(); 972 tr = dbch->bottom; 973 packets = 0; 974 while(dbch->xferq.queued > 0){ 975 LAST_DB(tr, db); 976 if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){ 977 if (fc->status != FWBUSRESET) 978 /* maybe out of order?? */ 979 goto out; 980 } 981 if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) { 982#ifdef OHCI_DEBUG 983 dump_dma(sc, ch); 984 dump_db(sc, ch); 985#endif 986/* Stop DMA */ 987 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 988 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 989 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 990 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 991 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 992 } 993 stat = db->db.desc.status & FWOHCIEV_MASK; 994 switch(stat){ 995 case FWOHCIEV_ACKCOMPL: 996 case FWOHCIEV_ACKPEND: 997 err = 0; 998 break; 999 case FWOHCIEV_ACKBSA: 1000 case FWOHCIEV_ACKBSB: 1001 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1002 case FWOHCIEV_ACKBSX: 1003 err = EBUSY; 1004 break; 1005 case FWOHCIEV_FLUSHED: 1006 case FWOHCIEV_ACKTARD: 1007 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1008 err = EAGAIN; 1009 break; 1010 case FWOHCIEV_MISSACK: 1011 case FWOHCIEV_UNDRRUN: 1012 case FWOHCIEV_OVRRUN: 1013 case FWOHCIEV_DESCERR: 1014 case FWOHCIEV_DTRDERR: 1015 case FWOHCIEV_TIMEOUT: 1016 case FWOHCIEV_TCODERR: 1017 case FWOHCIEV_UNKNOWN: 1018 case FWOHCIEV_ACKDERR: 1019 case FWOHCIEV_ACKTERR: 1020 default: 1021 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1022 stat, fwohcicode[stat]); 1023 err = EINVAL; 1024 break; 1025 } 1026 if(tr->xfer != NULL){ 1027 xfer = tr->xfer; 1028 xfer->state = FWXF_SENT; 1029 if(err == EBUSY && fc->status != FWBUSRESET){ 1030 xfer->state = FWXF_BUSY; 1031 switch(xfer->act_type){ 1032 case FWACT_XFER: 1033 xfer->resp = err; 1034 if(xfer->retry_req != NULL){ 1035 xfer->retry_req(xfer); 1036 } 1037 break; 1038 default: 1039 break; 1040 } 1041 } else if( stat != FWOHCIEV_ACKPEND){ 1042 if (stat != FWOHCIEV_ACKCOMPL) 1043 xfer->state = FWXF_SENTERR; 1044 xfer->resp = err; 1045 switch(xfer->act_type){ 1046 case FWACT_XFER: 1047 fw_xfer_done(xfer); 1048 break; 1049 default: 1050 break; 1051 } 1052 } 1053 dbch->xferq.queued --; 1054 } 1055 tr->xfer = NULL; 1056 1057 packets ++; 1058 tr = STAILQ_NEXT(tr, link); 1059 dbch->bottom = tr; 1060 } 1061out: 1062 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1063 printf("make free slot\n"); 1064 dbch->flags &= ~FWOHCI_DBCH_FULL; 1065 fwohci_start(sc, dbch); 1066 } 1067 splx(s); 1068} 1069 1070static void 1071fwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch) 1072{ 1073 int i, s; 1074 struct fwohcidb_tr *tr; 1075 1076 if(xfer->state != FWXF_START) return; 1077 1078 s = splfw(); 1079 tr = dbch->bottom; 1080 for( i = 0 ; i <= dbch->xferq.queued ; i ++){ 1081 if(tr->xfer == xfer){ 1082 s = splfw(); 1083 tr->xfer = NULL; 1084 dbch->xferq.queued --; 1085#if 1 1086 /* XXX */ 1087 if (tr == dbch->bottom) 1088 dbch->bottom = STAILQ_NEXT(tr, link); 1089#endif 1090 if (dbch->flags & FWOHCI_DBCH_FULL) { 1091 printf("fwohci_drain: make slot\n"); 1092 dbch->flags &= ~FWOHCI_DBCH_FULL; 1093 fwohci_start((struct fwohci_softc *)fc, dbch); 1094 } 1095 1096 splx(s); 1097 break; 1098 } 1099 tr = STAILQ_NEXT(tr, link); 1100 } 1101 splx(s); 1102 return; 1103} 1104 1105static void 1106fwohci_db_free(struct fwohci_dbch *dbch) 1107{ 1108 struct fwohcidb_tr *db_tr; 1109 int idb; 1110 1111 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1112 return; 1113 1114 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1115 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; 1116 idb < dbch->ndb; 1117 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1118 if (db_tr->buf != NULL) { 1119 free(db_tr->buf, M_DEVBUF); 1120 db_tr->buf = NULL; 1121 } 1122 } 1123 } 1124 dbch->ndb = 0; 1125 db_tr = STAILQ_FIRST(&dbch->db_trq); 1126 contigfree((void *)(uintptr_t)(volatile void *)db_tr->db, 1127 sizeof(struct fwohcidb) * dbch->ndesc * dbch->ndb, M_DEVBUF); 1128 free(db_tr, M_DEVBUF); 1129 STAILQ_INIT(&dbch->db_trq); 1130 dbch->flags &= ~FWOHCI_DBCH_INIT; 1131} 1132 1133static void 1134fwohci_db_init(struct fwohci_dbch *dbch) 1135{ 1136 int idb; 1137 struct fwohcidb *db; 1138 struct fwohcidb_tr *db_tr; 1139 1140 1141 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1142 goto out; 1143 1144 /* allocate DB entries and attach one to each DMA channels */ 1145 /* DB entry must start at 16 bytes bounary. */ 1146 STAILQ_INIT(&dbch->db_trq); 1147 db_tr = (struct fwohcidb_tr *) 1148 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1149 M_DEVBUF, M_DONTWAIT | M_ZERO); 1150 if(db_tr == NULL){ 1151 printf("fwohci_db_init: malloc failed\n"); 1152 return; 1153 } 1154 db = (struct fwohcidb *) 1155 contigmalloc(sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb, 1156 M_DEVBUF, M_DONTWAIT, 0x10000, 0xffffffff, PAGE_SIZE, 0ul); 1157 if(db == NULL){ 1158 printf("fwohci_db_init: contigmalloc failed\n"); 1159 free(db_tr, M_DEVBUF); 1160 return; 1161 } 1162 bzero(db, sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb); 1163 /* Attach DB to DMA ch. */ 1164 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1165 db_tr->dbcnt = 0; 1166 db_tr->db = &db[idb * dbch->ndesc]; 1167 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1168 if (!(dbch->xferq.flag & FWXFERQ_PACKET) && 1169 dbch->xferq.bnpacket != 0) { 1170 /* XXX what those for? */ 1171 if (idb % dbch->xferq.bnpacket == 0) 1172 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1173 ].start = (caddr_t)db_tr; 1174 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1175 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1176 ].end = (caddr_t)db_tr; 1177 } 1178 db_tr++; 1179 } 1180 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1181 = STAILQ_FIRST(&dbch->db_trq); 1182out: 1183 dbch->frag.buf = NULL; 1184 dbch->frag.len = 0; 1185 dbch->frag.plen = 0; 1186 dbch->xferq.queued = 0; 1187 dbch->pdb_tr = NULL; 1188 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1189 dbch->bottom = dbch->top; 1190 dbch->flags = FWOHCI_DBCH_INIT; 1191} 1192 1193static int 1194fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1195{ 1196 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1197 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1198 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1199 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1200 fwohci_db_free(&sc->it[dmach]); 1201 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1202 return 0; 1203} 1204 1205static int 1206fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1207{ 1208 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1209 1210 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1211 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1212 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1213 if(sc->ir[dmach].dummy != NULL){ 1214 free(sc->ir[dmach].dummy, M_DEVBUF); 1215 } 1216 sc->ir[dmach].dummy = NULL; 1217 fwohci_db_free(&sc->ir[dmach]); 1218 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1219 return 0; 1220} 1221 1222static void 1223fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1224{ 1225 qld[0] = ntohl(qld[0]); 1226 return; 1227} 1228 1229static int 1230fwohci_irxpp_enable(struct firewire_comm *fc, int dmach) 1231{ 1232 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1233 int err = 0; 1234 unsigned short tag, ich; 1235 1236 tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1237 ich = sc->ir[dmach].xferq.flag & 0x3f; 1238 1239#if 0 1240 if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){ 1241 wakeup(fc->ir[dmach]); 1242 return err; 1243 } 1244#endif 1245 1246 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1247 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1248 sc->ir[dmach].xferq.queued = 0; 1249 sc->ir[dmach].ndb = NDB; 1250 sc->ir[dmach].xferq.psize = FWPMAX_S400; 1251 sc->ir[dmach].ndesc = 1; 1252 fwohci_db_init(&sc->ir[dmach]); 1253 if ((sc->ir[dmach].flags & FWOHCI_DBCH_INIT) == 0) 1254 return ENOMEM; 1255 err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1256 } 1257 if(err){ 1258 device_printf(sc->fc.dev, "err in IRX setting\n"); 1259 return err; 1260 } 1261 if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1262 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1263 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1264 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1265 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1266 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000); 1267 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1268 OWRITE(sc, OHCI_IRCMD(dmach), 1269 vtophys(sc->ir[dmach].top->db) | 1); 1270 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1271 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1272 } 1273 return err; 1274} 1275 1276static int 1277fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1278{ 1279 int err = 0; 1280 int idb, z, i, dmach = 0; 1281 u_int32_t off = NULL; 1282 struct fwohcidb_tr *db_tr; 1283 1284 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1285 err = EINVAL; 1286 return err; 1287 } 1288 z = dbch->ndesc; 1289 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1290 if( &sc->it[dmach] == dbch){ 1291 off = OHCI_ITOFF(dmach); 1292 break; 1293 } 1294 } 1295 if(off == NULL){ 1296 err = EINVAL; 1297 return err; 1298 } 1299 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1300 return err; 1301 dbch->xferq.flag |= FWXFERQ_RUNNING; 1302 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1303 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1304 } 1305 db_tr = dbch->top; 1306 for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1307 fwohci_add_tx_buf(db_tr, 1308 dbch->xferq.psize, dbch->xferq.flag, 1309 dbch->xferq.buf + dbch->xferq.psize * idb); 1310 if(STAILQ_NEXT(db_tr, link) == NULL){ 1311 break; 1312 } 1313 db_tr->db[0].db.desc.depend 1314 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1315 db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1316 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1317 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1318 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1319 db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1320 |= OHCI_INTERRUPT_ALWAYS; 1321 db_tr->db[0].db.desc.depend &= ~0xf; 1322 db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1323 ~0xf; 1324 } 1325 } 1326 db_tr = STAILQ_NEXT(db_tr, link); 1327 } 1328 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1329 return err; 1330} 1331 1332static int 1333fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1334{ 1335 int err = 0; 1336 int idb, z, i, dmach = 0; 1337 u_int32_t off = NULL; 1338 struct fwohcidb_tr *db_tr; 1339 1340 z = dbch->ndesc; 1341 if(&sc->arrq == dbch){ 1342 off = OHCI_ARQOFF; 1343 }else if(&sc->arrs == dbch){ 1344 off = OHCI_ARSOFF; 1345 }else{ 1346 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1347 if( &sc->ir[dmach] == dbch){ 1348 off = OHCI_IROFF(dmach); 1349 break; 1350 } 1351 } 1352 } 1353 if(off == NULL){ 1354 err = EINVAL; 1355 return err; 1356 } 1357 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1358 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1359 return err; 1360 }else{ 1361 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1362 err = EBUSY; 1363 return err; 1364 } 1365 } 1366 dbch->xferq.flag |= FWXFERQ_RUNNING; 1367 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1368 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1369 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1370 } 1371 db_tr = dbch->top; 1372 for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1373 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1374 fwohci_add_rx_buf(db_tr, 1375 dbch->xferq.psize, dbch->xferq.flag, 0, NULL); 1376 }else{ 1377 fwohci_add_rx_buf(db_tr, 1378 dbch->xferq.psize, dbch->xferq.flag, 1379 dbch->xferq.buf + dbch->xferq.psize * idb, 1380 dbch->dummy + sizeof(u_int32_t) * idb); 1381 } 1382 if(STAILQ_NEXT(db_tr, link) == NULL){ 1383 break; 1384 } 1385 db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1386 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1387 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1388 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1389 db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1390 |= OHCI_INTERRUPT_ALWAYS; 1391 db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1392 ~0xf; 1393 } 1394 } 1395 db_tr = STAILQ_NEXT(db_tr, link); 1396 } 1397 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1398 dbch->buf_offset = 0; 1399 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1400 return err; 1401 }else{ 1402 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z); 1403 } 1404 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1405 return err; 1406} 1407 1408static int 1409fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1410{ 1411 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1412 int err = 0; 1413 unsigned short tag, ich; 1414 struct fwohci_dbch *dbch; 1415 struct fw_pkt *fp; 1416 struct fwohcidb_tr *db_tr; 1417 1418 tag = (sc->it[dmach].xferq.flag >> 6) & 3; 1419 ich = sc->it[dmach].xferq.flag & 0x3f; 1420 dbch = &sc->it[dmach]; 1421 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1422 dbch->xferq.queued = 0; 1423 dbch->ndb = dbch->xferq.bnpacket * dbch->xferq.bnchunk; 1424 dbch->ndesc = 3; 1425 fwohci_db_init(dbch); 1426 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1427 return ENOMEM; 1428 err = fwohci_tx_enable(sc, dbch); 1429 } 1430 if(err) 1431 return err; 1432 if(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){ 1433 if(dbch->xferq.stdma2 != NULL){ 1434 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1435 ((struct fwohcidb_tr *) 1436 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1437 |= OHCI_BRANCH_ALWAYS; 1438 ((struct fwohcidb_tr *) 1439 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1440 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1441 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1442 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1443 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1444 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1445 } 1446 }else if(!(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1447 fw_tbuf_update(&sc->fc, dmach, 0); 1448 if(dbch->xferq.stdma == NULL){ 1449 return err; 1450 } 1451 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1452 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1453 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1454 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1455 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xf0000000); 1456 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma); 1457 if(dbch->xferq.stdma2 != NULL){ 1458 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1459 ((struct fwohcidb_tr *) 1460 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1461 |= OHCI_BRANCH_ALWAYS; 1462 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1463 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1464 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1465 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1466 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1467 ((struct fwohcidb_tr *) (dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1468 }else{ 1469 ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1470 ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1471 } 1472 OWRITE(sc, OHCI_ITCMD(dmach), 1473 vtophys(((struct fwohcidb_tr *) 1474 (dbch->xferq.stdma->start))->db) | dbch->ndesc); 1475 if(dbch->xferq.flag & FWXFERQ_DV){ 1476 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1477 fp = (struct fw_pkt *)db_tr->buf; 1478 dbch->xferq.dvoffset = 1479 ((fc->cyctimer(fc) >> 12) + 4) & 0xf; 1480#if 0 1481 printf("dvoffset: %d\n", dbch->xferq.dvoffset); 1482#endif 1483 fp->mode.ld[2] |= htonl(dbch->xferq.dvoffset << 12); 1484 } 1485 1486 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1487 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1488 } 1489 return err; 1490} 1491 1492static int 1493fwohci_irxbuf_enable(struct firewire_comm *fc, int dmach) 1494{ 1495 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1496 int err = 0; 1497 unsigned short tag, ich; 1498 1499 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1500 tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1501 ich = sc->ir[dmach].xferq.flag & 0x3f; 1502 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1503 1504 sc->ir[dmach].xferq.queued = 0; 1505 sc->ir[dmach].ndb = sc->ir[dmach].xferq.bnpacket * 1506 sc->ir[dmach].xferq.bnchunk; 1507 sc->ir[dmach].dummy = 1508 malloc(sizeof(u_int32_t) * sc->ir[dmach].ndb, 1509 M_DEVBUF, M_DONTWAIT); 1510 if(sc->ir[dmach].dummy == NULL){ 1511 err = ENOMEM; 1512 return err; 1513 } 1514 sc->ir[dmach].ndesc = 2; 1515 fwohci_db_init(&sc->ir[dmach]); 1516 if ((sc->ir[dmach].flags & FWOHCI_DBCH_INIT) == 0) 1517 return ENOMEM; 1518 err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1519 } 1520 if(err) 1521 return err; 1522 1523 if(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){ 1524 if(sc->ir[dmach].xferq.stdma2 != NULL){ 1525 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1526 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1527 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1528 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1529 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1530 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1531 } 1532 }else if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE) 1533 && !(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET)){ 1534 fw_rbuf_update(&sc->fc, dmach, 0); 1535 1536 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1537 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1538 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1539 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1540 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1541 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1542 if(sc->ir[dmach].xferq.stdma2 != NULL){ 1543 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1544 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1545 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1546 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1547 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1548 }else{ 1549 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1550 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1551 } 1552 OWRITE(sc, OHCI_IRCMD(dmach), 1553 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->start))->db) | sc->ir[dmach].ndesc); 1554 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1555 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1556 } 1557 return err; 1558} 1559 1560static int 1561fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1562{ 1563 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1564 int err = 0; 1565 1566 if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){ 1567 err = fwohci_irxpp_enable(fc, dmach); 1568 return err; 1569 }else{ 1570 err = fwohci_irxbuf_enable(fc, dmach); 1571 return err; 1572 } 1573} 1574 1575int 1576fwohci_shutdown(struct fwohci_softc *sc, device_t dev) 1577{ 1578 u_int i; 1579 1580/* Now stopping all DMA channel */ 1581 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1582 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1583 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1584 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1585 1586 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1587 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1588 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1589 } 1590 1591/* FLUSH FIFO and reset Transmitter/Reciever */ 1592 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1593 1594/* Stop interrupt */ 1595 OWRITE(sc, FWOHCI_INTMASKCLR, 1596 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1597 | OHCI_INT_PHY_INT 1598 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1599 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1600 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1601 | OHCI_INT_PHY_BUS_R); 1602/* XXX Link down? Bus reset? */ 1603 return 0; 1604} 1605 1606int 1607fwohci_resume(struct fwohci_softc *sc, device_t dev) 1608{ 1609 int i; 1610 1611 fwohci_reset(sc, dev); 1612 /* XXX resume isochronus receive automatically. (how about TX?) */ 1613 for(i = 0; i < sc->fc.nisodma; i ++) { 1614 if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) { 1615 device_printf(sc->fc.dev, 1616 "resume iso receive ch: %d\n", i); 1617 sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING; 1618 sc->fc.irx_enable(&sc->fc, i); 1619 } 1620 } 1621 1622 bus_generic_resume(dev); 1623 sc->fc.ibr(&sc->fc); 1624 return 0; 1625} 1626 1627#define ACK_ALL 1628static void 1629fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1630{ 1631 u_int32_t irstat, itstat; 1632 u_int i; 1633 struct firewire_comm *fc = (struct firewire_comm *)sc; 1634 1635#ifdef OHCI_DEBUG 1636 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1637 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1638 stat & OHCI_INT_EN ? "DMA_EN ":"", 1639 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1640 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1641 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1642 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1643 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1644 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1645 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1646 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1647 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1648 stat & OHCI_INT_PHY_SID ? "SID ":"", 1649 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1650 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1651 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1652 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1653 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1654 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1655 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1656 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1657 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1658 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1659 stat, OREAD(sc, FWOHCI_INTMASK) 1660 ); 1661#endif 1662/* Bus reset */ 1663 if(stat & OHCI_INT_PHY_BUS_R ){ 1664 device_printf(fc->dev, "BUS reset\n"); 1665 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1666 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1667 1668 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1669 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1670 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1671 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1672 1673#if 0 1674 for( i = 0 ; i < fc->nisodma ; i ++ ){ 1675 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1676 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1677 } 1678 1679#endif 1680 fw_busreset(fc); 1681 1682 /* XXX need to wait DMA to stop */ 1683#ifndef ACK_ALL 1684 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1685#endif 1686#if 1 1687 /* pending all pre-bus_reset packets */ 1688 fwohci_txd(sc, &sc->atrq); 1689 fwohci_txd(sc, &sc->atrs); 1690 fwohci_arcv(sc, &sc->arrs, -1); 1691 fwohci_arcv(sc, &sc->arrq, -1); 1692#endif 1693 1694 1695 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1696 /* XXX insecure ?? */ 1697 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1698 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1699 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1700 1701 } 1702 if((stat & OHCI_INT_DMA_IR )){ 1703#ifndef ACK_ALL 1704 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1705#endif 1706 irstat = OREAD(sc, OHCI_IR_STAT); 1707 OWRITE(sc, OHCI_IR_STATCLR, ~0); 1708 for(i = 0; i < fc->nisodma ; i++){ 1709 if((irstat & (1 << i)) != 0){ 1710 if(sc->ir[i].xferq.flag & FWXFERQ_PACKET){ 1711 fwohci_ircv(sc, &sc->ir[i], count); 1712 }else{ 1713 fwohci_rbuf_update(sc, i); 1714 } 1715 } 1716 } 1717 } 1718 if((stat & OHCI_INT_DMA_IT )){ 1719#ifndef ACK_ALL 1720 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1721#endif 1722 itstat = OREAD(sc, OHCI_IT_STAT); 1723 OWRITE(sc, OHCI_IT_STATCLR, ~0); 1724 for(i = 0; i < fc->nisodma ; i++){ 1725 if((itstat & (1 << i)) != 0){ 1726 fwohci_tbuf_update(sc, i); 1727 } 1728 } 1729 } 1730 if((stat & OHCI_INT_DMA_PRRS )){ 1731#ifndef ACK_ALL 1732 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1733#endif 1734#if 0 1735 dump_dma(sc, ARRS_CH); 1736 dump_db(sc, ARRS_CH); 1737#endif 1738 fwohci_arcv(sc, &sc->arrs, count); 1739 } 1740 if((stat & OHCI_INT_DMA_PRRQ )){ 1741#ifndef ACK_ALL 1742 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1743#endif 1744#if 0 1745 dump_dma(sc, ARRQ_CH); 1746 dump_db(sc, ARRQ_CH); 1747#endif 1748 fwohci_arcv(sc, &sc->arrq, count); 1749 } 1750 if(stat & OHCI_INT_PHY_SID){ 1751 caddr_t buf; 1752 int plen; 1753 1754#ifndef ACK_ALL 1755 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1756#endif 1757/* 1758** Checking whether the node is root or not. If root, turn on 1759** cycle master. 1760*/ 1761 device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID)); 1762 if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){ 1763 printf("Bus reset failure\n"); 1764 goto sidout; 1765 } 1766 if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){ 1767 printf("CYCLEMASTER mode\n"); 1768 OWRITE(sc, OHCI_LNKCTL, 1769 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1770 }else{ 1771 printf("non CYCLEMASTER mode\n"); 1772 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1773 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1774 } 1775 fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f; 1776 1777 plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK; 1778 plen -= 4; /* chop control info */ 1779 buf = malloc( FWPMAX_S400, M_DEVBUF, M_NOWAIT); 1780 if(buf == NULL) goto sidout; 1781 bcopy((void *)(uintptr_t)(volatile void *)(fc->sid_buf + 1), 1782 buf, plen); 1783 fw_sidrcv(fc, buf, plen, 0); 1784 } 1785sidout: 1786 if((stat & OHCI_INT_DMA_ATRQ )){ 1787#ifndef ACK_ALL 1788 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1789#endif 1790 fwohci_txd(sc, &(sc->atrq)); 1791 } 1792 if((stat & OHCI_INT_DMA_ATRS )){ 1793#ifndef ACK_ALL 1794 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1795#endif 1796 fwohci_txd(sc, &(sc->atrs)); 1797 } 1798 if((stat & OHCI_INT_PW_ERR )){ 1799#ifndef ACK_ALL 1800 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1801#endif 1802 device_printf(fc->dev, "posted write error\n"); 1803 } 1804 if((stat & OHCI_INT_ERR )){ 1805#ifndef ACK_ALL 1806 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1807#endif 1808 device_printf(fc->dev, "unrecoverable error\n"); 1809 } 1810 if((stat & OHCI_INT_PHY_INT)) { 1811#ifndef ACK_ALL 1812 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1813#endif 1814 device_printf(fc->dev, "phy int\n"); 1815 } 1816 1817 return; 1818} 1819 1820void 1821fwohci_intr(void *arg) 1822{ 1823 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1824 u_int32_t stat; 1825 1826 if (!(sc->intmask & OHCI_INT_EN)) { 1827 /* polling mode */ 1828 return; 1829 } 1830 1831 while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) { 1832 if (stat == 0xffffffff) { 1833 device_printf(sc->fc.dev, 1834 "device physically ejected?\n"); 1835 return; 1836 } 1837#ifdef ACK_ALL 1838 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1839#endif 1840 fwohci_intr_body(sc, stat, -1); 1841 } 1842} 1843 1844static void 1845fwohci_poll(struct firewire_comm *fc, int quick, int count) 1846{ 1847 int s; 1848 u_int32_t stat; 1849 struct fwohci_softc *sc; 1850 1851 1852 sc = (struct fwohci_softc *)fc; 1853 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 1854 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 1855 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 1856#if 0 1857 if (!quick) { 1858#else 1859 if (1) { 1860#endif 1861 stat = OREAD(sc, FWOHCI_INTSTAT); 1862 if (stat == 0) 1863 return; 1864 if (stat == 0xffffffff) { 1865 device_printf(sc->fc.dev, 1866 "device physically ejected?\n"); 1867 return; 1868 } 1869#ifdef ACK_ALL 1870 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1871#endif 1872 } 1873 s = splfw(); 1874 fwohci_intr_body(sc, stat, count); 1875 splx(s); 1876} 1877 1878static void 1879fwohci_set_intr(struct firewire_comm *fc, int enable) 1880{ 1881 struct fwohci_softc *sc; 1882 1883 sc = (struct fwohci_softc *)fc; 1884 if (bootverbose) 1885 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 1886 if (enable) { 1887 sc->intmask |= OHCI_INT_EN; 1888 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 1889 } else { 1890 sc->intmask &= ~OHCI_INT_EN; 1891 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 1892 } 1893} 1894 1895static void 1896fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 1897{ 1898 int stat; 1899 struct firewire_comm *fc = &sc->fc; 1900 struct fw_pkt *fp; 1901 struct fwohci_dbch *dbch; 1902 struct fwohcidb_tr *db_tr; 1903 1904 dbch = &sc->it[dmach]; 1905#if 0 /* XXX OHCI interrupt before the last packet is really on the wire */ 1906 if((dbch->xferq.flag & FWXFERQ_DV) && (dbch->xferq.stdma2 != NULL)){ 1907 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma2->start; 1908/* 1909 * Overwrite highest significant 4 bits timestamp information 1910 */ 1911 fp = (struct fw_pkt *)db_tr->buf; 1912 fp->mode.ld[2] &= htonl(0xffff0fff); 1913 fp->mode.ld[2] |= htonl((fc->cyctimer(fc) + 0x4000) & 0xf000); 1914 } 1915#endif 1916 stat = OREAD(sc, OHCI_ITCTL(dmach)) & 0x1f; 1917 switch(stat){ 1918 case FWOHCIEV_ACKCOMPL: 1919#if 1 1920 if (dbch->xferq.flag & FWXFERQ_DV) { 1921 struct ciphdr *ciph; 1922 int timer, timestamp, cycl, diff; 1923 static int last_timer=0; 1924 1925 timer = (fc->cyctimer(fc) >> 12) & 0xffff; 1926 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1927 fp = (struct fw_pkt *)db_tr->buf; 1928 ciph = (struct ciphdr *) &fp->mode.ld[1]; 1929 timestamp = db_tr->db[2].db.desc.count & 0xffff; 1930 cycl = ntohs(ciph->fdf.dv.cyc) >> 12; 1931 diff = cycl - (timestamp & 0xf) - 1; 1932 if (diff < 0) 1933 diff += 16; 1934 if (diff > 8) 1935 diff -= 16; 1936 if (firewire_debug) 1937 printf("dbc: %3d timer: 0x%04x packet: 0x%04x" 1938 " cyc: 0x%x diff: %+1d\n", 1939 ciph->dbc, last_timer, timestamp, cycl, diff); 1940 last_timer = timer; 1941 /* XXX adjust dbch->xferq.dvoffset if diff != 0 or 1 */ 1942 } 1943#endif 1944 fw_tbuf_update(fc, dmach, 1); 1945 break; 1946 default: 1947 device_printf(fc->dev, "Isochronous transmit err %02x\n", stat); 1948 fw_tbuf_update(fc, dmach, 0); 1949 break; 1950 } 1951 fwohci_itxbuf_enable(fc, dmach); 1952} 1953 1954static void 1955fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 1956{ 1957 struct firewire_comm *fc = &sc->fc; 1958 int stat; 1959 1960 stat = OREAD(sc, OHCI_IRCTL(dmach)) & 0x1f; 1961 switch(stat){ 1962 case FWOHCIEV_ACKCOMPL: 1963 fw_rbuf_update(fc, dmach, 1); 1964 wakeup(fc->ir[dmach]); 1965 fwohci_irx_enable(fc, dmach); 1966 break; 1967 default: 1968 device_printf(fc->dev, "Isochronous receive err %02x\n", 1969 stat); 1970 break; 1971 } 1972} 1973 1974void 1975dump_dma(struct fwohci_softc *sc, u_int32_t ch) 1976{ 1977 u_int32_t off, cntl, stat, cmd, match; 1978 1979 if(ch == 0){ 1980 off = OHCI_ATQOFF; 1981 }else if(ch == 1){ 1982 off = OHCI_ATSOFF; 1983 }else if(ch == 2){ 1984 off = OHCI_ARQOFF; 1985 }else if(ch == 3){ 1986 off = OHCI_ARSOFF; 1987 }else if(ch < IRX_CH){ 1988 off = OHCI_ITCTL(ch - ITX_CH); 1989 }else{ 1990 off = OHCI_IRCTL(ch - IRX_CH); 1991 } 1992 cntl = stat = OREAD(sc, off); 1993 cmd = OREAD(sc, off + 0xc); 1994 match = OREAD(sc, off + 0x10); 1995 1996 device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n", 1997 ch, 1998 cntl, 1999 stat, 2000 cmd, 2001 match); 2002 stat &= 0xffff ; 2003 if(stat & 0xff00){ 2004 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2005 ch, 2006 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2007 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2008 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2009 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2010 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2011 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2012 fwohcicode[stat & 0x1f], 2013 stat & 0x1f 2014 ); 2015 }else{ 2016 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2017 } 2018} 2019 2020void 2021dump_db(struct fwohci_softc *sc, u_int32_t ch) 2022{ 2023 struct fwohci_dbch *dbch; 2024 struct fwohcidb_tr *cp = NULL, *pp, *np; 2025 volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2026 int idb, jdb; 2027 u_int32_t cmd, off; 2028 if(ch == 0){ 2029 off = OHCI_ATQOFF; 2030 dbch = &sc->atrq; 2031 }else if(ch == 1){ 2032 off = OHCI_ATSOFF; 2033 dbch = &sc->atrs; 2034 }else if(ch == 2){ 2035 off = OHCI_ARQOFF; 2036 dbch = &sc->arrq; 2037 }else if(ch == 3){ 2038 off = OHCI_ARSOFF; 2039 dbch = &sc->arrs; 2040 }else if(ch < IRX_CH){ 2041 off = OHCI_ITCTL(ch - ITX_CH); 2042 dbch = &sc->it[ch - ITX_CH]; 2043 }else { 2044 off = OHCI_IRCTL(ch - IRX_CH); 2045 dbch = &sc->ir[ch - IRX_CH]; 2046 } 2047 cmd = OREAD(sc, off + 0xc); 2048 2049 if( dbch->ndb == 0 ){ 2050 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2051 return; 2052 } 2053 pp = dbch->top; 2054 prev = pp->db; 2055 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2056 if(pp == NULL){ 2057 curr = NULL; 2058 goto outdb; 2059 } 2060 cp = STAILQ_NEXT(pp, link); 2061 if(cp == NULL){ 2062 curr = NULL; 2063 goto outdb; 2064 } 2065 np = STAILQ_NEXT(cp, link); 2066 if(cp == NULL) break; 2067 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2068 if((cmd & 0xfffffff0) 2069 == vtophys(&(cp->db[jdb]))){ 2070 curr = cp->db; 2071 if(np != NULL){ 2072 next = np->db; 2073 }else{ 2074 next = NULL; 2075 } 2076 goto outdb; 2077 } 2078 } 2079 pp = STAILQ_NEXT(pp, link); 2080 prev = pp->db; 2081 } 2082outdb: 2083 if( curr != NULL){ 2084 printf("Prev DB %d\n", ch); 2085 print_db(prev, ch, dbch->ndesc); 2086 printf("Current DB %d\n", ch); 2087 print_db(curr, ch, dbch->ndesc); 2088 printf("Next DB %d\n", ch); 2089 print_db(next, ch, dbch->ndesc); 2090 }else{ 2091 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2092 } 2093 return; 2094} 2095 2096void 2097print_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max) 2098{ 2099 fwohcireg_t stat; 2100 int i, key; 2101 2102 if(db == NULL){ 2103 printf("No Descriptor is found\n"); 2104 return; 2105 } 2106 2107 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2108 ch, 2109 "Current", 2110 "OP ", 2111 "KEY", 2112 "INT", 2113 "BR ", 2114 "len", 2115 "Addr", 2116 "Depend", 2117 "Stat", 2118 "Cnt"); 2119 for( i = 0 ; i <= max ; i ++){ 2120 key = db[i].db.desc.cmd & OHCI_KEY_MASK; 2121#if __FreeBSD_version >= 500000 2122 printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x", 2123#else 2124 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2125#endif 2126 vtophys(&db[i]), 2127 dbcode[(db[i].db.desc.cmd >> 28) & 0xf], 2128 dbkey[(db[i].db.desc.cmd >> 24) & 0x7], 2129 dbcond[(db[i].db.desc.cmd >> 20) & 0x3], 2130 dbcond[(db[i].db.desc.cmd >> 18) & 0x3], 2131 db[i].db.desc.cmd & 0xffff, 2132 db[i].db.desc.addr, 2133 db[i].db.desc.depend, 2134 db[i].db.desc.status, 2135 db[i].db.desc.count); 2136 stat = db[i].db.desc.status; 2137 if(stat & 0xff00){ 2138 printf(" %s%s%s%s%s%s %s(%x)\n", 2139 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2140 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2141 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2142 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2143 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2144 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2145 fwohcicode[stat & 0x1f], 2146 stat & 0x1f 2147 ); 2148 }else{ 2149 printf(" Nostat\n"); 2150 } 2151 if(key == OHCI_KEY_ST2 ){ 2152 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2153 db[i+1].db.immed[0], 2154 db[i+1].db.immed[1], 2155 db[i+1].db.immed[2], 2156 db[i+1].db.immed[3]); 2157 } 2158 if(key == OHCI_KEY_DEVICE){ 2159 return; 2160 } 2161 if((db[i].db.desc.cmd & OHCI_BRANCH_MASK) 2162 == OHCI_BRANCH_ALWAYS){ 2163 return; 2164 } 2165 if((db[i].db.desc.cmd & OHCI_CMD_MASK) 2166 == OHCI_OUTPUT_LAST){ 2167 return; 2168 } 2169 if((db[i].db.desc.cmd & OHCI_CMD_MASK) 2170 == OHCI_INPUT_LAST){ 2171 return; 2172 } 2173 if(key == OHCI_KEY_ST2 ){ 2174 i++; 2175 } 2176 } 2177 return; 2178} 2179 2180void 2181fwohci_ibr(struct firewire_comm *fc) 2182{ 2183 struct fwohci_softc *sc; 2184 u_int32_t fun; 2185 2186 sc = (struct fwohci_softc *)fc; 2187 2188 /* 2189 * Set root hold-off bit so that non cyclemaster capable node 2190 * shouldn't became the root node. 2191 */ 2192 fun = fwphy_rddata(sc, FW_PHY_RHB_REG); 2193 fun |= FW_PHY_RHB; 2194 fun = fwphy_wrdata(sc, FW_PHY_RHB_REG, fun); 2195#if 1 2196 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2197 fun |= FW_PHY_IBR; 2198 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2199#else 2200 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2201 fun |= FW_PHY_ISBR; 2202 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2203#endif 2204} 2205 2206void 2207fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2208{ 2209 struct fwohcidb_tr *db_tr, *fdb_tr; 2210 struct fwohci_dbch *dbch; 2211 struct fw_pkt *fp; 2212 volatile struct fwohci_txpkthdr *ohcifp; 2213 unsigned short chtag; 2214 int idb; 2215 2216 dbch = &sc->it[dmach]; 2217 chtag = sc->it[dmach].xferq.flag & 0xff; 2218 2219 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2220 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2221/* 2222device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2223*/ 2224 if(bulkxfer->flag != 0){ 2225 return; 2226 } 2227 bulkxfer->flag = 1; 2228 for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){ 2229 db_tr->db[0].db.desc.cmd 2230 = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2231 fp = (struct fw_pkt *)db_tr->buf; 2232 ohcifp = (volatile struct fwohci_txpkthdr *) 2233 db_tr->db[1].db.immed; 2234 ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]); 2235 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 2236 ohcifp->mode.stream.chtag = chtag; 2237 ohcifp->mode.stream.tcode = 0xa; 2238 ohcifp->mode.stream.spd = 4; 2239 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[1]); 2240 ohcifp->mode.ld[3] = ntohl(fp->mode.ld[2]); 2241 2242 db_tr->db[2].db.desc.cmd 2243 = OHCI_OUTPUT_LAST 2244 | OHCI_UPDATE 2245 | OHCI_BRANCH_ALWAYS 2246 | ((ntohs(fp->mode.stream.len) ) & 0xffff); 2247 db_tr->db[2].db.desc.status = 0; 2248 db_tr->db[2].db.desc.count = 0; 2249 if(dbch->xferq.flag & FWXFERQ_DV){ 2250 db_tr->db[0].db.desc.depend 2251 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2252 db_tr->db[dbch->ndesc - 1].db.desc.depend 2253 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2254 }else{ 2255 db_tr->db[0].db.desc.depend 2256 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2257 db_tr->db[dbch->ndesc - 1].db.desc.depend 2258 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2259 } 2260 bulkxfer->end = (caddr_t)db_tr; 2261 db_tr = STAILQ_NEXT(db_tr, link); 2262 } 2263 db_tr = (struct fwohcidb_tr *)bulkxfer->end; 2264 db_tr->db[0].db.desc.depend &= ~0xf; 2265 db_tr->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 2266/**/ 2267 db_tr->db[dbch->ndesc - 1].db.desc.cmd &= ~OHCI_BRANCH_ALWAYS; 2268 db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_BRANCH_NEVER; 2269/**/ 2270 db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS; 2271 2272 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2273 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2274/* 2275device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2276*/ 2277 return; 2278} 2279 2280static int 2281fwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size, 2282 int mode, void *buf) 2283{ 2284 volatile struct fwohcidb *db = db_tr->db; 2285 int err = 0; 2286 if(buf == 0){ 2287 err = EINVAL; 2288 return err; 2289 } 2290 db_tr->buf = buf; 2291 db_tr->dbcnt = 3; 2292 db_tr->dummy = NULL; 2293 2294 db[0].db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2295 2296 db[2].db.desc.depend = 0; 2297 db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t); 2298 db[2].db.desc.cmd = OHCI_OUTPUT_MORE; 2299 2300 db[0].db.desc.status = 0; 2301 db[0].db.desc.count = 0; 2302 2303 db[2].db.desc.status = 0; 2304 db[2].db.desc.count = 0; 2305 if( mode & FWXFERQ_STREAM ){ 2306 db[2].db.desc.cmd |= OHCI_OUTPUT_LAST; 2307 if(mode & FWXFERQ_PACKET ){ 2308 db[2].db.desc.cmd 2309 |= OHCI_INTERRUPT_ALWAYS; 2310 } 2311 } 2312 db[2].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2313 return 1; 2314} 2315 2316int 2317fwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode, 2318 void *buf, void *dummy) 2319{ 2320 volatile struct fwohcidb *db = db_tr->db; 2321 int i; 2322 void *dbuf[2]; 2323 int dsiz[2]; 2324 2325 if(buf == 0){ 2326 buf = malloc(size, M_DEVBUF, M_NOWAIT); 2327 if(buf == NULL) return 0; 2328 db_tr->buf = buf; 2329 db_tr->dbcnt = 1; 2330 db_tr->dummy = NULL; 2331 dsiz[0] = size; 2332 dbuf[0] = buf; 2333 }else if(dummy == NULL){ 2334 db_tr->buf = buf; 2335 db_tr->dbcnt = 1; 2336 db_tr->dummy = NULL; 2337 dsiz[0] = size; 2338 dbuf[0] = buf; 2339 }else{ 2340 db_tr->buf = buf; 2341 db_tr->dbcnt = 2; 2342 db_tr->dummy = dummy; 2343 dsiz[0] = sizeof(u_int32_t); 2344 dsiz[1] = size; 2345 dbuf[0] = dummy; 2346 dbuf[1] = buf; 2347 } 2348 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2349 db[i].db.desc.addr = vtophys(dbuf[i]) ; 2350 db[i].db.desc.cmd = OHCI_INPUT_MORE | dsiz[i]; 2351 if( mode & FWXFERQ_STREAM ){ 2352 db[i].db.desc.cmd |= OHCI_UPDATE; 2353 } 2354 db[i].db.desc.status = 0; 2355 db[i].db.desc.count = dsiz[i]; 2356 } 2357 if( mode & FWXFERQ_STREAM ){ 2358 db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_INPUT_LAST; 2359 if(mode & FWXFERQ_PACKET ){ 2360 db[db_tr->dbcnt - 1].db.desc.cmd 2361 |= OHCI_INTERRUPT_ALWAYS; 2362 } 2363 } 2364 db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2365 return 1; 2366} 2367 2368static void 2369fwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2370{ 2371 struct fwohcidb_tr *db_tr = dbch->top, *odb_tr; 2372 struct firewire_comm *fc = (struct firewire_comm *)sc; 2373 int z = 1; 2374 struct fw_pkt *fp; 2375 u_int8_t *ld; 2376 u_int32_t off = NULL; 2377 u_int32_t stat; 2378 u_int32_t *qld; 2379 u_int32_t reg; 2380 u_int spd; 2381 u_int dmach; 2382 int len, i, plen; 2383 caddr_t buf; 2384 2385 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 2386 if( &sc->ir[dmach] == dbch){ 2387 off = OHCI_IROFF(dmach); 2388 break; 2389 } 2390 } 2391 if(off == NULL){ 2392 return; 2393 } 2394 if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){ 2395 fwohci_irx_disable(&sc->fc, dmach); 2396 return; 2397 } 2398 2399 odb_tr = NULL; 2400 db_tr = dbch->top; 2401 i = 0; 2402 while ((reg = db_tr->db[0].db.desc.status) & 0x1f) { 2403 if (count >= 0 && count-- == 0) 2404 break; 2405 ld = (u_int8_t *)db_tr->buf; 2406 if (dbch->xferq.flag & FWXFERQ_PACKET) { 2407 /* skip timeStamp */ 2408 ld += sizeof(struct fwohci_trailer); 2409 } 2410 qld = (u_int32_t *)ld; 2411 len = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2412/* 2413{ 2414device_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len, 2415 db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]); 2416} 2417*/ 2418 fp=(struct fw_pkt *)ld; 2419 qld[0] = htonl(qld[0]); 2420 plen = sizeof(struct fw_isohdr) 2421 + ntohs(fp->mode.stream.len) + sizeof(u_int32_t); 2422 ld += plen; 2423 len -= plen; 2424 buf = db_tr->buf; 2425 db_tr->buf = NULL; 2426 stat = reg & 0x1f; 2427 spd = reg & 0x3; 2428 switch(stat){ 2429 case FWOHCIEV_ACKCOMPL: 2430 case FWOHCIEV_ACKPEND: 2431 fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd); 2432 break; 2433 default: 2434 free(buf, M_DEVBUF); 2435 device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat); 2436 break; 2437 } 2438 i++; 2439 fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2440 dbch->xferq.flag, 0, NULL); 2441 db_tr->db[0].db.desc.depend &= ~0xf; 2442 if(dbch->pdb_tr != NULL){ 2443 dbch->pdb_tr->db[0].db.desc.depend |= z; 2444 } else { 2445 /* XXX should be rewritten in better way */ 2446 dbch->bottom->db[0].db.desc.depend |= z; 2447 } 2448 dbch->pdb_tr = db_tr; 2449 db_tr = STAILQ_NEXT(db_tr, link); 2450 } 2451 dbch->top = db_tr; 2452 reg = OREAD(sc, OHCI_DMACTL(off)); 2453 if (reg & OHCI_CNTL_DMA_ACTIVE) 2454 return; 2455 device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n", 2456 dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i); 2457 dbch->top = db_tr; 2458 fwohci_irx_enable(fc, dmach); 2459} 2460 2461#define PLEN(x) (((ntohs(x))+0x3) & ~0x3) 2462static int 2463fwohci_get_plen(struct fwohci_softc *sc, struct fw_pkt *fp, int hlen) 2464{ 2465 int i; 2466 2467 for( i = 4; i < hlen ; i+=4){ 2468 fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]); 2469 } 2470 2471 switch(fp->mode.common.tcode){ 2472 case FWTCODE_RREQQ: 2473 return sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2474 case FWTCODE_WRES: 2475 return sizeof(fp->mode.wres) + sizeof(u_int32_t); 2476 case FWTCODE_WREQQ: 2477 return sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2478 case FWTCODE_RREQB: 2479 return sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2480 case FWTCODE_RRESQ: 2481 return sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2482 case FWTCODE_WREQB: 2483 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2484 + sizeof(u_int32_t); 2485 case FWTCODE_LREQ: 2486 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2487 + sizeof(u_int32_t); 2488 case FWTCODE_RRESB: 2489 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2490 + sizeof(u_int32_t); 2491 case FWTCODE_LRES: 2492 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2493 + sizeof(u_int32_t); 2494 case FWOHCITCODE_PHY: 2495 return 16; 2496 } 2497 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2498 return 0; 2499} 2500 2501static void 2502fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2503{ 2504 struct fwohcidb_tr *db_tr; 2505 int z = 1; 2506 struct fw_pkt *fp; 2507 u_int8_t *ld; 2508 u_int32_t stat, off; 2509 u_int spd; 2510 int len, plen, hlen, pcnt, poff = 0, rlen; 2511 int s; 2512 caddr_t buf; 2513 int resCount; 2514 2515 if(&sc->arrq == dbch){ 2516 off = OHCI_ARQOFF; 2517 }else if(&sc->arrs == dbch){ 2518 off = OHCI_ARSOFF; 2519 }else{ 2520 return; 2521 } 2522 2523 s = splfw(); 2524 db_tr = dbch->top; 2525 pcnt = 0; 2526 /* XXX we cannot handle a packet which lies in more than two buf */ 2527 while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) { 2528 ld = (u_int8_t *)db_tr->buf + dbch->buf_offset; 2529 resCount = db_tr->db[0].db.desc.count; 2530 len = dbch->xferq.psize - resCount 2531 - dbch->buf_offset; 2532 while (len > 0 ) { 2533 if (count >= 0 && count-- == 0) 2534 goto out; 2535 if(dbch->frag.buf != NULL){ 2536 buf = dbch->frag.buf; 2537 if (dbch->frag.plen < 0) { 2538 /* incomplete header */ 2539 int hlen; 2540 2541 hlen = - dbch->frag.plen; 2542 rlen = hlen - dbch->frag.len; 2543 bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen); 2544 ld += rlen; 2545 len -= rlen; 2546 dbch->frag.len += rlen; 2547#if 0 2548 printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2549#endif 2550 fp=(struct fw_pkt *)dbch->frag.buf; 2551 dbch->frag.plen 2552 = fwohci_get_plen(sc, fp, hlen); 2553 if (dbch->frag.plen == 0) 2554 goto out; 2555 } 2556 rlen = dbch->frag.plen - dbch->frag.len; 2557#if 0 2558 printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2559#endif 2560 bcopy(ld, dbch->frag.buf + dbch->frag.len, 2561 rlen); 2562 ld += rlen; 2563 len -= rlen; 2564 plen = dbch->frag.plen; 2565 dbch->frag.buf = NULL; 2566 dbch->frag.plen = 0; 2567 dbch->frag.len = 0; 2568 poff = 0; 2569 }else{ 2570 fp=(struct fw_pkt *)ld; 2571 fp->mode.ld[0] = htonl(fp->mode.ld[0]); 2572 switch(fp->mode.common.tcode){ 2573 case FWTCODE_RREQQ: 2574 case FWTCODE_WRES: 2575 case FWTCODE_WREQQ: 2576 case FWTCODE_RRESQ: 2577 case FWOHCITCODE_PHY: 2578 hlen = 12; 2579 break; 2580 case FWTCODE_RREQB: 2581 case FWTCODE_WREQB: 2582 case FWTCODE_LREQ: 2583 case FWTCODE_RRESB: 2584 case FWTCODE_LRES: 2585 hlen = 16; 2586 break; 2587 default: 2588 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2589 goto out; 2590 } 2591 if (len >= hlen) { 2592 plen = fwohci_get_plen(sc, fp, hlen); 2593 if (plen == 0) 2594 goto out; 2595 plen = (plen + 3) & ~3; 2596 len -= plen; 2597 } else { 2598 plen = -hlen; 2599 len -= hlen; 2600 } 2601 if(resCount > 0 || len > 0){ 2602 buf = malloc( dbch->xferq.psize, 2603 M_DEVBUF, M_NOWAIT); 2604 if(buf == NULL){ 2605 printf("cannot malloc!\n"); 2606 free(db_tr->buf, M_DEVBUF); 2607 goto out; 2608 } 2609 bcopy(ld, buf, plen); 2610 poff = 0; 2611 dbch->frag.buf = NULL; 2612 dbch->frag.plen = 0; 2613 dbch->frag.len = 0; 2614 }else if(len < 0){ 2615 dbch->frag.buf = db_tr->buf; 2616 if (plen < 0) { 2617#if 0 2618 printf("plen < 0:" 2619 "hlen: %d len: %d\n", 2620 hlen, len); 2621#endif 2622 dbch->frag.len = hlen + len; 2623 dbch->frag.plen = -hlen; 2624 } else { 2625 dbch->frag.len = plen + len; 2626 dbch->frag.plen = plen; 2627 } 2628 bcopy(ld, db_tr->buf, dbch->frag.len); 2629 buf = NULL; 2630 }else{ 2631 buf = db_tr->buf; 2632 poff = ld - (u_int8_t *)buf; 2633 dbch->frag.buf = NULL; 2634 dbch->frag.plen = 0; 2635 dbch->frag.len = 0; 2636 } 2637 ld += plen; 2638 } 2639 if( buf != NULL){ 2640/* DMA result-code will be written at the tail of packet */ 2641 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2642 spd = (stat >> 5) & 0x3; 2643 stat &= 0x1f; 2644 switch(stat){ 2645 case FWOHCIEV_ACKPEND: 2646#if 0 2647 printf("fwohci_arcv: ack pending..\n"); 2648#endif 2649 /* fall through */ 2650 case FWOHCIEV_ACKCOMPL: 2651 if( poff != 0 ) 2652 bcopy(buf+poff, buf, plen - 4); 2653 fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd); 2654 break; 2655 case FWOHCIEV_BUSRST: 2656 free(buf, M_DEVBUF); 2657 if (sc->fc.status != FWBUSRESET) 2658 printf("got BUSRST packet!?\n"); 2659 break; 2660 default: 2661 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2662#if 0 /* XXX */ 2663 goto out; 2664#endif 2665 break; 2666 } 2667 } 2668 pcnt ++; 2669 }; 2670out: 2671 if (resCount == 0) { 2672 /* done on this buffer */ 2673 fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2674 dbch->xferq.flag, 0, NULL); 2675 dbch->bottom->db[0].db.desc.depend |= z; 2676 dbch->bottom = db_tr; 2677 db_tr = STAILQ_NEXT(db_tr, link); 2678 dbch->top = db_tr; 2679 dbch->buf_offset = 0; 2680 } else { 2681 dbch->buf_offset = dbch->xferq.psize - resCount; 2682 break; 2683 } 2684 /* XXX make sure DMA is not dead */ 2685 } 2686#if 0 2687 if (pcnt < 1) 2688 printf("fwohci_arcv: no packets\n"); 2689#endif 2690 splx(s); 2691} 2692