if_ffec.c revision 271826
1/*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/ffec/if_ffec.c 271826 2014-09-18 20:58:04Z glebius $"); 30 31/* 32 * Driver for Freescale Fast Ethernet Controller, found on imx-series SoCs among 33 * others. Also works for the ENET Gigibit controller found on imx6 and imx28, 34 * but the driver doesn't currently use any of the ENET advanced features other 35 * than enabling gigabit. 36 * 37 * The interface name 'fec' is already taken by netgraph's Fast Etherchannel 38 * (netgraph/ng_fec.c), so we use 'ffec'. 39 * 40 * Requires an FDT entry with at least these properties: 41 * fec: ethernet@02188000 { 42 * compatible = "fsl,imxNN-fec"; 43 * reg = <0x02188000 0x4000>; 44 * interrupts = <150 151>; 45 * phy-mode = "rgmii"; 46 * phy-disable-preamble; // optional 47 * }; 48 * The second interrupt number is for IEEE-1588, and is not currently used; it 49 * need not be present. phy-mode must be one of: "mii", "rmii", "rgmii". 50 * There is also an optional property, phy-disable-preamble, which if present 51 * will disable the preamble bits, cutting the size of each mdio transaction 52 * (and thus the busy-wait time) in half. 53 */ 54 55#include <sys/param.h> 56#include <sys/systm.h> 57#include <sys/bus.h> 58#include <sys/endian.h> 59#include <sys/kernel.h> 60#include <sys/lock.h> 61#include <sys/malloc.h> 62#include <sys/mbuf.h> 63#include <sys/module.h> 64#include <sys/mutex.h> 65#include <sys/rman.h> 66#include <sys/socket.h> 67#include <sys/sockio.h> 68#include <sys/sysctl.h> 69 70#include <machine/bus.h> 71 72#include <net/bpf.h> 73#include <net/if.h> 74#include <net/ethernet.h> 75#include <net/if_dl.h> 76#include <net/if_media.h> 77#include <net/if_types.h> 78#include <net/if_var.h> 79#include <net/if_vlan_var.h> 80 81#include <dev/ffec/if_ffecreg.h> 82#include <dev/ofw/ofw_bus.h> 83#include <dev/ofw/ofw_bus_subr.h> 84#include <dev/mii/mii.h> 85#include <dev/mii/miivar.h> 86#include "miibus_if.h" 87 88/* 89 * There are small differences in the hardware on various SoCs. Not every SoC 90 * we support has its own FECTYPE; most work as GENERIC and only the ones that 91 * need different handling get their own entry. In addition to the types in 92 * this list, there are some flags below that can be ORed into the upper bits. 93 */ 94enum { 95 FECTYPE_NONE, 96 FECTYPE_GENERIC, 97 FECTYPE_IMX53, 98 FECTYPE_IMX6, 99 FECTYPE_MVF, 100}; 101 102/* 103 * Flags that describe general differences between the FEC hardware in various 104 * SoCs. These are ORed into the FECTYPE enum values. 105 */ 106#define FECTYPE_MASK 0x0000ffff 107#define FECFLAG_GBE (0x0001 << 16) 108 109/* 110 * Table of supported FDT compat strings and their associated FECTYPE values. 111 */ 112static struct ofw_compat_data compat_data[] = { 113 {"fsl,imx51-fec", FECTYPE_GENERIC}, 114 {"fsl,imx53-fec", FECTYPE_IMX53}, 115 {"fsl,imx6q-fec", FECTYPE_IMX6 | FECFLAG_GBE}, 116 {"fsl,mvf600-fec", FECTYPE_MVF}, 117 {"fsl,mvf-fec", FECTYPE_MVF}, 118 {NULL, FECTYPE_NONE}, 119}; 120 121/* 122 * Driver data and defines. 123 */ 124#define RX_DESC_COUNT 64 125#define RX_DESC_SIZE (sizeof(struct ffec_hwdesc) * RX_DESC_COUNT) 126#define TX_DESC_COUNT 64 127#define TX_DESC_SIZE (sizeof(struct ffec_hwdesc) * TX_DESC_COUNT) 128 129#define WATCHDOG_TIMEOUT_SECS 5 130#define STATS_HARVEST_INTERVAL 3 131 132struct ffec_bufmap { 133 struct mbuf *mbuf; 134 bus_dmamap_t map; 135}; 136 137enum { 138 PHY_CONN_UNKNOWN, 139 PHY_CONN_MII, 140 PHY_CONN_RMII, 141 PHY_CONN_RGMII 142}; 143 144struct ffec_softc { 145 device_t dev; 146 device_t miibus; 147 struct mii_data * mii_softc; 148 struct ifnet *ifp; 149 int if_flags; 150 struct mtx mtx; 151 struct resource *irq_res; 152 struct resource *mem_res; 153 void * intr_cookie; 154 struct callout ffec_callout; 155 uint8_t phy_conn_type; 156 uint8_t fectype; 157 boolean_t link_is_up; 158 boolean_t is_attached; 159 boolean_t is_detaching; 160 int tx_watchdog_count; 161 int stats_harvest_count; 162 163 bus_dma_tag_t rxdesc_tag; 164 bus_dmamap_t rxdesc_map; 165 struct ffec_hwdesc *rxdesc_ring; 166 bus_addr_t rxdesc_ring_paddr; 167 bus_dma_tag_t rxbuf_tag; 168 struct ffec_bufmap rxbuf_map[RX_DESC_COUNT]; 169 uint32_t rx_idx; 170 171 bus_dma_tag_t txdesc_tag; 172 bus_dmamap_t txdesc_map; 173 struct ffec_hwdesc *txdesc_ring; 174 bus_addr_t txdesc_ring_paddr; 175 bus_dma_tag_t txbuf_tag; 176 struct ffec_bufmap txbuf_map[RX_DESC_COUNT]; 177 uint32_t tx_idx_head; 178 uint32_t tx_idx_tail; 179 int txcount; 180}; 181 182#define FFEC_LOCK(sc) mtx_lock(&(sc)->mtx) 183#define FFEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 184#define FFEC_LOCK_INIT(sc) mtx_init(&(sc)->mtx, \ 185 device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF) 186#define FFEC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx); 187#define FFEC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED); 188#define FFEC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED); 189 190static void ffec_init_locked(struct ffec_softc *sc); 191static void ffec_stop_locked(struct ffec_softc *sc); 192static void ffec_txstart_locked(struct ffec_softc *sc); 193static void ffec_txfinish_locked(struct ffec_softc *sc); 194 195static inline uint16_t 196RD2(struct ffec_softc *sc, bus_size_t off) 197{ 198 199 return (bus_read_2(sc->mem_res, off)); 200} 201 202static inline void 203WR2(struct ffec_softc *sc, bus_size_t off, uint16_t val) 204{ 205 206 bus_write_2(sc->mem_res, off, val); 207} 208 209static inline uint32_t 210RD4(struct ffec_softc *sc, bus_size_t off) 211{ 212 213 return (bus_read_4(sc->mem_res, off)); 214} 215 216static inline void 217WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val) 218{ 219 220 bus_write_4(sc->mem_res, off, val); 221} 222 223static inline uint32_t 224next_rxidx(struct ffec_softc *sc, uint32_t curidx) 225{ 226 227 return ((curidx == RX_DESC_COUNT - 1) ? 0 : curidx + 1); 228} 229 230static inline uint32_t 231next_txidx(struct ffec_softc *sc, uint32_t curidx) 232{ 233 234 return ((curidx == TX_DESC_COUNT - 1) ? 0 : curidx + 1); 235} 236 237static void 238ffec_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 239{ 240 241 if (error != 0) 242 return; 243 *(bus_addr_t *)arg = segs[0].ds_addr; 244} 245 246static void 247ffec_miigasket_setup(struct ffec_softc *sc) 248{ 249 uint32_t ifmode; 250 251 /* 252 * We only need the gasket for MII and RMII connections on certain SoCs. 253 */ 254 255 switch (sc->fectype & FECTYPE_MASK) 256 { 257 case FECTYPE_IMX53: 258 break; 259 default: 260 return; 261 } 262 263 switch (sc->phy_conn_type) 264 { 265 case PHY_CONN_MII: 266 ifmode = 0; 267 break; 268 case PHY_CONN_RMII: 269 ifmode = FEC_MIIGSK_CFGR_IF_MODE_RMII; 270 break; 271 default: 272 return; 273 } 274 275 /* 276 * Disable the gasket, configure for either MII or RMII, then enable. 277 */ 278 279 WR2(sc, FEC_MIIGSK_ENR, 0); 280 while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY) 281 continue; 282 283 WR2(sc, FEC_MIIGSK_CFGR, ifmode); 284 285 WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN); 286 while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)) 287 continue; 288} 289 290static boolean_t 291ffec_miibus_iowait(struct ffec_softc *sc) 292{ 293 uint32_t timeout; 294 295 for (timeout = 10000; timeout != 0; --timeout) 296 if (RD4(sc, FEC_IER_REG) & FEC_IER_MII) 297 return (true); 298 299 return (false); 300} 301 302static int 303ffec_miibus_readreg(device_t dev, int phy, int reg) 304{ 305 struct ffec_softc *sc; 306 int val; 307 308 sc = device_get_softc(dev); 309 310 WR4(sc, FEC_IER_REG, FEC_IER_MII); 311 312 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ | 313 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 314 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 315 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK)); 316 317 if (!ffec_miibus_iowait(sc)) { 318 device_printf(dev, "timeout waiting for mii read\n"); 319 return (-1); /* All-ones is a symptom of bad mdio. */ 320 } 321 322 val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK; 323 324 return (val); 325} 326 327static int 328ffec_miibus_writereg(device_t dev, int phy, int reg, int val) 329{ 330 struct ffec_softc *sc; 331 332 sc = device_get_softc(dev); 333 334 WR4(sc, FEC_IER_REG, FEC_IER_MII); 335 336 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE | 337 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 338 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 339 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK) | 340 (val & FEC_MMFR_DATA_MASK)); 341 342 if (!ffec_miibus_iowait(sc)) { 343 device_printf(dev, "timeout waiting for mii write\n"); 344 return (-1); 345 } 346 347 return (0); 348} 349 350static void 351ffec_miibus_statchg(device_t dev) 352{ 353 struct ffec_softc *sc; 354 struct mii_data *mii; 355 uint32_t ecr, rcr, tcr; 356 357 /* 358 * Called by the MII bus driver when the PHY establishes link to set the 359 * MAC interface registers. 360 */ 361 362 sc = device_get_softc(dev); 363 364 FFEC_ASSERT_LOCKED(sc); 365 366 mii = sc->mii_softc; 367 368 if (mii->mii_media_status & IFM_ACTIVE) 369 sc->link_is_up = true; 370 else 371 sc->link_is_up = false; 372 373 ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED; 374 rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE | 375 FEC_RCR_RGMII_EN | FEC_RCR_DRT | FEC_RCR_FCE); 376 tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN; 377 378 rcr |= FEC_RCR_MII_MODE; /* Must always be on even for R[G]MII. */ 379 switch (sc->phy_conn_type) { 380 case PHY_CONN_MII: 381 break; 382 case PHY_CONN_RMII: 383 rcr |= FEC_RCR_RMII_MODE; 384 break; 385 case PHY_CONN_RGMII: 386 rcr |= FEC_RCR_RGMII_EN; 387 break; 388 } 389 390 switch (IFM_SUBTYPE(mii->mii_media_active)) { 391 case IFM_1000_T: 392 case IFM_1000_SX: 393 ecr |= FEC_ECR_SPEED; 394 break; 395 case IFM_100_TX: 396 /* Not-FEC_ECR_SPEED + not-FEC_RCR_RMII_10T means 100TX */ 397 break; 398 case IFM_10_T: 399 rcr |= FEC_RCR_RMII_10T; 400 break; 401 case IFM_NONE: 402 sc->link_is_up = false; 403 return; 404 default: 405 sc->link_is_up = false; 406 device_printf(dev, "Unsupported media %u\n", 407 IFM_SUBTYPE(mii->mii_media_active)); 408 return; 409 } 410 411 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 412 tcr |= FEC_TCR_FDEN; 413 else 414 rcr |= FEC_RCR_DRT; 415 416 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLOW) != 0) 417 rcr |= FEC_RCR_FCE; 418 419 WR4(sc, FEC_RCR_REG, rcr); 420 WR4(sc, FEC_TCR_REG, tcr); 421 WR4(sc, FEC_ECR_REG, ecr); 422} 423 424static void 425ffec_media_status(struct ifnet * ifp, struct ifmediareq *ifmr) 426{ 427 struct ffec_softc *sc; 428 struct mii_data *mii; 429 430 431 sc = ifp->if_softc; 432 mii = sc->mii_softc; 433 FFEC_LOCK(sc); 434 mii_pollstat(mii); 435 ifmr->ifm_active = mii->mii_media_active; 436 ifmr->ifm_status = mii->mii_media_status; 437 FFEC_UNLOCK(sc); 438} 439 440static int 441ffec_media_change_locked(struct ffec_softc *sc) 442{ 443 444 return (mii_mediachg(sc->mii_softc)); 445} 446 447static int 448ffec_media_change(struct ifnet * ifp) 449{ 450 struct ffec_softc *sc; 451 int error; 452 453 sc = ifp->if_softc; 454 455 FFEC_LOCK(sc); 456 error = ffec_media_change_locked(sc); 457 FFEC_UNLOCK(sc); 458 return (error); 459} 460 461static void ffec_clear_stats(struct ffec_softc *sc) 462{ 463 464 WR4(sc, FEC_RMON_R_PACKETS, 0); 465 WR4(sc, FEC_RMON_R_MC_PKT, 0); 466 WR4(sc, FEC_RMON_R_CRC_ALIGN, 0); 467 WR4(sc, FEC_RMON_R_UNDERSIZE, 0); 468 WR4(sc, FEC_RMON_R_OVERSIZE, 0); 469 WR4(sc, FEC_RMON_R_FRAG, 0); 470 WR4(sc, FEC_RMON_R_JAB, 0); 471 WR4(sc, FEC_RMON_T_PACKETS, 0); 472 WR4(sc, FEC_RMON_T_MC_PKT, 0); 473 WR4(sc, FEC_RMON_T_CRC_ALIGN, 0); 474 WR4(sc, FEC_RMON_T_UNDERSIZE, 0); 475 WR4(sc, FEC_RMON_T_OVERSIZE , 0); 476 WR4(sc, FEC_RMON_T_FRAG, 0); 477 WR4(sc, FEC_RMON_T_JAB, 0); 478 WR4(sc, FEC_RMON_T_COL, 0); 479} 480 481static void 482ffec_harvest_stats(struct ffec_softc *sc) 483{ 484 struct ifnet *ifp; 485 486 /* We don't need to harvest too often. */ 487 if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL) 488 return; 489 490 /* 491 * Try to avoid harvesting unless the IDLE flag is on, but if it has 492 * been too long just go ahead and do it anyway, the worst that'll 493 * happen is we'll lose a packet count or two as we clear at the end. 494 */ 495 if (sc->stats_harvest_count < (2 * STATS_HARVEST_INTERVAL) && 496 ((RD4(sc, FEC_MIBC_REG) & FEC_MIBC_IDLE) == 0)) 497 return; 498 499 sc->stats_harvest_count = 0; 500 ifp = sc->ifp; 501 502 if_inc_counter(ifp, IFCOUNTER_IPACKETS, RD4(sc, FEC_RMON_R_PACKETS)); 503 if_inc_counter(ifp, IFCOUNTER_IMCASTS, RD4(sc, FEC_RMON_R_MC_PKT)); 504 if_inc_counter(ifp, IFCOUNTER_IERRORS, 505 RD4(sc, FEC_RMON_R_CRC_ALIGN) + RD4(sc, FEC_RMON_R_UNDERSIZE) + 506 RD4(sc, FEC_RMON_R_OVERSIZE) + RD4(sc, FEC_RMON_R_FRAG) + 507 RD4(sc, FEC_RMON_R_JAB)); 508 509 if_inc_counter(ifp, IFCOUNTER_OPACKETS, RD4(sc, FEC_RMON_T_PACKETS)); 510 if_inc_counter(ifp, IFCOUNTER_OMCASTS, RD4(sc, FEC_RMON_T_MC_PKT)); 511 if_inc_counter(ifp, IFCOUNTER_OERRORS, 512 RD4(sc, FEC_RMON_T_CRC_ALIGN) + RD4(sc, FEC_RMON_T_UNDERSIZE) + 513 RD4(sc, FEC_RMON_T_OVERSIZE) + RD4(sc, FEC_RMON_T_FRAG) + 514 RD4(sc, FEC_RMON_T_JAB)); 515 516 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, RD4(sc, FEC_RMON_T_COL)); 517 518 ffec_clear_stats(sc); 519} 520 521static void 522ffec_tick(void *arg) 523{ 524 struct ffec_softc *sc; 525 struct ifnet *ifp; 526 int link_was_up; 527 528 sc = arg; 529 530 FFEC_ASSERT_LOCKED(sc); 531 532 ifp = sc->ifp; 533 534 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 535 return; 536 537 /* 538 * Typical tx watchdog. If this fires it indicates that we enqueued 539 * packets for output and never got a txdone interrupt for them. Maybe 540 * it's a missed interrupt somehow, just pretend we got one. 541 */ 542 if (sc->tx_watchdog_count > 0) { 543 if (--sc->tx_watchdog_count == 0) { 544 ffec_txfinish_locked(sc); 545 } 546 } 547 548 /* Gather stats from hardware counters. */ 549 ffec_harvest_stats(sc); 550 551 /* Check the media status. */ 552 link_was_up = sc->link_is_up; 553 mii_tick(sc->mii_softc); 554 if (sc->link_is_up && !link_was_up) 555 ffec_txstart_locked(sc); 556 557 /* Schedule another check one second from now. */ 558 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 559} 560 561inline static uint32_t 562ffec_setup_txdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr, 563 uint32_t len) 564{ 565 uint32_t nidx; 566 uint32_t flags; 567 568 nidx = next_txidx(sc, idx); 569 570 /* Addr/len 0 means we're clearing the descriptor after xmit done. */ 571 if (paddr == 0 || len == 0) { 572 flags = 0; 573 --sc->txcount; 574 } else { 575 flags = FEC_TXDESC_READY | FEC_TXDESC_L | FEC_TXDESC_TC; 576 ++sc->txcount; 577 } 578 if (nidx == 0) 579 flags |= FEC_TXDESC_WRAP; 580 581 /* 582 * The hardware requires 32-bit physical addresses. We set up the dma 583 * tag to indicate that, so the cast to uint32_t should never lose 584 * significant bits. 585 */ 586 sc->txdesc_ring[idx].buf_paddr = (uint32_t)paddr; 587 sc->txdesc_ring[idx].flags_len = flags | len; /* Must be set last! */ 588 589 return (nidx); 590} 591 592static int 593ffec_setup_txbuf(struct ffec_softc *sc, int idx, struct mbuf **mp) 594{ 595 struct mbuf * m; 596 int error, nsegs; 597 struct bus_dma_segment seg; 598 599 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) 600 return (ENOMEM); 601 *mp = m; 602 603 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, 604 m, &seg, &nsegs, 0); 605 if (error != 0) { 606 return (ENOMEM); 607 } 608 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, 609 BUS_DMASYNC_PREWRITE); 610 611 sc->txbuf_map[idx].mbuf = m; 612 ffec_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len); 613 614 return (0); 615 616} 617 618static void 619ffec_txstart_locked(struct ffec_softc *sc) 620{ 621 struct ifnet *ifp; 622 struct mbuf *m; 623 int enqueued; 624 625 FFEC_ASSERT_LOCKED(sc); 626 627 if (!sc->link_is_up) 628 return; 629 630 ifp = sc->ifp; 631 632 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 633 return; 634 635 enqueued = 0; 636 637 for (;;) { 638 if (sc->txcount == (TX_DESC_COUNT-1)) { 639 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 640 break; 641 } 642 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 643 if (m == NULL) 644 break; 645 if (ffec_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) { 646 IFQ_DRV_PREPEND(&ifp->if_snd, m); 647 break; 648 } 649 BPF_MTAP(ifp, m); 650 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head); 651 ++enqueued; 652 } 653 654 if (enqueued != 0) { 655 WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR); 656 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; 657 } 658} 659 660static void 661ffec_txstart(struct ifnet *ifp) 662{ 663 struct ffec_softc *sc = ifp->if_softc; 664 665 FFEC_LOCK(sc); 666 ffec_txstart_locked(sc); 667 FFEC_UNLOCK(sc); 668} 669 670static void 671ffec_txfinish_locked(struct ffec_softc *sc) 672{ 673 struct ifnet *ifp; 674 struct ffec_hwdesc *desc; 675 struct ffec_bufmap *bmap; 676 boolean_t retired_buffer; 677 678 FFEC_ASSERT_LOCKED(sc); 679 680 ifp = sc->ifp; 681 retired_buffer = false; 682 while (sc->tx_idx_tail != sc->tx_idx_head) { 683 desc = &sc->txdesc_ring[sc->tx_idx_tail]; 684 if (desc->flags_len & FEC_TXDESC_READY) 685 break; 686 retired_buffer = true; 687 bmap = &sc->txbuf_map[sc->tx_idx_tail]; 688 bus_dmamap_sync(sc->txbuf_tag, bmap->map, 689 BUS_DMASYNC_POSTWRITE); 690 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 691 m_freem(bmap->mbuf); 692 bmap->mbuf = NULL; 693 ffec_setup_txdesc(sc, sc->tx_idx_tail, 0, 0); 694 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail); 695 } 696 697 /* 698 * If we retired any buffers, there will be open tx slots available in 699 * the descriptor ring, go try to start some new output. 700 */ 701 if (retired_buffer) { 702 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 703 ffec_txstart_locked(sc); 704 } 705 706 /* If there are no buffers outstanding, muzzle the watchdog. */ 707 if (sc->tx_idx_tail == sc->tx_idx_head) { 708 sc->tx_watchdog_count = 0; 709 } 710} 711 712inline static uint32_t 713ffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr) 714{ 715 uint32_t nidx; 716 717 /* 718 * The hardware requires 32-bit physical addresses. We set up the dma 719 * tag to indicate that, so the cast to uint32_t should never lose 720 * significant bits. 721 */ 722 nidx = next_rxidx(sc, idx); 723 sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr; 724 sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY | 725 ((nidx == 0) ? FEC_RXDESC_WRAP : 0); 726 727 return (nidx); 728} 729 730static int 731ffec_setup_rxbuf(struct ffec_softc *sc, int idx, struct mbuf * m) 732{ 733 int error, nsegs; 734 struct bus_dma_segment seg; 735 736 /* 737 * We need to leave at least ETHER_ALIGN bytes free at the beginning of 738 * the buffer to allow the data to be re-aligned after receiving it (by 739 * copying it backwards ETHER_ALIGN bytes in the same buffer). We also 740 * have to ensure that the beginning of the buffer is aligned to the 741 * hardware's requirements. 742 */ 743 m_adj(m, roundup(ETHER_ALIGN, FEC_RXBUF_ALIGN)); 744 745 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 746 m, &seg, &nsegs, 0); 747 if (error != 0) { 748 return (error); 749 } 750 751 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 752 BUS_DMASYNC_PREREAD); 753 754 sc->rxbuf_map[idx].mbuf = m; 755 ffec_setup_rxdesc(sc, idx, seg.ds_addr); 756 757 return (0); 758} 759 760static struct mbuf * 761ffec_alloc_mbufcl(struct ffec_softc *sc) 762{ 763 struct mbuf *m; 764 765 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 766 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 767 768 return (m); 769} 770 771static void 772ffec_rxfinish_onebuf(struct ffec_softc *sc, int len) 773{ 774 struct mbuf *m, *newmbuf; 775 struct ffec_bufmap *bmap; 776 uint8_t *dst, *src; 777 int error; 778 779 /* 780 * First try to get a new mbuf to plug into this slot in the rx ring. 781 * If that fails, drop the current packet and recycle the current 782 * mbuf, which is still mapped and loaded. 783 */ 784 if ((newmbuf = ffec_alloc_mbufcl(sc)) == NULL) { 785 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1); 786 ffec_setup_rxdesc(sc, sc->rx_idx, 787 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 788 return; 789 } 790 791 /* 792 * Unfortunately, the protocol headers need to be aligned on a 32-bit 793 * boundary for the upper layers. The hardware requires receive 794 * buffers to be 16-byte aligned. The ethernet header is 14 bytes, 795 * leaving the protocol header unaligned. We used m_adj() after 796 * allocating the buffer to leave empty space at the start of the 797 * buffer, now we'll use the alignment agnostic bcopy() routine to 798 * shuffle all the data backwards 2 bytes and adjust m_data. 799 * 800 * XXX imx6 hardware is able to do this 2-byte alignment by setting the 801 * SHIFT16 bit in the RACC register. Older hardware doesn't have that 802 * feature, but for them could we speed this up by copying just the 803 * protocol headers into their own small mbuf then chaining the cluster 804 * to it? That way we'd only need to copy like 64 bytes or whatever 805 * the biggest header is, instead of the whole 1530ish-byte frame. 806 */ 807 808 FFEC_UNLOCK(sc); 809 810 bmap = &sc->rxbuf_map[sc->rx_idx]; 811 len -= ETHER_CRC_LEN; 812 bus_dmamap_sync(sc->rxbuf_tag, bmap->map, BUS_DMASYNC_POSTREAD); 813 bus_dmamap_unload(sc->rxbuf_tag, bmap->map); 814 m = bmap->mbuf; 815 bmap->mbuf = NULL; 816 m->m_len = len; 817 m->m_pkthdr.len = len; 818 m->m_pkthdr.rcvif = sc->ifp; 819 820 src = mtod(m, uint8_t*); 821 dst = src - ETHER_ALIGN; 822 bcopy(src, dst, len); 823 m->m_data = dst; 824 sc->ifp->if_input(sc->ifp, m); 825 826 FFEC_LOCK(sc); 827 828 if ((error = ffec_setup_rxbuf(sc, sc->rx_idx, newmbuf)) != 0) { 829 device_printf(sc->dev, "ffec_setup_rxbuf error %d\n", error); 830 /* XXX Now what? We've got a hole in the rx ring. */ 831 } 832 833} 834 835static void 836ffec_rxfinish_locked(struct ffec_softc *sc) 837{ 838 struct ffec_hwdesc *desc; 839 int len; 840 boolean_t produced_empty_buffer; 841 842 FFEC_ASSERT_LOCKED(sc); 843 844 produced_empty_buffer = false; 845 for (;;) { 846 desc = &sc->rxdesc_ring[sc->rx_idx]; 847 if (desc->flags_len & FEC_RXDESC_EMPTY) 848 break; 849 produced_empty_buffer = true; 850 len = (desc->flags_len & FEC_RXDESC_LEN_MASK); 851 if (len < 64) { 852 /* 853 * Just recycle the descriptor and continue. . 854 */ 855 ffec_setup_rxdesc(sc, sc->rx_idx, 856 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 857 } else if ((desc->flags_len & FEC_RXDESC_L) == 0) { 858 /* 859 * The entire frame is not in this buffer. Impossible. 860 * Recycle the descriptor and continue. 861 * 862 * XXX what's the right way to handle this? Probably we 863 * should stop/init the hardware because this should 864 * just really never happen when we have buffers bigger 865 * than the maximum frame size. 866 */ 867 device_printf(sc->dev, 868 "fec_rxfinish: received frame without LAST bit set"); 869 ffec_setup_rxdesc(sc, sc->rx_idx, 870 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 871 } else if (desc->flags_len & FEC_RXDESC_ERROR_BITS) { 872 /* 873 * Something went wrong with receiving the frame, we 874 * don't care what (the hardware has counted the error 875 * in the stats registers already), we just reuse the 876 * same mbuf, which is still dma-mapped, by resetting 877 * the rx descriptor. 878 */ 879 ffec_setup_rxdesc(sc, sc->rx_idx, 880 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 881 } else { 882 /* 883 * Normal case: a good frame all in one buffer. 884 */ 885 ffec_rxfinish_onebuf(sc, len); 886 } 887 sc->rx_idx = next_rxidx(sc, sc->rx_idx); 888 } 889 890 if (produced_empty_buffer) { 891 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 892 } 893} 894 895static void 896ffec_get_hwaddr(struct ffec_softc *sc, uint8_t *hwaddr) 897{ 898 uint32_t palr, paur, rnd; 899 900 /* 901 * Try to recover a MAC address from the running hardware. If there's 902 * something non-zero there, assume the bootloader did the right thing 903 * and just use it. 904 * 905 * Otherwise, set the address to a convenient locally assigned address, 906 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 907 * assigned bit set, and the broadcast/multicast bit clear. 908 */ 909 palr = RD4(sc, FEC_PALR_REG); 910 paur = RD4(sc, FEC_PAUR_REG) & FEC_PAUR_PADDR2_MASK; 911 if ((palr | paur) != 0) { 912 hwaddr[0] = palr >> 24; 913 hwaddr[1] = palr >> 16; 914 hwaddr[2] = palr >> 8; 915 hwaddr[3] = palr >> 0; 916 hwaddr[4] = paur >> 24; 917 hwaddr[5] = paur >> 16; 918 } else { 919 rnd = arc4random() & 0x00ffffff; 920 hwaddr[0] = 'b'; 921 hwaddr[1] = 's'; 922 hwaddr[2] = 'd'; 923 hwaddr[3] = rnd >> 16; 924 hwaddr[4] = rnd >> 8; 925 hwaddr[5] = rnd >> 0; 926 } 927 928 if (bootverbose) { 929 device_printf(sc->dev, 930 "MAC address %02x:%02x:%02x:%02x:%02x:%02x:\n", 931 hwaddr[0], hwaddr[1], hwaddr[2], 932 hwaddr[3], hwaddr[4], hwaddr[5]); 933 } 934} 935 936static void 937ffec_setup_rxfilter(struct ffec_softc *sc) 938{ 939 struct ifnet *ifp; 940 struct ifmultiaddr *ifma; 941 uint8_t *eaddr; 942 uint32_t crc; 943 uint64_t ghash, ihash; 944 945 FFEC_ASSERT_LOCKED(sc); 946 947 ifp = sc->ifp; 948 949 /* 950 * Set the multicast (group) filter hash. 951 */ 952 if ((ifp->if_flags & IFF_ALLMULTI)) 953 ghash = 0xffffffffffffffffLLU; 954 else { 955 ghash = 0; 956 if_maddr_rlock(ifp); 957 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 958 if (ifma->ifma_addr->sa_family != AF_LINK) 959 continue; 960 /* 6 bits from MSB in LE CRC32 are used for hash. */ 961 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 962 ifma->ifma_addr), ETHER_ADDR_LEN); 963 ghash |= 1LLU << (((uint8_t *)&crc)[3] >> 2); 964 } 965 if_maddr_runlock(ifp); 966 } 967 WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32)); 968 WR4(sc, FEC_GALR_REG, (uint32_t)ghash); 969 970 /* 971 * Set the individual address filter hash. 972 * 973 * XXX Is 0 the right value when promiscuous is off? This hw feature 974 * seems to support the concept of MAC address aliases, does such a 975 * thing even exist? 976 */ 977 if ((ifp->if_flags & IFF_PROMISC)) 978 ihash = 0xffffffffffffffffLLU; 979 else { 980 ihash = 0; 981 } 982 WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32)); 983 WR4(sc, FEC_IALR_REG, (uint32_t)ihash); 984 985 /* 986 * Set the primary address. 987 */ 988 eaddr = IF_LLADDR(ifp); 989 WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) | 990 (eaddr[2] << 8) | eaddr[3]); 991 WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16)); 992} 993 994static void 995ffec_stop_locked(struct ffec_softc *sc) 996{ 997 struct ifnet *ifp; 998 struct ffec_hwdesc *desc; 999 struct ffec_bufmap *bmap; 1000 int idx; 1001 1002 FFEC_ASSERT_LOCKED(sc); 1003 1004 ifp = sc->ifp; 1005 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1006 sc->tx_watchdog_count = 0; 1007 sc->stats_harvest_count = 0; 1008 1009 /* 1010 * Stop the hardware, mask all interrupts, and clear all current 1011 * interrupt status bits. 1012 */ 1013 WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN); 1014 WR4(sc, FEC_IEM_REG, 0x00000000); 1015 WR4(sc, FEC_IER_REG, 0xffffffff); 1016 1017 /* 1018 * Stop the media-check callout. Do not use callout_drain() because 1019 * we're holding a mutex the callout acquires, and if it's currently 1020 * waiting to acquire it, we'd deadlock. If it is waiting now, the 1021 * ffec_tick() routine will return without doing anything when it sees 1022 * that IFF_DRV_RUNNING is not set, so avoiding callout_drain() is safe. 1023 */ 1024 callout_stop(&sc->ffec_callout); 1025 1026 /* 1027 * Discard all untransmitted buffers. Each buffer is simply freed; 1028 * it's as if the bits were transmitted and then lost on the wire. 1029 * 1030 * XXX Is this right? Or should we use IFQ_DRV_PREPEND() to put them 1031 * back on the queue for when we get restarted later? 1032 */ 1033 idx = sc->tx_idx_tail; 1034 while (idx != sc->tx_idx_head) { 1035 desc = &sc->txdesc_ring[idx]; 1036 bmap = &sc->txbuf_map[idx]; 1037 if (desc->buf_paddr != 0) { 1038 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 1039 m_freem(bmap->mbuf); 1040 bmap->mbuf = NULL; 1041 ffec_setup_txdesc(sc, idx, 0, 0); 1042 } 1043 idx = next_txidx(sc, idx); 1044 } 1045 1046 /* 1047 * Discard all unprocessed receive buffers. This amounts to just 1048 * pretending that nothing ever got received into them. We reuse the 1049 * mbuf already mapped for each desc, simply turning the EMPTY flags 1050 * back on so they'll get reused when we start up again. 1051 */ 1052 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1053 desc = &sc->rxdesc_ring[idx]; 1054 ffec_setup_rxdesc(sc, idx, desc->buf_paddr); 1055 } 1056} 1057 1058static void 1059ffec_init_locked(struct ffec_softc *sc) 1060{ 1061 struct ifnet *ifp = sc->ifp; 1062 uint32_t maxbuf, maxfl, regval; 1063 1064 FFEC_ASSERT_LOCKED(sc); 1065 1066 /* 1067 * The hardware has a limit of 0x7ff as the max frame length (see 1068 * comments for MRBR below), and we use mbuf clusters as receive 1069 * buffers, and we currently are designed to receive an entire frame 1070 * into a single buffer. 1071 * 1072 * We start with a MCLBYTES-sized cluster, but we have to offset into 1073 * the buffer by ETHER_ALIGN to make room for post-receive re-alignment, 1074 * and then that value has to be rounded up to the hardware's DMA 1075 * alignment requirements, so all in all our buffer is that much smaller 1076 * than MCLBYTES. 1077 * 1078 * The resulting value is used as the frame truncation length and the 1079 * max buffer receive buffer size for now. It'll become more complex 1080 * when we support jumbo frames and receiving fragments of them into 1081 * separate buffers. 1082 */ 1083 maxbuf = MCLBYTES - roundup(ETHER_ALIGN, FEC_RXBUF_ALIGN); 1084 maxfl = min(maxbuf, 0x7ff); 1085 1086 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1087 return; 1088 1089 /* Mask all interrupts and clear all current interrupt status bits. */ 1090 WR4(sc, FEC_IEM_REG, 0x00000000); 1091 WR4(sc, FEC_IER_REG, 0xffffffff); 1092 1093 /* 1094 * Go set up palr/puar, galr/gaur, ialr/iaur. 1095 */ 1096 ffec_setup_rxfilter(sc); 1097 1098 /* 1099 * TFWR - Transmit FIFO watermark register. 1100 * 1101 * Set the transmit fifo watermark register to "store and forward" mode 1102 * and also set a threshold of 128 bytes in the fifo before transmission 1103 * of a frame begins (to avoid dma underruns). Recent FEC hardware 1104 * supports STRFWD and when that bit is set, the watermark level in the 1105 * low bits is ignored. Older hardware doesn't have STRFWD, but writing 1106 * to that bit is innocuous, and the TWFR bits get used instead. 1107 */ 1108 WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE); 1109 1110 /* RCR - Receive control register. 1111 * 1112 * Set max frame length + clean out anything left from u-boot. 1113 */ 1114 WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT)); 1115 1116 /* 1117 * TCR - Transmit control register. 1118 * 1119 * Clean out anything left from u-boot. Any necessary values are set in 1120 * ffec_miibus_statchg() based on the media type. 1121 */ 1122 WR4(sc, FEC_TCR_REG, 0); 1123 1124 /* 1125 * OPD - Opcode/pause duration. 1126 * 1127 * XXX These magic numbers come from u-boot. 1128 */ 1129 WR4(sc, FEC_OPD_REG, 0x00010020); 1130 1131 /* 1132 * FRSR - Fifo receive start register. 1133 * 1134 * This register does not exist on imx6, it is present on earlier 1135 * hardware. The u-boot code sets this to a non-default value that's 32 1136 * bytes larger than the default, with no clue as to why. The default 1137 * value should work fine, so there's no code to init it here. 1138 */ 1139 1140 /* 1141 * MRBR - Max RX buffer size. 1142 * 1143 * Note: For hardware prior to imx6 this value cannot exceed 0x07ff, 1144 * but the datasheet says no such thing for imx6. On the imx6, setting 1145 * this to 2K without setting EN1588 resulted in a crazy runaway 1146 * receive loop in the hardware, where every rx descriptor in the ring 1147 * had its EMPTY flag cleared, no completion or error flags set, and a 1148 * length of zero. I think maybe you can only exceed it when EN1588 is 1149 * set, like maybe that's what enables jumbo frames, because in general 1150 * the EN1588 flag seems to be the "enable new stuff" vs. "be legacy- 1151 * compatible" flag. 1152 */ 1153 WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT); 1154 1155 /* 1156 * FTRL - Frame truncation length. 1157 * 1158 * Must be greater than or equal to the value set in FEC_RCR_MAXFL. 1159 */ 1160 WR4(sc, FEC_FTRL_REG, maxfl); 1161 1162 /* 1163 * RDSR / TDSR descriptor ring pointers. 1164 * 1165 * When we turn on ECR_ETHEREN at the end, the hardware zeroes its 1166 * internal current descriptor index values for both rings, so we zero 1167 * our index values as well. 1168 */ 1169 sc->rx_idx = 0; 1170 sc->tx_idx_head = sc->tx_idx_tail = 0; 1171 sc->txcount = 0; 1172 WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr); 1173 WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr); 1174 1175 /* 1176 * EIM - interrupt mask register. 1177 * 1178 * We always enable the same set of interrupts while running; unlike 1179 * some drivers there's no need to change the mask on the fly depending 1180 * on what operations are in progress. 1181 */ 1182 WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR); 1183 1184 /* 1185 * MIBC - MIB control (hardware stats). 1186 */ 1187 regval = RD4(sc, FEC_MIBC_REG); 1188 WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS); 1189 ffec_clear_stats(sc); 1190 WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS); 1191 1192 /* 1193 * ECR - Ethernet control register. 1194 * 1195 * This must happen after all the other config registers are set. If 1196 * we're running on little-endian hardware, also set the flag for byte- 1197 * swapping descriptor ring entries. This flag doesn't exist on older 1198 * hardware, but it can be safely set -- the bit position it occupies 1199 * was unused. 1200 */ 1201 regval = RD4(sc, FEC_ECR_REG); 1202#if _BYTE_ORDER == _LITTLE_ENDIAN 1203 regval |= FEC_ECR_DBSWP; 1204#endif 1205 regval |= FEC_ECR_ETHEREN; 1206 WR4(sc, FEC_ECR_REG, regval); 1207 1208 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1209 1210 /* 1211 * Call mii_mediachg() which will call back into ffec_miibus_statchg() to 1212 * set up the remaining config registers based on the current media. 1213 */ 1214 mii_mediachg(sc->mii_softc); 1215 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 1216 1217 /* 1218 * Tell the hardware that receive buffers are available. They were made 1219 * available in ffec_attach() or ffec_stop(). 1220 */ 1221 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 1222} 1223 1224static void 1225ffec_init(void *if_softc) 1226{ 1227 struct ffec_softc *sc = if_softc; 1228 1229 FFEC_LOCK(sc); 1230 ffec_init_locked(sc); 1231 FFEC_UNLOCK(sc); 1232} 1233 1234static void 1235ffec_intr(void *arg) 1236{ 1237 struct ffec_softc *sc; 1238 uint32_t ier; 1239 1240 sc = arg; 1241 1242 FFEC_LOCK(sc); 1243 1244 ier = RD4(sc, FEC_IER_REG); 1245 1246 if (ier & FEC_IER_TXF) { 1247 WR4(sc, FEC_IER_REG, FEC_IER_TXF); 1248 ffec_txfinish_locked(sc); 1249 } 1250 1251 if (ier & FEC_IER_RXF) { 1252 WR4(sc, FEC_IER_REG, FEC_IER_RXF); 1253 ffec_rxfinish_locked(sc); 1254 } 1255 1256 /* 1257 * We actually don't care about most errors, because the hardware copes 1258 * with them just fine, discarding the incoming bad frame, or forcing a 1259 * bad CRC onto an outgoing bad frame, and counting the errors in the 1260 * stats registers. The one that really matters is EBERR (DMA bus 1261 * error) because the hardware automatically clears ECR[ETHEREN] and we 1262 * have to restart it here. It should never happen. 1263 */ 1264 if (ier & FEC_IER_EBERR) { 1265 WR4(sc, FEC_IER_REG, FEC_IER_EBERR); 1266 device_printf(sc->dev, 1267 "Ethernet DMA error, restarting controller.\n"); 1268 ffec_stop_locked(sc); 1269 ffec_init_locked(sc); 1270 } 1271 1272 FFEC_UNLOCK(sc); 1273 1274} 1275 1276static int 1277ffec_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1278{ 1279 struct ffec_softc *sc; 1280 struct mii_data *mii; 1281 struct ifreq *ifr; 1282 int mask, error; 1283 1284 sc = ifp->if_softc; 1285 ifr = (struct ifreq *)data; 1286 1287 error = 0; 1288 switch (cmd) { 1289 case SIOCSIFFLAGS: 1290 FFEC_LOCK(sc); 1291 if (ifp->if_flags & IFF_UP) { 1292 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1293 if ((ifp->if_flags ^ sc->if_flags) & 1294 (IFF_PROMISC | IFF_ALLMULTI)) 1295 ffec_setup_rxfilter(sc); 1296 } else { 1297 if (!sc->is_detaching) 1298 ffec_init_locked(sc); 1299 } 1300 } else { 1301 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1302 ffec_stop_locked(sc); 1303 } 1304 sc->if_flags = ifp->if_flags; 1305 FFEC_UNLOCK(sc); 1306 break; 1307 1308 case SIOCADDMULTI: 1309 case SIOCDELMULTI: 1310 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1311 FFEC_LOCK(sc); 1312 ffec_setup_rxfilter(sc); 1313 FFEC_UNLOCK(sc); 1314 } 1315 break; 1316 1317 case SIOCSIFMEDIA: 1318 case SIOCGIFMEDIA: 1319 mii = sc->mii_softc; 1320 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1321 break; 1322 1323 case SIOCSIFCAP: 1324 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1325 if (mask & IFCAP_VLAN_MTU) { 1326 /* No work to do except acknowledge the change took. */ 1327 ifp->if_capenable ^= IFCAP_VLAN_MTU; 1328 } 1329 break; 1330 1331 default: 1332 error = ether_ioctl(ifp, cmd, data); 1333 break; 1334 } 1335 1336 return (error); 1337} 1338 1339static int 1340ffec_detach(device_t dev) 1341{ 1342 struct ffec_softc *sc; 1343 bus_dmamap_t map; 1344 int idx; 1345 1346 /* 1347 * NB: This function can be called internally to unwind a failure to 1348 * attach. Make sure a resource got allocated/created before destroying. 1349 */ 1350 1351 sc = device_get_softc(dev); 1352 1353 if (sc->is_attached) { 1354 FFEC_LOCK(sc); 1355 sc->is_detaching = true; 1356 ffec_stop_locked(sc); 1357 FFEC_UNLOCK(sc); 1358 callout_drain(&sc->ffec_callout); 1359 ether_ifdetach(sc->ifp); 1360 } 1361 1362 /* XXX no miibus detach? */ 1363 1364 /* Clean up RX DMA resources and free mbufs. */ 1365 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1366 if ((map = sc->rxbuf_map[idx].map) != NULL) { 1367 bus_dmamap_unload(sc->rxbuf_tag, map); 1368 bus_dmamap_destroy(sc->rxbuf_tag, map); 1369 m_freem(sc->rxbuf_map[idx].mbuf); 1370 } 1371 } 1372 if (sc->rxbuf_tag != NULL) 1373 bus_dma_tag_destroy(sc->rxbuf_tag); 1374 if (sc->rxdesc_map != NULL) { 1375 bus_dmamap_unload(sc->rxdesc_tag, sc->rxdesc_map); 1376 bus_dmamap_destroy(sc->rxdesc_tag, sc->rxdesc_map); 1377 } 1378 if (sc->rxdesc_tag != NULL) 1379 bus_dma_tag_destroy(sc->rxdesc_tag); 1380 1381 /* Clean up TX DMA resources. */ 1382 for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1383 if ((map = sc->txbuf_map[idx].map) != NULL) { 1384 /* TX maps are already unloaded. */ 1385 bus_dmamap_destroy(sc->txbuf_tag, map); 1386 } 1387 } 1388 if (sc->txbuf_tag != NULL) 1389 bus_dma_tag_destroy(sc->txbuf_tag); 1390 if (sc->txdesc_map != NULL) { 1391 bus_dmamap_unload(sc->txdesc_tag, sc->txdesc_map); 1392 bus_dmamap_destroy(sc->txdesc_tag, sc->txdesc_map); 1393 } 1394 if (sc->txdesc_tag != NULL) 1395 bus_dma_tag_destroy(sc->txdesc_tag); 1396 1397 /* Release bus resources. */ 1398 if (sc->intr_cookie) 1399 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 1400 1401 if (sc->irq_res != NULL) 1402 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 1403 1404 if (sc->mem_res != NULL) 1405 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 1406 1407 FFEC_LOCK_DESTROY(sc); 1408 return (0); 1409} 1410 1411static int 1412ffec_attach(device_t dev) 1413{ 1414 struct ffec_softc *sc; 1415 struct ifnet *ifp = NULL; 1416 struct mbuf *m; 1417 phandle_t ofw_node; 1418 int error, rid; 1419 uint8_t eaddr[ETHER_ADDR_LEN]; 1420 char phy_conn_name[32]; 1421 uint32_t idx, mscr; 1422 1423 sc = device_get_softc(dev); 1424 sc->dev = dev; 1425 1426 FFEC_LOCK_INIT(sc); 1427 1428 /* 1429 * There are differences in the implementation and features of the FEC 1430 * hardware on different SoCs, so figure out what type we are. 1431 */ 1432 sc->fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1433 1434 /* 1435 * We have to be told what kind of electrical connection exists between 1436 * the MAC and PHY or we can't operate correctly. 1437 */ 1438 if ((ofw_node = ofw_bus_get_node(dev)) == -1) { 1439 device_printf(dev, "Impossible: Can't find ofw bus node\n"); 1440 error = ENXIO; 1441 goto out; 1442 } 1443 if (OF_searchprop(ofw_node, "phy-mode", 1444 phy_conn_name, sizeof(phy_conn_name)) != -1) { 1445 if (strcasecmp(phy_conn_name, "mii") == 0) 1446 sc->phy_conn_type = PHY_CONN_MII; 1447 else if (strcasecmp(phy_conn_name, "rmii") == 0) 1448 sc->phy_conn_type = PHY_CONN_RMII; 1449 else if (strcasecmp(phy_conn_name, "rgmii") == 0) 1450 sc->phy_conn_type = PHY_CONN_RGMII; 1451 } 1452 if (sc->phy_conn_type == PHY_CONN_UNKNOWN) { 1453 device_printf(sc->dev, "No valid 'phy-mode' " 1454 "property found in FDT data for device.\n"); 1455 error = ENOATTR; 1456 goto out; 1457 } 1458 1459 callout_init_mtx(&sc->ffec_callout, &sc->mtx, 0); 1460 1461 /* Allocate bus resources for accessing the hardware. */ 1462 rid = 0; 1463 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1464 RF_ACTIVE); 1465 if (sc->mem_res == NULL) { 1466 device_printf(dev, "could not allocate memory resources.\n"); 1467 error = ENOMEM; 1468 goto out; 1469 } 1470 rid = 0; 1471 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1472 RF_ACTIVE); 1473 if (sc->irq_res == NULL) { 1474 device_printf(dev, "could not allocate interrupt resources.\n"); 1475 error = ENOMEM; 1476 goto out; 1477 } 1478 1479 /* 1480 * Set up TX descriptor ring, descriptors, and dma maps. 1481 */ 1482 error = bus_dma_tag_create( 1483 bus_get_dma_tag(dev), /* Parent tag. */ 1484 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1485 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1486 BUS_SPACE_MAXADDR, /* highaddr */ 1487 NULL, NULL, /* filter, filterarg */ 1488 TX_DESC_SIZE, 1, /* maxsize, nsegments */ 1489 TX_DESC_SIZE, /* maxsegsize */ 1490 0, /* flags */ 1491 NULL, NULL, /* lockfunc, lockarg */ 1492 &sc->txdesc_tag); 1493 if (error != 0) { 1494 device_printf(sc->dev, 1495 "could not create TX ring DMA tag.\n"); 1496 goto out; 1497 } 1498 1499 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, 1500 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->txdesc_map); 1501 if (error != 0) { 1502 device_printf(sc->dev, 1503 "could not allocate TX descriptor ring.\n"); 1504 goto out; 1505 } 1506 1507 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring, 1508 TX_DESC_SIZE, ffec_get1paddr, &sc->txdesc_ring_paddr, 0); 1509 if (error != 0) { 1510 device_printf(sc->dev, 1511 "could not load TX descriptor ring map.\n"); 1512 goto out; 1513 } 1514 1515 error = bus_dma_tag_create( 1516 bus_get_dma_tag(dev), /* Parent tag. */ 1517 FEC_TXBUF_ALIGN, 0, /* alignment, boundary */ 1518 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1519 BUS_SPACE_MAXADDR, /* highaddr */ 1520 NULL, NULL, /* filter, filterarg */ 1521 MCLBYTES, 1, /* maxsize, nsegments */ 1522 MCLBYTES, /* maxsegsize */ 1523 0, /* flags */ 1524 NULL, NULL, /* lockfunc, lockarg */ 1525 &sc->txbuf_tag); 1526 if (error != 0) { 1527 device_printf(sc->dev, 1528 "could not create TX ring DMA tag.\n"); 1529 goto out; 1530 } 1531 1532 for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1533 error = bus_dmamap_create(sc->txbuf_tag, 0, 1534 &sc->txbuf_map[idx].map); 1535 if (error != 0) { 1536 device_printf(sc->dev, 1537 "could not create TX buffer DMA map.\n"); 1538 goto out; 1539 } 1540 ffec_setup_txdesc(sc, idx, 0, 0); 1541 } 1542 1543 /* 1544 * Set up RX descriptor ring, descriptors, dma maps, and mbufs. 1545 */ 1546 error = bus_dma_tag_create( 1547 bus_get_dma_tag(dev), /* Parent tag. */ 1548 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1549 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1550 BUS_SPACE_MAXADDR, /* highaddr */ 1551 NULL, NULL, /* filter, filterarg */ 1552 RX_DESC_SIZE, 1, /* maxsize, nsegments */ 1553 RX_DESC_SIZE, /* maxsegsize */ 1554 0, /* flags */ 1555 NULL, NULL, /* lockfunc, lockarg */ 1556 &sc->rxdesc_tag); 1557 if (error != 0) { 1558 device_printf(sc->dev, 1559 "could not create RX ring DMA tag.\n"); 1560 goto out; 1561 } 1562 1563 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, 1564 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rxdesc_map); 1565 if (error != 0) { 1566 device_printf(sc->dev, 1567 "could not allocate RX descriptor ring.\n"); 1568 goto out; 1569 } 1570 1571 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring, 1572 RX_DESC_SIZE, ffec_get1paddr, &sc->rxdesc_ring_paddr, 0); 1573 if (error != 0) { 1574 device_printf(sc->dev, 1575 "could not load RX descriptor ring map.\n"); 1576 goto out; 1577 } 1578 1579 error = bus_dma_tag_create( 1580 bus_get_dma_tag(dev), /* Parent tag. */ 1581 1, 0, /* alignment, boundary */ 1582 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1583 BUS_SPACE_MAXADDR, /* highaddr */ 1584 NULL, NULL, /* filter, filterarg */ 1585 MCLBYTES, 1, /* maxsize, nsegments */ 1586 MCLBYTES, /* maxsegsize */ 1587 0, /* flags */ 1588 NULL, NULL, /* lockfunc, lockarg */ 1589 &sc->rxbuf_tag); 1590 if (error != 0) { 1591 device_printf(sc->dev, 1592 "could not create RX buf DMA tag.\n"); 1593 goto out; 1594 } 1595 1596 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1597 error = bus_dmamap_create(sc->rxbuf_tag, 0, 1598 &sc->rxbuf_map[idx].map); 1599 if (error != 0) { 1600 device_printf(sc->dev, 1601 "could not create RX buffer DMA map.\n"); 1602 goto out; 1603 } 1604 if ((m = ffec_alloc_mbufcl(sc)) == NULL) { 1605 device_printf(dev, "Could not alloc mbuf\n"); 1606 error = ENOMEM; 1607 goto out; 1608 } 1609 if ((error = ffec_setup_rxbuf(sc, idx, m)) != 0) { 1610 device_printf(sc->dev, 1611 "could not create new RX buffer.\n"); 1612 goto out; 1613 } 1614 } 1615 1616 /* Try to get the MAC address from the hardware before resetting it. */ 1617 ffec_get_hwaddr(sc, eaddr); 1618 1619 /* Reset the hardware. Disables all interrupts. */ 1620 WR4(sc, FEC_ECR_REG, FEC_ECR_RESET); 1621 1622 /* Setup interrupt handler. */ 1623 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 1624 NULL, ffec_intr, sc, &sc->intr_cookie); 1625 if (error != 0) { 1626 device_printf(dev, "could not setup interrupt handler.\n"); 1627 goto out; 1628 } 1629 1630 /* 1631 * Set up the PHY control register. 1632 * 1633 * Speed formula for ENET is md_clock = mac_clock / ((N + 1) * 2). 1634 * Speed formula for FEC is md_clock = mac_clock / (N * 2) 1635 * 1636 * XXX - Revisit this... 1637 * 1638 * For a Wandboard imx6 (ENET) I was originally using 4, but the uboot 1639 * code uses 10. Both values seem to work, but I suspect many modern 1640 * PHY parts can do mdio at speeds far above the standard 2.5 MHz. 1641 * 1642 * Different imx manuals use confusingly different terminology (things 1643 * like "system clock" and "internal module clock") with examples that 1644 * use frequencies that have nothing to do with ethernet, giving the 1645 * vague impression that maybe the clock in question is the periphclock 1646 * or something. In fact, on an imx53 development board (FEC), 1647 * measuring the mdio clock at the pin on the PHY and playing with 1648 * various divisors showed that the root speed was 66 MHz (clk_ipg_root 1649 * aka periphclock) and 13 was the right divisor. 1650 * 1651 * All in all, it seems likely that 13 is a safe divisor for now, 1652 * because if we really do need to base it on the peripheral clock 1653 * speed, then we need a platform-independant get-clock-freq API. 1654 */ 1655 mscr = 13 << FEC_MSCR_MII_SPEED_SHIFT; 1656 if (OF_hasprop(ofw_node, "phy-disable-preamble")) { 1657 mscr |= FEC_MSCR_DIS_PRE; 1658 if (bootverbose) 1659 device_printf(dev, "PHY preamble disabled\n"); 1660 } 1661 WR4(sc, FEC_MSCR_REG, mscr); 1662 1663 /* Set up the ethernet interface. */ 1664 sc->ifp = ifp = if_alloc(IFT_ETHER); 1665 1666 ifp->if_softc = sc; 1667 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1668 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1669 ifp->if_capabilities = IFCAP_VLAN_MTU; 1670 ifp->if_capenable = ifp->if_capabilities; 1671 ifp->if_start = ffec_txstart; 1672 ifp->if_ioctl = ffec_ioctl; 1673 ifp->if_init = ffec_init; 1674 IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1); 1675 ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1; 1676 IFQ_SET_READY(&ifp->if_snd); 1677 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1678 1679#if 0 /* XXX The hardware keeps stats we could use for these. */ 1680 ifp->if_linkmib = &sc->mibdata; 1681 ifp->if_linkmiblen = sizeof(sc->mibdata); 1682#endif 1683 1684 /* Set up the miigasket hardware (if any). */ 1685 ffec_miigasket_setup(sc); 1686 1687 /* Attach the mii driver. */ 1688 error = mii_attach(dev, &sc->miibus, ifp, ffec_media_change, 1689 ffec_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 1690 (sc->fectype & FECTYPE_MVF) ? MIIF_FORCEANEG : 0); 1691 if (error != 0) { 1692 device_printf(dev, "PHY attach failed\n"); 1693 goto out; 1694 } 1695 sc->mii_softc = device_get_softc(sc->miibus); 1696 1697 /* All ready to run, attach the ethernet interface. */ 1698 ether_ifattach(ifp, eaddr); 1699 sc->is_attached = true; 1700 1701 error = 0; 1702out: 1703 1704 if (error != 0) 1705 ffec_detach(dev); 1706 1707 return (error); 1708} 1709 1710static int 1711ffec_probe(device_t dev) 1712{ 1713 uintptr_t fectype; 1714 1715 if (!ofw_bus_status_okay(dev)) 1716 return (ENXIO); 1717 1718 fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1719 if (fectype == FECTYPE_NONE) 1720 return (ENXIO); 1721 1722 device_set_desc(dev, (fectype & FECFLAG_GBE) ? 1723 "Freescale Gigabit Ethernet Controller" : 1724 "Freescale Fast Ethernet Controller"); 1725 1726 return (BUS_PROBE_DEFAULT); 1727} 1728 1729 1730static device_method_t ffec_methods[] = { 1731 /* Device interface. */ 1732 DEVMETHOD(device_probe, ffec_probe), 1733 DEVMETHOD(device_attach, ffec_attach), 1734 DEVMETHOD(device_detach, ffec_detach), 1735 1736/* 1737 DEVMETHOD(device_shutdown, ffec_shutdown), 1738 DEVMETHOD(device_suspend, ffec_suspend), 1739 DEVMETHOD(device_resume, ffec_resume), 1740*/ 1741 1742 /* MII interface. */ 1743 DEVMETHOD(miibus_readreg, ffec_miibus_readreg), 1744 DEVMETHOD(miibus_writereg, ffec_miibus_writereg), 1745 DEVMETHOD(miibus_statchg, ffec_miibus_statchg), 1746 1747 DEVMETHOD_END 1748}; 1749 1750static driver_t ffec_driver = { 1751 "ffec", 1752 ffec_methods, 1753 sizeof(struct ffec_softc) 1754}; 1755 1756static devclass_t ffec_devclass; 1757 1758DRIVER_MODULE(ffec, simplebus, ffec_driver, ffec_devclass, 0, 0); 1759DRIVER_MODULE(miibus, ffec, miibus_driver, miibus_devclass, 0, 0); 1760 1761MODULE_DEPEND(ffec, ether, 1, 1, 1); 1762MODULE_DEPEND(ffec, miibus, 1, 1, 1); 1763