if_ffec.c revision 261410
1256806Sian/*- 2256806Sian * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3256806Sian * All rights reserved. 4256806Sian * 5256806Sian * Redistribution and use in source and binary forms, with or without 6256806Sian * modification, are permitted provided that the following conditions 7256806Sian * are met: 8256806Sian * 1. Redistributions of source code must retain the above copyright 9256806Sian * notice, this list of conditions and the following disclaimer. 10256806Sian * 2. Redistributions in binary form must reproduce the above copyright 11256806Sian * notice, this list of conditions and the following disclaimer in the 12256806Sian * documentation and/or other materials provided with the distribution. 13256806Sian * 14256806Sian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15256806Sian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16256806Sian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17256806Sian * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18256806Sian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19256806Sian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20256806Sian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21256806Sian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22256806Sian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23256806Sian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24256806Sian * SUCH DAMAGE. 25256806Sian * 26256806Sian */ 27256806Sian 28256806Sian#include <sys/cdefs.h> 29256806Sian__FBSDID("$FreeBSD: head/sys/dev/ffec/if_ffec.c 261410 2014-02-02 19:17:28Z ian $"); 30256806Sian 31256806Sian/* 32256806Sian * Driver for Freescale Fast Ethernet Controller, found on imx-series SoCs among 33256806Sian * others. Also works for the ENET Gigibit controller found on imx6 and imx28, 34256806Sian * but the driver doesn't currently use any of the ENET advanced features other 35256806Sian * than enabling gigabit. 36256806Sian * 37256806Sian * The interface name 'fec' is already taken by netgraph's Fast Etherchannel 38256806Sian * (netgraph/ng_fec.c), so we use 'ffec'. 39256806Sian * 40256806Sian * Requires an FDT entry with at least these properties: 41256806Sian * fec: ethernet@02188000 { 42256806Sian * compatible = "fsl,imxNN-fec"; 43256806Sian * reg = <0x02188000 0x4000>; 44256806Sian * interrupts = <150 151>; 45256806Sian * phy-mode = "rgmii"; 46256806Sian * phy-disable-preamble; // optional 47256806Sian * }; 48256806Sian * The second interrupt number is for IEEE-1588, and is not currently used; it 49256806Sian * need not be present. phy-mode must be one of: "mii", "rmii", "rgmii". 50256806Sian * There is also an optional property, phy-disable-preamble, which if present 51256806Sian * will disable the preamble bits, cutting the size of each mdio transaction 52256806Sian * (and thus the busy-wait time) in half. 53256806Sian */ 54256806Sian 55256806Sian#include <sys/param.h> 56256806Sian#include <sys/systm.h> 57256806Sian#include <sys/bus.h> 58256806Sian#include <sys/endian.h> 59256806Sian#include <sys/kernel.h> 60256806Sian#include <sys/lock.h> 61256806Sian#include <sys/malloc.h> 62256806Sian#include <sys/mbuf.h> 63256806Sian#include <sys/module.h> 64256806Sian#include <sys/mutex.h> 65256806Sian#include <sys/rman.h> 66256806Sian#include <sys/socket.h> 67256806Sian#include <sys/sockio.h> 68256806Sian#include <sys/sysctl.h> 69256806Sian 70256806Sian#include <machine/bus.h> 71256806Sian 72256806Sian#include <net/bpf.h> 73256806Sian#include <net/if.h> 74256806Sian#include <net/ethernet.h> 75256806Sian#include <net/if_dl.h> 76256806Sian#include <net/if_media.h> 77256806Sian#include <net/if_types.h> 78256806Sian#include <net/if_var.h> 79256806Sian#include <net/if_vlan_var.h> 80256806Sian 81256806Sian#include <dev/ffec/if_ffecreg.h> 82256806Sian#include <dev/ofw/ofw_bus.h> 83256806Sian#include <dev/ofw/ofw_bus_subr.h> 84256806Sian#include <dev/mii/mii.h> 85256806Sian#include <dev/mii/miivar.h> 86256806Sian#include "miibus_if.h" 87256806Sian 88256806Sian/* 89257167Sian * There are small differences in the hardware on various SoCs. Not every SoC 90257167Sian * we support has its own FECTYPE; most work as GENERIC and only the ones that 91257167Sian * need different handling get their own entry. In addition to the types in 92257167Sian * this list, there are some flags below that can be ORed into the upper bits. 93257167Sian */ 94257167Sianenum { 95257167Sian FECTYPE_NONE, 96257167Sian FECTYPE_GENERIC, 97257167Sian FECTYPE_IMX53, 98257167Sian FECTYPE_IMX6, 99260256Sbr FECTYPE_MVF, 100257167Sian}; 101257167Sian 102257167Sian/* 103257167Sian * Flags that describe general differences between the FEC hardware in various 104257167Sian * SoCs. These are ORed into the FECTYPE enum values. 105257167Sian */ 106257167Sian#define FECTYPE_MASK 0x0000ffff 107257167Sian#define FECFLAG_GBE (0x0001 << 16) 108257167Sian 109257167Sian/* 110257167Sian * Table of supported FDT compat strings and their associated FECTYPE values. 111257167Sian */ 112257167Sianstatic struct ofw_compat_data compat_data[] = { 113257167Sian {"fsl,imx51-fec", FECTYPE_GENERIC}, 114257167Sian {"fsl,imx53-fec", FECTYPE_IMX53}, 115257167Sian {"fsl,imx6q-fec", FECTYPE_IMX6 | FECFLAG_GBE}, 116260256Sbr {"fsl,mvf600-fec", FECTYPE_MVF}, 117260256Sbr {"fsl,mvf-fec", FECTYPE_MVF}, 118257167Sian {NULL, FECTYPE_NONE}, 119257167Sian}; 120257167Sian 121257167Sian/* 122256806Sian * Driver data and defines. 123256806Sian */ 124256806Sian#define RX_DESC_COUNT 64 125256806Sian#define RX_DESC_SIZE (sizeof(struct ffec_hwdesc) * RX_DESC_COUNT) 126256806Sian#define TX_DESC_COUNT 64 127256806Sian#define TX_DESC_SIZE (sizeof(struct ffec_hwdesc) * TX_DESC_COUNT) 128256806Sian 129256806Sian#define WATCHDOG_TIMEOUT_SECS 5 130256806Sian#define STATS_HARVEST_INTERVAL 3 131256806Sian 132256806Sianstruct ffec_bufmap { 133256806Sian struct mbuf *mbuf; 134256806Sian bus_dmamap_t map; 135256806Sian}; 136256806Sian 137256806Sianenum { 138256806Sian PHY_CONN_UNKNOWN, 139256806Sian PHY_CONN_MII, 140256806Sian PHY_CONN_RMII, 141256806Sian PHY_CONN_RGMII 142256806Sian}; 143256806Sian 144256806Sianstruct ffec_softc { 145256806Sian device_t dev; 146256806Sian device_t miibus; 147256806Sian struct mii_data * mii_softc; 148256806Sian struct ifnet *ifp; 149256806Sian int if_flags; 150256806Sian struct mtx mtx; 151256806Sian struct resource *irq_res; 152256806Sian struct resource *mem_res; 153256806Sian void * intr_cookie; 154256806Sian struct callout ffec_callout; 155256806Sian uint8_t phy_conn_type; 156256806Sian uint8_t fectype; 157256806Sian boolean_t link_is_up; 158256806Sian boolean_t is_attached; 159256806Sian boolean_t is_detaching; 160256806Sian int tx_watchdog_count; 161256806Sian int stats_harvest_count; 162256806Sian 163256806Sian bus_dma_tag_t rxdesc_tag; 164256806Sian bus_dmamap_t rxdesc_map; 165256806Sian struct ffec_hwdesc *rxdesc_ring; 166256806Sian bus_addr_t rxdesc_ring_paddr; 167256806Sian bus_dma_tag_t rxbuf_tag; 168256806Sian struct ffec_bufmap rxbuf_map[RX_DESC_COUNT]; 169256806Sian uint32_t rx_idx; 170256806Sian 171256806Sian bus_dma_tag_t txdesc_tag; 172256806Sian bus_dmamap_t txdesc_map; 173256806Sian struct ffec_hwdesc *txdesc_ring; 174256806Sian bus_addr_t txdesc_ring_paddr; 175256806Sian bus_dma_tag_t txbuf_tag; 176256806Sian struct ffec_bufmap txbuf_map[RX_DESC_COUNT]; 177256806Sian uint32_t tx_idx_head; 178256806Sian uint32_t tx_idx_tail; 179256806Sian int txcount; 180256806Sian}; 181256806Sian 182256806Sian#define FFEC_LOCK(sc) mtx_lock(&(sc)->mtx) 183256806Sian#define FFEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 184256806Sian#define FFEC_LOCK_INIT(sc) mtx_init(&(sc)->mtx, \ 185256806Sian device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF) 186256806Sian#define FFEC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx); 187256806Sian#define FFEC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED); 188256806Sian#define FFEC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED); 189256806Sian 190256806Sianstatic void ffec_init_locked(struct ffec_softc *sc); 191256806Sianstatic void ffec_stop_locked(struct ffec_softc *sc); 192256806Sianstatic void ffec_txstart_locked(struct ffec_softc *sc); 193256806Sianstatic void ffec_txfinish_locked(struct ffec_softc *sc); 194256806Sian 195256806Sianstatic inline uint16_t 196256806SianRD2(struct ffec_softc *sc, bus_size_t off) 197256806Sian{ 198256806Sian 199256806Sian return (bus_read_2(sc->mem_res, off)); 200256806Sian} 201256806Sian 202256806Sianstatic inline void 203256806SianWR2(struct ffec_softc *sc, bus_size_t off, uint16_t val) 204256806Sian{ 205256806Sian 206256806Sian bus_write_2(sc->mem_res, off, val); 207256806Sian} 208256806Sian 209256806Sianstatic inline uint32_t 210256806SianRD4(struct ffec_softc *sc, bus_size_t off) 211256806Sian{ 212256806Sian 213256806Sian return (bus_read_4(sc->mem_res, off)); 214256806Sian} 215256806Sian 216256806Sianstatic inline void 217256806SianWR4(struct ffec_softc *sc, bus_size_t off, uint32_t val) 218256806Sian{ 219256806Sian 220256806Sian bus_write_4(sc->mem_res, off, val); 221256806Sian} 222256806Sian 223256806Sianstatic inline uint32_t 224256806Siannext_rxidx(struct ffec_softc *sc, uint32_t curidx) 225256806Sian{ 226256806Sian 227256806Sian return ((curidx == RX_DESC_COUNT - 1) ? 0 : curidx + 1); 228256806Sian} 229256806Sian 230256806Sianstatic inline uint32_t 231256806Siannext_txidx(struct ffec_softc *sc, uint32_t curidx) 232256806Sian{ 233256806Sian 234256806Sian return ((curidx == TX_DESC_COUNT - 1) ? 0 : curidx + 1); 235256806Sian} 236256806Sian 237256806Sianstatic void 238256806Sianffec_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 239256806Sian{ 240256806Sian 241256806Sian if (error != 0) 242256806Sian return; 243256806Sian *(bus_addr_t *)arg = segs[0].ds_addr; 244256806Sian} 245256806Sian 246256806Sianstatic void 247256806Sianffec_miigasket_setup(struct ffec_softc *sc) 248256806Sian{ 249256806Sian uint32_t ifmode; 250256806Sian 251256806Sian /* 252256806Sian * We only need the gasket for MII and RMII connections on certain SoCs. 253256806Sian */ 254256806Sian 255257167Sian switch (sc->fectype & FECTYPE_MASK) 256256806Sian { 257256806Sian case FECTYPE_IMX53: 258256806Sian break; 259256806Sian default: 260256806Sian return; 261256806Sian } 262256806Sian 263256806Sian switch (sc->phy_conn_type) 264256806Sian { 265256806Sian case PHY_CONN_MII: 266256806Sian ifmode = 0; 267256806Sian break; 268256806Sian case PHY_CONN_RMII: 269256806Sian ifmode = FEC_MIIGSK_CFGR_IF_MODE_RMII; 270256806Sian break; 271256806Sian default: 272256806Sian return; 273256806Sian } 274256806Sian 275256806Sian /* 276256806Sian * Disable the gasket, configure for either MII or RMII, then enable. 277256806Sian */ 278256806Sian 279256806Sian WR2(sc, FEC_MIIGSK_ENR, 0); 280256806Sian while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY) 281256806Sian continue; 282256806Sian 283256806Sian WR2(sc, FEC_MIIGSK_CFGR, ifmode); 284256806Sian 285256806Sian WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN); 286256806Sian while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)) 287256806Sian continue; 288256806Sian} 289256806Sian 290256806Sianstatic boolean_t 291256806Sianffec_miibus_iowait(struct ffec_softc *sc) 292256806Sian{ 293256806Sian uint32_t timeout; 294256806Sian 295256806Sian for (timeout = 10000; timeout != 0; --timeout) 296256806Sian if (RD4(sc, FEC_IER_REG) & FEC_IER_MII) 297256806Sian return (true); 298256806Sian 299256806Sian return (false); 300256806Sian} 301256806Sian 302256806Sianstatic int 303256806Sianffec_miibus_readreg(device_t dev, int phy, int reg) 304256806Sian{ 305256806Sian struct ffec_softc *sc; 306256806Sian int val; 307256806Sian 308256806Sian sc = device_get_softc(dev); 309256806Sian 310256806Sian WR4(sc, FEC_IER_REG, FEC_IER_MII); 311256806Sian 312256806Sian WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ | 313256806Sian FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 314256806Sian ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 315256806Sian ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK)); 316256806Sian 317256806Sian if (!ffec_miibus_iowait(sc)) { 318256806Sian device_printf(dev, "timeout waiting for mii read\n"); 319256806Sian return (-1); /* All-ones is a symptom of bad mdio. */ 320256806Sian } 321256806Sian 322256806Sian val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK; 323256806Sian 324256806Sian return (val); 325256806Sian} 326256806Sian 327256806Sianstatic int 328256806Sianffec_miibus_writereg(device_t dev, int phy, int reg, int val) 329256806Sian{ 330256806Sian struct ffec_softc *sc; 331256806Sian 332256806Sian sc = device_get_softc(dev); 333256806Sian 334256806Sian WR4(sc, FEC_IER_REG, FEC_IER_MII); 335256806Sian 336256806Sian WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE | 337256806Sian FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 338256806Sian ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 339256806Sian ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK) | 340256806Sian (val & FEC_MMFR_DATA_MASK)); 341256806Sian 342256806Sian if (!ffec_miibus_iowait(sc)) { 343256806Sian device_printf(dev, "timeout waiting for mii write\n"); 344256806Sian return (-1); 345256806Sian } 346256806Sian 347256806Sian return (0); 348256806Sian} 349256806Sian 350256806Sianstatic void 351256806Sianffec_miibus_statchg(device_t dev) 352256806Sian{ 353256806Sian struct ffec_softc *sc; 354256806Sian struct mii_data *mii; 355256806Sian uint32_t ecr, rcr, tcr; 356256806Sian 357256806Sian /* 358256806Sian * Called by the MII bus driver when the PHY establishes link to set the 359256806Sian * MAC interface registers. 360256806Sian */ 361256806Sian 362256806Sian sc = device_get_softc(dev); 363256806Sian 364256806Sian FFEC_ASSERT_LOCKED(sc); 365256806Sian 366256806Sian mii = sc->mii_softc; 367256806Sian 368256806Sian if (mii->mii_media_status & IFM_ACTIVE) 369256806Sian sc->link_is_up = true; 370256806Sian else 371256806Sian sc->link_is_up = false; 372256806Sian 373256806Sian ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED; 374256806Sian rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE | 375256806Sian FEC_RCR_RGMII_EN | FEC_RCR_DRT | FEC_RCR_FCE); 376256806Sian tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN; 377256806Sian 378256806Sian rcr |= FEC_RCR_MII_MODE; /* Must always be on even for R[G]MII. */ 379256806Sian switch (sc->phy_conn_type) { 380256806Sian case PHY_CONN_MII: 381256806Sian break; 382256806Sian case PHY_CONN_RMII: 383256806Sian rcr |= FEC_RCR_RMII_MODE; 384256806Sian break; 385256806Sian case PHY_CONN_RGMII: 386256806Sian rcr |= FEC_RCR_RGMII_EN; 387256806Sian break; 388256806Sian } 389256806Sian 390256806Sian switch (IFM_SUBTYPE(mii->mii_media_active)) { 391256806Sian case IFM_1000_T: 392256806Sian case IFM_1000_SX: 393256806Sian ecr |= FEC_ECR_SPEED; 394256806Sian break; 395256806Sian case IFM_100_TX: 396256806Sian /* Not-FEC_ECR_SPEED + not-FEC_RCR_RMII_10T means 100TX */ 397256806Sian break; 398256806Sian case IFM_10_T: 399256806Sian rcr |= FEC_RCR_RMII_10T; 400256806Sian break; 401256806Sian case IFM_NONE: 402256806Sian sc->link_is_up = false; 403256806Sian return; 404256806Sian default: 405256806Sian sc->link_is_up = false; 406256806Sian device_printf(dev, "Unsupported media %u\n", 407256806Sian IFM_SUBTYPE(mii->mii_media_active)); 408256806Sian return; 409256806Sian } 410256806Sian 411256806Sian if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 412256806Sian tcr |= FEC_TCR_FDEN; 413256806Sian else 414256806Sian rcr |= FEC_RCR_DRT; 415256806Sian 416256806Sian if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLOW) != 0) 417256806Sian rcr |= FEC_RCR_FCE; 418256806Sian 419256806Sian WR4(sc, FEC_RCR_REG, rcr); 420256806Sian WR4(sc, FEC_TCR_REG, tcr); 421256806Sian WR4(sc, FEC_ECR_REG, ecr); 422256806Sian} 423256806Sian 424256806Sianstatic void 425256806Sianffec_media_status(struct ifnet * ifp, struct ifmediareq *ifmr) 426256806Sian{ 427256806Sian struct ffec_softc *sc; 428256806Sian struct mii_data *mii; 429256806Sian 430256806Sian 431256806Sian sc = ifp->if_softc; 432256806Sian mii = sc->mii_softc; 433256806Sian FFEC_LOCK(sc); 434256806Sian mii_pollstat(mii); 435256806Sian ifmr->ifm_active = mii->mii_media_active; 436256806Sian ifmr->ifm_status = mii->mii_media_status; 437256806Sian FFEC_UNLOCK(sc); 438256806Sian} 439256806Sian 440256806Sianstatic int 441256806Sianffec_media_change_locked(struct ffec_softc *sc) 442256806Sian{ 443256806Sian 444256806Sian return (mii_mediachg(sc->mii_softc)); 445256806Sian} 446256806Sian 447256806Sianstatic int 448256806Sianffec_media_change(struct ifnet * ifp) 449256806Sian{ 450256806Sian struct ffec_softc *sc; 451256806Sian int error; 452256806Sian 453256806Sian sc = ifp->if_softc; 454256806Sian 455256806Sian FFEC_LOCK(sc); 456256806Sian error = ffec_media_change_locked(sc); 457256806Sian FFEC_UNLOCK(sc); 458256806Sian return (error); 459256806Sian} 460256806Sian 461256806Sianstatic void ffec_clear_stats(struct ffec_softc *sc) 462256806Sian{ 463256806Sian 464256806Sian WR4(sc, FEC_RMON_R_PACKETS, 0); 465256806Sian WR4(sc, FEC_RMON_R_MC_PKT, 0); 466256806Sian WR4(sc, FEC_RMON_R_CRC_ALIGN, 0); 467256806Sian WR4(sc, FEC_RMON_R_UNDERSIZE, 0); 468256806Sian WR4(sc, FEC_RMON_R_OVERSIZE, 0); 469256806Sian WR4(sc, FEC_RMON_R_FRAG, 0); 470256806Sian WR4(sc, FEC_RMON_R_JAB, 0); 471256806Sian WR4(sc, FEC_RMON_T_PACKETS, 0); 472256806Sian WR4(sc, FEC_RMON_T_MC_PKT, 0); 473256806Sian WR4(sc, FEC_RMON_T_CRC_ALIGN, 0); 474256806Sian WR4(sc, FEC_RMON_T_UNDERSIZE, 0); 475256806Sian WR4(sc, FEC_RMON_T_OVERSIZE , 0); 476256806Sian WR4(sc, FEC_RMON_T_FRAG, 0); 477256806Sian WR4(sc, FEC_RMON_T_JAB, 0); 478256806Sian WR4(sc, FEC_RMON_T_COL, 0); 479256806Sian} 480256806Sian 481256806Sianstatic void 482256806Sianffec_harvest_stats(struct ffec_softc *sc) 483256806Sian{ 484256806Sian struct ifnet *ifp; 485256806Sian 486256806Sian /* We don't need to harvest too often. */ 487256806Sian if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL) 488256806Sian return; 489256806Sian 490256806Sian /* 491256806Sian * Try to avoid harvesting unless the IDLE flag is on, but if it has 492256806Sian * been too long just go ahead and do it anyway, the worst that'll 493256806Sian * happen is we'll lose a packet count or two as we clear at the end. 494256806Sian */ 495256806Sian if (sc->stats_harvest_count < (2 * STATS_HARVEST_INTERVAL) && 496256806Sian ((RD4(sc, FEC_MIBC_REG) & FEC_MIBC_IDLE) == 0)) 497256806Sian return; 498256806Sian 499256806Sian sc->stats_harvest_count = 0; 500256806Sian ifp = sc->ifp; 501256806Sian 502256806Sian ifp->if_ipackets += RD4(sc, FEC_RMON_R_PACKETS); 503256806Sian ifp->if_imcasts += RD4(sc, FEC_RMON_R_MC_PKT); 504256806Sian ifp->if_ierrors += RD4(sc, FEC_RMON_R_CRC_ALIGN); 505256806Sian ifp->if_ierrors += RD4(sc, FEC_RMON_R_UNDERSIZE); 506256806Sian ifp->if_ierrors += RD4(sc, FEC_RMON_R_OVERSIZE); 507256806Sian ifp->if_ierrors += RD4(sc, FEC_RMON_R_FRAG); 508256806Sian ifp->if_ierrors += RD4(sc, FEC_RMON_R_JAB); 509256806Sian 510256806Sian ifp->if_opackets += RD4(sc, FEC_RMON_T_PACKETS); 511256806Sian ifp->if_omcasts += RD4(sc, FEC_RMON_T_MC_PKT); 512256806Sian ifp->if_oerrors += RD4(sc, FEC_RMON_T_CRC_ALIGN); 513256806Sian ifp->if_oerrors += RD4(sc, FEC_RMON_T_UNDERSIZE); 514256806Sian ifp->if_oerrors += RD4(sc, FEC_RMON_T_OVERSIZE ); 515256806Sian ifp->if_oerrors += RD4(sc, FEC_RMON_T_FRAG); 516256806Sian ifp->if_oerrors += RD4(sc, FEC_RMON_T_JAB); 517256806Sian 518256806Sian ifp->if_collisions += RD4(sc, FEC_RMON_T_COL); 519256806Sian 520256806Sian ffec_clear_stats(sc); 521256806Sian} 522256806Sian 523256806Sianstatic void 524256806Sianffec_tick(void *arg) 525256806Sian{ 526256806Sian struct ffec_softc *sc; 527256806Sian struct ifnet *ifp; 528256806Sian int link_was_up; 529256806Sian 530256806Sian sc = arg; 531256806Sian 532256806Sian FFEC_ASSERT_LOCKED(sc); 533256806Sian 534256806Sian ifp = sc->ifp; 535256806Sian 536256806Sian if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 537256806Sian return; 538256806Sian 539256806Sian /* 540256806Sian * Typical tx watchdog. If this fires it indicates that we enqueued 541256806Sian * packets for output and never got a txdone interrupt for them. Maybe 542256806Sian * it's a missed interrupt somehow, just pretend we got one. 543256806Sian */ 544256806Sian if (sc->tx_watchdog_count > 0) { 545256806Sian if (--sc->tx_watchdog_count == 0) { 546256806Sian ffec_txfinish_locked(sc); 547256806Sian } 548256806Sian } 549256806Sian 550256806Sian /* Gather stats from hardware counters. */ 551256806Sian ffec_harvest_stats(sc); 552256806Sian 553256806Sian /* Check the media status. */ 554256806Sian link_was_up = sc->link_is_up; 555256806Sian mii_tick(sc->mii_softc); 556256806Sian if (sc->link_is_up && !link_was_up) 557256806Sian ffec_txstart_locked(sc); 558256806Sian 559256806Sian /* Schedule another check one second from now. */ 560256806Sian callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 561256806Sian} 562256806Sian 563256806Sianinline static uint32_t 564256806Sianffec_setup_txdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr, 565256806Sian uint32_t len) 566256806Sian{ 567256806Sian uint32_t nidx; 568256806Sian uint32_t flags; 569256806Sian 570256806Sian nidx = next_txidx(sc, idx); 571256806Sian 572256806Sian /* Addr/len 0 means we're clearing the descriptor after xmit done. */ 573256806Sian if (paddr == 0 || len == 0) { 574256806Sian flags = 0; 575256806Sian --sc->txcount; 576256806Sian } else { 577256806Sian flags = FEC_TXDESC_READY | FEC_TXDESC_L | FEC_TXDESC_TC; 578256806Sian ++sc->txcount; 579256806Sian } 580256806Sian if (nidx == 0) 581256806Sian flags |= FEC_TXDESC_WRAP; 582256806Sian 583256806Sian /* 584256806Sian * The hardware requires 32-bit physical addresses. We set up the dma 585256806Sian * tag to indicate that, so the cast to uint32_t should never lose 586256806Sian * significant bits. 587256806Sian */ 588256806Sian sc->txdesc_ring[idx].buf_paddr = (uint32_t)paddr; 589256806Sian sc->txdesc_ring[idx].flags_len = flags | len; /* Must be set last! */ 590256806Sian 591256806Sian return (nidx); 592256806Sian} 593256806Sian 594256806Sianstatic int 595256806Sianffec_setup_txbuf(struct ffec_softc *sc, int idx, struct mbuf **mp) 596256806Sian{ 597256806Sian struct mbuf * m; 598256806Sian int error, nsegs; 599256806Sian struct bus_dma_segment seg; 600256806Sian 601256806Sian if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) 602256806Sian return (ENOMEM); 603256806Sian *mp = m; 604256806Sian 605256806Sian error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, 606256806Sian m, &seg, &nsegs, 0); 607256806Sian if (error != 0) { 608256806Sian return (ENOMEM); 609256806Sian } 610256806Sian bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, 611256806Sian BUS_DMASYNC_PREWRITE); 612256806Sian 613256806Sian sc->txbuf_map[idx].mbuf = m; 614256806Sian ffec_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len); 615256806Sian 616256806Sian return (0); 617256806Sian 618256806Sian} 619256806Sian 620256806Sianstatic void 621256806Sianffec_txstart_locked(struct ffec_softc *sc) 622256806Sian{ 623256806Sian struct ifnet *ifp; 624256806Sian struct mbuf *m; 625256806Sian int enqueued; 626256806Sian 627256806Sian FFEC_ASSERT_LOCKED(sc); 628256806Sian 629256806Sian if (!sc->link_is_up) 630256806Sian return; 631256806Sian 632256806Sian ifp = sc->ifp; 633256806Sian 634256806Sian if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 635256806Sian return; 636256806Sian 637256806Sian enqueued = 0; 638256806Sian 639256806Sian for (;;) { 640256806Sian if (sc->txcount == (TX_DESC_COUNT-1)) { 641256806Sian ifp->if_drv_flags |= IFF_DRV_OACTIVE; 642256806Sian break; 643256806Sian } 644256806Sian IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 645256806Sian if (m == NULL) 646256806Sian break; 647256806Sian if (ffec_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) { 648256806Sian IFQ_DRV_PREPEND(&ifp->if_snd, m); 649256806Sian break; 650256806Sian } 651256806Sian BPF_MTAP(ifp, m); 652256806Sian sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head); 653256806Sian ++enqueued; 654256806Sian } 655256806Sian 656256806Sian if (enqueued != 0) { 657256806Sian WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR); 658256806Sian sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; 659256806Sian } 660256806Sian} 661256806Sian 662256806Sianstatic void 663256806Sianffec_txstart(struct ifnet *ifp) 664256806Sian{ 665256806Sian struct ffec_softc *sc = ifp->if_softc; 666256806Sian 667256806Sian FFEC_LOCK(sc); 668256806Sian ffec_txstart_locked(sc); 669256806Sian FFEC_UNLOCK(sc); 670256806Sian} 671256806Sian 672256806Sianstatic void 673256806Sianffec_txfinish_locked(struct ffec_softc *sc) 674256806Sian{ 675256806Sian struct ifnet *ifp; 676256806Sian struct ffec_hwdesc *desc; 677256806Sian struct ffec_bufmap *bmap; 678256806Sian boolean_t retired_buffer; 679256806Sian 680256806Sian FFEC_ASSERT_LOCKED(sc); 681256806Sian 682256806Sian ifp = sc->ifp; 683256806Sian retired_buffer = false; 684256806Sian while (sc->tx_idx_tail != sc->tx_idx_head) { 685256806Sian desc = &sc->txdesc_ring[sc->tx_idx_tail]; 686256806Sian if (desc->flags_len & FEC_TXDESC_READY) 687256806Sian break; 688256806Sian retired_buffer = true; 689256806Sian bmap = &sc->txbuf_map[sc->tx_idx_tail]; 690256806Sian bus_dmamap_sync(sc->txbuf_tag, bmap->map, 691256806Sian BUS_DMASYNC_POSTWRITE); 692256806Sian bus_dmamap_unload(sc->txbuf_tag, bmap->map); 693256806Sian m_freem(bmap->mbuf); 694256806Sian bmap->mbuf = NULL; 695256806Sian ffec_setup_txdesc(sc, sc->tx_idx_tail, 0, 0); 696256806Sian sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail); 697256806Sian } 698256806Sian 699256806Sian /* 700256806Sian * If we retired any buffers, there will be open tx slots available in 701256806Sian * the descriptor ring, go try to start some new output. 702256806Sian */ 703256806Sian if (retired_buffer) { 704256806Sian ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 705256806Sian ffec_txstart_locked(sc); 706256806Sian } 707256806Sian 708256806Sian /* If there are no buffers outstanding, muzzle the watchdog. */ 709256806Sian if (sc->tx_idx_tail == sc->tx_idx_head) { 710256806Sian sc->tx_watchdog_count = 0; 711256806Sian } 712256806Sian} 713256806Sian 714256806Sianinline static uint32_t 715256806Sianffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr) 716256806Sian{ 717256806Sian uint32_t nidx; 718256806Sian 719256806Sian /* 720256806Sian * The hardware requires 32-bit physical addresses. We set up the dma 721256806Sian * tag to indicate that, so the cast to uint32_t should never lose 722256806Sian * significant bits. 723256806Sian */ 724256806Sian nidx = next_rxidx(sc, idx); 725256806Sian sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr; 726256806Sian sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY | 727256806Sian ((nidx == 0) ? FEC_RXDESC_WRAP : 0); 728256806Sian 729256806Sian return (nidx); 730256806Sian} 731256806Sian 732256806Sianstatic int 733256806Sianffec_setup_rxbuf(struct ffec_softc *sc, int idx, struct mbuf * m) 734256806Sian{ 735256806Sian int error, nsegs; 736256806Sian struct bus_dma_segment seg; 737256806Sian 738256806Sian /* 739256806Sian * We need to leave at least ETHER_ALIGN bytes free at the beginning of 740256806Sian * the buffer to allow the data to be re-aligned after receiving it (by 741256806Sian * copying it backwards ETHER_ALIGN bytes in the same buffer). We also 742256806Sian * have to ensure that the beginning of the buffer is aligned to the 743256806Sian * hardware's requirements. 744256806Sian */ 745256806Sian m_adj(m, roundup(ETHER_ALIGN, FEC_RXBUF_ALIGN)); 746256806Sian 747256806Sian error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 748256806Sian m, &seg, &nsegs, 0); 749256806Sian if (error != 0) { 750256806Sian return (error); 751256806Sian } 752256806Sian 753256806Sian bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 754256806Sian BUS_DMASYNC_PREREAD); 755256806Sian 756256806Sian sc->rxbuf_map[idx].mbuf = m; 757256806Sian ffec_setup_rxdesc(sc, idx, seg.ds_addr); 758256806Sian 759256806Sian return (0); 760256806Sian} 761256806Sian 762256806Sianstatic struct mbuf * 763256806Sianffec_alloc_mbufcl(struct ffec_softc *sc) 764256806Sian{ 765256806Sian struct mbuf *m; 766256806Sian 767256806Sian m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 768256806Sian m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 769256806Sian 770256806Sian return (m); 771256806Sian} 772256806Sian 773256806Sianstatic void 774256806Sianffec_rxfinish_onebuf(struct ffec_softc *sc, int len) 775256806Sian{ 776256806Sian struct mbuf *m, *newmbuf; 777256806Sian struct ffec_bufmap *bmap; 778256806Sian uint8_t *dst, *src; 779256806Sian int error; 780256806Sian 781256806Sian /* 782256806Sian * First try to get a new mbuf to plug into this slot in the rx ring. 783256806Sian * If that fails, drop the current packet and recycle the current 784256806Sian * mbuf, which is still mapped and loaded. 785256806Sian */ 786256806Sian if ((newmbuf = ffec_alloc_mbufcl(sc)) == NULL) { 787256806Sian ++sc->ifp->if_iqdrops; 788256806Sian ffec_setup_rxdesc(sc, sc->rx_idx, 789256806Sian sc->rxdesc_ring[sc->rx_idx].buf_paddr); 790256806Sian return; 791256806Sian } 792256806Sian 793256806Sian /* 794256806Sian * Unfortunately, the protocol headers need to be aligned on a 32-bit 795256806Sian * boundary for the upper layers. The hardware requires receive 796256806Sian * buffers to be 16-byte aligned. The ethernet header is 14 bytes, 797256806Sian * leaving the protocol header unaligned. We used m_adj() after 798256806Sian * allocating the buffer to leave empty space at the start of the 799256806Sian * buffer, now we'll use the alignment agnostic bcopy() routine to 800256806Sian * shuffle all the data backwards 2 bytes and adjust m_data. 801256806Sian * 802256806Sian * XXX imx6 hardware is able to do this 2-byte alignment by setting the 803256806Sian * SHIFT16 bit in the RACC register. Older hardware doesn't have that 804256806Sian * feature, but for them could we speed this up by copying just the 805256806Sian * protocol headers into their own small mbuf then chaining the cluster 806256806Sian * to it? That way we'd only need to copy like 64 bytes or whatever 807256806Sian * the biggest header is, instead of the whole 1530ish-byte frame. 808256806Sian */ 809256806Sian 810256806Sian FFEC_UNLOCK(sc); 811256806Sian 812256806Sian bmap = &sc->rxbuf_map[sc->rx_idx]; 813256806Sian len -= ETHER_CRC_LEN; 814256806Sian bus_dmamap_sync(sc->rxbuf_tag, bmap->map, BUS_DMASYNC_POSTREAD); 815256806Sian bus_dmamap_unload(sc->rxbuf_tag, bmap->map); 816256806Sian m = bmap->mbuf; 817256806Sian bmap->mbuf = NULL; 818256806Sian m->m_len = len; 819256806Sian m->m_pkthdr.len = len; 820256806Sian m->m_pkthdr.rcvif = sc->ifp; 821256806Sian 822256806Sian src = mtod(m, uint8_t*); 823256806Sian dst = src - ETHER_ALIGN; 824256806Sian bcopy(src, dst, len); 825256806Sian m->m_data = dst; 826256806Sian sc->ifp->if_input(sc->ifp, m); 827256806Sian 828256806Sian FFEC_LOCK(sc); 829256806Sian 830256806Sian if ((error = ffec_setup_rxbuf(sc, sc->rx_idx, newmbuf)) != 0) { 831256806Sian device_printf(sc->dev, "ffec_setup_rxbuf error %d\n", error); 832256806Sian /* XXX Now what? We've got a hole in the rx ring. */ 833256806Sian } 834256806Sian 835256806Sian} 836256806Sian 837256806Sianstatic void 838256806Sianffec_rxfinish_locked(struct ffec_softc *sc) 839256806Sian{ 840256806Sian struct ffec_hwdesc *desc; 841256806Sian int len; 842256806Sian boolean_t produced_empty_buffer; 843256806Sian 844256806Sian FFEC_ASSERT_LOCKED(sc); 845256806Sian 846256806Sian produced_empty_buffer = false; 847256806Sian for (;;) { 848256806Sian desc = &sc->rxdesc_ring[sc->rx_idx]; 849256806Sian if (desc->flags_len & FEC_RXDESC_EMPTY) 850256806Sian break; 851256806Sian produced_empty_buffer = true; 852256806Sian len = (desc->flags_len & FEC_RXDESC_LEN_MASK); 853256806Sian if (len < 64) { 854256806Sian /* 855256806Sian * Just recycle the descriptor and continue. . 856256806Sian */ 857256806Sian ffec_setup_rxdesc(sc, sc->rx_idx, 858256806Sian sc->rxdesc_ring[sc->rx_idx].buf_paddr); 859256806Sian } else if ((desc->flags_len & FEC_RXDESC_L) == 0) { 860256806Sian /* 861256806Sian * The entire frame is not in this buffer. Impossible. 862256806Sian * Recycle the descriptor and continue. 863256806Sian * 864256806Sian * XXX what's the right way to handle this? Probably we 865256806Sian * should stop/init the hardware because this should 866256806Sian * just really never happen when we have buffers bigger 867256806Sian * than the maximum frame size. 868256806Sian */ 869256806Sian device_printf(sc->dev, 870256806Sian "fec_rxfinish: received frame without LAST bit set"); 871256806Sian ffec_setup_rxdesc(sc, sc->rx_idx, 872256806Sian sc->rxdesc_ring[sc->rx_idx].buf_paddr); 873256806Sian } else if (desc->flags_len & FEC_RXDESC_ERROR_BITS) { 874256806Sian /* 875256806Sian * Something went wrong with receiving the frame, we 876256806Sian * don't care what (the hardware has counted the error 877256806Sian * in the stats registers already), we just reuse the 878256806Sian * same mbuf, which is still dma-mapped, by resetting 879256806Sian * the rx descriptor. 880256806Sian */ 881256806Sian ffec_setup_rxdesc(sc, sc->rx_idx, 882256806Sian sc->rxdesc_ring[sc->rx_idx].buf_paddr); 883256806Sian } else { 884256806Sian /* 885256806Sian * Normal case: a good frame all in one buffer. 886256806Sian */ 887256806Sian ffec_rxfinish_onebuf(sc, len); 888256806Sian } 889256806Sian sc->rx_idx = next_rxidx(sc, sc->rx_idx); 890256806Sian } 891256806Sian 892256806Sian if (produced_empty_buffer) { 893256806Sian WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 894256806Sian } 895256806Sian} 896256806Sian 897256806Sianstatic void 898256806Sianffec_get_hwaddr(struct ffec_softc *sc, uint8_t *hwaddr) 899256806Sian{ 900256806Sian uint32_t palr, paur, rnd; 901256806Sian 902256806Sian /* 903256806Sian * Try to recover a MAC address from the running hardware. If there's 904256806Sian * something non-zero there, assume the bootloader did the right thing 905256806Sian * and just use it. 906256806Sian * 907256806Sian * Otherwise, set the address to a convenient locally assigned address, 908256806Sian * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 909256806Sian * assigned bit set, and the broadcast/multicast bit clear. 910256806Sian */ 911256806Sian palr = RD4(sc, FEC_PALR_REG); 912256919Sian paur = RD4(sc, FEC_PAUR_REG) & FEC_PAUR_PADDR2_MASK; 913256806Sian if ((palr | paur) != 0) { 914256806Sian hwaddr[0] = palr >> 24; 915256806Sian hwaddr[1] = palr >> 16; 916256806Sian hwaddr[2] = palr >> 8; 917256806Sian hwaddr[3] = palr >> 0; 918256806Sian hwaddr[4] = paur >> 24; 919256806Sian hwaddr[5] = paur >> 16; 920256806Sian } else { 921256806Sian rnd = arc4random() & 0x00ffffff; 922256806Sian hwaddr[0] = 'b'; 923256806Sian hwaddr[1] = 's'; 924256806Sian hwaddr[2] = 'd'; 925256806Sian hwaddr[3] = rnd >> 16; 926256806Sian hwaddr[4] = rnd >> 8; 927256806Sian hwaddr[5] = rnd >> 0; 928256806Sian } 929256806Sian 930256806Sian if (bootverbose) { 931256806Sian device_printf(sc->dev, 932256806Sian "MAC address %02x:%02x:%02x:%02x:%02x:%02x:\n", 933256806Sian hwaddr[0], hwaddr[1], hwaddr[2], 934256806Sian hwaddr[3], hwaddr[4], hwaddr[5]); 935256806Sian } 936256806Sian} 937256806Sian 938256806Sianstatic void 939256806Sianffec_setup_rxfilter(struct ffec_softc *sc) 940256806Sian{ 941256806Sian struct ifnet *ifp; 942256806Sian struct ifmultiaddr *ifma; 943256806Sian uint8_t *eaddr; 944256806Sian uint32_t crc; 945256806Sian uint64_t ghash, ihash; 946256806Sian 947256806Sian FFEC_ASSERT_LOCKED(sc); 948256806Sian 949256806Sian ifp = sc->ifp; 950256806Sian 951256806Sian /* 952256806Sian * Set the multicast (group) filter hash. 953256806Sian */ 954256806Sian if ((ifp->if_flags & IFF_ALLMULTI)) 955256806Sian ghash = 0xffffffffffffffffLLU; 956256806Sian else { 957256806Sian ghash = 0; 958256806Sian if_maddr_rlock(ifp); 959256806Sian TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 960256806Sian if (ifma->ifma_addr->sa_family != AF_LINK) 961256806Sian continue; 962256806Sian crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 963256806Sian ifma->ifma_addr), ETHER_ADDR_LEN); 964256806Sian ghash |= 1 << (crc & 0x3f); 965256806Sian } 966256806Sian if_maddr_runlock(ifp); 967256806Sian } 968256806Sian WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32)); 969256806Sian WR4(sc, FEC_GALR_REG, (uint32_t)ghash); 970256806Sian 971256806Sian /* 972256806Sian * Set the individual address filter hash. 973256806Sian * 974256806Sian * XXX Is 0 the right value when promiscuous is off? This hw feature 975256806Sian * seems to support the concept of MAC address aliases, does such a 976256806Sian * thing even exist? 977256806Sian */ 978256806Sian if ((ifp->if_flags & IFF_PROMISC)) 979256806Sian ihash = 0xffffffffffffffffLLU; 980256806Sian else { 981256806Sian ihash = 0; 982256806Sian } 983256806Sian WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32)); 984256806Sian WR4(sc, FEC_IALR_REG, (uint32_t)ihash); 985256806Sian 986256806Sian /* 987256806Sian * Set the primary address. 988256806Sian */ 989256806Sian eaddr = IF_LLADDR(ifp); 990256806Sian WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) | 991256806Sian (eaddr[2] << 8) | eaddr[3]); 992256806Sian WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16)); 993256806Sian} 994256806Sian 995256806Sianstatic void 996256806Sianffec_stop_locked(struct ffec_softc *sc) 997256806Sian{ 998256806Sian struct ifnet *ifp; 999256806Sian struct ffec_hwdesc *desc; 1000256806Sian struct ffec_bufmap *bmap; 1001256806Sian int idx; 1002256806Sian 1003256806Sian FFEC_ASSERT_LOCKED(sc); 1004256806Sian 1005256806Sian ifp = sc->ifp; 1006256806Sian ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1007256806Sian sc->tx_watchdog_count = 0; 1008256806Sian sc->stats_harvest_count = 0; 1009256806Sian 1010256806Sian /* 1011256806Sian * Stop the hardware, mask all interrupts, and clear all current 1012256806Sian * interrupt status bits. 1013256806Sian */ 1014256806Sian WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN); 1015256806Sian WR4(sc, FEC_IEM_REG, 0x00000000); 1016256806Sian WR4(sc, FEC_IER_REG, 0xffffffff); 1017256806Sian 1018256806Sian /* 1019256806Sian * Stop the media-check callout. Do not use callout_drain() because 1020256806Sian * we're holding a mutex the callout acquires, and if it's currently 1021256806Sian * waiting to acquire it, we'd deadlock. If it is waiting now, the 1022256806Sian * ffec_tick() routine will return without doing anything when it sees 1023256806Sian * that IFF_DRV_RUNNING is not set, so avoiding callout_drain() is safe. 1024256806Sian */ 1025256806Sian callout_stop(&sc->ffec_callout); 1026256806Sian 1027256806Sian /* 1028256806Sian * Discard all untransmitted buffers. Each buffer is simply freed; 1029256806Sian * it's as if the bits were transmitted and then lost on the wire. 1030256806Sian * 1031256806Sian * XXX Is this right? Or should we use IFQ_DRV_PREPEND() to put them 1032256806Sian * back on the queue for when we get restarted later? 1033256806Sian */ 1034256806Sian idx = sc->tx_idx_tail; 1035256806Sian while (idx != sc->tx_idx_head) { 1036256806Sian desc = &sc->txdesc_ring[idx]; 1037256806Sian bmap = &sc->txbuf_map[idx]; 1038256806Sian if (desc->buf_paddr != 0) { 1039256806Sian bus_dmamap_unload(sc->txbuf_tag, bmap->map); 1040256806Sian m_freem(bmap->mbuf); 1041256806Sian bmap->mbuf = NULL; 1042256806Sian ffec_setup_txdesc(sc, idx, 0, 0); 1043256806Sian } 1044256806Sian idx = next_txidx(sc, idx); 1045256806Sian } 1046256806Sian 1047256806Sian /* 1048256806Sian * Discard all unprocessed receive buffers. This amounts to just 1049256806Sian * pretending that nothing ever got received into them. We reuse the 1050256806Sian * mbuf already mapped for each desc, simply turning the EMPTY flags 1051256806Sian * back on so they'll get reused when we start up again. 1052256806Sian */ 1053256806Sian for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1054256806Sian desc = &sc->rxdesc_ring[idx]; 1055256806Sian ffec_setup_rxdesc(sc, idx, desc->buf_paddr); 1056256806Sian } 1057256806Sian} 1058256806Sian 1059256806Sianstatic void 1060256806Sianffec_init_locked(struct ffec_softc *sc) 1061256806Sian{ 1062256806Sian struct ifnet *ifp = sc->ifp; 1063256806Sian uint32_t maxbuf, maxfl, regval; 1064256806Sian 1065256806Sian FFEC_ASSERT_LOCKED(sc); 1066256806Sian 1067256806Sian /* 1068256806Sian * The hardware has a limit of 0x7ff as the max frame length (see 1069256806Sian * comments for MRBR below), and we use mbuf clusters as receive 1070256806Sian * buffers, and we currently are designed to receive an entire frame 1071256806Sian * into a single buffer. 1072256806Sian * 1073256806Sian * We start with a MCLBYTES-sized cluster, but we have to offset into 1074256806Sian * the buffer by ETHER_ALIGN to make room for post-receive re-alignment, 1075256806Sian * and then that value has to be rounded up to the hardware's DMA 1076256806Sian * alignment requirements, so all in all our buffer is that much smaller 1077256806Sian * than MCLBYTES. 1078256806Sian * 1079256806Sian * The resulting value is used as the frame truncation length and the 1080256806Sian * max buffer receive buffer size for now. It'll become more complex 1081256806Sian * when we support jumbo frames and receiving fragments of them into 1082256806Sian * separate buffers. 1083256806Sian */ 1084256806Sian maxbuf = MCLBYTES - roundup(ETHER_ALIGN, FEC_RXBUF_ALIGN); 1085256806Sian maxfl = min(maxbuf, 0x7ff); 1086256806Sian 1087256806Sian if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1088256806Sian return; 1089256806Sian 1090256806Sian /* Mask all interrupts and clear all current interrupt status bits. */ 1091256806Sian WR4(sc, FEC_IEM_REG, 0x00000000); 1092256806Sian WR4(sc, FEC_IER_REG, 0xffffffff); 1093256806Sian 1094256806Sian /* 1095256806Sian * Go set up palr/puar, galr/gaur, ialr/iaur. 1096256806Sian */ 1097256806Sian ffec_setup_rxfilter(sc); 1098256806Sian 1099256806Sian /* 1100256806Sian * TFWR - Transmit FIFO watermark register. 1101256806Sian * 1102256806Sian * Set the transmit fifo watermark register to "store and forward" mode 1103256806Sian * and also set a threshold of 128 bytes in the fifo before transmission 1104256806Sian * of a frame begins (to avoid dma underruns). Recent FEC hardware 1105256806Sian * supports STRFWD and when that bit is set, the watermark level in the 1106256806Sian * low bits is ignored. Older hardware doesn't have STRFWD, but writing 1107256806Sian * to that bit is innocuous, and the TWFR bits get used instead. 1108256806Sian */ 1109256806Sian WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE); 1110256806Sian 1111256806Sian /* RCR - Receive control register. 1112256806Sian * 1113256806Sian * Set max frame length + clean out anything left from u-boot. 1114256806Sian */ 1115256806Sian WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT)); 1116256806Sian 1117256806Sian /* 1118256806Sian * TCR - Transmit control register. 1119256806Sian * 1120256806Sian * Clean out anything left from u-boot. Any necessary values are set in 1121256806Sian * ffec_miibus_statchg() based on the media type. 1122256806Sian */ 1123256806Sian WR4(sc, FEC_TCR_REG, 0); 1124256806Sian 1125256806Sian /* 1126256806Sian * OPD - Opcode/pause duration. 1127256806Sian * 1128256806Sian * XXX These magic numbers come from u-boot. 1129256806Sian */ 1130256806Sian WR4(sc, FEC_OPD_REG, 0x00010020); 1131256806Sian 1132256806Sian /* 1133256806Sian * FRSR - Fifo receive start register. 1134256806Sian * 1135256806Sian * This register does not exist on imx6, it is present on earlier 1136256806Sian * hardware. The u-boot code sets this to a non-default value that's 32 1137256806Sian * bytes larger than the default, with no clue as to why. The default 1138256806Sian * value should work fine, so there's no code to init it here. 1139256806Sian */ 1140256806Sian 1141256806Sian /* 1142256806Sian * MRBR - Max RX buffer size. 1143256806Sian * 1144256806Sian * Note: For hardware prior to imx6 this value cannot exceed 0x07ff, 1145256806Sian * but the datasheet says no such thing for imx6. On the imx6, setting 1146256806Sian * this to 2K without setting EN1588 resulted in a crazy runaway 1147256806Sian * receive loop in the hardware, where every rx descriptor in the ring 1148256806Sian * had its EMPTY flag cleared, no completion or error flags set, and a 1149256806Sian * length of zero. I think maybe you can only exceed it when EN1588 is 1150256806Sian * set, like maybe that's what enables jumbo frames, because in general 1151256806Sian * the EN1588 flag seems to be the "enable new stuff" vs. "be legacy- 1152256806Sian * compatible" flag. 1153256806Sian */ 1154256806Sian WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT); 1155256806Sian 1156256806Sian /* 1157256806Sian * FTRL - Frame truncation length. 1158256806Sian * 1159256806Sian * Must be greater than or equal to the value set in FEC_RCR_MAXFL. 1160256806Sian */ 1161256806Sian WR4(sc, FEC_FTRL_REG, maxfl); 1162256806Sian 1163256806Sian /* 1164256806Sian * RDSR / TDSR descriptor ring pointers. 1165256806Sian * 1166256806Sian * When we turn on ECR_ETHEREN at the end, the hardware zeroes its 1167256806Sian * internal current descriptor index values for both rings, so we zero 1168256806Sian * our index values as well. 1169256806Sian */ 1170256806Sian sc->rx_idx = 0; 1171256806Sian sc->tx_idx_head = sc->tx_idx_tail = 0; 1172256806Sian sc->txcount = 0; 1173256806Sian WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr); 1174256806Sian WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr); 1175256806Sian 1176256806Sian /* 1177256806Sian * EIM - interrupt mask register. 1178256806Sian * 1179256806Sian * We always enable the same set of interrupts while running; unlike 1180256806Sian * some drivers there's no need to change the mask on the fly depending 1181256806Sian * on what operations are in progress. 1182256806Sian */ 1183256806Sian WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR); 1184256806Sian 1185256806Sian /* 1186256806Sian * MIBC - MIB control (hardware stats). 1187256806Sian */ 1188256806Sian regval = RD4(sc, FEC_MIBC_REG); 1189256806Sian WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS); 1190256806Sian ffec_clear_stats(sc); 1191256806Sian WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS); 1192256806Sian 1193256806Sian /* 1194256806Sian * ECR - Ethernet control register. 1195256806Sian * 1196256806Sian * This must happen after all the other config registers are set. If 1197256806Sian * we're running on little-endian hardware, also set the flag for byte- 1198256806Sian * swapping descriptor ring entries. This flag doesn't exist on older 1199256806Sian * hardware, but it can be safely set -- the bit position it occupies 1200256806Sian * was unused. 1201256806Sian */ 1202256806Sian regval = RD4(sc, FEC_ECR_REG); 1203256806Sian#if _BYTE_ORDER == _LITTLE_ENDIAN 1204256806Sian regval |= FEC_ECR_DBSWP; 1205256806Sian#endif 1206256806Sian regval |= FEC_ECR_ETHEREN; 1207256806Sian WR4(sc, FEC_ECR_REG, regval); 1208256806Sian 1209256806Sian ifp->if_drv_flags |= IFF_DRV_RUNNING; 1210256806Sian 1211256806Sian /* 1212256806Sian * Call mii_mediachg() which will call back into ffec_miibus_statchg() to 1213256806Sian * set up the remaining config registers based on the current media. 1214256806Sian */ 1215256806Sian mii_mediachg(sc->mii_softc); 1216256806Sian callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 1217256806Sian 1218256806Sian /* 1219256806Sian * Tell the hardware that receive buffers are available. They were made 1220256806Sian * available in ffec_attach() or ffec_stop(). 1221256806Sian */ 1222256806Sian WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 1223256806Sian} 1224256806Sian 1225256806Sianstatic void 1226256806Sianffec_init(void *if_softc) 1227256806Sian{ 1228256806Sian struct ffec_softc *sc = if_softc; 1229256806Sian 1230256806Sian FFEC_LOCK(sc); 1231256806Sian ffec_init_locked(sc); 1232256806Sian FFEC_UNLOCK(sc); 1233256806Sian} 1234256806Sian 1235256806Sianstatic void 1236256806Sianffec_intr(void *arg) 1237256806Sian{ 1238256806Sian struct ffec_softc *sc; 1239256806Sian uint32_t ier; 1240256806Sian 1241256806Sian sc = arg; 1242256806Sian 1243256806Sian FFEC_LOCK(sc); 1244256806Sian 1245256806Sian ier = RD4(sc, FEC_IER_REG); 1246256806Sian 1247256806Sian if (ier & FEC_IER_TXF) { 1248256806Sian WR4(sc, FEC_IER_REG, FEC_IER_TXF); 1249256806Sian ffec_txfinish_locked(sc); 1250256806Sian } 1251256806Sian 1252256806Sian if (ier & FEC_IER_RXF) { 1253256806Sian WR4(sc, FEC_IER_REG, FEC_IER_RXF); 1254256806Sian ffec_rxfinish_locked(sc); 1255256806Sian } 1256256806Sian 1257256806Sian /* 1258256806Sian * We actually don't care about most errors, because the hardware copes 1259256806Sian * with them just fine, discarding the incoming bad frame, or forcing a 1260256806Sian * bad CRC onto an outgoing bad frame, and counting the errors in the 1261256806Sian * stats registers. The one that really matters is EBERR (DMA bus 1262256806Sian * error) because the hardware automatically clears ECR[ETHEREN] and we 1263256806Sian * have to restart it here. It should never happen. 1264256806Sian */ 1265256806Sian if (ier & FEC_IER_EBERR) { 1266256806Sian WR4(sc, FEC_IER_REG, FEC_IER_EBERR); 1267256806Sian device_printf(sc->dev, 1268256806Sian "Ethernet DMA error, restarting controller.\n"); 1269256806Sian ffec_stop_locked(sc); 1270256806Sian ffec_init_locked(sc); 1271256806Sian } 1272256806Sian 1273256806Sian FFEC_UNLOCK(sc); 1274256806Sian 1275256806Sian} 1276256806Sian 1277256806Sianstatic int 1278256806Sianffec_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1279256806Sian{ 1280256806Sian struct ffec_softc *sc; 1281256806Sian struct mii_data *mii; 1282256806Sian struct ifreq *ifr; 1283256806Sian int mask, error; 1284256806Sian 1285256806Sian sc = ifp->if_softc; 1286256806Sian ifr = (struct ifreq *)data; 1287256806Sian 1288256806Sian error = 0; 1289256806Sian switch (cmd) { 1290256806Sian case SIOCSIFFLAGS: 1291256806Sian FFEC_LOCK(sc); 1292256806Sian if (ifp->if_flags & IFF_UP) { 1293256806Sian if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1294256806Sian if ((ifp->if_flags ^ sc->if_flags) & 1295256806Sian (IFF_PROMISC | IFF_ALLMULTI)) 1296256806Sian ffec_setup_rxfilter(sc); 1297256806Sian } else { 1298256806Sian if (!sc->is_detaching) 1299256806Sian ffec_init_locked(sc); 1300256806Sian } 1301256806Sian } else { 1302256806Sian if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1303256806Sian ffec_stop_locked(sc); 1304256806Sian } 1305256806Sian sc->if_flags = ifp->if_flags; 1306256806Sian FFEC_UNLOCK(sc); 1307256806Sian break; 1308256806Sian 1309256806Sian case SIOCADDMULTI: 1310256806Sian case SIOCDELMULTI: 1311256806Sian if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1312256806Sian FFEC_LOCK(sc); 1313256806Sian ffec_setup_rxfilter(sc); 1314256806Sian FFEC_UNLOCK(sc); 1315256806Sian } 1316256806Sian break; 1317256806Sian 1318256806Sian case SIOCSIFMEDIA: 1319256806Sian case SIOCGIFMEDIA: 1320256806Sian mii = sc->mii_softc; 1321256806Sian error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1322256806Sian break; 1323256806Sian 1324256806Sian case SIOCSIFCAP: 1325256806Sian mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1326256806Sian if (mask & IFCAP_VLAN_MTU) { 1327256806Sian /* No work to do except acknowledge the change took. */ 1328256806Sian ifp->if_capenable ^= IFCAP_VLAN_MTU; 1329256806Sian } 1330256806Sian break; 1331256806Sian 1332256806Sian default: 1333256806Sian error = ether_ioctl(ifp, cmd, data); 1334256806Sian break; 1335256806Sian } 1336256806Sian 1337256806Sian return (error); 1338256806Sian} 1339256806Sian 1340256806Sianstatic int 1341256806Sianffec_detach(device_t dev) 1342256806Sian{ 1343256806Sian struct ffec_softc *sc; 1344256806Sian bus_dmamap_t map; 1345256806Sian int idx; 1346256806Sian 1347256806Sian /* 1348256806Sian * NB: This function can be called internally to unwind a failure to 1349256806Sian * attach. Make sure a resource got allocated/created before destroying. 1350256806Sian */ 1351256806Sian 1352256806Sian sc = device_get_softc(dev); 1353256806Sian 1354256806Sian if (sc->is_attached) { 1355256806Sian FFEC_LOCK(sc); 1356256806Sian sc->is_detaching = true; 1357256806Sian ffec_stop_locked(sc); 1358256806Sian FFEC_UNLOCK(sc); 1359256806Sian callout_drain(&sc->ffec_callout); 1360256806Sian ether_ifdetach(sc->ifp); 1361256806Sian } 1362256806Sian 1363256806Sian /* XXX no miibus detach? */ 1364256806Sian 1365256806Sian /* Clean up RX DMA resources and free mbufs. */ 1366256806Sian for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1367256806Sian if ((map = sc->rxbuf_map[idx].map) != NULL) { 1368256806Sian bus_dmamap_unload(sc->rxbuf_tag, map); 1369256806Sian bus_dmamap_destroy(sc->rxbuf_tag, map); 1370256806Sian m_freem(sc->rxbuf_map[idx].mbuf); 1371256806Sian } 1372256806Sian } 1373256806Sian if (sc->rxbuf_tag != NULL) 1374256806Sian bus_dma_tag_destroy(sc->rxbuf_tag); 1375256806Sian if (sc->rxdesc_map != NULL) { 1376256806Sian bus_dmamap_unload(sc->rxdesc_tag, sc->rxdesc_map); 1377256806Sian bus_dmamap_destroy(sc->rxdesc_tag, sc->rxdesc_map); 1378256806Sian } 1379256806Sian if (sc->rxdesc_tag != NULL) 1380256806Sian bus_dma_tag_destroy(sc->rxdesc_tag); 1381256806Sian 1382256806Sian /* Clean up TX DMA resources. */ 1383256806Sian for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1384256806Sian if ((map = sc->txbuf_map[idx].map) != NULL) { 1385256806Sian /* TX maps are already unloaded. */ 1386256806Sian bus_dmamap_destroy(sc->txbuf_tag, map); 1387256806Sian } 1388256806Sian } 1389256806Sian if (sc->txbuf_tag != NULL) 1390256806Sian bus_dma_tag_destroy(sc->txbuf_tag); 1391256806Sian if (sc->txdesc_map != NULL) { 1392256806Sian bus_dmamap_unload(sc->txdesc_tag, sc->txdesc_map); 1393256806Sian bus_dmamap_destroy(sc->txdesc_tag, sc->txdesc_map); 1394256806Sian } 1395256806Sian if (sc->txdesc_tag != NULL) 1396256806Sian bus_dma_tag_destroy(sc->txdesc_tag); 1397256806Sian 1398256806Sian /* Release bus resources. */ 1399256806Sian if (sc->intr_cookie) 1400256806Sian bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 1401256806Sian 1402256806Sian if (sc->irq_res != NULL) 1403256806Sian bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 1404256806Sian 1405256806Sian if (sc->mem_res != NULL) 1406256806Sian bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 1407256806Sian 1408256806Sian FFEC_LOCK_DESTROY(sc); 1409256806Sian return (0); 1410256806Sian} 1411256806Sian 1412256806Sianstatic int 1413256806Sianffec_attach(device_t dev) 1414256806Sian{ 1415256806Sian struct ffec_softc *sc; 1416256806Sian struct ifnet *ifp = NULL; 1417256806Sian struct mbuf *m; 1418256806Sian phandle_t ofw_node; 1419256806Sian int error, rid; 1420256806Sian uint8_t eaddr[ETHER_ADDR_LEN]; 1421256806Sian char phy_conn_name[32]; 1422256806Sian uint32_t idx, mscr; 1423256806Sian 1424256806Sian sc = device_get_softc(dev); 1425256806Sian sc->dev = dev; 1426256806Sian 1427256806Sian FFEC_LOCK_INIT(sc); 1428256806Sian 1429256806Sian /* 1430256806Sian * There are differences in the implementation and features of the FEC 1431256806Sian * hardware on different SoCs, so figure out what type we are. 1432256806Sian */ 1433257167Sian sc->fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1434256806Sian 1435256806Sian /* 1436256806Sian * We have to be told what kind of electrical connection exists between 1437256806Sian * the MAC and PHY or we can't operate correctly. 1438256806Sian */ 1439256806Sian if ((ofw_node = ofw_bus_get_node(dev)) == -1) { 1440256806Sian device_printf(dev, "Impossible: Can't find ofw bus node\n"); 1441256806Sian error = ENXIO; 1442256806Sian goto out; 1443256806Sian } 1444256806Sian if (OF_searchprop(ofw_node, "phy-mode", 1445256806Sian phy_conn_name, sizeof(phy_conn_name)) != -1) { 1446256806Sian if (strcasecmp(phy_conn_name, "mii") == 0) 1447256806Sian sc->phy_conn_type = PHY_CONN_MII; 1448256806Sian else if (strcasecmp(phy_conn_name, "rmii") == 0) 1449256806Sian sc->phy_conn_type = PHY_CONN_RMII; 1450256806Sian else if (strcasecmp(phy_conn_name, "rgmii") == 0) 1451256806Sian sc->phy_conn_type = PHY_CONN_RGMII; 1452256806Sian } 1453256806Sian if (sc->phy_conn_type == PHY_CONN_UNKNOWN) { 1454256806Sian device_printf(sc->dev, "No valid 'phy-mode' " 1455256806Sian "property found in FDT data for device.\n"); 1456256806Sian error = ENOATTR; 1457256806Sian goto out; 1458256806Sian } 1459256806Sian 1460256806Sian callout_init_mtx(&sc->ffec_callout, &sc->mtx, 0); 1461256806Sian 1462256806Sian /* Allocate bus resources for accessing the hardware. */ 1463256806Sian rid = 0; 1464256806Sian sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1465256806Sian RF_ACTIVE); 1466256806Sian if (sc->mem_res == NULL) { 1467256806Sian device_printf(dev, "could not allocate memory resources.\n"); 1468256806Sian error = ENOMEM; 1469256806Sian goto out; 1470256806Sian } 1471256806Sian rid = 0; 1472256806Sian sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1473256806Sian RF_ACTIVE); 1474256806Sian if (sc->irq_res == NULL) { 1475256806Sian device_printf(dev, "could not allocate interrupt resources.\n"); 1476256806Sian error = ENOMEM; 1477256806Sian goto out; 1478256806Sian } 1479256806Sian 1480256806Sian /* 1481256806Sian * Set up TX descriptor ring, descriptors, and dma maps. 1482256806Sian */ 1483256806Sian error = bus_dma_tag_create( 1484256806Sian bus_get_dma_tag(dev), /* Parent tag. */ 1485256806Sian FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1486256806Sian BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1487256806Sian BUS_SPACE_MAXADDR, /* highaddr */ 1488256806Sian NULL, NULL, /* filter, filterarg */ 1489256806Sian TX_DESC_SIZE, 1, /* maxsize, nsegments */ 1490256806Sian TX_DESC_SIZE, /* maxsegsize */ 1491256806Sian 0, /* flags */ 1492256806Sian NULL, NULL, /* lockfunc, lockarg */ 1493256806Sian &sc->txdesc_tag); 1494256806Sian if (error != 0) { 1495256806Sian device_printf(sc->dev, 1496256806Sian "could not create TX ring DMA tag.\n"); 1497256806Sian goto out; 1498256806Sian } 1499256806Sian 1500256806Sian error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, 1501256806Sian BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->txdesc_map); 1502256806Sian if (error != 0) { 1503256806Sian device_printf(sc->dev, 1504256806Sian "could not allocate TX descriptor ring.\n"); 1505256806Sian goto out; 1506256806Sian } 1507256806Sian 1508256806Sian error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring, 1509256806Sian TX_DESC_SIZE, ffec_get1paddr, &sc->txdesc_ring_paddr, 0); 1510256806Sian if (error != 0) { 1511256806Sian device_printf(sc->dev, 1512256806Sian "could not load TX descriptor ring map.\n"); 1513256806Sian goto out; 1514256806Sian } 1515256806Sian 1516256806Sian error = bus_dma_tag_create( 1517256806Sian bus_get_dma_tag(dev), /* Parent tag. */ 1518256806Sian FEC_TXBUF_ALIGN, 0, /* alignment, boundary */ 1519256806Sian BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1520256806Sian BUS_SPACE_MAXADDR, /* highaddr */ 1521256806Sian NULL, NULL, /* filter, filterarg */ 1522256806Sian MCLBYTES, 1, /* maxsize, nsegments */ 1523256806Sian MCLBYTES, /* maxsegsize */ 1524256806Sian 0, /* flags */ 1525256806Sian NULL, NULL, /* lockfunc, lockarg */ 1526256806Sian &sc->txbuf_tag); 1527256806Sian if (error != 0) { 1528256806Sian device_printf(sc->dev, 1529256806Sian "could not create TX ring DMA tag.\n"); 1530256806Sian goto out; 1531256806Sian } 1532256806Sian 1533256806Sian for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1534256806Sian error = bus_dmamap_create(sc->txbuf_tag, 0, 1535256806Sian &sc->txbuf_map[idx].map); 1536256806Sian if (error != 0) { 1537256806Sian device_printf(sc->dev, 1538256806Sian "could not create TX buffer DMA map.\n"); 1539256806Sian goto out; 1540256806Sian } 1541256806Sian ffec_setup_txdesc(sc, idx, 0, 0); 1542256806Sian } 1543256806Sian 1544256806Sian /* 1545256806Sian * Set up RX descriptor ring, descriptors, dma maps, and mbufs. 1546256806Sian */ 1547256806Sian error = bus_dma_tag_create( 1548256806Sian bus_get_dma_tag(dev), /* Parent tag. */ 1549256806Sian FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1550256806Sian BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1551256806Sian BUS_SPACE_MAXADDR, /* highaddr */ 1552256806Sian NULL, NULL, /* filter, filterarg */ 1553256806Sian RX_DESC_SIZE, 1, /* maxsize, nsegments */ 1554256806Sian RX_DESC_SIZE, /* maxsegsize */ 1555256806Sian 0, /* flags */ 1556256806Sian NULL, NULL, /* lockfunc, lockarg */ 1557256806Sian &sc->rxdesc_tag); 1558256806Sian if (error != 0) { 1559256806Sian device_printf(sc->dev, 1560256806Sian "could not create RX ring DMA tag.\n"); 1561256806Sian goto out; 1562256806Sian } 1563256806Sian 1564256806Sian error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, 1565256806Sian BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rxdesc_map); 1566256806Sian if (error != 0) { 1567256806Sian device_printf(sc->dev, 1568256806Sian "could not allocate RX descriptor ring.\n"); 1569256806Sian goto out; 1570256806Sian } 1571256806Sian 1572256806Sian error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring, 1573256806Sian RX_DESC_SIZE, ffec_get1paddr, &sc->rxdesc_ring_paddr, 0); 1574256806Sian if (error != 0) { 1575256806Sian device_printf(sc->dev, 1576256806Sian "could not load RX descriptor ring map.\n"); 1577256806Sian goto out; 1578256806Sian } 1579256806Sian 1580256806Sian error = bus_dma_tag_create( 1581256806Sian bus_get_dma_tag(dev), /* Parent tag. */ 1582256806Sian 1, 0, /* alignment, boundary */ 1583256806Sian BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1584256806Sian BUS_SPACE_MAXADDR, /* highaddr */ 1585256806Sian NULL, NULL, /* filter, filterarg */ 1586256806Sian MCLBYTES, 1, /* maxsize, nsegments */ 1587256806Sian MCLBYTES, /* maxsegsize */ 1588256806Sian 0, /* flags */ 1589256806Sian NULL, NULL, /* lockfunc, lockarg */ 1590256806Sian &sc->rxbuf_tag); 1591256806Sian if (error != 0) { 1592256806Sian device_printf(sc->dev, 1593256806Sian "could not create RX buf DMA tag.\n"); 1594256806Sian goto out; 1595256806Sian } 1596256806Sian 1597256806Sian for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1598256806Sian error = bus_dmamap_create(sc->rxbuf_tag, 0, 1599256806Sian &sc->rxbuf_map[idx].map); 1600256806Sian if (error != 0) { 1601256806Sian device_printf(sc->dev, 1602256806Sian "could not create RX buffer DMA map.\n"); 1603256806Sian goto out; 1604256806Sian } 1605256806Sian if ((m = ffec_alloc_mbufcl(sc)) == NULL) { 1606256806Sian device_printf(dev, "Could not alloc mbuf\n"); 1607256806Sian error = ENOMEM; 1608256806Sian goto out; 1609256806Sian } 1610256806Sian if ((error = ffec_setup_rxbuf(sc, idx, m)) != 0) { 1611256806Sian device_printf(sc->dev, 1612256806Sian "could not create new RX buffer.\n"); 1613256806Sian goto out; 1614256806Sian } 1615256806Sian } 1616256806Sian 1617256806Sian /* Try to get the MAC address from the hardware before resetting it. */ 1618256806Sian ffec_get_hwaddr(sc, eaddr); 1619256806Sian 1620256806Sian /* Reset the hardware. Disables all interrupts. */ 1621256806Sian WR4(sc, FEC_ECR_REG, FEC_ECR_RESET); 1622256806Sian 1623256806Sian /* Setup interrupt handler. */ 1624256806Sian error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 1625256806Sian NULL, ffec_intr, sc, &sc->intr_cookie); 1626256806Sian if (error != 0) { 1627256806Sian device_printf(dev, "could not setup interrupt handler.\n"); 1628256806Sian goto out; 1629256806Sian } 1630256806Sian 1631256806Sian /* 1632256806Sian * Set up the PHY control register. 1633256806Sian * 1634256806Sian * Speed formula for ENET is md_clock = mac_clock / ((N + 1) * 2). 1635256806Sian * Speed formula for FEC is md_clock = mac_clock / (N * 2) 1636256806Sian * 1637256806Sian * XXX - Revisit this... 1638256806Sian * 1639256806Sian * For a Wandboard imx6 (ENET) I was originally using 4, but the uboot 1640256806Sian * code uses 10. Both values seem to work, but I suspect many modern 1641256806Sian * PHY parts can do mdio at speeds far above the standard 2.5 MHz. 1642256806Sian * 1643256806Sian * Different imx manuals use confusingly different terminology (things 1644256806Sian * like "system clock" and "internal module clock") with examples that 1645256806Sian * use frequencies that have nothing to do with ethernet, giving the 1646256806Sian * vague impression that maybe the clock in question is the periphclock 1647256806Sian * or something. In fact, on an imx53 development board (FEC), 1648256806Sian * measuring the mdio clock at the pin on the PHY and playing with 1649256806Sian * various divisors showed that the root speed was 66 MHz (clk_ipg_root 1650256806Sian * aka periphclock) and 13 was the right divisor. 1651256806Sian * 1652256806Sian * All in all, it seems likely that 13 is a safe divisor for now, 1653256806Sian * because if we really do need to base it on the peripheral clock 1654256806Sian * speed, then we need a platform-independant get-clock-freq API. 1655256806Sian */ 1656256806Sian mscr = 13 << FEC_MSCR_MII_SPEED_SHIFT; 1657256806Sian if (OF_hasprop(ofw_node, "phy-disable-preamble")) { 1658256806Sian mscr |= FEC_MSCR_DIS_PRE; 1659256806Sian if (bootverbose) 1660256806Sian device_printf(dev, "PHY preamble disabled\n"); 1661256806Sian } 1662256806Sian WR4(sc, FEC_MSCR_REG, mscr); 1663256806Sian 1664256806Sian /* Set up the ethernet interface. */ 1665256806Sian sc->ifp = ifp = if_alloc(IFT_ETHER); 1666256806Sian 1667256806Sian ifp->if_softc = sc; 1668256806Sian if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1669256806Sian ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1670256806Sian ifp->if_capabilities = IFCAP_VLAN_MTU; 1671256806Sian ifp->if_capenable = ifp->if_capabilities; 1672256806Sian ifp->if_start = ffec_txstart; 1673256806Sian ifp->if_ioctl = ffec_ioctl; 1674256806Sian ifp->if_init = ffec_init; 1675256806Sian IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1); 1676256806Sian ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1; 1677256806Sian IFQ_SET_READY(&ifp->if_snd); 1678256806Sian ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1679256806Sian 1680256806Sian#if 0 /* XXX The hardware keeps stats we could use for these. */ 1681256806Sian ifp->if_linkmib = &sc->mibdata; 1682256806Sian ifp->if_linkmiblen = sizeof(sc->mibdata); 1683256806Sian#endif 1684256806Sian 1685256806Sian /* Set up the miigasket hardware (if any). */ 1686256806Sian ffec_miigasket_setup(sc); 1687256806Sian 1688256806Sian /* Attach the mii driver. */ 1689256806Sian error = mii_attach(dev, &sc->miibus, ifp, ffec_media_change, 1690260256Sbr ffec_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 1691260256Sbr (sc->fectype & FECTYPE_MVF) ? MIIF_FORCEANEG : 0); 1692256806Sian if (error != 0) { 1693256806Sian device_printf(dev, "PHY attach failed\n"); 1694256806Sian goto out; 1695256806Sian } 1696256806Sian sc->mii_softc = device_get_softc(sc->miibus); 1697256806Sian 1698256806Sian /* All ready to run, attach the ethernet interface. */ 1699256806Sian ether_ifattach(ifp, eaddr); 1700256806Sian sc->is_attached = true; 1701256806Sian 1702256806Sian error = 0; 1703256806Sianout: 1704256806Sian 1705256806Sian if (error != 0) 1706256806Sian ffec_detach(dev); 1707256806Sian 1708256806Sian return (error); 1709256806Sian} 1710256806Sian 1711256806Sianstatic int 1712256806Sianffec_probe(device_t dev) 1713256806Sian{ 1714257167Sian uintptr_t fectype; 1715256806Sian 1716261410Sian if (!ofw_bus_status_okay(dev)) 1717261410Sian return (ENXIO); 1718261410Sian 1719257167Sian fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1720257167Sian if (fectype == FECTYPE_NONE) 1721256806Sian return (ENXIO); 1722257167Sian 1723257167Sian device_set_desc(dev, (fectype & FECFLAG_GBE) ? 1724257167Sian "Freescale Gigabit Ethernet Controller" : 1725257167Sian "Freescale Fast Ethernet Controller"); 1726257167Sian 1727256806Sian return (BUS_PROBE_DEFAULT); 1728256806Sian} 1729256806Sian 1730256806Sian 1731256806Sianstatic device_method_t ffec_methods[] = { 1732256806Sian /* Device interface. */ 1733256806Sian DEVMETHOD(device_probe, ffec_probe), 1734256806Sian DEVMETHOD(device_attach, ffec_attach), 1735256806Sian DEVMETHOD(device_detach, ffec_detach), 1736256806Sian 1737256806Sian/* 1738256806Sian DEVMETHOD(device_shutdown, ffec_shutdown), 1739256806Sian DEVMETHOD(device_suspend, ffec_suspend), 1740256806Sian DEVMETHOD(device_resume, ffec_resume), 1741256806Sian*/ 1742256806Sian 1743256806Sian /* MII interface. */ 1744256806Sian DEVMETHOD(miibus_readreg, ffec_miibus_readreg), 1745256806Sian DEVMETHOD(miibus_writereg, ffec_miibus_writereg), 1746256806Sian DEVMETHOD(miibus_statchg, ffec_miibus_statchg), 1747256806Sian 1748256806Sian DEVMETHOD_END 1749256806Sian}; 1750256806Sian 1751256806Sianstatic driver_t ffec_driver = { 1752256806Sian "ffec", 1753256806Sian ffec_methods, 1754256806Sian sizeof(struct ffec_softc) 1755256806Sian}; 1756256806Sian 1757256806Sianstatic devclass_t ffec_devclass; 1758256806Sian 1759256806SianDRIVER_MODULE(ffec, simplebus, ffec_driver, ffec_devclass, 0, 0); 1760256806SianDRIVER_MODULE(miibus, ffec, miibus_driver, miibus_devclass, 0, 0); 1761256806Sian 1762256806SianMODULE_DEPEND(ffec, ether, 1, 1, 1); 1763256806SianMODULE_DEPEND(ffec, miibus, 1, 1, 1); 1764