1/*- 2 * Copyright (c) 2011-2012 Stefan Bethke. 3 * Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30#include <sys/param.h> 31#include <sys/bus.h> 32#include <sys/errno.h> 33#include <sys/kernel.h> 34#include <sys/module.h> 35#include <sys/socket.h> 36#include <sys/sockio.h> 37#include <sys/sysctl.h> 38#include <sys/systm.h> 39 40#include <net/if.h> 41#include <net/if_arp.h> 42#include <net/ethernet.h> 43#include <net/if_dl.h> 44#include <net/if_media.h> 45#include <net/if_types.h> 46 47#include <machine/bus.h> 48#include <dev/iicbus/iic.h> 49#include <dev/iicbus/iiconf.h> 50#include <dev/iicbus/iicbus.h> 51#include <dev/mii/mii.h> 52#include <dev/mii/miivar.h> 53#include <dev/mdio/mdio.h> 54 55#include <dev/etherswitch/etherswitch.h> 56 57#include <dev/etherswitch/arswitch/arswitchreg.h> 58#include <dev/etherswitch/arswitch/arswitchvar.h> 59#include <dev/etherswitch/arswitch/arswitch_reg.h> 60#include <dev/etherswitch/arswitch/arswitch_phy.h> /* XXX for probe */ 61#include <dev/etherswitch/arswitch/arswitch_9340.h> 62 63#include "mdio_if.h" 64#include "miibus_if.h" 65#include "etherswitch_if.h" 66 67/* 68 * AR9340 specific functions 69 */ 70static int 71ar9340_hw_setup(struct arswitch_softc *sc) 72{ 73 74 return (0); 75} 76 77/* 78 * Initialise other global values for the AR9340. 79 */ 80static int 81ar9340_hw_global_setup(struct arswitch_softc *sc) 82{ 83 84 /* Enable CPU port; disable mirror port */ 85 arswitch_writereg(sc->sc_dev, AR8X16_REG_CPU_PORT, 86 AR8X16_CPU_PORT_EN | AR8X16_CPU_MIRROR_DIS); 87 88 /* Setup TAG priority mapping */ 89 arswitch_writereg(sc->sc_dev, AR8X16_REG_TAG_PRIO, 0xfa50); 90 91 /* Enable aging, MAC replacing */ 92 arswitch_writereg(sc->sc_dev, AR934X_REG_AT_CTRL, 93 0x2b /* 5 min age time */ | 94 AR934X_AT_CTRL_AGE_EN | 95 AR934X_AT_CTRL_LEARN_CHANGE); 96 97 /* Enable ARP frame acknowledge */ 98 arswitch_modifyreg(sc->sc_dev, AR934X_REG_QM_CTRL, 99 AR934X_QM_CTRL_ARP_EN, AR934X_QM_CTRL_ARP_EN); 100 101 /* Enable Broadcast frames transmitted to the CPU */ 102 arswitch_modifyreg(sc->sc_dev, AR934X_REG_FLOOD_MASK, 103 AR934X_FLOOD_MASK_BC_DP(0), 104 AR934X_FLOOD_MASK_BC_DP(0)); 105 arswitch_modifyreg(sc->sc_dev, AR934X_REG_FLOOD_MASK, 106 AR934X_FLOOD_MASK_MC_DP(0), 107 AR934X_FLOOD_MASK_MC_DP(0)); 108 109 /* Enable MIB counters */ 110 arswitch_modifyreg(sc->sc_dev, AR8X16_REG_MIB_FUNC0, 111 AR934X_MIB_ENABLE, AR934X_MIB_ENABLE); 112 113 /* Setup MTU */ 114 arswitch_modifyreg(sc->sc_dev, AR8X16_REG_GLOBAL_CTRL, 115 AR7240_GLOBAL_CTRL_MTU_MASK, 116 SM(1536, AR7240_GLOBAL_CTRL_MTU_MASK)); 117 118 /* Service Tag */ 119 arswitch_modifyreg(sc->sc_dev, AR8X16_REG_SERVICE_TAG, 120 AR8X16_SERVICE_TAG_MASK, 0); 121 122 /* Settle time */ 123 DELAY(1000); 124 125 /* 126 * Check PHY mode bits. 127 * 128 * This dictates whether the connected port is to be wired 129 * up via GMII or MII. I'm not sure why - this is an internal 130 * wiring issue. 131 */ 132 if (sc->is_gmii) { 133 device_printf(sc->sc_dev, "%s: GMII\n", __func__); 134 arswitch_modifyreg(sc->sc_dev, AR934X_REG_OPER_MODE0, 135 AR934X_OPER_MODE0_MAC_GMII_EN, 136 AR934X_OPER_MODE0_MAC_GMII_EN); 137 } else if (sc->is_mii) { 138 device_printf(sc->sc_dev, "%s: MII\n", __func__); 139 arswitch_modifyreg(sc->sc_dev, AR934X_REG_OPER_MODE0, 140 AR934X_OPER_MODE0_PHY_MII_EN, 141 AR934X_OPER_MODE0_PHY_MII_EN); 142 } else { 143 device_printf(sc->sc_dev, "%s: need is_gmii or is_mii set\n", 144 __func__); 145 return (ENXIO); 146 } 147 148 /* 149 * Whether to connect PHY 4 via MII (ie a switch port) or 150 * treat it as a CPU port. 151 */ 152 if (sc->phy4cpu) { 153 device_printf(sc->sc_dev, "%s: PHY4 - CPU\n", __func__); 154 arswitch_modifyreg(sc->sc_dev, AR934X_REG_OPER_MODE1, 155 AR934X_REG_OPER_MODE1_PHY4_MII_EN, 156 AR934X_REG_OPER_MODE1_PHY4_MII_EN); 157 sc->info.es_nports = 5; 158 } else { 159 device_printf(sc->sc_dev, "%s: PHY4 - Local\n", __func__); 160 sc->info.es_nports = 6; 161 } 162 163 /* Settle time */ 164 DELAY(1000); 165 166 return (0); 167} 168 169/* 170 * The AR9340 switch probes (almost) the same as the AR7240 on-chip switch. 171 * 172 * However, the support is slightly different. 173 * 174 * So instead of checking the PHY revision or mask register contents, 175 * we simply fall back to a hint check. 176 */ 177int 178ar9340_probe(device_t dev) 179{ 180 int is_9340 = 0; 181 182 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 183 "is_9340", &is_9340) != 0) 184 return (ENXIO); 185 186 if (is_9340 == 0) 187 return (ENXIO); 188 189 return (0); 190} 191 192void 193ar9340_attach(struct arswitch_softc *sc) 194{ 195 196 sc->hal.arswitch_hw_setup = ar9340_hw_setup; 197 sc->hal.arswitch_hw_global_setup = ar9340_hw_global_setup; 198 199 /* Set the switch vlan capabilities. */ 200 sc->info.es_vlan_caps = ETHERSWITCH_VLAN_DOT1Q | 201 ETHERSWITCH_VLAN_PORT | ETHERSWITCH_VLAN_DOUBLE_TAG; 202 sc->info.es_nvlangroups = AR8X16_MAX_VLANS; 203} 204