if_etvar.h revision 199558
1139776Simp/*- 275374Sbp * Copyright (c) 2007 The DragonFly Project. All rights reserved. 375374Sbp * 475374Sbp * This code is derived from software contributed to The DragonFly Project 575374Sbp * by Sepherosa Ziehau <sepherosa@gmail.com> 675374Sbp * 775374Sbp * Redistribution and use in source and binary forms, with or without 875374Sbp * modification, are permitted provided that the following conditions 975374Sbp * are met: 1075374Sbp * 1175374Sbp * 1. Redistributions of source code must retain the above copyright 1275374Sbp * notice, this list of conditions and the following disclaimer. 1375374Sbp * 2. Redistributions in binary form must reproduce the above copyright 1475374Sbp * notice, this list of conditions and the following disclaimer in 1575374Sbp * the documentation and/or other materials provided with the 1675374Sbp * distribution. 1775374Sbp * 3. Neither the name of The DragonFly Project nor the names of its 1875374Sbp * contributors may be used to endorse or promote products derived 1975374Sbp * from this software without specific, prior written permission. 2075374Sbp * 2175374Sbp * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2275374Sbp * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2375374Sbp * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 2475374Sbp * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 2575374Sbp * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 2675374Sbp * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 2775374Sbp * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 2875374Sbp * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 2975374Sbp * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 3075374Sbp * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 3175374Sbp * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3275374Sbp * SUCH DAMAGE. 3375374Sbp * 3475374Sbp * $DragonFly: src/sys/dev/netif/et/if_etvar.h,v 1.4 2007/10/23 14:28:42 sephe Exp $ 3575374Sbp * $FreeBSD: head/sys/dev/et/if_etvar.h 199558 2009-11-19 22:06:19Z yongari $ 3675374Sbp */ 3775374Sbp 3875374Sbp#ifndef _IF_ETVAR_H 3975374Sbp#define _IF_ETVAR_H 4075374Sbp 4175374Sbp/* DragonFly compatibility */ 4275374Sbp#define EVL_ENCAPLEN ETHER_VLAN_ENCAP_LEN 4375374Sbp 4475374Sbp/* 4575374Sbp * Allocate the right type of mbuf for the desired total length. 4675374Sbp */ 4775374Sbpstatic __inline struct mbuf * 4875374Sbpm_getl(int len, int how, int type, int flags, int *psize) 4975374Sbp{ 5075374Sbp struct mbuf *m; 5175374Sbp int size; 5275374Sbp 5375374Sbp if (len >= MINCLSIZE) { 54151897Srwatson m = m_getcl(how, type, flags); 5575374Sbp size = MCLBYTES; 5675374Sbp } else if (flags & M_PKTHDR) { 5775374Sbp m = m_gethdr(how, type); 5875374Sbp size = MHLEN; 5975374Sbp } else { 6075374Sbp m = m_get(how, type); 6175374Sbp size = MLEN; 6275374Sbp } 6375374Sbp if (psize != NULL) 6475374Sbp *psize = size; 6575374Sbp return (m); 6675374Sbp} 6775374Sbp 6875374Sbp 6975374Sbp#define ET_ALIGN 0x1000 7075374Sbp#define ET_NSEG_MAX 32 /* XXX no limit actually */ 7175374Sbp#define ET_NSEG_SPARE 8 7275374Sbp 7375374Sbp#define ET_TX_NDESC 512 7475374Sbp#define ET_RX_NDESC 512 7575374Sbp#define ET_RX_NRING 2 7675374Sbp#define ET_RX_NSTAT (ET_RX_NRING * ET_RX_NDESC) 7775374Sbp 7875374Sbp#define ET_TX_RING_SIZE (ET_TX_NDESC * sizeof(struct et_txdesc)) 7975374Sbp#define ET_RX_RING_SIZE (ET_RX_NDESC * sizeof(struct et_rxdesc)) 8075374Sbp#define ET_RXSTAT_RING_SIZE (ET_RX_NSTAT * sizeof(struct et_rxstat)) 8175374Sbp 8275374Sbp#define ET_JUMBO_FRAMELEN (ET_MEM_SIZE - ET_MEM_RXSIZE_MIN - \ 8375374Sbp ET_MEM_TXSIZE_EX) 8475374Sbp#define ET_JUMBO_MTU (ET_JUMBO_FRAMELEN - ETHER_HDR_LEN - \ 8575374Sbp EVL_ENCAPLEN - ETHER_CRC_LEN) 8675374Sbp 8775374Sbp#define ET_FRAMELEN(mtu) (ETHER_HDR_LEN + EVL_ENCAPLEN + (mtu) + \ 8875374Sbp ETHER_CRC_LEN) 8975374Sbp 9075374Sbp#define ET_JSLOTS (ET_RX_NDESC + 128) 9175374Sbp#define ET_JLEN (ET_JUMBO_FRAMELEN + ETHER_ALIGN) 9275374Sbp#define ET_JUMBO_MEM_SIZE (ET_JSLOTS * ET_JLEN) 9375374Sbp 9475374Sbp#define CSR_WRITE_4(sc, reg, val) \ 9575374Sbp bus_write_4((sc)->sc_mem_res, (reg), (val)) 9675374Sbp#define CSR_READ_4(sc, reg) \ 9775374Sbp bus_read_4((sc)->sc_mem_res, (reg)) 9875374Sbp 9975374Sbp#define ET_ADDR_HI(addr) ((uint64_t) (addr) >> 32) 10075374Sbp#define ET_ADDR_LO(addr) ((uint64_t) (addr) & 0xffffffff) 10175374Sbp 10275374Sbpstruct et_txdesc { 10375374Sbp uint32_t td_addr_hi; 10475374Sbp uint32_t td_addr_lo; 10575374Sbp uint32_t td_ctrl1; /* ET_TDCTRL1_ */ 10675374Sbp uint32_t td_ctrl2; /* ET_TDCTRL2_ */ 10775374Sbp} __packed; 10875374Sbp 10975374Sbp#define ET_TDCTRL1_LEN_MASK 0x0000FFFF 11075374Sbp 111110299Sphk#define ET_TDCTRL2_LAST_FRAG 0x00000001 11275374Sbp#define ET_TDCTRL2_FIRST_FRAG 0x00000002 11375374Sbp#define ET_TDCTRL2_INTR 0x00000004 11475374Sbp 11575374Sbpstruct et_rxdesc { 11675374Sbp uint32_t rd_addr_lo; 11775374Sbp uint32_t rd_addr_hi; 11875374Sbp uint32_t rd_ctrl; /* ET_RDCTRL_ */ 119110299Sphk} __packed; 12075374Sbp 12175374Sbp#define ET_RDCTRL_BUFIDX_MASK 0x000003FF 12275374Sbp 12375374Sbpstruct et_rxstat { 12475374Sbp uint32_t rxst_info1; 125145974Sanholt uint32_t rxst_info2; /* ET_RXST_INFO2_ */ 12675374Sbp} __packed; 12775374Sbp 12875374Sbp#define ET_RXST_INFO2_LEN_MASK 0x0000FFFF 12975374Sbp#define ET_RXST_INFO2_LEN_SHIFT 0 13075374Sbp#define ET_RXST_INFO2_BUFIDX_MASK 0x03FF0000 13175374Sbp#define ET_RXST_INFO2_BUFIDX_SHIFT 16 13275374Sbp#define ET_RXST_INFO2_RINGIDX_MASK 0x0C000000 13375374Sbp#define ET_RXST_INFO2_RINGIDX_SHIFT 26 13475374Sbp 13575374Sbpstruct et_rxstatus { 13675374Sbp uint32_t rxs_ring; 13775374Sbp uint32_t rxs_stat_ring; /* ET_RXS_STATRING_ */ 13875374Sbp} __packed; 13975374Sbp 14075374Sbp#define ET_RXS_STATRING_INDEX_MASK 0x0FFF0000 14175374Sbp#define ET_RXS_STATRING_INDEX_SHIFT 16 14275374Sbp#define ET_RXS_STATRING_WRAP 0x10000000 14375374Sbp 14475374Sbpstruct et_dmamap_ctx { 14575374Sbp int nsegs; 14675374Sbp bus_dma_segment_t *segs; 14775374Sbp}; 14875374Sbp 14975374Sbpstruct et_txbuf { 15075374Sbp struct mbuf *tb_mbuf; 15175374Sbp bus_dmamap_t tb_dmap; 15275374Sbp}; 15375374Sbp 15475374Sbpstruct et_rxbuf { 15575374Sbp struct mbuf *rb_mbuf; 15675374Sbp bus_dmamap_t rb_dmap; 15775374Sbp bus_addr_t rb_paddr; 15875374Sbp}; 15975374Sbp 16075374Sbpstruct et_txstatus_data { 16175374Sbp uint32_t *txsd_status; 16275374Sbp bus_addr_t txsd_paddr; 16375374Sbp bus_dma_tag_t txsd_dtag; 16475374Sbp bus_dmamap_t txsd_dmap; 16575374Sbp}; 16675374Sbp 16775374Sbpstruct et_rxstatus_data { 16875374Sbp struct et_rxstatus *rxsd_status; 16975374Sbp bus_addr_t rxsd_paddr; 17075374Sbp bus_dma_tag_t rxsd_dtag; 17175374Sbp bus_dmamap_t rxsd_dmap; 17275374Sbp}; 17375374Sbp 17475374Sbpstruct et_rxstat_ring { 17575374Sbp struct et_rxstat *rsr_stat; 17675374Sbp bus_addr_t rsr_paddr; 17775374Sbp bus_dma_tag_t rsr_dtag; 17875374Sbp bus_dmamap_t rsr_dmap; 17975374Sbp 18075374Sbp int rsr_index; 18175374Sbp int rsr_wrap; 18275374Sbp}; 18375374Sbp 18475374Sbpstruct et_txdesc_ring { 18575374Sbp struct et_txdesc *tr_desc; 18675374Sbp bus_addr_t tr_paddr; 18775374Sbp bus_dma_tag_t tr_dtag; 18875374Sbp bus_dmamap_t tr_dmap; 18975374Sbp 19075374Sbp int tr_ready_index; 19175374Sbp int tr_ready_wrap; 19275374Sbp}; 19375374Sbp 19475374Sbpstruct et_rxdesc_ring { 19575374Sbp struct et_rxdesc *rr_desc; 19675374Sbp bus_addr_t rr_paddr; 19775374Sbp bus_dma_tag_t rr_dtag; 19875374Sbp bus_dmamap_t rr_dmap; 19975374Sbp 20075374Sbp uint32_t rr_posreg; 20175374Sbp int rr_index; 20275374Sbp int rr_wrap; 20375374Sbp}; 20475374Sbp 20575374Sbpstruct et_txbuf_data { 20675374Sbp struct et_txbuf tbd_buf[ET_TX_NDESC]; 20775374Sbp 20875374Sbp int tbd_start_index; 20975374Sbp int tbd_start_wrap; 21075374Sbp int tbd_used; 21175374Sbp}; 21275374Sbp 21375374Sbpstruct et_softc; 21475374Sbpstruct et_rxbuf_data; 21575374Sbptypedef int (*et_newbuf_t)(struct et_rxbuf_data *, int, int); 21675374Sbp 21775374Sbpstruct et_rxbuf_data { 21875374Sbp struct et_rxbuf rbd_buf[ET_RX_NDESC]; 21975374Sbp 22075374Sbp struct et_softc *rbd_softc; 22175374Sbp struct et_rxdesc_ring *rbd_ring; 22275374Sbp 22375374Sbp int rbd_bufsize; 22475374Sbp et_newbuf_t rbd_newbuf; 22575374Sbp}; 22675374Sbp 22775374Sbpstruct et_softc { 22875374Sbp struct ifnet *ifp; 22975374Sbp device_t dev; 23075374Sbp struct mtx sc_mtx; 23175374Sbp device_t sc_miibus; 23275374Sbp void *sc_irq_handle; 23375374Sbp struct resource *sc_irq_res; 23475374Sbp struct resource *sc_mem_res; 23575374Sbp 23675374Sbp struct arpcom arpcom; 23775374Sbp int sc_if_flags; 23875374Sbp uint32_t sc_flags; /* ET_FLAG_ */ 23975374Sbp int sc_expcap; 24075374Sbp 24175374Sbp int sc_mem_rid; 24275374Sbp 24375374Sbp int sc_irq_rid; 24475374Sbp 24575374Sbp struct callout sc_tick; 24675374Sbp 24775374Sbp int watchdog_timer; 24875374Sbp 24975374Sbp bus_dma_tag_t sc_dtag; 25075374Sbp 25175374Sbp struct et_rxdesc_ring sc_rx_ring[ET_RX_NRING]; 25275374Sbp struct et_rxstat_ring sc_rxstat_ring; 25375374Sbp struct et_rxstatus_data sc_rx_status; 25475374Sbp 25575374Sbp struct et_txdesc_ring sc_tx_ring; 25675374Sbp struct et_txstatus_data sc_tx_status; 25775374Sbp 25875374Sbp bus_dma_tag_t sc_mbuf_dtag; 25975374Sbp bus_dmamap_t sc_mbuf_tmp_dmap; 26075374Sbp struct et_rxbuf_data sc_rx_data[ET_RX_NRING]; 26175374Sbp struct et_txbuf_data sc_tx_data; 26275374Sbp 26375374Sbp uint32_t sc_tx; 26475374Sbp uint32_t sc_tx_intr; 26575374Sbp 26675374Sbp /* 26775374Sbp * Sysctl variables 26875374Sbp */ 26975374Sbp int sc_rx_intr_npkts; 27075374Sbp int sc_rx_intr_delay; 27175374Sbp int sc_tx_intr_nsegs; 27275374Sbp uint32_t sc_timer; 273116338Stjr}; 274116338Stjr 275107821Stjr#define ET_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 27675374Sbp#define ET_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 27775374Sbp#define ET_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 27875374Sbp 27975374Sbp#define ET_FLAG_PCIE 0x0001 28075374Sbp#define ET_FLAG_MSI 0x0002 28175374Sbp#define ET_FLAG_TXRX_ENABLED 0x0100 28275374Sbp#define ET_FLAG_JUMBO 0x0200 28375374Sbp 28475374Sbp#endif /* !_IF_ETVAR_H */ 28575374Sbp