1179895Sdelphij/*- 2210661Sdelphij * Copyright (c) 2007 Sepherosa Ziehau. All rights reserved. 3199553Syongari * 4179895Sdelphij * This code is derived from software contributed to The DragonFly Project 5179895Sdelphij * by Sepherosa Ziehau <sepherosa@gmail.com> 6199553Syongari * 7179895Sdelphij * Redistribution and use in source and binary forms, with or without 8179895Sdelphij * modification, are permitted provided that the following conditions 9179895Sdelphij * are met: 10199553Syongari * 11179895Sdelphij * 1. Redistributions of source code must retain the above copyright 12179895Sdelphij * notice, this list of conditions and the following disclaimer. 13179895Sdelphij * 2. Redistributions in binary form must reproduce the above copyright 14179895Sdelphij * notice, this list of conditions and the following disclaimer in 15179895Sdelphij * the documentation and/or other materials provided with the 16179895Sdelphij * distribution. 17179895Sdelphij * 3. Neither the name of The DragonFly Project nor the names of its 18179895Sdelphij * contributors may be used to endorse or promote products derived 19179895Sdelphij * from this software without specific, prior written permission. 20199553Syongari * 21179895Sdelphij * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22179895Sdelphij * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23179895Sdelphij * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24179895Sdelphij * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25179895Sdelphij * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26179895Sdelphij * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27179895Sdelphij * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28179895Sdelphij * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29179895Sdelphij * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30179895Sdelphij * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31179895Sdelphij * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32179895Sdelphij * SUCH DAMAGE. 33199553Syongari * 34179895Sdelphij * $DragonFly: src/sys/dev/netif/et/if_etvar.h,v 1.4 2007/10/23 14:28:42 sephe Exp $ 35179895Sdelphij * $FreeBSD$ 36179895Sdelphij */ 37179895Sdelphij 38179895Sdelphij#ifndef _IF_ETVAR_H 39179895Sdelphij#define _IF_ETVAR_H 40179895Sdelphij 41228335Syongari#define ET_RING_ALIGN 4096 42228335Syongari#define ET_STATUS_ALIGN 8 43228335Syongari#define ET_NSEG_MAX 32 /* XXX no limit actually */ 44228335Syongari#define ET_NSEG_SPARE 4 45179895Sdelphij 46228335Syongari#define ET_TX_NDESC 512 47228335Syongari#define ET_RX_NDESC 512 48228335Syongari#define ET_RX_NRING 2 49228335Syongari#define ET_RX_NSTAT (ET_RX_NRING * ET_RX_NDESC) 50179895Sdelphij 51228335Syongari#define ET_TX_RING_SIZE (ET_TX_NDESC * sizeof(struct et_txdesc)) 52228335Syongari#define ET_RX_RING_SIZE (ET_RX_NDESC * sizeof(struct et_rxdesc)) 53228335Syongari#define ET_RXSTAT_RING_SIZE (ET_RX_NSTAT * sizeof(struct et_rxstat)) 54179895Sdelphij 55228335Syongari#define ET_JUMBO_FRAMELEN (ET_MEM_SIZE - ET_MEM_RXSIZE_MIN - \ 56179895Sdelphij ET_MEM_TXSIZE_EX) 57228335Syongari#define ET_JUMBO_MTU (ET_JUMBO_FRAMELEN - ETHER_HDR_LEN - \ 58179895Sdelphij EVL_ENCAPLEN - ETHER_CRC_LEN) 59179895Sdelphij 60228335Syongari#define ET_FRAMELEN(mtu) (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + \ 61228325Syongari (mtu) + ETHER_CRC_LEN) 62179895Sdelphij 63228335Syongari#define ET_JSLOTS (ET_RX_NDESC + 128) 64228335Syongari#define ET_JLEN (ET_JUMBO_FRAMELEN + ETHER_ALIGN) 65228335Syongari#define ET_JUMBO_MEM_SIZE (ET_JSLOTS * ET_JLEN) 66179895Sdelphij 67228335Syongari#define CSR_WRITE_4(sc, reg, val) \ 68199558Syongari bus_write_4((sc)->sc_mem_res, (reg), (val)) 69228335Syongari#define CSR_READ_4(sc, reg) \ 70199558Syongari bus_read_4((sc)->sc_mem_res, (reg)) 71179895Sdelphij 72228335Syongari#define ET_ADDR_HI(addr) ((uint64_t) (addr) >> 32) 73228335Syongari#define ET_ADDR_LO(addr) ((uint64_t) (addr) & 0xffffffff) 74179895Sdelphij 75179895Sdelphijstruct et_txdesc { 76179895Sdelphij uint32_t td_addr_hi; 77179895Sdelphij uint32_t td_addr_lo; 78179895Sdelphij uint32_t td_ctrl1; /* ET_TDCTRL1_ */ 79179895Sdelphij uint32_t td_ctrl2; /* ET_TDCTRL2_ */ 80199608Syongari}; 81179895Sdelphij 82228335Syongari#define ET_TDCTRL1_LEN_MASK 0x0000FFFF 83179895Sdelphij 84228335Syongari#define ET_TDCTRL2_LAST_FRAG 0x00000001 85228335Syongari#define ET_TDCTRL2_FIRST_FRAG 0x00000002 86228335Syongari#define ET_TDCTRL2_INTR 0x00000004 87228335Syongari#define ET_TDCTRL2_CTRL_WORD 0x00000008 88228335Syongari#define ET_TDCTRL2_HDX_BACKP 0x00000010 89228335Syongari#define ET_TDCTRL2_XMIT_PAUSE 0x00000020 90228335Syongari#define ET_TDCTRL2_FRAME_ERR 0x00000040 91228335Syongari#define ET_TDCTRL2_NO_CRC 0x00000080 92228335Syongari#define ET_TDCTRL2_MAC_OVRRD 0x00000100 93228335Syongari#define ET_TDCTRL2_PAD_PACKET 0x00000200 94228335Syongari#define ET_TDCTRL2_JUMBO_PACKET 0x00000400 95228335Syongari#define ET_TDCTRL2_INS_VLAN 0x00000800 96228335Syongari#define ET_TDCTRL2_CSUM_IP 0x00001000 97228335Syongari#define ET_TDCTRL2_CSUM_TCP 0x00002000 98228335Syongari#define ET_TDCTRL2_CSUM_UDP 0x00004000 99179895Sdelphij 100179895Sdelphijstruct et_rxdesc { 101179895Sdelphij uint32_t rd_addr_lo; 102179895Sdelphij uint32_t rd_addr_hi; 103179895Sdelphij uint32_t rd_ctrl; /* ET_RDCTRL_ */ 104199608Syongari}; 105179895Sdelphij 106228335Syongari#define ET_RDCTRL_BUFIDX_MASK 0x000003FF 107179895Sdelphij 108179895Sdelphijstruct et_rxstat { 109179895Sdelphij uint32_t rxst_info1; 110179895Sdelphij uint32_t rxst_info2; /* ET_RXST_INFO2_ */ 111199608Syongari}; 112179895Sdelphij 113228335Syongari#define ET_RXST_INFO1_HASH_PASS 0x00000001 114228335Syongari#define ET_RXST_INFO1_IPCSUM 0x00000002 115228335Syongari#define ET_RXST_INFO1_IPCSUM_OK 0x00000004 116228335Syongari#define ET_RXST_INFO1_TCPCSUM 0x00000008 117228335Syongari#define ET_RXST_INFO1_TCPCSUM_OK 0x00000010 118228335Syongari#define ET_RXST_INFO1_WOL 0x00000020 119228335Syongari#define ET_RXST_INFO1_RXMAC_ERR 0x00000040 120228335Syongari#define ET_RXST_INFO1_DROP 0x00000080 121228335Syongari#define ET_RXST_INFO1_FRAME_TRUNC 0x00000100 122228335Syongari#define ET_RXST_INFO1_JUMBO 0x00000200 123228335Syongari#define ET_RXST_INFO1_VLAN 0x00000400 124228335Syongari#define ET_RXST_INFO1_PREV_FRMAE_DROP 0x00010000 125228335Syongari#define ET_RXST_INFO1_SHORT 0x00020000 126228335Syongari#define ET_RXST_INFO1_BAD_CARRIER 0x00040000 127228335Syongari#define ET_RXST_INFO1_CODE_ERR 0x00080000 128228335Syongari#define ET_RXST_INFO1_CRC_ERR 0x00100000 129228335Syongari#define ET_RXST_INFO1_LEN_MISMATCH 0x00200000 130228335Syongari#define ET_RXST_INFO1_TOO_LONG 0x00400000 131228335Syongari#define ET_RXST_INFO1_OK 0x00800000 132228335Syongari#define ET_RXST_INFO1_MULTICAST 0x01000000 133228335Syongari#define ET_RXST_INFO1_BROADCAST 0x02000000 134228335Syongari#define ET_RXST_INFO1_DRIBBLE 0x04000000 135228335Syongari#define ET_RXST_INFO1_CTL_FRAME 0x08000000 136228335Syongari#define ET_RXST_INFO1_PAUSE_FRAME 0x10000000 137228335Syongari#define ET_RXST_INFO1_UNKWN_CTL_FRAME 0x20000000 138228335Syongari#define ET_RXST_INFO1_VLAN_TAG 0x40000000 139228335Syongari#define ET_RXST_INFO1_LONG_EVENT 0x80000000 140228325Syongari 141228335Syongari#define ET_RXST_INFO2_LEN_MASK 0x0000FFFF 142228335Syongari#define ET_RXST_INFO2_LEN_SHIFT 0 143228335Syongari#define ET_RXST_INFO2_BUFIDX_MASK 0x03FF0000 144228335Syongari#define ET_RXST_INFO2_BUFIDX_SHIFT 16 145228335Syongari#define ET_RXST_INFO2_RINGIDX_MASK 0x0C000000 146228335Syongari#define ET_RXST_INFO2_RINGIDX_SHIFT 26 147179895Sdelphij 148179895Sdelphijstruct et_rxstatus { 149179895Sdelphij uint32_t rxs_ring; 150179895Sdelphij uint32_t rxs_stat_ring; /* ET_RXS_STATRING_ */ 151199608Syongari}; 152179895Sdelphij 153228335Syongari#define ET_RXS_STATRING_INDEX_MASK 0x0FFF0000 154228335Syongari#define ET_RXS_STATRING_INDEX_SHIFT 16 155228335Syongari#define ET_RXS_STATRING_WRAP 0x10000000 156179895Sdelphij 157179895Sdelphijstruct et_txbuf { 158179895Sdelphij struct mbuf *tb_mbuf; 159179895Sdelphij bus_dmamap_t tb_dmap; 160179895Sdelphij}; 161179895Sdelphij 162179895Sdelphijstruct et_rxbuf { 163179895Sdelphij struct mbuf *rb_mbuf; 164179895Sdelphij bus_dmamap_t rb_dmap; 165179895Sdelphij}; 166179895Sdelphij 167179895Sdelphijstruct et_txstatus_data { 168179895Sdelphij uint32_t *txsd_status; 169179895Sdelphij bus_addr_t txsd_paddr; 170179895Sdelphij bus_dma_tag_t txsd_dtag; 171179895Sdelphij bus_dmamap_t txsd_dmap; 172179895Sdelphij}; 173179895Sdelphij 174179895Sdelphijstruct et_rxstatus_data { 175179895Sdelphij struct et_rxstatus *rxsd_status; 176179895Sdelphij bus_addr_t rxsd_paddr; 177179895Sdelphij bus_dma_tag_t rxsd_dtag; 178179895Sdelphij bus_dmamap_t rxsd_dmap; 179179895Sdelphij}; 180179895Sdelphij 181179895Sdelphijstruct et_rxstat_ring { 182179895Sdelphij struct et_rxstat *rsr_stat; 183179895Sdelphij bus_addr_t rsr_paddr; 184179895Sdelphij bus_dma_tag_t rsr_dtag; 185179895Sdelphij bus_dmamap_t rsr_dmap; 186179895Sdelphij 187179895Sdelphij int rsr_index; 188179895Sdelphij int rsr_wrap; 189179895Sdelphij}; 190179895Sdelphij 191179895Sdelphijstruct et_txdesc_ring { 192179895Sdelphij struct et_txdesc *tr_desc; 193179895Sdelphij bus_addr_t tr_paddr; 194179895Sdelphij bus_dma_tag_t tr_dtag; 195179895Sdelphij bus_dmamap_t tr_dmap; 196179895Sdelphij 197179895Sdelphij int tr_ready_index; 198179895Sdelphij int tr_ready_wrap; 199179895Sdelphij}; 200179895Sdelphij 201179895Sdelphijstruct et_rxdesc_ring { 202179895Sdelphij struct et_rxdesc *rr_desc; 203179895Sdelphij bus_addr_t rr_paddr; 204179895Sdelphij bus_dma_tag_t rr_dtag; 205179895Sdelphij bus_dmamap_t rr_dmap; 206179895Sdelphij 207179895Sdelphij uint32_t rr_posreg; 208179895Sdelphij int rr_index; 209179895Sdelphij int rr_wrap; 210179895Sdelphij}; 211179895Sdelphij 212179895Sdelphijstruct et_txbuf_data { 213179895Sdelphij struct et_txbuf tbd_buf[ET_TX_NDESC]; 214179895Sdelphij 215179895Sdelphij int tbd_start_index; 216179895Sdelphij int tbd_start_wrap; 217179895Sdelphij int tbd_used; 218179895Sdelphij}; 219179895Sdelphij 220179895Sdelphijstruct et_softc; 221179895Sdelphijstruct et_rxbuf_data; 222179895Sdelphij 223179895Sdelphijstruct et_rxbuf_data { 224179895Sdelphij struct et_rxbuf rbd_buf[ET_RX_NDESC]; 225179895Sdelphij 226179895Sdelphij struct et_softc *rbd_softc; 227179895Sdelphij struct et_rxdesc_ring *rbd_ring; 228179895Sdelphij 229179895Sdelphij int rbd_bufsize; 230228325Syongari int (*rbd_newbuf)(struct et_rxbuf_data *, int); 231228325Syongari void (*rbd_discard)(struct et_rxbuf_data *, int); 232179895Sdelphij}; 233179895Sdelphij 234228332Syongaristruct et_hw_stats { 235228332Syongari /* RX/TX stats. */ 236228332Syongari uint64_t pkts_64; 237228332Syongari uint64_t pkts_65; 238228332Syongari uint64_t pkts_128; 239228332Syongari uint64_t pkts_256; 240228332Syongari uint64_t pkts_512; 241228332Syongari uint64_t pkts_1024; 242228332Syongari uint64_t pkts_1519; 243228332Syongari /* RX stats. */ 244228332Syongari uint64_t rx_bytes; 245228332Syongari uint64_t rx_frames; 246228332Syongari uint32_t rx_crcerrs; 247228332Syongari uint64_t rx_mcast; 248228332Syongari uint64_t rx_bcast; 249228332Syongari uint32_t rx_control; 250228332Syongari uint32_t rx_pause; 251228332Syongari uint32_t rx_unknown_control; 252228332Syongari uint32_t rx_alignerrs; 253228332Syongari uint32_t rx_lenerrs; 254228332Syongari uint32_t rx_codeerrs; 255228332Syongari uint32_t rx_cserrs; 256228332Syongari uint32_t rx_runts; 257228332Syongari uint64_t rx_oversize; 258228332Syongari uint32_t rx_fragments; 259228332Syongari uint32_t rx_jabbers; 260228332Syongari uint32_t rx_drop; 261228332Syongari /* TX stats. */ 262228332Syongari uint64_t tx_bytes; 263228332Syongari uint64_t tx_frames; 264228332Syongari uint64_t tx_mcast; 265228332Syongari uint64_t tx_bcast; 266228332Syongari uint32_t tx_pause; 267228332Syongari uint32_t tx_deferred; 268228332Syongari uint32_t tx_excess_deferred; 269228332Syongari uint32_t tx_single_colls; 270228332Syongari uint32_t tx_multi_colls; 271228332Syongari uint32_t tx_late_colls; 272228332Syongari uint32_t tx_excess_colls; 273228332Syongari uint32_t tx_total_colls; 274228332Syongari uint32_t tx_pause_honored; 275228332Syongari uint32_t tx_drop; 276228332Syongari uint32_t tx_jabbers; 277228332Syongari uint32_t tx_crcerrs; 278228332Syongari uint32_t tx_control; 279228332Syongari uint64_t tx_oversize; 280228332Syongari uint32_t tx_undersize; 281228332Syongari uint32_t tx_fragments; 282228332Syongari}; 283228332Syongari 284179895Sdelphijstruct et_softc { 285179895Sdelphij struct ifnet *ifp; 286179895Sdelphij device_t dev; 287179895Sdelphij struct mtx sc_mtx; 288179895Sdelphij device_t sc_miibus; 289179895Sdelphij void *sc_irq_handle; 290179895Sdelphij struct resource *sc_irq_res; 291179895Sdelphij struct resource *sc_mem_res; 292179895Sdelphij 293179895Sdelphij int sc_if_flags; 294179895Sdelphij uint32_t sc_flags; /* ET_FLAG_ */ 295199552Syongari int sc_expcap; 296179895Sdelphij 297179895Sdelphij int sc_mem_rid; 298179895Sdelphij 299179895Sdelphij int sc_irq_rid; 300179895Sdelphij 301179895Sdelphij struct callout sc_tick; 302179895Sdelphij 303179895Sdelphij int watchdog_timer; 304179895Sdelphij 305179895Sdelphij bus_dma_tag_t sc_dtag; 306179895Sdelphij 307179895Sdelphij struct et_rxdesc_ring sc_rx_ring[ET_RX_NRING]; 308179895Sdelphij struct et_rxstat_ring sc_rxstat_ring; 309179895Sdelphij struct et_rxstatus_data sc_rx_status; 310179895Sdelphij 311179895Sdelphij struct et_txdesc_ring sc_tx_ring; 312179895Sdelphij struct et_txstatus_data sc_tx_status; 313179895Sdelphij 314179895Sdelphij bus_dma_tag_t sc_mbuf_dtag; 315228325Syongari bus_dma_tag_t sc_rx_mini_tag; 316228325Syongari bus_dmamap_t sc_rx_mini_sparemap; 317228325Syongari bus_dma_tag_t sc_rx_tag; 318228325Syongari bus_dmamap_t sc_rx_sparemap; 319228325Syongari bus_dma_tag_t sc_tx_tag; 320179895Sdelphij struct et_rxbuf_data sc_rx_data[ET_RX_NRING]; 321179895Sdelphij struct et_txbuf_data sc_tx_data; 322179895Sdelphij 323228332Syongari struct et_hw_stats sc_stats; 324179895Sdelphij uint32_t sc_tx; 325179895Sdelphij uint32_t sc_tx_intr; 326179895Sdelphij 327179895Sdelphij /* 328179895Sdelphij * Sysctl variables 329179895Sdelphij */ 330179895Sdelphij int sc_rx_intr_npkts; 331179895Sdelphij int sc_rx_intr_delay; 332179895Sdelphij int sc_tx_intr_nsegs; 333179895Sdelphij uint32_t sc_timer; 334179895Sdelphij}; 335179895Sdelphij 336228335Syongari#define ET_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 337228335Syongari#define ET_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 338228335Syongari#define ET_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 339179895Sdelphij 340228335Syongari#define ET_FLAG_PCIE 0x0001 341228335Syongari#define ET_FLAG_MSI 0x0002 342228335Syongari#define ET_FLAG_FASTETHER 0x0004 343228335Syongari#define ET_FLAG_TXRX_ENABLED 0x0100 344228335Syongari#define ET_FLAG_JUMBO 0x0200 345228335Syongari#define ET_FLAG_LINK 0x8000 346179895Sdelphij 347179895Sdelphij#endif /* !_IF_ETVAR_H */ 348