1/* $NetBSD: ncr53c9xvar.h,v 1.55 2011/07/31 18:39:00 jakllsch Exp $ */ 2 3/*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/*- 34 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by Peter Galbavy. 47 * 4. The name of the author may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 54 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 55 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 59 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62/* $FreeBSD$ */ 63 64#ifndef _NCR53C9XVAR_H_ 65#define _NCR53C9XVAR_H_ 66 67#include <sys/lock.h> 68 69/* Set this to 1 for normal debug, or 2 for per-target tracing. */ 70/* #define NCR53C9X_DEBUG 2 */ 71 72/* Wide or differential can have 16 targets */ 73#define NCR_NLUN 8 74 75#define NCR_ABORT_TIMEOUT 2000 /* time to wait for abort */ 76#define NCR_SENSE_TIMEOUT 1000 /* time to wait for sense */ 77 78#define FREQTOCCF(freq) (((freq + 4) / 5)) 79 80/* 81 * NCR 53c9x variants. Note these values are used as indexes into 82 * a table; do not modify them unless you know what you are doing. 83 */ 84#define NCR_VARIANT_ESP100 0 85#define NCR_VARIANT_ESP100A 1 86#define NCR_VARIANT_ESP200 2 87#define NCR_VARIANT_NCR53C94 3 88#define NCR_VARIANT_NCR53C96 4 89#define NCR_VARIANT_ESP406 5 90#define NCR_VARIANT_FAS408 6 91#define NCR_VARIANT_FAS216 7 92#define NCR_VARIANT_AM53C974 8 93#define NCR_VARIANT_FAS366 9 94#define NCR_VARIANT_NCR53C90_86C01 10 95#define NCR_VARIANT_FAS100A 11 96#define NCR_VARIANT_FAS236 12 97#define NCR_VARIANT_MAX 13 98 99/* XXX Max tag depth. Should this be defined in the register header? */ 100#define NCR_TAG_DEPTH 256 101 102/* 103 * ECB. Holds additional information for each SCSI command Comments: We 104 * need a separate scsi command block because we may need to overwrite it 105 * with a request sense command. Basically, we refrain from fiddling with 106 * the ccb union (except do the expected updating of return values). 107 * We'll generally update: ccb->ccb_h.status and ccb->csio.{resid, 108 * scsi_status,sense_data}. 109 */ 110struct ncr53c9x_ecb { 111 /* These fields are preserved between alloc and free. */ 112 struct callout ch; 113 struct ncr53c9x_softc *sc; 114 int tag_id; 115 int flags; 116 117 union ccb *ccb; /* SCSI xfer ctrl block from above */ 118 TAILQ_ENTRY(ncr53c9x_ecb) free_links; 119 TAILQ_ENTRY(ncr53c9x_ecb) chain; 120#define ECB_ALLOC 0x01 121#define ECB_READY 0x02 122#define ECB_SENSE 0x04 123#define ECB_ABORT 0x40 124#define ECB_RESET 0x80 125#define ECB_TENTATIVE_DONE 0x100 126 int timeout; 127 128 struct { 129 uint8_t msg[3]; /* Selection Id msg and tags */ 130 struct scsi_generic cmd; /* SCSI command block */ 131 } cmd; 132 uint8_t *daddr; /* Saved data pointer */ 133 int clen; /* Size of command in cmd.cmd */ 134 int dleft; /* Residue */ 135 uint8_t stat; /* SCSI status byte */ 136 uint8_t tag[2]; /* TAG bytes */ 137 uint8_t pad[1]; 138 139#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1 140 char trace[1000]; 141#endif 142}; 143#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1 144#define ECB_TRACE(ecb, msg, a, b) do { \ 145 const char *f = "[" msg "]"; \ 146 int n = strlen((ecb)->trace); \ 147 if (n < (sizeof((ecb)->trace)-100)) \ 148 sprintf((ecb)->trace + n, f, a, b); \ 149} while (/* CONSTCOND */0) 150#else 151#define ECB_TRACE(ecb, msg, a, b) 152#endif 153 154/* 155 * Some info about each (possible) target and LUN on the SCSI bus. 156 * 157 * SCSI I and II devices can have up to 8 LUNs, each with up to 256 158 * outstanding tags. SCSI III devices have 64-bit LUN identifiers 159 * that can be sparsely allocated. 160 * 161 * Since SCSI II devices can have up to 8 LUNs, we use an array 162 * of 8 pointers to ncr53c9x_linfo structures for fast lookup. 163 * Longer LUNs need to traverse the linked list. 164 */ 165 166struct ncr53c9x_linfo { 167 int64_t lun; 168 LIST_ENTRY(ncr53c9x_linfo) link; 169 time_t last_used; 170 uint8_t used; /* # slots in use */ 171 uint8_t avail; /* where to start scanning */ 172 uint8_t busy; 173 struct ncr53c9x_ecb *untagged; 174 struct ncr53c9x_ecb *queued[NCR_TAG_DEPTH]; 175}; 176 177struct ncr53c9x_xinfo { 178 uint8_t period; 179 uint8_t offset; 180 uint8_t width; 181}; 182 183struct ncr53c9x_tinfo { 184 int cmds; /* # of commands processed */ 185 int dconns; /* # of disconnects */ 186 int touts; /* # of timeouts */ 187 int perrs; /* # of parity errors */ 188 int senses; /* # of request sense commands sent */ 189 uint8_t flags; 190#define T_SYNCHOFF 0x01 /* SYNC mode is permanently off */ 191#define T_RSELECTOFF 0x02 /* RE-SELECT mode is off */ 192#define T_TAG 0x04 /* Turn on TAG QUEUEs */ 193#define T_SDTRSENT 0x08 /* SDTR message has been sent to */ 194#define T_WDTRSENT 0x10 /* WDTR message has been sent to */ 195 struct ncr53c9x_xinfo curr; 196 struct ncr53c9x_xinfo goal; 197 LIST_HEAD(lun_list, ncr53c9x_linfo) luns; 198 struct ncr53c9x_linfo *lun[NCR_NLUN]; /* For speedy lookups */ 199}; 200 201/* Look up a lun in a tinfo */ 202#define TINFO_LUN(t, l) ( \ 203 (((l) < NCR_NLUN) && (((t)->lun[(l)]) != NULL)) \ 204 ? ((t)->lun[(l)]) \ 205 : ncr53c9x_lunsearch((t), (int64_t)(l)) \ 206) 207 208/* Register a linenumber (for debugging). */ 209#define LOGLINE(p) 210 211#define NCR_SHOWECBS 0x01 212#define NCR_SHOWINTS 0x02 213#define NCR_SHOWCMDS 0x04 214#define NCR_SHOWMISC 0x08 215#define NCR_SHOWTRAC 0x10 216#define NCR_SHOWSTART 0x20 217#define NCR_SHOWPHASE 0x40 218#define NCR_SHOWDMA 0x80 219#define NCR_SHOWCCMDS 0x100 220#define NCR_SHOWMSGS 0x200 221 222#ifdef NCR53C9X_DEBUG 223extern int ncr53c9x_debug; 224#define NCR_ECBS(str) \ 225 do { \ 226 if ((ncr53c9x_debug & NCR_SHOWECBS) != 0) \ 227 printf str; \ 228 } while (/* CONSTCOND */0) 229#define NCR_MISC(str) \ 230 do { \ 231 if ((ncr53c9x_debug & NCR_SHOWMISC) != 0) \ 232 printf str; \ 233 } while (/* CONSTCOND */0) 234#define NCR_INTS(str) \ 235 do { \ 236 if ((ncr53c9x_debug & NCR_SHOWINTS) != 0) \ 237 printf str; \ 238 } while (/* CONSTCOND */0) 239#define NCR_TRACE(str) \ 240 do { \ 241 if ((ncr53c9x_debug & NCR_SHOWTRAC) != 0) \ 242 printf str; \ 243 } while (/* CONSTCOND */0) 244#define NCR_CMDS(str) \ 245 do { \ 246 if ((ncr53c9x_debug & NCR_SHOWCMDS) != 0) \ 247 printf str; \ 248 } while (/* CONSTCOND */0) 249#define NCR_START(str) \ 250 do { \ 251 if ((ncr53c9x_debug & NCR_SHOWSTART) != 0) \ 252 printf str; \ 253 } while (/* CONSTCOND */0) 254#define NCR_PHASE(str) \ 255 do { \ 256 if ((ncr53c9x_debug & NCR_SHOWPHASE) != 0) \ 257 printf str; \ 258 } while (/* CONSTCOND */0) 259#define NCR_DMA(str) \ 260 do { \ 261 if ((ncr53c9x_debug & NCR_SHOWDMA) != 0) \ 262 printf str; \ 263 } while (/* CONSTCOND */0) 264#define NCR_MSGS(str) \ 265 do { \ 266 if ((ncr53c9x_debug & NCR_SHOWMSGS) != 0) \ 267 printf str; \ 268 } while (/* CONSTCOND */0) 269#else 270#define NCR_ECBS(str) 271#define NCR_MISC(str) 272#define NCR_INTS(str) 273#define NCR_TRACE(str) 274#define NCR_CMDS(str) 275#define NCR_START(str) 276#define NCR_PHASE(str) 277#define NCR_DMA(str) 278#define NCR_MSGS(str) 279#endif 280 281#define NCR_MAX_MSG_LEN 8 282 283struct ncr53c9x_softc; 284 285/* 286 * Function switch used as glue to MD code 287 */ 288struct ncr53c9x_glue { 289 /* Mandatory entry points. */ 290 uint8_t (*gl_read_reg)(struct ncr53c9x_softc *, int); 291 void (*gl_write_reg)(struct ncr53c9x_softc *, int, uint8_t); 292 int (*gl_dma_isintr)(struct ncr53c9x_softc *); 293 void (*gl_dma_reset)(struct ncr53c9x_softc *); 294 int (*gl_dma_intr)(struct ncr53c9x_softc *); 295 int (*gl_dma_setup)(struct ncr53c9x_softc *, void **, size_t *, 296 int, size_t *); 297 void (*gl_dma_go)(struct ncr53c9x_softc *); 298 void (*gl_dma_stop)(struct ncr53c9x_softc *); 299 int (*gl_dma_isactive)(struct ncr53c9x_softc *); 300}; 301 302struct ncr53c9x_softc { 303 device_t sc_dev; /* us as a device */ 304 305 struct cam_sim *sc_sim; /* our scsi adapter */ 306 struct cam_path *sc_path; /* our scsi channel */ 307 struct callout sc_watchdog; /* periodic timer */ 308 309 const struct ncr53c9x_glue *sc_glue; /* glue to MD code */ 310 311 int sc_cfflags; /* Copy of config flags */ 312 313 /* register defaults */ 314 uint8_t sc_cfg1; /* Config 1 */ 315 uint8_t sc_cfg2; /* Config 2, not ESP100 */ 316 uint8_t sc_cfg3; /* Config 3, ESP200,FAS */ 317 uint8_t sc_cfg3_fscsi; /* Chip-specific FSCSI bit */ 318 uint8_t sc_cfg4; /* Config 4, only ESP200 */ 319 uint8_t sc_cfg5; /* Config 5, only ESP200 */ 320 uint8_t sc_ccf; /* Clock Conversion */ 321 uint8_t sc_timeout; 322 323 /* register copies, see ncr53c9x_readregs() */ 324 uint8_t sc_espintr; 325 uint8_t sc_espstat; 326 uint8_t sc_espstep; 327 uint8_t sc_espstat2; 328 uint8_t sc_espfflags; 329 330 /* Lists of command blocks */ 331 TAILQ_HEAD(ecb_list, ncr53c9x_ecb) ready_list; 332 333 struct ncr53c9x_ecb *sc_nexus; /* Current command */ 334 int sc_ntarg; 335 struct ncr53c9x_tinfo *sc_tinfo; 336 337 /* Data about the current nexus (updated for every cmd switch) */ 338 void *sc_dp; /* Current data pointer */ 339 ssize_t sc_dleft; /* Data left to transfer */ 340 341 /* Adapter state */ 342 int sc_phase; /* Copy of what bus phase we are in */ 343 int sc_prevphase; /* Copy of what bus phase we were in */ 344 uint8_t sc_state; /* State applicable to the adapter */ 345 uint8_t sc_flags; /* See below */ 346 uint8_t sc_selid; 347 uint8_t sc_lastcmd; 348 349 /* Message stuff */ 350 uint16_t sc_msgify; /* IDENTIFY message associated with nexus */ 351 uint16_t sc_msgout; /* What message is on its way out? */ 352 uint16_t sc_msgpriq; /* One or more messages to send (encoded) */ 353 uint16_t sc_msgoutq; /* What messages have been sent so far? */ 354 355 uint8_t *sc_omess; /* MSGOUT buffer */ 356 int sc_omess_self; /* MSGOUT buffer is self-allocated */ 357 void *sc_omp; /* Message pointer (for multibyte messages) */ 358 size_t sc_omlen; 359 uint8_t *sc_imess; /* MSGIN buffer */ 360 int sc_imess_self; /* MSGIN buffer is self-allocated */ 361 void *sc_imp; /* Message pointer (for multibyte messages) */ 362 size_t sc_imlen; 363 364 void *sc_cmdp; /* Command pointer (for DMAed commands) */ 365 size_t sc_cmdlen; /* Size of command in transit */ 366 367 /* Hardware attributes */ 368 int sc_freq; /* SCSI bus frequency in MHz */ 369 int sc_id; /* Our SCSI id */ 370 int sc_rev; /* Chip revision */ 371 int sc_features; /* Chip features */ 372 int sc_minsync; /* Minimum sync period / 4 */ 373 int sc_maxxfer; /* Maximum transfer size */ 374 int sc_maxoffset; /* Maximum offset */ 375 int sc_maxwidth; /* Maximum width */ 376 int sc_extended_geom; /* Should we return extended geometry */ 377 378 struct mtx sc_lock; /* driver mutex */ 379 380 struct ncr53c9x_ecb *ecb_array; 381 TAILQ_HEAD(,ncr53c9x_ecb) free_list; 382}; 383 384/* values for sc_state */ 385#define NCR_IDLE 1 /* Waiting for something to do */ 386#define NCR_SELECTING 2 /* SCSI command is arbiting */ 387#define NCR_RESELECTED 3 /* Has been reselected */ 388#define NCR_IDENTIFIED 4 /* Has gotten IFY but not TAG */ 389#define NCR_CONNECTED 5 /* Actively using the SCSI bus */ 390#define NCR_DISCONNECT 6 /* MSG_DISCONNECT received */ 391#define NCR_CMDCOMPLETE 7 /* MSG_CMDCOMPLETE received */ 392#define NCR_CLEANING 8 393#define NCR_SBR 9 /* Expect a SCSI RST because we commanded it */ 394 395/* values for sc_flags */ 396#define NCR_DROP_MSGI 0x01 /* Discard all msgs (parity err detected) */ 397#define NCR_ABORTING 0x02 /* Bailing out */ 398#define NCR_ICCS 0x04 /* Expect status phase results */ 399#define NCR_WAITI 0x08 /* Waiting for non-DMA data to arrive */ 400#define NCR_ATN 0x10 /* ATN asserted */ 401#define NCR_EXPECT_ILLCMD 0x20 /* Expect Illegal Command Interrupt */ 402 403/* values for sc_features */ 404#define NCR_F_HASCFG3 0x01 /* chip has CFG3 register */ 405#define NCR_F_FASTSCSI 0x02 /* chip supports Fast mode */ 406#define NCR_F_DMASELECT 0x04 /* can do dmaselect */ 407#define NCR_F_SELATN3 0x08 /* chip supports SELATN3 command */ 408#define NCR_F_LARGEXFER 0x10 /* chip supports transfers > 64k */ 409 410/* values for sc_msgout */ 411#define SEND_DEV_RESET 0x0001 412#define SEND_PARITY_ERROR 0x0002 413#define SEND_INIT_DET_ERR 0x0004 414#define SEND_REJECT 0x0008 415#define SEND_IDENTIFY 0x0010 416#define SEND_ABORT 0x0020 417#define SEND_TAG 0x0040 418#define SEND_WDTR 0x0080 419#define SEND_SDTR 0x0100 420 421/* SCSI Status codes */ 422#define ST_MASK 0x3e /* bit 0,6,7 is reserved */ 423 424/* phase bits */ 425#define IOI 0x01 426#define CDI 0x02 427#define MSGI 0x04 428 429/* Information transfer phases */ 430#define DATA_OUT_PHASE (0) 431#define DATA_IN_PHASE (IOI) 432#define COMMAND_PHASE (CDI) 433#define STATUS_PHASE (CDI | IOI) 434#define MESSAGE_OUT_PHASE (MSGI | CDI) 435#define MESSAGE_IN_PHASE (MSGI | CDI | IOI) 436 437#define PHASE_MASK (MSGI | CDI | IOI) 438 439/* Some pseudo phases for getphase()*/ 440#define BUSFREE_PHASE 0x100 /* Re/Selection no longer valid */ 441#define INVALID_PHASE 0x101 /* Re/Selection valid, but no REQ yet */ 442#define PSEUDO_PHASE 0x100 /* "pseudo" bit */ 443 444/* 445 * Macros to read and write the chip's registers. 446 */ 447#define NCR_READ_REG(sc, reg) \ 448 (*(sc)->sc_glue->gl_read_reg)((sc), (reg)) 449#define NCR_WRITE_REG(sc, reg, val) \ 450 (*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val)) 451 452#ifdef NCR53C9X_DEBUG 453#define NCRCMD(sc, cmd) do { \ 454 if ((ncr53c9x_debug & NCR_SHOWCCMDS) != 0) \ 455 printf("<CMD:0x%x %d>", (unsigned int)cmd, __LINE__); \ 456 sc->sc_lastcmd = cmd; \ 457 NCR_WRITE_REG(sc, NCR_CMD, cmd); \ 458} while (/* CONSTCOND */ 0) 459#else 460#define NCRCMD(sc, cmd) NCR_WRITE_REG(sc, NCR_CMD, cmd) 461#endif 462 463/* 464 * Macros for locking 465 */ 466#define NCR_LOCK_INIT(_sc) \ 467 mtx_init(&(_sc)->sc_lock, "ncr", "ncr53c9x lock", MTX_DEF); 468#define NCR_LOCK_INITIALIZED(_sc) mtx_initialized(&(_sc)->sc_lock) 469#define NCR_LOCK(_sc) mtx_lock(&(_sc)->sc_lock) 470#define NCR_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_lock) 471#define NCR_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_lock, (_what)) 472#define NCR_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_lock) 473 474/* 475 * DMA macros for NCR53c9x 476 */ 477#define NCRDMA_ISINTR(sc) (*(sc)->sc_glue->gl_dma_isintr)((sc)) 478#define NCRDMA_RESET(sc) (*(sc)->sc_glue->gl_dma_reset)((sc)) 479#define NCRDMA_INTR(sc) (*(sc)->sc_glue->gl_dma_intr)((sc)) 480#define NCRDMA_SETUP(sc, addr, len, datain, dmasize) \ 481 (*(sc)->sc_glue->gl_dma_setup)((sc), (addr), (len), (datain), (dmasize)) 482#define NCRDMA_GO(sc) (*(sc)->sc_glue->gl_dma_go)((sc)) 483#define NCRDMA_STOP(sc) (*(sc)->sc_glue->gl_dma_stop)((sc)) 484#define NCRDMA_ISACTIVE(sc) (*(sc)->sc_glue->gl_dma_isactive)((sc)) 485 486/* 487 * Macro to convert the chip register Clock Per Byte value to 488 * Synchronous Transfer Period. 489 */ 490#define ncr53c9x_cpb2stp(sc, cpb) \ 491 ((250 * (cpb)) / (sc)->sc_freq) 492 493extern devclass_t esp_devclass; 494 495int ncr53c9x_attach(struct ncr53c9x_softc *sc); 496int ncr53c9x_detach(struct ncr53c9x_softc *sc); 497void ncr53c9x_intr(void *arg); 498 499#endif /* _NCR53C9XVAR_H_ */ 500