1/*- 2 * Copyright (C) 1993, David Greenman. This software may be used, modified, 3 * copied, distributed, and sold, in both source and binary form provided 4 * that the above copyright and these terms are retained. Under no 5 * circumstances is the author responsible for the proper functioning 6 * of this software, nor does the author assume any responsibility 7 * for damages incurred with its use. 8 * 9 * $FreeBSD$ 10 */ 11/* 12 * National Semiconductor DS8390 NIC register definitions 13 * 14 * 15 * Modification history 16 * 17 * Revision 2.2 1993/11/29 16:33:39 davidg 18 * From Thomas Sandford <t.d.g.sandford@comp.brad.ac.uk> 19 * Add support for the 8013W board type 20 * 21 * Revision 2.1 1993/11/22 10:52:33 davidg 22 * patch to add support for SMC8216 (Elite-Ultra) boards 23 * from Glen H. Lowe 24 * 25 * Revision 2.0 93/09/29 00:37:15 davidg 26 * changed double buffering flag to multi buffering 27 * made changes/additions for 3c503 multi-buffering 28 * ...companion to Rev. 2.0 of 'ed' driver. 29 * 30 * Revision 1.1 93/06/23 03:01:07 davidg 31 * Initial revision 32 * 33 */ 34 35/* 36 * Page 0 register offsets 37 */ 38#define ED_P0_CR 0x00 /* Command Register */ 39 40#define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */ 41#define ED_P0_PSTART 0x01 /* Page Start register (write) */ 42 43#define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */ 44#define ED_P0_PSTOP 0x02 /* Page Stop register (write) */ 45 46#define ED_P0_BNRY 0x03 /* Boundary Pointer */ 47 48#define ED_P0_TSR 0x04 /* Transmit Status Register (read) */ 49#define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */ 50 51#define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */ 52#define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */ 53 54#define ED_P0_FIFO 0x06 /* FIFO register (read) */ 55#define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */ 56 57#define ED_P0_ISR 0x07 /* Interrupt Status Register */ 58 59#define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */ 60#define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */ 61 62#define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */ 63#define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */ 64 65#define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */ 66 67#define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */ 68 69#define ED_P0_RSR 0x0c /* Receive Status (read) */ 70#define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */ 71 72#define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */ 73#define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */ 74 75#define ED_P0_CNTR1 0x0e /* CRC error counter (read) */ 76#define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */ 77 78#define ED_P0_CNTR2 0x0f /* missed packet counter (read) */ 79#define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */ 80 81/* 82 * Page 1 register offsets 83 */ 84#define ED_P1_CR 0x00 /* Command Register */ 85#define ED_P1_PAR0 0x01 /* Physical Address Register 0 */ 86#define ED_P1_PAR1 0x02 /* Physical Address Register 1 */ 87#define ED_P1_PAR2 0x03 /* Physical Address Register 2 */ 88#define ED_P1_PAR3 0x04 /* Physical Address Register 3 */ 89#define ED_P1_PAR4 0x05 /* Physical Address Register 4 */ 90#define ED_P1_PAR5 0x06 /* Physical Address Register 5 */ 91#define ED_P1_PAR(i) (ED_P1_PAR0 + i) 92#define ED_P1_CURR 0x07 /* Current RX ring-buffer page */ 93#define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */ 94#define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */ 95#define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */ 96#define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */ 97#define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */ 98#define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */ 99#define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */ 100#define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */ 101#define ED_P1_MAR(i) (ED_P1_MAR0 + i) 102 103/* 104 * Page 2 register offsets 105 */ 106#define ED_P2_CR 0x00 /* Command Register */ 107#define ED_P2_PSTART 0x01 /* Page Start (read) */ 108#define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */ 109#define ED_P2_PSTOP 0x02 /* Page Stop (read) */ 110#define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */ 111#define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */ 112#define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */ 113#define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */ 114#define ED_P2_ACU 0x06 /* Address Counter Upper */ 115#define ED_P2_ACL 0x07 /* Address Counter Lower */ 116#define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */ 117#define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */ 118#define ED_P2_DCR 0x0e /* Data Configuration Register (read) */ 119#define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */ 120 121/* 122 * Command Register (CR) definitions 123 */ 124 125/* 126 * STP: SToP. Software reset command. Takes the controller offline. No 127 * packets will be received or transmitted. Any reception or 128 * transmission in progress will continue to completion before 129 * entering reset state. To exit this state, the STP bit must 130 * reset and the STA bit must be set. The software reset has 131 * executed only when indicated by the RST bit in the ISR being 132 * set. 133 */ 134#define ED_CR_STP 0x01 135 136/* 137 * STA: STArt. This bit is used to activate the NIC after either power-up, 138 * or when the NIC has been put in reset mode by software command 139 * or error. 140 */ 141#define ED_CR_STA 0x02 142 143/* 144 * TXP: Transmit Packet. This bit must be set to indicate transmission of 145 * a packet. TXP is internally reset either after the transmission is 146 * completed or aborted. This bit should be set only after the Transmit 147 * Byte Count and Transmit Page Start register have been programmed. 148 */ 149#define ED_CR_TXP 0x04 150 151/* 152 * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation 153 * of the remote DMA channel. RD2 can be set to abort any remote DMA 154 * command in progress. The Remote Byte Count registers should be cleared 155 * when a remote DMA has been aborted. The Remote Start Addresses are not 156 * restored to the starting address if the remote DMA is aborted. 157 * 158 * RD2 RD1 RD0 function 159 * 0 0 0 not allowed 160 * 0 0 1 remote read 161 * 0 1 0 remote write 162 * 0 1 1 send packet 163 * 1 X X abort 164 */ 165#define ED_CR_RD0 0x08 166#define ED_CR_RD1 0x10 167#define ED_CR_RD2 0x20 168 169/* 170 * PS0, PS1: Page Select. The two bits select which register set or 'page' to 171 * access. 172 * 173 * PS1 PS0 page 174 * 0 0 0 175 * 0 1 1 176 * 1 0 2 177 * 1 1 3 (some chips it is reserved) 178 */ 179#define ED_CR_PS0 0x40 180#define ED_CR_PS1 0x80 181/* bit encoded aliases */ 182#define ED_CR_PAGE_0 0x00 /* (for consistency) */ 183#define ED_CR_PAGE_1 0x40 184#define ED_CR_PAGE_2 0x80 185#define ED_CR_PAGE_3 0xc0 186 187/* 188 * Interrupt Status Register (ISR) definitions 189 */ 190 191/* 192 * PRX: Packet Received. Indicates packet received with no errors. 193 */ 194#define ED_ISR_PRX 0x01 195 196/* 197 * PTX: Packet Transmitted. Indicates packet transmitted with no errors. 198 */ 199#define ED_ISR_PTX 0x02 200 201/* 202 * RXE: Receive Error. Indicates that a packet was received with one or more 203 * the following errors: CRC error, frame alignment error, FIFO overrun, 204 * missed packet. 205 */ 206#define ED_ISR_RXE 0x04 207 208/* 209 * TXE: Transmission Error. Indicates that an attempt to transmit a packet 210 * resulted in one or more of the following errors: excessive 211 * collisions, FIFO underrun. 212 */ 213#define ED_ISR_TXE 0x08 214 215/* 216 * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network 217 * would exceed (has exceeded?) the boundary pointer, resulting in data 218 * that was previously received and not yet read from the buffer to be 219 * overwritten. 220 */ 221#define ED_ISR_OVW 0x10 222 223/* 224 * CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley 225 * Counters has been set. 226 */ 227#define ED_ISR_CNT 0x20 228 229/* 230 * RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed. 231 */ 232#define ED_ISR_RDC 0x40 233 234/* 235 * RST: Reset status. Set when the NIC enters the reset state and cleared when a 236 * Start Command is issued to the CR. This bit is also set when a receive 237 * ring-buffer overrun (OverWrite) occurs and is cleared when one or more 238 * packets have been removed from the ring. This is a read-only bit. 239 */ 240#define ED_ISR_RST 0x80 241 242/* 243 * Interrupt Mask Register (IMR) definitions 244 */ 245 246/* 247 * PRXE: Packet Received interrupt Enable. If set, a received packet will cause 248 * an interrupt. 249 */ 250#define ED_IMR_PRXE 0x01 251 252/* 253 * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when 254 * a packet transmission completes. 255 */ 256#define ED_IMR_PTXE 0x02 257 258/* 259 * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a 260 * packet is received with an error. 261 */ 262#define ED_IMR_RXEE 0x04 263 264/* 265 * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever 266 * a transmission results in an error. 267 */ 268#define ED_IMR_TXEE 0x08 269 270/* 271 * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever 272 * the receive ring-buffer is overrun. i.e. when the boundary pointer is exceeded. 273 */ 274#define ED_IMR_OVWE 0x10 275 276/* 277 * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever 278 * the MSB of one or more of the Network Statistics counters has been set. 279 */ 280#define ED_IMR_CNTE 0x20 281 282/* 283 * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated 284 * when a remote DMA transfer has completed. 285 */ 286#define ED_IMR_RDCE 0x40 287 288/* 289 * bit 7 is unused/reserved 290 */ 291 292/* 293 * Data Configuration Register (DCR) definitions 294 */ 295 296/* 297 * WTS: Word Transfer Select. WTS establishes byte or word transfers for 298 * both remote and local DMA transfers 299 */ 300#define ED_DCR_WTS 0x01 301 302/* 303 * BOS: Byte Order Select. BOS sets the byte order for the host. 304 * Should be 0 for 80x86, and 1 for 68000 series processors 305 */ 306#define ED_DCR_BOS 0x02 307 308/* 309 * LAS: Long Address Select. When LAS is 1, the contents of the remote 310 * DMA registers RSAR0 and RSAR1 are used to provide A16-A31 311 */ 312#define ED_DCR_LAS 0x04 313 314/* 315 * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2 316 * of the TCR must also be programmed for loopback operation. 317 * When 1, normal operation is selected. 318 */ 319#define ED_DCR_LS 0x08 320 321/* 322 * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer 323 * under program control. When 1, remote DMA is automatically initiated 324 * and the boundary pointer is automatically updated 325 */ 326#define ED_DCR_AR 0x10 327 328/* 329 * FT0, FT1: Fifo Threshold select. 330 * FT1 FT0 Word-width Byte-width 331 * 0 0 1 word 2 bytes 332 * 0 1 2 words 4 bytes 333 * 1 0 4 words 8 bytes 334 * 1 1 8 words 12 bytes 335 * 336 * During transmission, the FIFO threshold indicates the number of bytes 337 * or words that the FIFO has filled from the local DMA before BREQ is 338 * asserted. The transmission threshold is 16 bytes minus the receiver 339 * threshold. 340 */ 341#define ED_DCR_FT0 0x20 342#define ED_DCR_FT1 0x40 343 344/* 345 * bit 7 (0x80) is unused/reserved 346 */ 347 348/* 349 * Transmit Configuration Register (TCR) definitions 350 */ 351 352/* 353 * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC 354 * is not appended by the transmitter. 355 */ 356#define ED_TCR_CRC 0x01 357 358/* 359 * LB0, LB1: Loopback control. These two bits set the type of loopback that is 360 * to be performed. 361 * 362 * LB1 LB0 mode 363 * 0 0 0 - normal operation (DCR_LS = 0) 364 * 0 1 1 - internal loopback (DCR_LS = 0) 365 * 1 0 2 - external loopback (DCR_LS = 1) 366 * 1 1 3 - external loopback (DCR_LS = 0) 367 */ 368#define ED_TCR_LB0 0x02 369#define ED_TCR_LB1 0x04 370 371/* 372 * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows 373 * another station to disable the NIC's transmitter by transmitting to 374 * a multicast address hashing to bit 62. Reception of a multicast address 375 * hashing to bit 63 enables the transmitter. 376 */ 377#define ED_TCR_ATD 0x08 378 379/* 380 * OFST: Collision Offset enable. This bit when set modifies the backoff 381 * algorithm to allow prioritization of nodes. 382 */ 383#define ED_TCR_OFST 0x10 384 385/* 386 * bits 5, 6, and 7 are unused/reserved 387 */ 388 389/* 390 * Transmit Status Register (TSR) definitions 391 */ 392 393/* 394 * PTX: Packet Transmitted. Indicates successful transmission of packet. 395 */ 396#define ED_TSR_PTX 0x01 397 398/* 399 * bit 1 (0x02) is unused/reserved 400 */ 401 402/* 403 * COL: Transmit Collided. Indicates that the transmission collided at least 404 * once with another station on the network. 405 */ 406#define ED_TSR_COL 0x04 407 408/* 409 * ABT: Transmit aborted. Indicates that the transmission was aborted due to 410 * excessive collisions. 411 */ 412#define ED_TSR_ABT 0x08 413 414/* 415 * CRS: Carrier Sense Lost. Indicates that carrier was lost during the 416 * transmission of the packet. (Transmission is not aborted because 417 * of a loss of carrier) 418 */ 419#define ED_TSR_CRS 0x10 420 421/* 422 * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/ 423 * transmission memory before the FIFO emptied. Transmission of the 424 * packet was aborted. 425 */ 426#define ED_TSR_FU 0x20 427 428/* 429 * CDH: CD Heartbeat. Indicates that the collision detection circuitry 430 * isn't working correctly during a collision heartbeat test. 431 */ 432#define ED_TSR_CDH 0x40 433 434/* 435 * OWC: Out of Window Collision: Indicates that a collision occurred after 436 * a slot time (51.2us). The transmission is rescheduled just as in 437 * normal collisions. 438 */ 439#define ED_TSR_OWC 0x80 440 441/* 442 * Receiver Configuration Register (RCR) definitions 443 */ 444 445/* 446 * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1, 447 * packets with CRC and frame errors are not discarded. 448 */ 449#define ED_RCR_SEP 0x01 450 451/* 452 * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded. 453 * If set to 1, packets with less than 64 byte are not discarded. 454 */ 455#define ED_RCR_AR 0x02 456 457/* 458 * AB: Accept Broadcast. If set, packets sent to the broadcast address will be 459 * accepted. 460 */ 461#define ED_RCR_AB 0x04 462 463/* 464 * AM: Accept Multicast. If set, packets sent to a multicast address are checked 465 * for a match in the hashing array. If clear, multicast packets are ignored. 466 */ 467#define ED_RCR_AM 0x08 468 469/* 470 * PRO: Promiscuous Physical. If set, all packets with a physical addresses are 471 * accepted. If clear, a physical destination address must match this 472 * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM 473 * must also be set. In addition, the multicast hashing array must be set 474 * to all 1's so that all multicast addresses are accepted. 475 */ 476#define ED_RCR_PRO 0x10 477 478/* 479 * MON: Monitor Mode. If set, packets will be checked for good CRC and framing, 480 * but are not stored in the ring-buffer. If clear, packets are stored (normal 481 * operation). 482 */ 483#define ED_RCR_MON 0x20 484 485/* 486 * INTT: Interrupt Trigger Mode for AX88190. 487 */ 488#define ED_RCR_INTT 0x40 489 490/* 491 * bit 7 is unused/reserved. 492 */ 493 494/* 495 * Receiver Status Register (RSR) definitions 496 */ 497 498/* 499 * PRX: Packet Received without error. 500 */ 501#define ED_RSR_PRX 0x01 502 503/* 504 * CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame 505 * alignment errors. 506 */ 507#define ED_RSR_CRC 0x02 508 509/* 510 * FAE: Frame Alignment Error. Indicates that the incoming packet did not end on 511 * a byte boundary and the CRC did not match at the last byte boundary. 512 */ 513#define ED_RSR_FAE 0x04 514 515/* 516 * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA) 517 * causing it to overrun. Reception of the packet is aborted. 518 */ 519#define ED_RSR_FO 0x08 520 521/* 522 * MPA: Missed Packet. Indicates that the received packet couldn't be stored in 523 * the ring-buffer because of insufficient buffer space (exceeding the 524 * boundary pointer), or because the transfer to the ring-buffer was inhibited 525 * by RCR_MON - monitor mode. 526 */ 527#define ED_RSR_MPA 0x10 528 529/* 530 * PHY: Physical address. If 0, the packet received was sent to a physical address. 531 * If 1, the packet was accepted because of a multicast/broadcast address 532 * match. 533 */ 534#define ED_RSR_PHY 0x20 535 536/* 537 * DIS: Receiver Disabled. Set to indicate that the receiver has entered monitor 538 * mode. Cleared when the receiver exits monitor mode. 539 */ 540#define ED_RSR_DIS 0x40 541 542/* 543 * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs 544 * are active, and the transceiver has set the CD line as a result of the 545 * jabber. 546 */ 547#define ED_RSR_DFR 0x80 548 549/* 550 * receive ring descriptor 551 * 552 * The National Semiconductor DS8390 Network interface controller uses 553 * the following receive ring headers. The way this works is that the 554 * memory on the interface card is chopped up into 256 bytes blocks. 555 * A contiguous portion of those blocks are marked for receive packets 556 * by setting start and end block #'s in the NIC. For each packet that 557 * is put into the receive ring, one of these headers (4 bytes each) is 558 * tacked onto the front. The first byte is a copy of the receiver status 559 * register at the time the packet was received. 560 */ 561struct ed_ring { 562 u_char rsr; /* receiver status */ 563 u_char next_packet; /* pointer to next packet */ 564 u_short count; /* bytes in packet (length + 4) */ 565}; 566 567/* 568 * Common constants 569 */ 570#define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */ 571#define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */ 572 573/* 574 * Definitions for Western digital/SMC WD80x3 series ASIC 575 */ 576/* 577 * Memory Select Register (MSR) 578 */ 579#define ED_WD_MSR 0 580 581/* next three definitions for Toshiba */ 582#define ED_WD_MSR_POW 0x02 /* 0 = power save, 1 = normal (R/W) */ 583#define ED_WD_MSR_BSY 0x04 /* gate array busy (R) */ 584#define ED_WD_MSR_LEN 0x20 /* data bus width, 0 = 16 bits, 585 1 = 8 bits (R/W) */ 586#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */ 587#define ED_WD_MSR_MENB 0x40 /* Memory enable */ 588#define ED_WD_MSR_RST 0x80 /* Reset board */ 589 590/* 591 * Interface Configuration Register (ICR) 592 */ 593#define ED_WD_ICR 1 594 595#define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */ 596#define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */ 597#define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */ 598#define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */ 599#define ED_WD_ICR_RLA 0x10 /* recall LAN address */ 600#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */ 601#define ED_WD_ICR_RIO 0x40 /* recall i/o address */ 602#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */ 603#define ED_WD_ICR_MEM 0xe0 /* shared mem address A15-A13 (R/W) */ 604#define ED_WD_ICR_MSZ1 0x0f /* memory size, 0x08 = 64K, 0x04 = 32K, 605 0x02 = 16K, 0x01 = 8K */ 606 /* 64K can only be used if mem address 607 above 1Mb */ 608 /* IAR holds address A23-A16 (R/W) */ 609 610/* 611 * IO Address Register (IAR) 612 */ 613#define ED_WD_IAR 2 614 615/* 616 * EEROM Address Register 617 */ 618#define ED_WD_EAR 3 619 620/* 621 * Interrupt Request Register (IRR) 622 */ 623#define ED_WD_IRR 4 624 625#define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */ 626#define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */ 627#define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */ 628#define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */ 629#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */ 630 631/* 632 * The three bits of the encoded IRQ are decoded as follows: 633 * 634 * IR2 IR1 IR0 IRQ 635 * 0 0 0 2/9 636 * 0 0 1 3 637 * 0 1 0 5 638 * 0 1 1 7 639 * 1 0 0 10 640 * 1 0 1 11 641 * 1 1 0 15 642 * 1 1 1 4 643 */ 644#define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */ 645#define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */ 646#define ED_WD_IRR_IEN 0x80 /* Interrupt enable */ 647 648/* 649 * LA Address Register (LAAR) 650 */ 651#define ED_WD_LAAR 5 652 653#define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */ 654#define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */ 655#define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */ 656#define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */ 657 658/* i/o base offset to station address/card-ID PROM */ 659#define ED_WD_PROM 8 660 661/* 662 * 83C790 specific registers 663 */ 664/* 665 * Hardware Support Register (HWR) ('790) 666 */ 667#define ED_WD790_HWR 4 668 669#define WD_WD790_HWR_NUKE 0x10 /* hardware reset */ 670#define ED_WD790_HWR_LPRM 0x40 /* LAN PROM select */ 671#define ED_WD790_HWR_SWH 0x80 /* switch register set */ 672 673/* 674 * ICR790 Interrupt Control Register for the 83C790 675 */ 676#define ED_WD790_ICR 6 677 678#define ED_WD790_ICR_EIL 0x01 /* enable interrupts */ 679 680/* 681 * REV/IOPA Revision / I/O Pipe register for the 83C79X 682 */ 683#define ED_WD790_REV 7 684 685#define ED_WD790 0x20 686#define ED_WD795 0x40 687 688/* 689 * 79X RAM Address Register (RAR) 690 * Enabled with SWH bit=1 in HWR register 691 */ 692#define ED_WD790_RAR 0x0b 693 694#define ED_WD790_RAR_SZ8 0x00 /* 8k memory buffer */ 695#define ED_WD790_RAR_SZ16 0x10 /* 16k memory buffer */ 696#define ED_WD790_RAR_SZ32 0x20 /* 32k memory buffer */ 697#define ED_WD790_RAR_SZ64 0x30 /* 64k memory buffer */ 698 699/* 700 * General Control Register (GCR) 701 * Enabled with SWH bit=1 in HWR register 702 */ 703#define ED_WD790_GCR 0x0d 704 705#define ED_WD790_GCR_IR0 0x04 /* bit 0 of encoded IRQ */ 706#define ED_WD790_GCR_IR1 0x08 /* bit 1 of encoded IRQ */ 707#define ED_WD790_GCR_ZWSEN 0x20 /* zero wait state enable */ 708#define ED_WD790_GCR_IR2 0x40 /* bit 2 of encoded IRQ */ 709#define ED_WD790_GCR_LIT 0x01 /* Link Integrity Test Enable */ 710/* 711 * The three bits of the encoded IRQ are decoded as follows: 712 * 713 * IR2 IR1 IR0 IRQ 714 * 0 0 0 none 715 * 0 0 1 9 716 * 0 1 0 3 717 * 0 1 1 5 718 * 1 0 0 7 719 * 1 0 1 10 720 * 1 1 0 11 721 * 1 1 1 15 722 */ 723 724/* i/o base offset to CARD ID */ 725#define ED_WD_CARD_ID ED_WD_PROM+6 726 727/* Board type codes in card ID */ 728#define ED_TYPE_WD8003S 0x02 729#define ED_TYPE_WD8003E 0x03 730#define ED_TYPE_WD8013EBT 0x05 731#define ED_TYPE_TOSHIBA1 0x11 /* named PCETA1 */ 732#define ED_TYPE_TOSHIBA2 0x12 /* named PCETA2 */ 733#define ED_TYPE_TOSHIBA3 0x13 /* named PCETB */ 734#define ED_TYPE_TOSHIBA4 0x14 /* named PCETC */ 735#define ED_TYPE_WD8003W 0x24 736#define ED_TYPE_WD8003EB 0x25 737#define ED_TYPE_WD8013W 0x26 738#define ED_TYPE_WD8013EP 0x27 739#define ED_TYPE_WD8013WC 0x28 740#define ED_TYPE_WD8013EPC 0x29 741#define ED_TYPE_SMC8216T 0x2a 742#define ED_TYPE_SMC8216C 0x2b 743#define ED_TYPE_WD8013EBP 0x2c 744 745/* Bit definitions in card ID */ 746#define ED_WD_REV_MASK 0x1f /* Revision mask */ 747#define ED_WD_SOFTCONFIG 0x20 /* Soft config */ 748#define ED_WD_LARGERAM 0x40 /* Large RAM */ 749#define ED_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */ 750 751/* 752 * Checksum total. All 8 bytes in station address PROM will add up to this 753 */ 754#define ED_WD_ROM_CHECKSUM_TOTAL 0xFF 755#define ED_WD_ROM_CHECKSUM_TOTAL_TOSH_ETHER 0xA5 756 757#define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */ 758#define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */ 759#define ED_WD_IO_PORTS 32 /* # of i/o addresses used */ 760 761#define ED_WD_PAGE_OFFSET 0 /* page offset for NIC access to mem */ 762 763/* 764 * Definitions for 3Com 3c503 765 */ 766#define ED_3COM_NIC_OFFSET 0 767#define ED_3COM_ASIC_OFFSET 0x400 /* offset to nic i/o regs */ 768 769/* 770 * XXX - The I/O address range is fragmented in the 3c503; this is the 771 * number of regs at iobase. 772 */ 773#define ED_3COM_IO_PORTS 16 /* # of i/o addresses used */ 774 775/* tx memory starts in second bank on 8bit cards */ 776#define ED_3COM_TX_PAGE_OFFSET_8BIT 0x20 777 778/* tx memory starts in first bank on 16bit cards */ 779#define ED_3COM_TX_PAGE_OFFSET_16BIT 0x0 780 781/* ...and rx memory starts in second bank */ 782#define ED_3COM_RX_PAGE_OFFSET_16BIT 0x20 783 784 785/* 786 * Page Start Register. Must match PSTART in NIC 787 */ 788#define ED_3COM_PSTR 0 789 790/* 791 * Page Stop Register. Must match PSTOP in NIC 792 */ 793#define ED_3COM_PSPR 1 794 795/* 796 * Drq Timer Register. Determines number of bytes to be transferred during 797 * a DMA burst. 798 */ 799#define ED_3COM_DQTR 2 800 801/* 802 * Base Configuration Register. Read-only register which contains the 803 * board-configured I/O base address of the adapter. Bit encoded. 804 */ 805#define ED_3COM_BCFR 3 806 807#define ED_3COM_BCFR_2E0 0x01 808#define ED_3COM_BCFR_2A0 0x02 809#define ED_3COM_BCFR_280 0x04 810#define ED_3COM_BCFR_250 0x08 811#define ED_3COM_BCFR_350 0x10 812#define ED_3COM_BCFR_330 0x20 813#define ED_3COM_BCFR_310 0x40 814#define ED_3COM_BCFR_300 0x80 815 816/* 817 * EPROM Configuration Register. Read-only register which contains the 818 * board-configured memory base address. Bit encoded. 819 */ 820#define ED_3COM_PCFR 4 821 822#define ED_3COM_PCFR_C8000 0x10 823#define ED_3COM_PCFR_CC000 0x20 824#define ED_3COM_PCFR_D8000 0x40 825#define ED_3COM_PCFR_DC000 0x80 826 827/* 828 * GA Configuration Register. Gate-Array Configuration Register. 829 */ 830#define ED_3COM_GACFR 5 831 832/* 833 * mbs2 mbs1 mbs0 start address 834 * 0 0 0 0x0000 835 * 0 0 1 0x2000 836 * 0 1 0 0x4000 837 * 0 1 1 0x6000 838 * 839 * Note that with adapters with only 8K, the setting for 0x2000 must 840 * always be used. 841 */ 842#define ED_3COM_GACFR_MBS0 0x01 843#define ED_3COM_GACFR_MBS1 0x02 844#define ED_3COM_GACFR_MBS2 0x04 845 846#define ED_3COM_GACFR_RSEL 0x08 /* enable shared memory */ 847#define ED_3COM_GACFR_TEST 0x10 /* for GA testing */ 848#define ED_3COM_GACFR_OWS 0x20 /* select 0WS access to GA */ 849#define ED_3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */ 850#define ED_3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */ 851 852/* 853 * Control Register. Miscellaneous control functions. 854 */ 855#define ED_3COM_CR 6 856 857#define ED_3COM_CR_RST 0x01 /* Reset GA and NIC */ 858#define ED_3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */ 859#define ED_3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */ 860#define ED_3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */ 861#define ED_3COM_CR_SHARE 0x10 /* select interrupt sharing option */ 862#define ED_3COM_CR_DBSEL 0x20 /* Double buffer select */ 863#define ED_3COM_CR_DDIR 0x40 /* DMA direction select */ 864#define ED_3COM_CR_START 0x80 /* Start DMA controller */ 865 866/* 867 * Status Register. Miscellaneous status information. 868 */ 869#define ED_3COM_STREG 7 870 871#define ED_3COM_STREG_REV 0x07 /* GA revision */ 872#define ED_3COM_STREG_DIP 0x08 /* DMA in progress */ 873#define ED_3COM_STREG_DTC 0x10 /* DMA terminal count */ 874#define ED_3COM_STREG_OFLW 0x20 /* Overflow */ 875#define ED_3COM_STREG_UFLW 0x40 /* Underflow */ 876#define ED_3COM_STREG_DPRDY 0x80 /* Data port ready */ 877 878/* 879 * Interrupt/DMA Configuration Register 880 */ 881#define ED_3COM_IDCFR 8 882 883#define ED_3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */ 884#define ED_3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */ 885#define ED_3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */ 886#define ED_3COM_IDCFR_UNUSED 0x08 /* not used */ 887#define ED_3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */ 888#define ED_3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */ 889#define ED_3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */ 890#define ED_3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */ 891 892/* 893 * DMA Address Register MSB 894 */ 895#define ED_3COM_DAMSB 9 896 897/* 898 * DMA Address Register LSB 899 */ 900#define ED_3COM_DALSB 0x0a 901 902/* 903 * Vector Pointer Register 2 904 */ 905#define ED_3COM_VPTR2 0x0b 906 907/* 908 * Vector Pointer Register 1 909 */ 910#define ED_3COM_VPTR1 0x0c 911 912/* 913 * Vector Pointer Register 0 914 */ 915#define ED_3COM_VPTR0 0x0d 916 917/* 918 * Register File Access MSB 919 */ 920#define ED_3COM_RFMSB 0x0e 921 922/* 923 * Register File Access LSB 924 */ 925#define ED_3COM_RFLSB 0x0f 926 927/* 928 * Definitions for Novell NE1000/2000 boards 929 */ 930 931/* 932 * Board type codes 933 */ 934#define ED_TYPE_NE1000 0x01 935#define ED_TYPE_NE2000 0x02 936 937/* 938 * Register offsets/total 939 */ 940#define ED_NOVELL_NIC_OFFSET 0x00 941#define ED_NOVELL_ASIC_OFFSET 0x10 942#define ED_NOVELL_IO_PORTS 32 943 944/* 945 * Remote DMA data register; for reading or writing to the NIC mem 946 * via programmed I/O (offset from ASIC base) 947 */ 948#define ED_NOVELL_DATA 0x00 949 950/* 951 * Reset register; reading from this register causes a board reset 952 */ 953#define ED_NOVELL_RESET 0x0f 954 955/* 956 * Definitions for PCCARD 957 */ 958#define ED_PC_PAGE_OFFSET 0x40 /* page offset for NIC access to mem */ 959#define ED_PC_IO_PORTS 32 960#define ED_PC_ASIC_OFFSET 0x10 961#define ED_PC_RESET 0x0f /* Reset(offset from ASIC base) */ 962#define ED_PC_MISC 0x08 /* Misc (offset from ASIC base) */ 963 964/* 965 * if_ze.h constants 966 */ 967 968#define ZE_PAGE_OFFSET 0x40 /* mem buffer starts at 0x4000 */ 969 970#define ZE_DATA_IO 0x10 971#define ZE_MISC 0x18 972#define ZE_RESET 0x1F 973 974/* 975 * Definitions for HP PC LAN Adapter Plus; based on the CRYNWR packet 976 * driver for the card. 977 */ 978 979#define ED_HPP_ASIC_OFFSET 0x00 /* Offset to ASIC registers */ 980#define ED_HPP_NIC_OFFSET 0x10 /* Offset to 8390 registers */ 981 982#define ED_HPP_ID 0x00 /* ID register, always 0x4850 */ 983#define ED_HPP_PAGING 0x02 /* Page select register */ 984#define ED_HPP_OPTION 0x04 /* Bitmask of supported options */ 985#define ED_HPP_PAGE_0 0x08 /* Page 0 */ 986#define ED_HPP_PAGE_2 0x0A /* Page 2 */ 987#define ED_HPP_PAGE_4 0x0C /* Page 4 */ 988#define ED_HPP_PAGE_6 0x0E /* Page 6 */ 989 990/* PERF PAGE */ 991#define ED_HPP_OUT_ADDR ED_HPP_PAGE_0 /* I/O output location */ 992#define ED_HPP_IN_ADDR ED_HPP_PAGE_2 /* I/O input location */ 993#define ED_HPP_DATAPORT ED_HPP_PAGE_4 /* I/O data transfer */ 994/* MAC PAGE */ 995#define ED_HPP_MAC_ADDR 0x08 /* Offset of MAC address in MAC page */ 996 997#define ED_HPP_IO_PORTS 32 /* Number of IO ports */ 998 999#define ED_HPP_TX_PAGE_OFFSET 0x00 /* first page of TX buffer */ 1000#define ED_HPP_RX_PAGE_START 0x06 /* start at page 6 */ 1001#define ED_HPP_RX_PAGE_STOP 0x80 /* end at page 128 */ 1002 1003/* 1004 * Register pages supported. 1005 */ 1006 1007#define ED_HPP_PAGE_PERF 0 /* Normal operation */ 1008#define ED_HPP_PAGE_MAC 1 /* The ethernet address and checksum */ 1009#define ED_HPP_PAGE_HW 2 /* Hardware parameters in EEPROM */ 1010#define ED_HPP_PAGE_LAN 4 /* Transciever selection etc */ 1011#define ED_HPP_PAGE_ID 6 /* ID */ 1012 1013/* 1014 * Options supported. 1015 */ 1016 1017#define ED_HPP_OPTION_NIC_RESET 0x0001 /* active low */ 1018#define ED_HPP_OPTION_CHIP_RESET 0x0002 /* active low */ 1019#define ED_HPP_OPTION_ENABLE_IRQ 0x0004 1020#define ED_HPP_OPTION_FAKE_INTR 0x0008 1021#define ED_HPP_OPTION_BOOT_ROM_ENB 0x0010 1022#define ED_HPP_OPTION_IO_ENB 0x0020 1023#define ED_HPP_OPTION_MEM_ENABLE 0x0040 1024#define ED_HPP_OPTION_ZERO_WAIT 0x0080 1025#define ED_HPP_OPTION_MEM_DISABLE 0x1000 1026 1027/* 1028 * Page ID configuration. 1029 */ 1030 1031#define ED_HPP_ID_REVISION_MASK 0x0300 /* revision id */ 1032#define ED_HPP_ID_SOFT_MODEL_MASK 0xFC00 /* soft model number */ 1033#define ED_HPP_ID_16_BIT_ACCESS 0x0010 /* if set use 16 bit accesses */ 1034#define ED_HPP_ID_TWISTED_PAIR 0x0040 1035 1036/* 1037 * Hardware configuration. 1038 */ 1039 1040#define ED_HPP_HW_MEM_MAP 0x09 /* low mem map location in HW page */ 1041#define ED_HPP_HW_ID 0x0C /* revision number, capabilities */ 1042#define ED_HPP_HW_IRQ 0x0D /* IRQ channel register in HW page */ 1043#define ED_HPP_HW_WRAP 0x0E /* mem wrap page for rcv */ 1044 1045/* 1046 * Lan configuration 1047 */ 1048 1049#define ED_HPP_LAN_AUI 0x01 /* Use AUI */ 1050#define ED_HPP_LAN_TL 0x40 /* Don't use AUI */ 1051 1052/* 1053 * Card types. 1054 */ 1055 1056#define ED_TYPE_HP_PCLANPLUS 0x00 1057 1058/* 1059 * Definitions for Allied-Telesis SIC 1060 */ 1061#define ED_SIC_NIC_OFFSET 0 1062#define ED_SIC_ASIC_OFFSET 0x10 /* offset to nic i/o regs */ 1063 1064#define ED_SIC_IO_PORTS 17 /* # of i/o addresses used */ 1065 1066/* 1067 * Chip types. 1068 */ 1069#define ED_CHIP_TYPE_AX88190 0 1070#define ED_CHIP_TYPE_AX88790 1 1071#define ED_CHIP_TYPE_DL10019 2 1072#define ED_CHIP_TYPE_DL10022 3 1073#define ED_CHIP_TYPE_DP8390 4 1074#define ED_CHIP_TYPE_NS83903 5 1075#define ED_CHIP_TYPE_NS83926 6 1076#define ED_CHIP_TYPE_RTL8019 7 1077#define ED_CHIP_TYPE_RTL8029 8 1078#define ED_CHIP_TYPE_TC3299 9 1079#define ED_CHIP_TYPE_TC5299J 10 1080#define ED_CHIP_TYPE_W89C926 11 1081#define ED_CHIP_TYPE_WD790 12 1082