if_igb.h revision 293854
1/****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/if_igb.h 293854 2016-01-13 21:47:27Z marius $*/ 34 35#ifndef _IF_IGB_H_ 36#define _IF_IGB_H_ 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#ifndef IGB_LEGACY_TX 41#include <sys/buf_ring.h> 42#endif 43#include <sys/bus.h> 44#include <sys/endian.h> 45#include <sys/kernel.h> 46#include <sys/kthread.h> 47#include <sys/malloc.h> 48#include <sys/mbuf.h> 49#include <sys/module.h> 50#include <sys/rman.h> 51#include <sys/socket.h> 52#include <sys/sockio.h> 53#include <sys/sysctl.h> 54#include <sys/taskqueue.h> 55#include <sys/eventhandler.h> 56#include <sys/pcpu.h> 57#include <sys/smp.h> 58#include <machine/smp.h> 59#include <machine/bus.h> 60#include <machine/resource.h> 61 62#include <net/bpf.h> 63#include <net/ethernet.h> 64#include <net/if.h> 65#include <net/if_var.h> 66#include <net/if_arp.h> 67#include <net/if_dl.h> 68#include <net/if_media.h> 69#ifdef RSS 70#include <net/rss_config.h> 71#include <netinet/in_rss.h> 72#endif 73 74#include <net/if_types.h> 75#include <net/if_vlan_var.h> 76 77#include <netinet/in_systm.h> 78#include <netinet/in.h> 79#include <netinet/if_ether.h> 80#include <netinet/ip.h> 81#include <netinet/ip6.h> 82#include <netinet/tcp.h> 83#include <netinet/tcp_lro.h> 84#include <netinet/udp.h> 85 86#include <machine/in_cksum.h> 87#include <dev/led/led.h> 88#include <dev/pci/pcivar.h> 89#include <dev/pci/pcireg.h> 90 91#include "e1000_api.h" 92#include "e1000_82575.h" 93 94/* Tunables */ 95/* 96 * IGB_TXD: Maximum number of Transmit Descriptors 97 * 98 * This value is the number of transmit descriptors allocated by the driver. 99 * Increasing this value allows the driver to queue more transmits. Each 100 * descriptor is 16 bytes. 101 * Since TDLEN should be multiple of 128bytes, the number of transmit 102 * desscriptors should meet the following condition. 103 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 104 */ 105#define IGB_MIN_TXD 256 106#define IGB_DEFAULT_TXD 1024 107#define IGB_MAX_TXD 4096 108 109/* 110 * IGB_RXD: Maximum number of Receive Descriptors 111 * 112 * This value is the number of receive descriptors allocated by the driver. 113 * Increasing this value allows the driver to buffer more incoming packets. 114 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 115 * descriptor. The maximum MTU size is 16110. 116 * Since TDLEN should be multiple of 128bytes, the number of transmit 117 * desscriptors should meet the following condition. 118 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 119 */ 120#define IGB_MIN_RXD 256 121#define IGB_DEFAULT_RXD 1024 122#define IGB_MAX_RXD 4096 123 124/* 125 * IGB_TIDV - Transmit Interrupt Delay Value 126 * Valid Range: 0-65535 (0=off) 127 * Default Value: 64 128 * This value delays the generation of transmit interrupts in units of 129 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 130 * efficiency if properly tuned for specific network traffic. If the 131 * system is reporting dropped transmits, this value may be set too high 132 * causing the driver to run out of available transmit descriptors. 133 */ 134#define IGB_TIDV 64 135 136/* 137 * IGB_TADV - Transmit Absolute Interrupt Delay Value 138 * Valid Range: 0-65535 (0=off) 139 * Default Value: 64 140 * This value, in units of 1.024 microseconds, limits the delay in which a 141 * transmit interrupt is generated. Useful only if IGB_TIDV is non-zero, 142 * this value ensures that an interrupt is generated after the initial 143 * packet is sent on the wire within the set amount of time. Proper tuning, 144 * along with IGB_TIDV, may improve traffic throughput in specific 145 * network conditions. 146 */ 147#define IGB_TADV 64 148 149/* 150 * IGB_RDTR - Receive Interrupt Delay Timer (Packet Timer) 151 * Valid Range: 0-65535 (0=off) 152 * Default Value: 0 153 * This value delays the generation of receive interrupts in units of 1.024 154 * microseconds. Receive interrupt reduction can improve CPU efficiency if 155 * properly tuned for specific network traffic. Increasing this value adds 156 * extra latency to frame reception and can end up decreasing the throughput 157 * of TCP traffic. If the system is reporting dropped receives, this value 158 * may be set too high, causing the driver to run out of available receive 159 * descriptors. 160 * 161 * CAUTION: When setting IGB_RDTR to a value other than 0, adapters 162 * may hang (stop transmitting) under certain network conditions. 163 * If this occurs a WATCHDOG message is logged in the system 164 * event log. In addition, the controller is automatically reset, 165 * restoring the network connection. To eliminate the potential 166 * for the hang ensure that IGB_RDTR is set to 0. 167 */ 168#define IGB_RDTR 0 169 170/* 171 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 172 * Valid Range: 0-65535 (0=off) 173 * Default Value: 64 174 * This value, in units of 1.024 microseconds, limits the delay in which a 175 * receive interrupt is generated. Useful only if IGB_RDTR is non-zero, 176 * this value ensures that an interrupt is generated after the initial 177 * packet is received within the set amount of time. Proper tuning, 178 * along with IGB_RDTR, may improve traffic throughput in specific network 179 * conditions. 180 */ 181#define IGB_RADV 64 182 183/* 184 * This parameter controls the duration of transmit watchdog timer. 185 */ 186#define IGB_WATCHDOG (10 * hz) 187 188/* 189 * This parameter controls when the driver calls the routine to reclaim 190 * transmit descriptors. Cleaning earlier seems a win. 191 */ 192#define IGB_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 2) 193 194/* 195 * This parameter controls whether or not autonegotation is enabled. 196 * 0 - Disable autonegotiation 197 * 1 - Enable autonegotiation 198 */ 199#define DO_AUTO_NEG 1 200 201/* 202 * This parameter control whether or not the driver will wait for 203 * autonegotiation to complete. 204 * 1 - Wait for autonegotiation to complete 205 * 0 - Don't wait for autonegotiation to complete 206 */ 207#define WAIT_FOR_AUTO_NEG_DEFAULT 0 208 209/* Tunables -- End */ 210 211#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 212 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 213 ADVERTISE_1000_FULL) 214 215#define AUTO_ALL_MODES 0 216 217/* PHY master/slave setting */ 218#define IGB_MASTER_SLAVE e1000_ms_hw_default 219 220/* Support AutoMediaDetect for Marvell M88 PHY in i354 */ 221#define IGB_MEDIA_RESET (1 << 0) 222 223/* 224 * Micellaneous constants 225 */ 226#define IGB_INTEL_VENDOR_ID 0x8086 227 228#define IGB_JUMBO_PBA 0x00000028 229#define IGB_DEFAULT_PBA 0x00000030 230#define IGB_SMARTSPEED_DOWNSHIFT 3 231#define IGB_SMARTSPEED_MAX 15 232#define IGB_MAX_LOOP 10 233 234#define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : \ 235 ((hw->mac.type <= e1000_82576) ? 16 : 8)) 236#define IGB_RX_HTHRESH 8 237#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ 238 adapter->msix_mem) ? 1 : 4) 239 240#define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) 241#define IGB_TX_HTHRESH 1 242#define IGB_TX_WTHRESH ((hw->mac.type != e1000_82575 && \ 243 adapter->msix_mem) ? 1 : 16) 244 245#define MAX_NUM_MULTICAST_ADDRESSES 128 246#define PCI_ANY_ID (~0U) 247#define ETHER_ALIGN 2 248#define IGB_TX_BUFFER_SIZE ((uint32_t) 1514) 249#define IGB_FC_PAUSE_TIME 0x0680 250#define IGB_EEPROM_APME 0x400; 251/* Queue minimum free for use */ 252#define IGB_QUEUE_THRESHOLD (adapter->num_tx_desc / 8) 253 254/* 255 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 256 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 257 * also optimize cache line size effect. H/W supports up to cache line size 128. 258 */ 259#define IGB_DBA_ALIGN 128 260 261#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 262 263/* PCI Config defines */ 264#define IGB_MSIX_BAR 3 265 266/* Defines for printing debug information */ 267#define DEBUG_INIT 0 268#define DEBUG_IOCTL 0 269#define DEBUG_HW 0 270 271#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 272#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 273#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 274#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 275#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 276#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 277#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 278#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 279#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 280 281#define IGB_MAX_SCATTER 64 282#define IGB_VFTA_SIZE 128 283#define IGB_BR_SIZE 4096 /* ring buf size */ 284#define IGB_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 285#define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */ 286#define IGB_TXPBSIZE 20408 287#define IGB_HDR_BUF 128 288#define IGB_PKTTYPE_MASK 0x0000FFF0 289#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ 290#define ETH_ZLEN 60 291#define ETH_ADDR_LEN 6 292 293/* Offload bits in mbuf flag */ 294#if __FreeBSD_version >= 800000 295#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 296#else 297#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 298#endif 299 300/* Define the starting Interrupt rate per Queue */ 301#define IGB_INTS_PER_SEC 8000 302#define IGB_DEFAULT_ITR ((1000000/IGB_INTS_PER_SEC) << 2) 303 304#define IGB_LINK_ITR 2000 305#define I210_LINK_DELAY 1000 306 307/* Precision Time Sync (IEEE 1588) defines */ 308#define ETHERTYPE_IEEE1588 0x88F7 309#define PICOSECS_PER_TICK 20833 310#define TSYNC_PORT 319 /* UDP port for the protocol */ 311 312/* 313 * Bus dma allocation structure used by 314 * e1000_dma_malloc and e1000_dma_free. 315 */ 316struct igb_dma_alloc { 317 bus_addr_t dma_paddr; 318 caddr_t dma_vaddr; 319 bus_dma_tag_t dma_tag; 320 bus_dmamap_t dma_map; 321 bus_dma_segment_t dma_seg; 322 int dma_nseg; 323}; 324 325 326/* 327** Driver queue struct: this is the interrupt container 328** for the associated tx and rx ring. 329*/ 330struct igb_queue { 331 struct adapter *adapter; 332 u32 msix; /* This queue's MSIX vector */ 333 u32 eims; /* This queue's EIMS bit */ 334 u32 eitr_setting; 335 struct resource *res; 336 void *tag; 337 struct tx_ring *txr; 338 struct rx_ring *rxr; 339 struct task que_task; 340 struct taskqueue *tq; 341 u64 irqs; 342}; 343 344/* 345 * The transmit ring, one per queue 346 */ 347struct tx_ring { 348 struct adapter *adapter; 349 struct mtx tx_mtx; 350 u32 me; 351 int watchdog_time; 352 union e1000_adv_tx_desc *tx_base; 353 struct igb_tx_buf *tx_buffers; 354 struct igb_dma_alloc txdma; 355 volatile u16 tx_avail; 356 u16 next_avail_desc; 357 u16 next_to_clean; 358 u16 num_desc; 359 enum { 360 IGB_QUEUE_IDLE = 1, 361 IGB_QUEUE_WORKING = 2, 362 IGB_QUEUE_HUNG = 4, 363 IGB_QUEUE_DEPLETED = 8, 364 } queue_status; 365 u32 txd_cmd; 366 bus_dma_tag_t txtag; 367 char mtx_name[16]; 368#ifndef IGB_LEGACY_TX 369 struct buf_ring *br; 370 struct task txq_task; 371#endif 372 u32 bytes; /* used for AIM */ 373 u32 packets; 374 /* Soft Stats */ 375 unsigned long tso_tx; 376 unsigned long no_tx_map_avail; 377 unsigned long no_tx_dma_setup; 378 u64 no_desc_avail; 379 u64 total_packets; 380}; 381 382/* 383 * Receive ring: one per queue 384 */ 385struct rx_ring { 386 struct adapter *adapter; 387 u32 me; 388 struct igb_dma_alloc rxdma; 389 union e1000_adv_rx_desc *rx_base; 390 struct lro_ctrl lro; 391 bool lro_enabled; 392 bool hdr_split; 393 struct mtx rx_mtx; 394 char mtx_name[16]; 395 u32 next_to_refresh; 396 u32 next_to_check; 397 struct igb_rx_buf *rx_buffers; 398 bus_dma_tag_t htag; /* dma tag for rx head */ 399 bus_dma_tag_t ptag; /* dma tag for rx packet */ 400 /* 401 * First/last mbuf pointers, for 402 * collecting multisegment RX packets. 403 */ 404 struct mbuf *fmp; 405 struct mbuf *lmp; 406 407 u32 bytes; 408 u32 packets; 409 int rdt; 410 int rdh; 411 412 /* Soft stats */ 413 u64 rx_split_packets; 414 u64 rx_discarded; 415 u64 rx_packets; 416 u64 rx_bytes; 417}; 418 419struct adapter { 420 struct ifnet *ifp; 421 struct e1000_hw hw; 422 423 struct e1000_osdep osdep; 424 struct device *dev; 425 struct cdev *led_dev; 426 427 struct resource *pci_mem; 428 struct resource *msix_mem; 429 int memrid; 430 431 /* 432 * Interrupt resources: this set is 433 * either used for legacy, or for Link 434 * when doing MSIX 435 */ 436 void *tag; 437 struct resource *res; 438 439 struct ifmedia media; 440 struct callout timer; 441 int msix; 442 int if_flags; 443 int pause_frames; 444 445 struct mtx core_mtx; 446 447 eventhandler_tag vlan_attach; 448 eventhandler_tag vlan_detach; 449 450 u16 num_vlans; 451 u16 num_queues; 452 453 /* 454 ** Shadow VFTA table, this is needed because 455 ** the real vlan filter table gets cleared during 456 ** a soft reset and the driver needs to be able 457 ** to repopulate it. 458 */ 459 u32 shadow_vfta[IGB_VFTA_SIZE]; 460 461 /* Info about the interface */ 462 u32 optics; 463 u32 fc; /* local flow ctrl setting */ 464 int advertise; /* link speeds */ 465 bool link_active; 466 u16 max_frame_size; 467 u16 num_segs; 468 u16 link_speed; 469 bool link_up; 470 u32 linkvec; 471 u16 link_duplex; 472 u32 dmac; 473 int link_mask; 474 475 /* Flags */ 476 u32 flags; 477 478 /* Mbuf cluster size */ 479 u32 rx_mbuf_sz; 480 481 /* Support for pluggable optics */ 482 bool sfp_probe; 483 struct task link_task; /* Link tasklet */ 484 struct task mod_task; /* SFP tasklet */ 485 struct task msf_task; /* Multispeed Fiber */ 486 struct taskqueue *tq; 487 488 /* 489 ** Queues: 490 ** This is the irq holder, it has 491 ** and RX/TX pair or rings associated 492 ** with it. 493 */ 494 struct igb_queue *queues; 495 496 /* 497 * Transmit rings: 498 * Allocated at run time, an array of rings. 499 */ 500 struct tx_ring *tx_rings; 501 u32 num_tx_desc; 502 503 /* 504 * Receive rings: 505 * Allocated at run time, an array of rings. 506 */ 507 struct rx_ring *rx_rings; 508 u64 que_mask; 509 u32 num_rx_desc; 510 511 /* Multicast array memory */ 512 u8 *mta; 513 514 /* Misc stats maintained by the driver */ 515 unsigned long device_control; 516 unsigned long dropped_pkts; 517 unsigned long eint_mask; 518 unsigned long int_mask; 519 unsigned long link_irq; 520 unsigned long mbuf_defrag_failed; 521 unsigned long no_tx_dma_setup; 522 unsigned long packet_buf_alloc_rx; 523 unsigned long packet_buf_alloc_tx; 524 unsigned long rx_control; 525 unsigned long rx_overruns; 526 unsigned long watchdog_events; 527 528 /* Used in pf and vf */ 529 void *stats; 530 531 int enable_aim; 532 int has_manage; 533 int wol; 534 int rx_process_limit; 535 int tx_process_limit; 536 u16 vf_ifp; /* a VF interface */ 537 bool in_detach; /* Used only in igb_ioctl */ 538 539}; 540 541/* ****************************************************************************** 542 * vendor_info_array 543 * 544 * This array contains the list of Subvendor/Subdevice IDs on which the driver 545 * should load. 546 * 547 * ******************************************************************************/ 548typedef struct _igb_vendor_info_t { 549 unsigned int vendor_id; 550 unsigned int device_id; 551 unsigned int subvendor_id; 552 unsigned int subdevice_id; 553 unsigned int index; 554} igb_vendor_info_t; 555 556struct igb_tx_buf { 557 union e1000_adv_tx_desc *eop; 558 struct mbuf *m_head; 559 bus_dmamap_t map; 560}; 561 562struct igb_rx_buf { 563 struct mbuf *m_head; 564 struct mbuf *m_pack; 565 bus_dmamap_t hmap; /* bus_dma map for header */ 566 bus_dmamap_t pmap; /* bus_dma map for packet */ 567}; 568 569/* 570** Find the number of unrefreshed RX descriptors 571*/ 572static inline u16 573igb_rx_unrefreshed(struct rx_ring *rxr) 574{ 575 struct adapter *adapter = rxr->adapter; 576 577 if (rxr->next_to_check > rxr->next_to_refresh) 578 return (rxr->next_to_check - rxr->next_to_refresh - 1); 579 else 580 return ((adapter->num_rx_desc + rxr->next_to_check) - 581 rxr->next_to_refresh - 1); 582} 583 584#define IGB_CORE_LOCK_INIT(_sc, _name) \ 585 mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF) 586#define IGB_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 587#define IGB_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 588#define IGB_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 589#define IGB_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 590 591#define IGB_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 592#define IGB_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 593#define IGB_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 594#define IGB_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 595#define IGB_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 596 597#define IGB_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 598#define IGB_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 599#define IGB_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 600#define IGB_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rx_mtx, MA_OWNED) 601 602#define UPDATE_VF_REG(reg, last, cur) \ 603{ \ 604 u32 new = E1000_READ_REG(hw, reg); \ 605 if (new < last) \ 606 cur += 0x100000000LL; \ 607 last = new; \ 608 cur &= 0xFFFFFFFF00000000LL; \ 609 cur |= new; \ 610} 611 612#if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504 613static __inline int 614drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 615{ 616#ifdef ALTQ 617 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 618 return (1); 619#endif 620 return (!buf_ring_empty(br)); 621} 622#endif 623 624#endif /* _IF_IGB_H_ */ 625 626 627