1/****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD$*/ 34 35#ifndef _IF_IGB_H_ 36#define _IF_IGB_H_ 37 38#ifdef ALTQ 39#define IGB_LEGACY_TX 40#endif 41 42#include <sys/param.h> 43#include <sys/systm.h> 44#ifndef IGB_LEGACY_TX 45#include <sys/buf_ring.h> 46#endif 47#include <sys/bus.h> 48#include <sys/endian.h> 49#include <sys/kernel.h> 50#include <sys/kthread.h> 51#include <sys/malloc.h> 52#include <sys/mbuf.h> 53#include <sys/module.h> 54#include <sys/rman.h> 55#include <sys/socket.h> 56#include <sys/sockio.h> 57#include <sys/sysctl.h> 58#include <sys/taskqueue.h> 59#include <sys/eventhandler.h> 60#include <sys/pcpu.h> 61#include <sys/smp.h> 62#include <machine/smp.h> 63#include <machine/bus.h> 64#include <machine/resource.h> 65 66#include <net/bpf.h> 67#include <net/ethernet.h> 68#include <net/if.h> 69#include <net/if_var.h> 70#include <net/if_arp.h> 71#include <net/if_dl.h> 72#include <net/if_media.h> 73#ifdef RSS 74#include <net/rss_config.h> 75#include <netinet/in_rss.h> 76#endif 77 78#include <net/if_types.h> 79#include <net/if_vlan_var.h> 80 81#include <netinet/in_systm.h> 82#include <netinet/in.h> 83#include <netinet/if_ether.h> 84#include <netinet/ip.h> 85#include <netinet/ip6.h> 86#include <netinet/tcp.h> 87#include <netinet/tcp_lro.h> 88#include <netinet/udp.h> 89 90#include <machine/in_cksum.h> 91#include <dev/led/led.h> 92#include <dev/pci/pcivar.h> 93#include <dev/pci/pcireg.h> 94 95#include "e1000_api.h" 96#include "e1000_82575.h" 97 98/* Tunables */ 99/* 100 * IGB_TXD: Maximum number of Transmit Descriptors 101 * 102 * This value is the number of transmit descriptors allocated by the driver. 103 * Increasing this value allows the driver to queue more transmits. Each 104 * descriptor is 16 bytes. 105 * Since TDLEN should be multiple of 128bytes, the number of transmit 106 * desscriptors should meet the following condition. 107 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 108 */ 109#define IGB_MIN_TXD 256 110#define IGB_DEFAULT_TXD 1024 111#define IGB_MAX_TXD 4096 112 113/* 114 * IGB_RXD: Maximum number of Receive Descriptors 115 * 116 * This value is the number of receive descriptors allocated by the driver. 117 * Increasing this value allows the driver to buffer more incoming packets. 118 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 119 * descriptor. The maximum MTU size is 16110. 120 * Since TDLEN should be multiple of 128bytes, the number of transmit 121 * desscriptors should meet the following condition. 122 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 123 */ 124#define IGB_MIN_RXD 256 125#define IGB_DEFAULT_RXD 1024 126#define IGB_MAX_RXD 4096 127 128/* 129 * IGB_TIDV - Transmit Interrupt Delay Value 130 * Valid Range: 0-65535 (0=off) 131 * Default Value: 64 132 * This value delays the generation of transmit interrupts in units of 133 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 134 * efficiency if properly tuned for specific network traffic. If the 135 * system is reporting dropped transmits, this value may be set too high 136 * causing the driver to run out of available transmit descriptors. 137 */ 138#define IGB_TIDV 64 139 140/* 141 * IGB_TADV - Transmit Absolute Interrupt Delay Value 142 * Valid Range: 0-65535 (0=off) 143 * Default Value: 64 144 * This value, in units of 1.024 microseconds, limits the delay in which a 145 * transmit interrupt is generated. Useful only if IGB_TIDV is non-zero, 146 * this value ensures that an interrupt is generated after the initial 147 * packet is sent on the wire within the set amount of time. Proper tuning, 148 * along with IGB_TIDV, may improve traffic throughput in specific 149 * network conditions. 150 */ 151#define IGB_TADV 64 152 153/* 154 * IGB_RDTR - Receive Interrupt Delay Timer (Packet Timer) 155 * Valid Range: 0-65535 (0=off) 156 * Default Value: 0 157 * This value delays the generation of receive interrupts in units of 1.024 158 * microseconds. Receive interrupt reduction can improve CPU efficiency if 159 * properly tuned for specific network traffic. Increasing this value adds 160 * extra latency to frame reception and can end up decreasing the throughput 161 * of TCP traffic. If the system is reporting dropped receives, this value 162 * may be set too high, causing the driver to run out of available receive 163 * descriptors. 164 * 165 * CAUTION: When setting IGB_RDTR to a value other than 0, adapters 166 * may hang (stop transmitting) under certain network conditions. 167 * If this occurs a WATCHDOG message is logged in the system 168 * event log. In addition, the controller is automatically reset, 169 * restoring the network connection. To eliminate the potential 170 * for the hang ensure that IGB_RDTR is set to 0. 171 */ 172#define IGB_RDTR 0 173 174/* 175 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 176 * Valid Range: 0-65535 (0=off) 177 * Default Value: 64 178 * This value, in units of 1.024 microseconds, limits the delay in which a 179 * receive interrupt is generated. Useful only if IGB_RDTR is non-zero, 180 * this value ensures that an interrupt is generated after the initial 181 * packet is received within the set amount of time. Proper tuning, 182 * along with IGB_RDTR, may improve traffic throughput in specific network 183 * conditions. 184 */ 185#define IGB_RADV 64 186 187/* 188 * This parameter controls the duration of transmit watchdog timer. 189 */ 190#define IGB_WATCHDOG (10 * hz) 191 192/* 193 * This parameter controls when the driver calls the routine to reclaim 194 * transmit descriptors. Cleaning earlier seems a win. 195 */ 196#define IGB_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 2) 197 198/* 199 * This parameter controls whether or not autonegotation is enabled. 200 * 0 - Disable autonegotiation 201 * 1 - Enable autonegotiation 202 */ 203#define DO_AUTO_NEG 1 204 205/* 206 * This parameter control whether or not the driver will wait for 207 * autonegotiation to complete. 208 * 1 - Wait for autonegotiation to complete 209 * 0 - Don't wait for autonegotiation to complete 210 */ 211#define WAIT_FOR_AUTO_NEG_DEFAULT 0 212 213/* Tunables -- End */ 214 215#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 216 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 217 ADVERTISE_1000_FULL) 218 219#define AUTO_ALL_MODES 0 220 221/* PHY master/slave setting */ 222#define IGB_MASTER_SLAVE e1000_ms_hw_default 223 224/* Support AutoMediaDetect for Marvell M88 PHY in i354 */ 225#define IGB_MEDIA_RESET (1 << 0) 226 227/* 228 * Micellaneous constants 229 */ 230#define IGB_INTEL_VENDOR_ID 0x8086 231 232#define IGB_JUMBO_PBA 0x00000028 233#define IGB_DEFAULT_PBA 0x00000030 234#define IGB_SMARTSPEED_DOWNSHIFT 3 235#define IGB_SMARTSPEED_MAX 15 236#define IGB_MAX_LOOP 10 237 238#define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : \ 239 ((hw->mac.type <= e1000_82576) ? 16 : 8)) 240#define IGB_RX_HTHRESH 8 241#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ 242 adapter->msix_mem) ? 1 : 4) 243 244#define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) 245#define IGB_TX_HTHRESH 1 246#define IGB_TX_WTHRESH ((hw->mac.type != e1000_82575 && \ 247 adapter->msix_mem) ? 1 : 16) 248 249#define MAX_NUM_MULTICAST_ADDRESSES 128 250#define PCI_ANY_ID (~0U) 251#define ETHER_ALIGN 2 252#define IGB_TX_BUFFER_SIZE ((uint32_t) 1514) 253#define IGB_FC_PAUSE_TIME 0x0680 254#define IGB_EEPROM_APME 0x400; 255/* Queue minimum free for use */ 256#define IGB_QUEUE_THRESHOLD (adapter->num_tx_desc / 8) 257 258/* 259 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 260 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 261 * also optimize cache line size effect. H/W supports up to cache line size 128. 262 */ 263#define IGB_DBA_ALIGN 128 264 265#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 266 267/* PCI Config defines */ 268#define IGB_MSIX_BAR 3 269 270/* Defines for printing debug information */ 271#define DEBUG_INIT 0 272#define DEBUG_IOCTL 0 273#define DEBUG_HW 0 274 275#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 276#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 277#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 278#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 279#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 280#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 281#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 282#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 283#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 284 285#define IGB_MAX_SCATTER 40 286#define IGB_VFTA_SIZE 128 287#define IGB_BR_SIZE 4096 /* ring buf size */ 288#define IGB_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 289#define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */ 290#define IGB_TXPBSIZE 20408 291#define IGB_HDR_BUF 128 292#define IGB_PKTTYPE_MASK 0x0000FFF0 293#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ 294#define ETH_ZLEN 60 295#define ETH_ADDR_LEN 6 296 297/* Offload bits in mbuf flag */ 298#if __FreeBSD_version >= 1000000 299#define CSUM_OFFLOAD_IPV4 (CSUM_IP|CSUM_IP_TCP|CSUM_IP_UDP|CSUM_IP_SCTP) 300#define CSUM_OFFLOAD_IPV6 (CSUM_IP6_TCP|CSUM_IP6_UDP|CSUM_IP6_SCTP) 301#define CSUM_OFFLOAD (CSUM_OFFLOAD_IPV4|CSUM_OFFLOAD_IPV6) 302#elif __FreeBSD_version >= 800000 303#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 304#else 305#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 306#endif 307 308/* Define the starting Interrupt rate per Queue */ 309#define IGB_INTS_PER_SEC 8000 310#define IGB_DEFAULT_ITR ((1000000/IGB_INTS_PER_SEC) << 2) 311 312#define IGB_LINK_ITR 2000 313#define I210_LINK_DELAY 1000 314 315/* Precision Time Sync (IEEE 1588) defines */ 316#define ETHERTYPE_IEEE1588 0x88F7 317#define PICOSECS_PER_TICK 20833 318#define TSYNC_PORT 319 /* UDP port for the protocol */ 319 320/* 321 * Bus dma allocation structure used by 322 * e1000_dma_malloc and e1000_dma_free. 323 */ 324struct igb_dma_alloc { 325 bus_addr_t dma_paddr; 326 caddr_t dma_vaddr; 327 bus_dma_tag_t dma_tag; 328 bus_dmamap_t dma_map; 329 bus_dma_segment_t dma_seg; 330 int dma_nseg; 331}; 332 333 334/* 335** Driver queue struct: this is the interrupt container 336** for the associated tx and rx ring. 337*/ 338struct igb_queue { 339 struct adapter *adapter; 340 u32 msix; /* This queue's MSIX vector */ 341 u32 eims; /* This queue's EIMS bit */ 342 u32 eitr_setting; 343 struct resource *res; 344 void *tag; 345 struct tx_ring *txr; 346 struct rx_ring *rxr; 347 struct task que_task; 348 struct taskqueue *tq; 349 u64 irqs; 350}; 351 352/* 353 * The transmit ring, one per queue 354 */ 355struct tx_ring { 356 struct adapter *adapter; 357 struct mtx tx_mtx; 358 u32 me; 359 int watchdog_time; 360 union e1000_adv_tx_desc *tx_base; 361 struct igb_tx_buf *tx_buffers; 362 struct igb_dma_alloc txdma; 363 volatile u16 tx_avail; 364 u16 next_avail_desc; 365 u16 next_to_clean; 366 u16 num_desc; 367 enum { 368 IGB_QUEUE_IDLE = 1, 369 IGB_QUEUE_WORKING = 2, 370 IGB_QUEUE_HUNG = 4, 371 IGB_QUEUE_DEPLETED = 8, 372 } queue_status; 373 u32 txd_cmd; 374 bus_dma_tag_t txtag; 375 char mtx_name[16]; 376#ifndef IGB_LEGACY_TX 377 struct buf_ring *br; 378 struct task txq_task; 379#endif 380 u32 bytes; /* used for AIM */ 381 u32 packets; 382 /* Soft Stats */ 383 unsigned long tso_tx; 384 unsigned long no_tx_map_avail; 385 unsigned long no_tx_dma_setup; 386 u64 no_desc_avail; 387 u64 total_packets; 388}; 389 390/* 391 * Receive ring: one per queue 392 */ 393struct rx_ring { 394 struct adapter *adapter; 395 u32 me; 396 struct igb_dma_alloc rxdma; 397 union e1000_adv_rx_desc *rx_base; 398 struct lro_ctrl lro; 399 bool lro_enabled; 400 bool hdr_split; 401 struct mtx rx_mtx; 402 char mtx_name[16]; 403 u32 next_to_refresh; 404 u32 next_to_check; 405 struct igb_rx_buf *rx_buffers; 406 bus_dma_tag_t htag; /* dma tag for rx head */ 407 bus_dma_tag_t ptag; /* dma tag for rx packet */ 408 /* 409 * First/last mbuf pointers, for 410 * collecting multisegment RX packets. 411 */ 412 struct mbuf *fmp; 413 struct mbuf *lmp; 414 415 u32 bytes; 416 u32 packets; 417 int rdt; 418 int rdh; 419 420 /* Soft stats */ 421 u64 rx_split_packets; 422 u64 rx_discarded; 423 u64 rx_packets; 424 u64 rx_bytes; 425}; 426 427struct adapter { 428 struct ifnet *ifp; 429 struct e1000_hw hw; 430 431 struct e1000_osdep osdep; 432 struct device *dev; 433 struct cdev *led_dev; 434 435 struct resource *pci_mem; 436 struct resource *msix_mem; 437 int memrid; 438 439 /* 440 * Interrupt resources: this set is 441 * either used for legacy, or for Link 442 * when doing MSIX 443 */ 444 void *tag; 445 struct resource *res; 446 447 struct ifmedia media; 448 struct callout timer; 449 int msix; 450 int if_flags; 451 int pause_frames; 452 453 struct mtx core_mtx; 454 455 eventhandler_tag vlan_attach; 456 eventhandler_tag vlan_detach; 457 458 u16 num_vlans; 459 u16 num_queues; 460 461 /* 462 ** Shadow VFTA table, this is needed because 463 ** the real vlan filter table gets cleared during 464 ** a soft reset and the driver needs to be able 465 ** to repopulate it. 466 */ 467 u32 shadow_vfta[IGB_VFTA_SIZE]; 468 469 /* Info about the interface */ 470 u32 optics; 471 u32 fc; /* local flow ctrl setting */ 472 int advertise; /* link speeds */ 473 bool link_active; 474 u16 max_frame_size; 475 u16 num_segs; 476 u16 link_speed; 477 bool link_up; 478 u32 linkvec; 479 u16 link_duplex; 480 u32 dmac; 481 int link_mask; 482 483 /* Flags */ 484 u32 flags; 485 486 /* Mbuf cluster size */ 487 u32 rx_mbuf_sz; 488 489 /* Support for pluggable optics */ 490 bool sfp_probe; 491 struct task link_task; /* Link tasklet */ 492 struct task mod_task; /* SFP tasklet */ 493 struct task msf_task; /* Multispeed Fiber */ 494 struct taskqueue *tq; 495 496 /* 497 ** Queues: 498 ** This is the irq holder, it has 499 ** and RX/TX pair or rings associated 500 ** with it. 501 */ 502 struct igb_queue *queues; 503 504 /* 505 * Transmit rings: 506 * Allocated at run time, an array of rings. 507 */ 508 struct tx_ring *tx_rings; 509 u32 num_tx_desc; 510 511 /* 512 * Receive rings: 513 * Allocated at run time, an array of rings. 514 */ 515 struct rx_ring *rx_rings; 516 u64 que_mask; 517 u32 num_rx_desc; 518 519 /* Multicast array memory */ 520 u8 *mta; 521 522 /* Misc stats maintained by the driver */ 523 unsigned long device_control; 524 unsigned long dropped_pkts; 525 unsigned long eint_mask; 526 unsigned long int_mask; 527 unsigned long link_irq; 528 unsigned long mbuf_defrag_failed; 529 unsigned long no_tx_dma_setup; 530 unsigned long packet_buf_alloc_rx; 531 unsigned long packet_buf_alloc_tx; 532 unsigned long rx_control; 533 unsigned long rx_overruns; 534 unsigned long watchdog_events; 535 536 /* Used in pf and vf */ 537 void *stats; 538 539 int enable_aim; 540 int has_manage; 541 int wol; 542 int rx_process_limit; 543 int tx_process_limit; 544 u16 vf_ifp; /* a VF interface */ 545 bool in_detach; /* Used only in igb_ioctl */ 546 547}; 548 549/* ****************************************************************************** 550 * vendor_info_array 551 * 552 * This array contains the list of Subvendor/Subdevice IDs on which the driver 553 * should load. 554 * 555 * ******************************************************************************/ 556typedef struct _igb_vendor_info_t { 557 unsigned int vendor_id; 558 unsigned int device_id; 559 unsigned int subvendor_id; 560 unsigned int subdevice_id; 561 unsigned int index; 562} igb_vendor_info_t; 563 564struct igb_tx_buf { 565 union e1000_adv_tx_desc *eop; 566 struct mbuf *m_head; 567 bus_dmamap_t map; 568}; 569 570struct igb_rx_buf { 571 struct mbuf *m_head; 572 struct mbuf *m_pack; 573 bus_dmamap_t hmap; /* bus_dma map for header */ 574 bus_dmamap_t pmap; /* bus_dma map for packet */ 575}; 576 577/* 578** Find the number of unrefreshed RX descriptors 579*/ 580static inline u16 581igb_rx_unrefreshed(struct rx_ring *rxr) 582{ 583 struct adapter *adapter = rxr->adapter; 584 585 if (rxr->next_to_check > rxr->next_to_refresh) 586 return (rxr->next_to_check - rxr->next_to_refresh - 1); 587 else 588 return ((adapter->num_rx_desc + rxr->next_to_check) - 589 rxr->next_to_refresh - 1); 590} 591 592#define IGB_CORE_LOCK_INIT(_sc, _name) \ 593 mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF) 594#define IGB_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 595#define IGB_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 596#define IGB_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 597#define IGB_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 598 599#define IGB_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 600#define IGB_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 601#define IGB_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 602#define IGB_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 603#define IGB_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 604 605#define IGB_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 606#define IGB_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 607#define IGB_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 608#define IGB_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rx_mtx, MA_OWNED) 609 610#define UPDATE_VF_REG(reg, last, cur) \ 611{ \ 612 u32 new = E1000_READ_REG(hw, reg); \ 613 if (new < last) \ 614 cur += 0x100000000LL; \ 615 last = new; \ 616 cur &= 0xFFFFFFFF00000000LL; \ 617 cur |= new; \ 618} 619 620#if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504 621static __inline int 622drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 623{ 624#ifdef ALTQ 625 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 626 return (1); 627#endif 628 return (!buf_ring_empty(br)); 629} 630#endif 631 632#endif /* _IF_IGB_H_ */ 633 634 635