if_igb.h revision 248908
1/****************************************************************************** 2 3 Copyright (c) 2001-2011, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/if_igb.h 248908 2013-03-29 18:46:13Z jfv $*/ 34 35#ifndef _IGB_H_DEFINED_ 36#define _IGB_H_DEFINED_ 37 38/* Tunables */ 39 40/* 41 * IGB_TXD: Maximum number of Transmit Descriptors 42 * 43 * This value is the number of transmit descriptors allocated by the driver. 44 * Increasing this value allows the driver to queue more transmits. Each 45 * descriptor is 16 bytes. 46 * Since TDLEN should be multiple of 128bytes, the number of transmit 47 * desscriptors should meet the following condition. 48 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 49 */ 50#define IGB_MIN_TXD 256 51#define IGB_DEFAULT_TXD 1024 52#define IGB_MAX_TXD 4096 53 54/* 55 * IGB_RXD: Maximum number of Receive Descriptors 56 * 57 * This value is the number of receive descriptors allocated by the driver. 58 * Increasing this value allows the driver to buffer more incoming packets. 59 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 60 * descriptor. The maximum MTU size is 16110. 61 * Since TDLEN should be multiple of 128bytes, the number of transmit 62 * desscriptors should meet the following condition. 63 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 64 */ 65#define IGB_MIN_RXD 256 66#define IGB_DEFAULT_RXD 1024 67#define IGB_MAX_RXD 4096 68 69/* 70 * IGB_TIDV - Transmit Interrupt Delay Value 71 * Valid Range: 0-65535 (0=off) 72 * Default Value: 64 73 * This value delays the generation of transmit interrupts in units of 74 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 75 * efficiency if properly tuned for specific network traffic. If the 76 * system is reporting dropped transmits, this value may be set too high 77 * causing the driver to run out of available transmit descriptors. 78 */ 79#define IGB_TIDV 64 80 81/* 82 * IGB_TADV - Transmit Absolute Interrupt Delay Value 83 * Valid Range: 0-65535 (0=off) 84 * Default Value: 64 85 * This value, in units of 1.024 microseconds, limits the delay in which a 86 * transmit interrupt is generated. Useful only if IGB_TIDV is non-zero, 87 * this value ensures that an interrupt is generated after the initial 88 * packet is sent on the wire within the set amount of time. Proper tuning, 89 * along with IGB_TIDV, may improve traffic throughput in specific 90 * network conditions. 91 */ 92#define IGB_TADV 64 93 94/* 95 * IGB_RDTR - Receive Interrupt Delay Timer (Packet Timer) 96 * Valid Range: 0-65535 (0=off) 97 * Default Value: 0 98 * This value delays the generation of receive interrupts in units of 1.024 99 * microseconds. Receive interrupt reduction can improve CPU efficiency if 100 * properly tuned for specific network traffic. Increasing this value adds 101 * extra latency to frame reception and can end up decreasing the throughput 102 * of TCP traffic. If the system is reporting dropped receives, this value 103 * may be set too high, causing the driver to run out of available receive 104 * descriptors. 105 * 106 * CAUTION: When setting IGB_RDTR to a value other than 0, adapters 107 * may hang (stop transmitting) under certain network conditions. 108 * If this occurs a WATCHDOG message is logged in the system 109 * event log. In addition, the controller is automatically reset, 110 * restoring the network connection. To eliminate the potential 111 * for the hang ensure that IGB_RDTR is set to 0. 112 */ 113#define IGB_RDTR 0 114 115/* 116 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 117 * Valid Range: 0-65535 (0=off) 118 * Default Value: 64 119 * This value, in units of 1.024 microseconds, limits the delay in which a 120 * receive interrupt is generated. Useful only if IGB_RDTR is non-zero, 121 * this value ensures that an interrupt is generated after the initial 122 * packet is received within the set amount of time. Proper tuning, 123 * along with IGB_RDTR, may improve traffic throughput in specific network 124 * conditions. 125 */ 126#define IGB_RADV 64 127 128/* 129 * This parameter controls the duration of transmit watchdog timer. 130 */ 131#define IGB_WATCHDOG (10 * hz) 132 133/* 134 * This parameter controls when the driver calls the routine to reclaim 135 * transmit descriptors. Cleaning earlier seems a win. 136 */ 137#define IGB_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 2) 138 139/* 140 * This parameter controls whether or not autonegotation is enabled. 141 * 0 - Disable autonegotiation 142 * 1 - Enable autonegotiation 143 */ 144#define DO_AUTO_NEG 1 145 146/* 147 * This parameter control whether or not the driver will wait for 148 * autonegotiation to complete. 149 * 1 - Wait for autonegotiation to complete 150 * 0 - Don't wait for autonegotiation to complete 151 */ 152#define WAIT_FOR_AUTO_NEG_DEFAULT 0 153 154/* Tunables -- End */ 155 156#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 157 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 158 ADVERTISE_1000_FULL) 159 160#define AUTO_ALL_MODES 0 161 162/* PHY master/slave setting */ 163#define IGB_MASTER_SLAVE e1000_ms_hw_default 164 165/* 166 * Micellaneous constants 167 */ 168#define IGB_VENDOR_ID 0x8086 169 170#define IGB_JUMBO_PBA 0x00000028 171#define IGB_DEFAULT_PBA 0x00000030 172#define IGB_SMARTSPEED_DOWNSHIFT 3 173#define IGB_SMARTSPEED_MAX 15 174#define IGB_MAX_LOOP 10 175 176#define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8) 177#define IGB_RX_HTHRESH 8 178#define IGB_RX_WTHRESH 1 179 180#define IGB_TX_PTHRESH 8 181#define IGB_TX_HTHRESH 1 182#define IGB_TX_WTHRESH ((hw->mac.type != e1000_82575 && \ 183 adapter->msix_mem) ? 1 : 16) 184 185#define MAX_NUM_MULTICAST_ADDRESSES 128 186#define PCI_ANY_ID (~0U) 187#define ETHER_ALIGN 2 188#define IGB_TX_BUFFER_SIZE ((uint32_t) 1514) 189#define IGB_FC_PAUSE_TIME 0x0680 190#define IGB_EEPROM_APME 0x400; 191/* Queue minimum free for use */ 192#define IGB_QUEUE_THRESHOLD (adapter->num_tx_desc / 8) 193/* Queue bit defines */ 194#define IGB_QUEUE_IDLE 1 195#define IGB_QUEUE_WORKING 2 196#define IGB_QUEUE_HUNG 4 197#define IGB_QUEUE_DEPLETED 8 198 199/* 200 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 201 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 202 * also optimize cache line size effect. H/W supports up to cache line size 128. 203 */ 204#define IGB_DBA_ALIGN 128 205 206#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 207 208/* PCI Config defines */ 209#define IGB_MSIX_BAR 3 210 211/* Defines for printing debug information */ 212#define DEBUG_INIT 0 213#define DEBUG_IOCTL 0 214#define DEBUG_HW 0 215 216#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 217#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 218#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 219#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 220#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 221#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 222#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 223#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 224#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 225 226#define IGB_MAX_SCATTER 64 227#define IGB_VFTA_SIZE 128 228#define IGB_BR_SIZE 4096 /* ring buf size */ 229#define IGB_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 230#define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */ 231#define IGB_HDR_BUF 128 232#define IGB_PKTTYPE_MASK 0x0000FFF0 233#define ETH_ZLEN 60 234#define ETH_ADDR_LEN 6 235 236/* Offload bits in mbuf flag */ 237#if __FreeBSD_version >= 800000 238#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 239#else 240#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 241#endif 242 243/* Define the starting Interrupt rate per Queue */ 244#define IGB_INTS_PER_SEC 8000 245#define IGB_DEFAULT_ITR ((1000000/IGB_INTS_PER_SEC) << 2) 246 247#define IGB_LINK_ITR 2000 248 249/* Precision Time Sync (IEEE 1588) defines */ 250#define ETHERTYPE_IEEE1588 0x88F7 251#define PICOSECS_PER_TICK 20833 252#define TSYNC_PORT 319 /* UDP port for the protocol */ 253 254/* 255 * Bus dma allocation structure used by 256 * e1000_dma_malloc and e1000_dma_free. 257 */ 258struct igb_dma_alloc { 259 bus_addr_t dma_paddr; 260 caddr_t dma_vaddr; 261 bus_dma_tag_t dma_tag; 262 bus_dmamap_t dma_map; 263 bus_dma_segment_t dma_seg; 264 int dma_nseg; 265}; 266 267 268/* 269** Driver queue struct: this is the interrupt container 270** for the associated tx and rx ring. 271*/ 272struct igb_queue { 273 struct adapter *adapter; 274 u32 msix; /* This queue's MSIX vector */ 275 u32 eims; /* This queue's EIMS bit */ 276 u32 eitr_setting; 277 struct resource *res; 278 void *tag; 279 struct tx_ring *txr; 280 struct rx_ring *rxr; 281 struct task que_task; 282 struct taskqueue *tq; 283 u64 irqs; 284}; 285 286/* 287 * Transmit ring: one per queue 288 */ 289struct tx_ring { 290 struct adapter *adapter; 291 u32 me; 292 struct mtx tx_mtx; 293 char mtx_name[16]; 294 struct igb_dma_alloc txdma; 295 struct e1000_tx_desc *tx_base; 296 u32 next_avail_desc; 297 u32 next_to_clean; 298 volatile u16 tx_avail; 299 struct igb_tx_buffer *tx_buffers; 300#ifndef IGB_LEGACY_TX 301 struct buf_ring *br; 302 struct task txq_task; 303#endif 304 bus_dma_tag_t txtag; 305 306 u32 bytes; 307 u32 packets; 308 309 int queue_status; 310 int watchdog_time; 311 int tdt; 312 int tdh; 313 u64 no_desc_avail; 314 u64 tx_packets; 315}; 316 317/* 318 * Receive ring: one per queue 319 */ 320struct rx_ring { 321 struct adapter *adapter; 322 u32 me; 323 struct igb_dma_alloc rxdma; 324 union e1000_adv_rx_desc *rx_base; 325 struct lro_ctrl lro; 326 bool lro_enabled; 327 bool hdr_split; 328 bool discard; 329 struct mtx rx_mtx; 330 char mtx_name[16]; 331 u32 next_to_refresh; 332 u32 next_to_check; 333 struct igb_rx_buf *rx_buffers; 334 bus_dma_tag_t htag; /* dma tag for rx head */ 335 bus_dma_tag_t ptag; /* dma tag for rx packet */ 336 /* 337 * First/last mbuf pointers, for 338 * collecting multisegment RX packets. 339 */ 340 struct mbuf *fmp; 341 struct mbuf *lmp; 342 343 u32 bytes; 344 u32 packets; 345 int rdt; 346 int rdh; 347 348 /* Soft stats */ 349 u64 rx_split_packets; 350 u64 rx_discarded; 351 u64 rx_packets; 352 u64 rx_bytes; 353}; 354 355struct adapter { 356 struct ifnet *ifp; 357 struct e1000_hw hw; 358 359 struct e1000_osdep osdep; 360 struct device *dev; 361 struct cdev *led_dev; 362 363 struct resource *pci_mem; 364 struct resource *msix_mem; 365 struct resource *res; 366 void *tag; 367 u32 que_mask; 368 369 int linkvec; 370 int link_mask; 371 struct task link_task; 372 int link_irq; 373 374 struct ifmedia media; 375 struct callout timer; 376 int msix; /* total vectors allocated */ 377 int if_flags; 378 int max_frame_size; 379 int min_frame_size; 380 int pause_frames; 381 struct mtx core_mtx; 382 int igb_insert_vlan_header; 383 u16 num_queues; 384 u16 vf_ifp; /* a VF interface */ 385 386 eventhandler_tag vlan_attach; 387 eventhandler_tag vlan_detach; 388 u32 num_vlans; 389 390 /* Management and WOL features */ 391 int wol; 392 int has_manage; 393 394 /* 395 ** Shadow VFTA table, this is needed because 396 ** the real vlan filter table gets cleared during 397 ** a soft reset and the driver needs to be able 398 ** to repopulate it. 399 */ 400 u32 shadow_vfta[IGB_VFTA_SIZE]; 401 402 /* Info about the interface */ 403 u16 link_active; 404 u16 fc; 405 u16 link_speed; 406 u16 link_duplex; 407 u32 smartspeed; 408 u32 dmac; 409 int enable_aim; 410 411 /* Interface queues */ 412 struct igb_queue *queues; 413 414 /* 415 * Transmit rings 416 */ 417 struct tx_ring *tx_rings; 418 u16 num_tx_desc; 419 420 /* Multicast array pointer */ 421 u8 *mta; 422 423 /* 424 * Receive rings 425 */ 426 struct rx_ring *rx_rings; 427 bool rx_hdr_split; 428 u16 num_rx_desc; 429 int rx_process_limit; 430 u32 rx_mbuf_sz; 431 u32 rx_mask; 432 433 /* Misc stats maintained by the driver */ 434 unsigned long dropped_pkts; 435 unsigned long mbuf_defrag_failed; 436 unsigned long mbuf_header_failed; 437 unsigned long mbuf_packet_failed; 438 unsigned long no_tx_map_avail; 439 unsigned long no_tx_dma_setup; 440 unsigned long watchdog_events; 441 unsigned long rx_overruns; 442 unsigned long device_control; 443 unsigned long rx_control; 444 unsigned long int_mask; 445 unsigned long eint_mask; 446 unsigned long packet_buf_alloc_rx; 447 unsigned long packet_buf_alloc_tx; 448 449 boolean_t in_detach; 450 451#ifdef IGB_IEEE1588 452 /* IEEE 1588 precision time support */ 453 struct cyclecounter cycles; 454 struct nettimer clock; 455 struct nettime_compare compare; 456 struct hwtstamp_ctrl hwtstamp; 457#endif 458 459 void *stats; 460}; 461 462/* ****************************************************************************** 463 * vendor_info_array 464 * 465 * This array contains the list of Subvendor/Subdevice IDs on which the driver 466 * should load. 467 * 468 * ******************************************************************************/ 469typedef struct _igb_vendor_info_t { 470 unsigned int vendor_id; 471 unsigned int device_id; 472 unsigned int subvendor_id; 473 unsigned int subdevice_id; 474 unsigned int index; 475} igb_vendor_info_t; 476 477 478struct igb_tx_buffer { 479 int next_eop; /* Index of the desc to watch */ 480 struct mbuf *m_head; 481 bus_dmamap_t map; /* bus_dma map for packet */ 482}; 483 484struct igb_rx_buf { 485 struct mbuf *m_head; 486 struct mbuf *m_pack; 487 bus_dmamap_t hmap; /* bus_dma map for header */ 488 bus_dmamap_t pmap; /* bus_dma map for packet */ 489}; 490 491/* 492** Find the number of unrefreshed RX descriptors 493*/ 494static inline u16 495igb_rx_unrefreshed(struct rx_ring *rxr) 496{ 497 struct adapter *adapter = rxr->adapter; 498 499 if (rxr->next_to_check > rxr->next_to_refresh) 500 return (rxr->next_to_check - rxr->next_to_refresh - 1); 501 else 502 return ((adapter->num_rx_desc + rxr->next_to_check) - 503 rxr->next_to_refresh - 1); 504} 505 506#define IGB_CORE_LOCK_INIT(_sc, _name) \ 507 mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF) 508#define IGB_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 509#define IGB_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 510#define IGB_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 511#define IGB_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 512 513#define IGB_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 514#define IGB_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 515#define IGB_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 516#define IGB_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 517#define IGB_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 518 519#define IGB_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 520#define IGB_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 521#define IGB_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 522#define IGB_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rx_mtx, MA_OWNED) 523 524#define UPDATE_VF_REG(reg, last, cur) \ 525{ \ 526 u32 new = E1000_READ_REG(hw, reg); \ 527 if (new < last) \ 528 cur += 0x100000000LL; \ 529 last = new; \ 530 cur &= 0xFFFFFFFF00000000LL; \ 531 cur |= new; \ 532} 533 534#if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504 535static __inline int 536drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 537{ 538#ifdef ALTQ 539 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 540 return (1); 541#endif 542 return (!buf_ring_empty(br)); 543} 544#endif 545 546#endif /* _IGB_H_DEFINED_ */ 547 548 549