if_igb.h revision 220375
1/****************************************************************************** 2 3 Copyright (c) 2001-2011, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/if_igb.h 220375 2011-04-05 21:55:43Z jfv $*/ 34 35#ifndef _IGB_H_DEFINED_ 36#define _IGB_H_DEFINED_ 37 38/* Tunables */ 39 40/* 41 * IGB_TXD: Maximum number of Transmit Descriptors 42 * 43 * This value is the number of transmit descriptors allocated by the driver. 44 * Increasing this value allows the driver to queue more transmits. Each 45 * descriptor is 16 bytes. 46 * Since TDLEN should be multiple of 128bytes, the number of transmit 47 * desscriptors should meet the following condition. 48 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 49 */ 50#define IGB_MIN_TXD 256 51#define IGB_DEFAULT_TXD 1024 52#define IGB_MAX_TXD 4096 53 54/* 55 * IGB_RXD: Maximum number of Transmit Descriptors 56 * 57 * This value is the number of receive descriptors allocated by the driver. 58 * Increasing this value allows the driver to buffer more incoming packets. 59 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 60 * descriptor. The maximum MTU size is 16110. 61 * Since TDLEN should be multiple of 128bytes, the number of transmit 62 * desscriptors should meet the following condition. 63 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 64 */ 65#define IGB_MIN_RXD 256 66#define IGB_DEFAULT_RXD 1024 67#define IGB_MAX_RXD 4096 68 69/* 70 * IGB_TIDV - Transmit Interrupt Delay Value 71 * Valid Range: 0-65535 (0=off) 72 * Default Value: 64 73 * This value delays the generation of transmit interrupts in units of 74 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 75 * efficiency if properly tuned for specific network traffic. If the 76 * system is reporting dropped transmits, this value may be set too high 77 * causing the driver to run out of available transmit descriptors. 78 */ 79#define IGB_TIDV 64 80 81/* 82 * IGB_TADV - Transmit Absolute Interrupt Delay Value 83 * Valid Range: 0-65535 (0=off) 84 * Default Value: 64 85 * This value, in units of 1.024 microseconds, limits the delay in which a 86 * transmit interrupt is generated. Useful only if IGB_TIDV is non-zero, 87 * this value ensures that an interrupt is generated after the initial 88 * packet is sent on the wire within the set amount of time. Proper tuning, 89 * along with IGB_TIDV, may improve traffic throughput in specific 90 * network conditions. 91 */ 92#define IGB_TADV 64 93 94/* 95 * IGB_RDTR - Receive Interrupt Delay Timer (Packet Timer) 96 * Valid Range: 0-65535 (0=off) 97 * Default Value: 0 98 * This value delays the generation of receive interrupts in units of 1.024 99 * microseconds. Receive interrupt reduction can improve CPU efficiency if 100 * properly tuned for specific network traffic. Increasing this value adds 101 * extra latency to frame reception and can end up decreasing the throughput 102 * of TCP traffic. If the system is reporting dropped receives, this value 103 * may be set too high, causing the driver to run out of available receive 104 * descriptors. 105 * 106 * CAUTION: When setting IGB_RDTR to a value other than 0, adapters 107 * may hang (stop transmitting) under certain network conditions. 108 * If this occurs a WATCHDOG message is logged in the system 109 * event log. In addition, the controller is automatically reset, 110 * restoring the network connection. To eliminate the potential 111 * for the hang ensure that IGB_RDTR is set to 0. 112 */ 113#define IGB_RDTR 0 114 115/* 116 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 117 * Valid Range: 0-65535 (0=off) 118 * Default Value: 64 119 * This value, in units of 1.024 microseconds, limits the delay in which a 120 * receive interrupt is generated. Useful only if IGB_RDTR is non-zero, 121 * this value ensures that an interrupt is generated after the initial 122 * packet is received within the set amount of time. Proper tuning, 123 * along with IGB_RDTR, may improve traffic throughput in specific network 124 * conditions. 125 */ 126#define IGB_RADV 64 127 128/* 129 * This parameter controls the duration of transmit watchdog timer. 130 */ 131#define IGB_WATCHDOG (10 * hz) 132 133/* 134 * This parameter controls when the driver calls the routine to reclaim 135 * transmit descriptors. Cleaning earlier seems a win. 136 */ 137#define IGB_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 2) 138 139/* 140 * This parameter controls whether or not autonegotation is enabled. 141 * 0 - Disable autonegotiation 142 * 1 - Enable autonegotiation 143 */ 144#define DO_AUTO_NEG 1 145 146/* 147 * This parameter control whether or not the driver will wait for 148 * autonegotiation to complete. 149 * 1 - Wait for autonegotiation to complete 150 * 0 - Don't wait for autonegotiation to complete 151 */ 152#define WAIT_FOR_AUTO_NEG_DEFAULT 0 153 154/* Tunables -- End */ 155 156#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 157 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 158 ADVERTISE_1000_FULL) 159 160#define AUTO_ALL_MODES 0 161 162/* PHY master/slave setting */ 163#define IGB_MASTER_SLAVE e1000_ms_hw_default 164 165/* 166 * Micellaneous constants 167 */ 168#define IGB_VENDOR_ID 0x8086 169 170#define IGB_JUMBO_PBA 0x00000028 171#define IGB_DEFAULT_PBA 0x00000030 172#define IGB_SMARTSPEED_DOWNSHIFT 3 173#define IGB_SMARTSPEED_MAX 15 174#define IGB_MAX_LOOP 10 175 176#define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8) 177#define IGB_RX_HTHRESH 8 178#define IGB_RX_WTHRESH 1 179 180#define IGB_TX_PTHRESH 8 181#define IGB_TX_HTHRESH 1 182#define IGB_TX_WTHRESH ((hw->mac.type != e1000_82575 && \ 183 adapter->msix_mem) ? 1 : 16) 184 185#define MAX_NUM_MULTICAST_ADDRESSES 128 186#define PCI_ANY_ID (~0U) 187#define ETHER_ALIGN 2 188#define IGB_TX_BUFFER_SIZE ((uint32_t) 1514) 189#define IGB_FC_PAUSE_TIME 0x0680 190#define IGB_EEPROM_APME 0x400; 191#define IGB_QUEUE_IDLE 0 192#define IGB_QUEUE_WORKING 1 193#define IGB_QUEUE_HUNG 2 194 195/* 196 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 197 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 198 * also optimize cache line size effect. H/W supports up to cache line size 128. 199 */ 200#define IGB_DBA_ALIGN 128 201 202#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 203 204/* PCI Config defines */ 205#define IGB_MSIX_BAR 3 206 207/* Defines for printing debug information */ 208#define DEBUG_INIT 0 209#define DEBUG_IOCTL 0 210#define DEBUG_HW 0 211 212#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 213#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 214#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 215#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 216#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 217#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 218#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 219#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 220#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 221 222#define IGB_MAX_SCATTER 64 223#define IGB_VFTA_SIZE 128 224#define IGB_BR_SIZE 4096 /* ring buf size */ 225#define IGB_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 226#define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */ 227#define IGB_HDR_BUF 128 228#define IGB_PKTTYPE_MASK 0x0000FFF0 229#define ETH_ZLEN 60 230#define ETH_ADDR_LEN 6 231 232/* Offload bits in mbuf flag */ 233#if __FreeBSD_version >= 800000 234#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 235#else 236#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 237#endif 238 239/* Define the starting Interrupt rate per Queue */ 240#define IGB_INTS_PER_SEC 8000 241#define IGB_DEFAULT_ITR ((1000000/IGB_INTS_PER_SEC) << 2) 242 243#define IGB_LINK_ITR 2000 244 245/* Precision Time Sync (IEEE 1588) defines */ 246#define ETHERTYPE_IEEE1588 0x88F7 247#define PICOSECS_PER_TICK 20833 248#define TSYNC_PORT 319 /* UDP port for the protocol */ 249 250/* 251 * Bus dma allocation structure used by 252 * e1000_dma_malloc and e1000_dma_free. 253 */ 254struct igb_dma_alloc { 255 bus_addr_t dma_paddr; 256 caddr_t dma_vaddr; 257 bus_dma_tag_t dma_tag; 258 bus_dmamap_t dma_map; 259 bus_dma_segment_t dma_seg; 260 int dma_nseg; 261}; 262 263 264/* 265** Driver queue struct: this is the interrupt container 266** for the associated tx and rx ring. 267*/ 268struct igb_queue { 269 struct adapter *adapter; 270 u32 msix; /* This queue's MSIX vector */ 271 u32 eims; /* This queue's EIMS bit */ 272 u32 eitr_setting; 273 struct resource *res; 274 void *tag; 275 struct tx_ring *txr; 276 struct rx_ring *rxr; 277 struct task que_task; 278 struct taskqueue *tq; 279 u64 irqs; 280}; 281 282/* 283 * Transmit ring: one per queue 284 */ 285struct tx_ring { 286 struct adapter *adapter; 287 u32 me; 288 struct mtx tx_mtx; 289 char mtx_name[16]; 290 struct igb_dma_alloc txdma; 291 struct e1000_tx_desc *tx_base; 292 u32 next_avail_desc; 293 u32 next_to_clean; 294 volatile u16 tx_avail; 295 struct igb_tx_buffer *tx_buffers; 296#if __FreeBSD_version >= 800000 297 struct buf_ring *br; 298#endif 299 bus_dma_tag_t txtag; 300 301 u32 bytes; 302 u32 packets; 303 304 int queue_status; 305 int watchdog_time; 306 int tdt; 307 int tdh; 308 u64 no_desc_avail; 309 u64 tx_packets; 310}; 311 312/* 313 * Receive ring: one per queue 314 */ 315struct rx_ring { 316 struct adapter *adapter; 317 u32 me; 318 struct igb_dma_alloc rxdma; 319 union e1000_adv_rx_desc *rx_base; 320 struct lro_ctrl lro; 321 bool lro_enabled; 322 bool hdr_split; 323 bool discard; 324 struct mtx rx_mtx; 325 char mtx_name[16]; 326 u32 next_to_refresh; 327 u32 next_to_check; 328 struct igb_rx_buf *rx_buffers; 329 bus_dma_tag_t htag; /* dma tag for rx head */ 330 bus_dma_tag_t ptag; /* dma tag for rx packet */ 331 /* 332 * First/last mbuf pointers, for 333 * collecting multisegment RX packets. 334 */ 335 struct mbuf *fmp; 336 struct mbuf *lmp; 337 338 u32 bytes; 339 u32 packets; 340 int rdt; 341 int rdh; 342 343 /* Soft stats */ 344 u64 rx_split_packets; 345 u64 rx_discarded; 346 u64 rx_packets; 347 u64 rx_bytes; 348}; 349 350struct adapter { 351 struct ifnet *ifp; 352 struct e1000_hw hw; 353 354 struct e1000_osdep osdep; 355 struct device *dev; 356 struct cdev *led_dev; 357 358 struct resource *pci_mem; 359 struct resource *msix_mem; 360 struct resource *res; 361 void *tag; 362 u32 que_mask; 363 364 int linkvec; 365 int link_mask; 366 struct task link_task; 367 int link_irq; 368 369 struct ifmedia media; 370 struct callout timer; 371 int msix; /* total vectors allocated */ 372 int if_flags; 373 int max_frame_size; 374 int min_frame_size; 375 int pause_frames; 376 struct mtx core_mtx; 377 int igb_insert_vlan_header; 378 u16 num_queues; 379 u16 vf_ifp; /* a VF interface */ 380 381 eventhandler_tag vlan_attach; 382 eventhandler_tag vlan_detach; 383 u32 num_vlans; 384 385 /* Management and WOL features */ 386 int wol; 387 int has_manage; 388 389 /* 390 ** Shadow VFTA table, this is needed because 391 ** the real vlan filter table gets cleared during 392 ** a soft reset and the driver needs to be able 393 ** to repopulate it. 394 */ 395 u32 shadow_vfta[IGB_VFTA_SIZE]; 396 397 /* Info about the interface */ 398 u8 link_active; 399 u16 link_speed; 400 u16 link_duplex; 401 u32 smartspeed; 402 u32 dma_coalesce; 403 404 /* Interface queues */ 405 struct igb_queue *queues; 406 407 /* 408 * Transmit rings 409 */ 410 struct tx_ring *tx_rings; 411 u16 num_tx_desc; 412 413 /* Multicast array pointer */ 414 u8 *mta; 415 416 /* 417 * Receive rings 418 */ 419 struct rx_ring *rx_rings; 420 bool rx_hdr_split; 421 u16 num_rx_desc; 422 int rx_process_limit; 423 u32 rx_mbuf_sz; 424 u32 rx_mask; 425 426 /* Misc stats maintained by the driver */ 427 unsigned long dropped_pkts; 428 unsigned long mbuf_defrag_failed; 429 unsigned long mbuf_header_failed; 430 unsigned long mbuf_packet_failed; 431 unsigned long no_tx_map_avail; 432 unsigned long no_tx_dma_setup; 433 unsigned long watchdog_events; 434 unsigned long rx_overruns; 435 unsigned long device_control; 436 unsigned long rx_control; 437 unsigned long int_mask; 438 unsigned long eint_mask; 439 unsigned long packet_buf_alloc_rx; 440 unsigned long packet_buf_alloc_tx; 441 442 boolean_t in_detach; 443 444#ifdef IGB_IEEE1588 445 /* IEEE 1588 precision time support */ 446 struct cyclecounter cycles; 447 struct nettimer clock; 448 struct nettime_compare compare; 449 struct hwtstamp_ctrl hwtstamp; 450#endif 451 452 void *stats; 453}; 454 455/* ****************************************************************************** 456 * vendor_info_array 457 * 458 * This array contains the list of Subvendor/Subdevice IDs on which the driver 459 * should load. 460 * 461 * ******************************************************************************/ 462typedef struct _igb_vendor_info_t { 463 unsigned int vendor_id; 464 unsigned int device_id; 465 unsigned int subvendor_id; 466 unsigned int subdevice_id; 467 unsigned int index; 468} igb_vendor_info_t; 469 470 471struct igb_tx_buffer { 472 int next_eop; /* Index of the desc to watch */ 473 struct mbuf *m_head; 474 bus_dmamap_t map; /* bus_dma map for packet */ 475}; 476 477struct igb_rx_buf { 478 struct mbuf *m_head; 479 struct mbuf *m_pack; 480 bus_dmamap_t hmap; /* bus_dma map for header */ 481 bus_dmamap_t pmap; /* bus_dma map for packet */ 482}; 483 484/* 485** Find the number of unrefreshed RX descriptors 486*/ 487static inline u16 488igb_rx_unrefreshed(struct rx_ring *rxr) 489{ 490 struct adapter *adapter = rxr->adapter; 491 492 if (rxr->next_to_check > rxr->next_to_refresh) 493 return (rxr->next_to_check - rxr->next_to_refresh - 1); 494 else 495 return ((adapter->num_rx_desc + rxr->next_to_check) - 496 rxr->next_to_refresh - 1); 497} 498 499#define IGB_CORE_LOCK_INIT(_sc, _name) \ 500 mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF) 501#define IGB_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 502#define IGB_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 503#define IGB_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 504#define IGB_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 505 506#define IGB_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 507#define IGB_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 508#define IGB_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 509#define IGB_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 510#define IGB_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 511 512#define IGB_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 513#define IGB_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 514#define IGB_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 515#define IGB_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rx_mtx, MA_OWNED) 516 517#define UPDATE_VF_REG(reg, last, cur) \ 518{ \ 519 u32 new = E1000_READ_REG(hw, reg); \ 520 if (new < last) \ 521 cur += 0x100000000LL; \ 522 last = new; \ 523 cur &= 0xFFFFFFFF00000000LL; \ 524 cur |= new; \ 525} 526 527#if __FreeBSD_version < 800504 528static __inline int 529drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 530{ 531#ifdef ALTQ 532 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 533 return (1); 534#endif 535 return (!buf_ring_empty(br)); 536} 537#endif 538 539#endif /* _IGB_H_DEFINED_ */ 540 541 542