if_igb.h revision 213234
1/****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/if_igb.h 213234 2010-09-28 00:13:15Z jfv $*/ 34 35#ifndef _IGB_H_DEFINED_ 36#define _IGB_H_DEFINED_ 37 38/* Tunables */ 39 40/* 41 * IGB_TXD: Maximum number of Transmit Descriptors 42 * 43 * This value is the number of transmit descriptors allocated by the driver. 44 * Increasing this value allows the driver to queue more transmits. Each 45 * descriptor is 16 bytes. 46 * Since TDLEN should be multiple of 128bytes, the number of transmit 47 * desscriptors should meet the following condition. 48 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 49 */ 50#define IGB_MIN_TXD 256 51#define IGB_DEFAULT_TXD 1024 52#define IGB_MAX_TXD 4096 53 54/* 55 * IGB_RXD: Maximum number of Transmit Descriptors 56 * 57 * This value is the number of receive descriptors allocated by the driver. 58 * Increasing this value allows the driver to buffer more incoming packets. 59 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 60 * descriptor. The maximum MTU size is 16110. 61 * Since TDLEN should be multiple of 128bytes, the number of transmit 62 * desscriptors should meet the following condition. 63 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 64 */ 65#define IGB_MIN_RXD 256 66#define IGB_DEFAULT_RXD 1024 67#define IGB_MAX_RXD 4096 68 69/* 70 * IGB_TIDV - Transmit Interrupt Delay Value 71 * Valid Range: 0-65535 (0=off) 72 * Default Value: 64 73 * This value delays the generation of transmit interrupts in units of 74 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 75 * efficiency if properly tuned for specific network traffic. If the 76 * system is reporting dropped transmits, this value may be set too high 77 * causing the driver to run out of available transmit descriptors. 78 */ 79#define IGB_TIDV 64 80 81/* 82 * IGB_TADV - Transmit Absolute Interrupt Delay Value 83 * Valid Range: 0-65535 (0=off) 84 * Default Value: 64 85 * This value, in units of 1.024 microseconds, limits the delay in which a 86 * transmit interrupt is generated. Useful only if IGB_TIDV is non-zero, 87 * this value ensures that an interrupt is generated after the initial 88 * packet is sent on the wire within the set amount of time. Proper tuning, 89 * along with IGB_TIDV, may improve traffic throughput in specific 90 * network conditions. 91 */ 92#define IGB_TADV 64 93 94/* 95 * IGB_RDTR - Receive Interrupt Delay Timer (Packet Timer) 96 * Valid Range: 0-65535 (0=off) 97 * Default Value: 0 98 * This value delays the generation of receive interrupts in units of 1.024 99 * microseconds. Receive interrupt reduction can improve CPU efficiency if 100 * properly tuned for specific network traffic. Increasing this value adds 101 * extra latency to frame reception and can end up decreasing the throughput 102 * of TCP traffic. If the system is reporting dropped receives, this value 103 * may be set too high, causing the driver to run out of available receive 104 * descriptors. 105 * 106 * CAUTION: When setting IGB_RDTR to a value other than 0, adapters 107 * may hang (stop transmitting) under certain network conditions. 108 * If this occurs a WATCHDOG message is logged in the system 109 * event log. In addition, the controller is automatically reset, 110 * restoring the network connection. To eliminate the potential 111 * for the hang ensure that IGB_RDTR is set to 0. 112 */ 113#define IGB_RDTR 0 114 115/* 116 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 117 * Valid Range: 0-65535 (0=off) 118 * Default Value: 64 119 * This value, in units of 1.024 microseconds, limits the delay in which a 120 * receive interrupt is generated. Useful only if IGB_RDTR is non-zero, 121 * this value ensures that an interrupt is generated after the initial 122 * packet is received within the set amount of time. Proper tuning, 123 * along with IGB_RDTR, may improve traffic throughput in specific network 124 * conditions. 125 */ 126#define IGB_RADV 64 127 128/* 129 * This parameter controls the duration of transmit watchdog timer. 130 */ 131#define IGB_WATCHDOG (10 * hz) 132 133/* 134 * This parameter controls when the driver calls the routine to reclaim 135 * transmit descriptors. 136 */ 137#define IGB_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 138#define IGB_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 139 140/* 141 * This parameter controls whether or not autonegotation is enabled. 142 * 0 - Disable autonegotiation 143 * 1 - Enable autonegotiation 144 */ 145#define DO_AUTO_NEG 1 146 147/* 148 * This parameter control whether or not the driver will wait for 149 * autonegotiation to complete. 150 * 1 - Wait for autonegotiation to complete 151 * 0 - Don't wait for autonegotiation to complete 152 */ 153#define WAIT_FOR_AUTO_NEG_DEFAULT 0 154 155/* Tunables -- End */ 156 157#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 158 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 159 ADVERTISE_1000_FULL) 160 161#define AUTO_ALL_MODES 0 162 163/* PHY master/slave setting */ 164#define IGB_MASTER_SLAVE e1000_ms_hw_default 165 166/* 167 * Micellaneous constants 168 */ 169#define IGB_VENDOR_ID 0x8086 170 171#define IGB_JUMBO_PBA 0x00000028 172#define IGB_DEFAULT_PBA 0x00000030 173#define IGB_SMARTSPEED_DOWNSHIFT 3 174#define IGB_SMARTSPEED_MAX 15 175#define IGB_MAX_LOOP 10 176 177#define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8) 178#define IGB_RX_HTHRESH 8 179#define IGB_RX_WTHRESH 1 180 181#define IGB_TX_PTHRESH 8 182#define IGB_TX_HTHRESH 1 183#define IGB_TX_WTHRESH (((hw->mac.type == e1000_82576 || \ 184 hw->mac.type == e1000_vfadapt) && \ 185 adapter->msix_mem) ? 1 : 16) 186 187#define MAX_NUM_MULTICAST_ADDRESSES 128 188#define PCI_ANY_ID (~0U) 189#define ETHER_ALIGN 2 190#define IGB_TX_BUFFER_SIZE ((uint32_t) 1514) 191#define IGB_FC_PAUSE_TIME 0x0680 192#define IGB_EEPROM_APME 0x400; 193 194/* 195 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 196 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 197 * also optimize cache line size effect. H/W supports up to cache line size 128. 198 */ 199#define IGB_DBA_ALIGN 128 200 201#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 202 203/* PCI Config defines */ 204#define IGB_MSIX_BAR 3 205 206/* Defines for printing debug information */ 207#define DEBUG_INIT 0 208#define DEBUG_IOCTL 0 209#define DEBUG_HW 0 210 211#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 212#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 213#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 214#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 215#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 216#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 217#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 218#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 219#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 220 221#define IGB_MAX_SCATTER 64 222#define IGB_VFTA_SIZE 128 223#define IGB_BR_SIZE 4096 /* ring buf size */ 224#define IGB_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 225#define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */ 226#define IGB_HDR_BUF 128 227#define IGB_PKTTYPE_MASK 0x0000FFF0 228#define ETH_ZLEN 60 229#define ETH_ADDR_LEN 6 230 231/* Offload bits in mbuf flag */ 232#if __FreeBSD_version >= 800000 233#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 234#else 235#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 236#endif 237 238/* Define the starting Interrupt rate per Queue */ 239#define IGB_INTS_PER_SEC 8000 240#define IGB_DEFAULT_ITR 1000000000/(IGB_INTS_PER_SEC * 256) 241 242#define IGB_LINK_ITR 2000 243 244/* Precision Time Sync (IEEE 1588) defines */ 245#define ETHERTYPE_IEEE1588 0x88F7 246#define PICOSECS_PER_TICK 20833 247#define TSYNC_PORT 319 /* UDP port for the protocol */ 248 249/* 250 * Bus dma allocation structure used by 251 * e1000_dma_malloc and e1000_dma_free. 252 */ 253struct igb_dma_alloc { 254 bus_addr_t dma_paddr; 255 caddr_t dma_vaddr; 256 bus_dma_tag_t dma_tag; 257 bus_dmamap_t dma_map; 258 bus_dma_segment_t dma_seg; 259 int dma_nseg; 260}; 261 262 263/* 264** Driver queue struct: this is the interrupt container 265** for the associated tx and rx ring. 266*/ 267struct igb_queue { 268 struct adapter *adapter; 269 u32 msix; /* This queue's MSIX vector */ 270 u32 eims; /* This queue's EIMS bit */ 271 u32 eitr_setting; 272 struct resource *res; 273 void *tag; 274 struct tx_ring *txr; 275 struct rx_ring *rxr; 276 struct task que_task; 277 struct taskqueue *tq; 278 u64 irqs; 279}; 280 281/* 282 * Transmit ring: one per queue 283 */ 284struct tx_ring { 285 struct adapter *adapter; 286 u32 me; 287 struct mtx tx_mtx; 288 char mtx_name[16]; 289 struct igb_dma_alloc txdma; 290 struct e1000_tx_desc *tx_base; 291 u32 next_avail_desc; 292 u32 next_to_clean; 293 volatile u16 tx_avail; 294 struct igb_tx_buffer *tx_buffers; 295#if __FreeBSD_version >= 800000 296 struct buf_ring *br; 297#endif 298 bus_dma_tag_t txtag; 299 300 u32 bytes; 301 u32 packets; 302 303 bool watchdog_check; 304 int watchdog_time; 305 int tdt; 306 int tdh; 307 u64 no_desc_avail; 308 u64 tx_packets; 309}; 310 311/* 312 * Receive ring: one per queue 313 */ 314struct rx_ring { 315 struct adapter *adapter; 316 u32 me; 317 struct igb_dma_alloc rxdma; 318 union e1000_adv_rx_desc *rx_base; 319 struct lro_ctrl lro; 320 bool lro_enabled; 321 bool hdr_split; 322 bool discard; 323 struct mtx rx_mtx; 324 char mtx_name[16]; 325 u32 next_to_refresh; 326 u32 next_to_check; 327 struct igb_rx_buf *rx_buffers; 328 bus_dma_tag_t htag; /* dma tag for rx head */ 329 bus_dma_tag_t ptag; /* dma tag for rx packet */ 330 /* 331 * First/last mbuf pointers, for 332 * collecting multisegment RX packets. 333 */ 334 struct mbuf *fmp; 335 struct mbuf *lmp; 336 337 u32 bytes; 338 u32 packets; 339 int rdt; 340 int rdh; 341 342 /* Soft stats */ 343 u64 rx_split_packets; 344 u64 rx_discarded; 345 u64 rx_packets; 346 u64 rx_bytes; 347}; 348 349struct adapter { 350 struct ifnet *ifp; 351 struct e1000_hw hw; 352 353 struct e1000_osdep osdep; 354 struct device *dev; 355 struct cdev *led_dev; 356 357 struct resource *pci_mem; 358 struct resource *msix_mem; 359 struct resource *res; 360 void *tag; 361 u32 eims_mask; 362 363 int linkvec; 364 int link_mask; 365 struct task link_task; 366 int link_irq; 367 368 struct ifmedia media; 369 struct callout timer; 370 int msix; /* total vectors allocated */ 371 int if_flags; 372 int max_frame_size; 373 int min_frame_size; 374 int pause_frames; 375 struct mtx core_mtx; 376 int igb_insert_vlan_header; 377 u16 num_queues; 378 379 eventhandler_tag vlan_attach; 380 eventhandler_tag vlan_detach; 381 u32 num_vlans; 382 383 /* Management and WOL features */ 384 int wol; 385 int has_manage; 386 387 /* Info about the board itself */ 388 u8 link_active; 389 u16 link_speed; 390 u16 link_duplex; 391 u32 smartspeed; 392 393 /* Interface queues */ 394 struct igb_queue *queues; 395 396 /* 397 * Transmit rings 398 */ 399 struct tx_ring *tx_rings; 400 u16 num_tx_desc; 401 402 /* Multicast array pointer */ 403 u8 *mta; 404 405 /* 406 * Receive rings 407 */ 408 struct rx_ring *rx_rings; 409 bool rx_hdr_split; 410 u16 num_rx_desc; 411 int rx_process_limit; 412 u32 rx_mbuf_sz; 413 u32 rx_mask; 414 415 /* Misc stats maintained by the driver */ 416 unsigned long dropped_pkts; 417 unsigned long mbuf_defrag_failed; 418 unsigned long mbuf_header_failed; 419 unsigned long mbuf_packet_failed; 420 unsigned long no_tx_map_avail; 421 unsigned long no_tx_dma_setup; 422 unsigned long watchdog_events; 423 unsigned long rx_overruns; 424 unsigned long device_control; 425 unsigned long rx_control; 426 unsigned long int_mask; 427 unsigned long eint_mask; 428 unsigned long packet_buf_alloc_rx; 429 unsigned long packet_buf_alloc_tx; 430 431 boolean_t in_detach; 432 433#ifdef IGB_IEEE1588 434 /* IEEE 1588 precision time support */ 435 struct cyclecounter cycles; 436 struct nettimer clock; 437 struct nettime_compare compare; 438 struct hwtstamp_ctrl hwtstamp; 439#endif 440 441 void *stats; 442}; 443 444/* ****************************************************************************** 445 * vendor_info_array 446 * 447 * This array contains the list of Subvendor/Subdevice IDs on which the driver 448 * should load. 449 * 450 * ******************************************************************************/ 451typedef struct _igb_vendor_info_t { 452 unsigned int vendor_id; 453 unsigned int device_id; 454 unsigned int subvendor_id; 455 unsigned int subdevice_id; 456 unsigned int index; 457} igb_vendor_info_t; 458 459 460struct igb_tx_buffer { 461 int next_eop; /* Index of the desc to watch */ 462 struct mbuf *m_head; 463 bus_dmamap_t map; /* bus_dma map for packet */ 464}; 465 466struct igb_rx_buf { 467 struct mbuf *m_head; 468 struct mbuf *m_pack; 469 bus_dmamap_t hmap; /* bus_dma map for header */ 470 bus_dmamap_t pmap; /* bus_dma map for packet */ 471}; 472 473#define IGB_CORE_LOCK_INIT(_sc, _name) \ 474 mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF) 475#define IGB_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 476#define IGB_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 477#define IGB_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 478#define IGB_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 479 480#define IGB_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 481#define IGB_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 482#define IGB_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 483#define IGB_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 484#define IGB_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 485 486#define IGB_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 487#define IGB_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 488#define IGB_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 489#define IGB_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rx_mtx, MA_OWNED) 490 491#define UPDATE_VF_REG(reg, last, cur) \ 492{ \ 493 u32 new = E1000_READ_REG(hw, reg); \ 494 if (new < last) \ 495 cur += 0x100000000LL; \ 496 last = new; \ 497 cur &= 0xFFFFFFFF00000000LL; \ 498 cur |= new; \ 499} 500 501#if __FreeBSD_version < 800504 502static __inline int 503drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 504{ 505#ifdef ALTQ 506 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 507 return (1); 508#endif 509 return (!buf_ring_empty(br)); 510} 511#endif 512 513#endif /* _IGB_H_DEFINED_ */ 514 515 516