if_igb.h revision 209218
1/****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/if_igb.h 209218 2010-06-15 21:11:51Z jfv $*/ 34 35#ifndef _IGB_H_DEFINED_ 36#define _IGB_H_DEFINED_ 37 38/* Tunables */ 39 40/* 41 * IGB_TXD: Maximum number of Transmit Descriptors 42 * 43 * This value is the number of transmit descriptors allocated by the driver. 44 * Increasing this value allows the driver to queue more transmits. Each 45 * descriptor is 16 bytes. 46 * Since TDLEN should be multiple of 128bytes, the number of transmit 47 * desscriptors should meet the following condition. 48 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 49 */ 50#define IGB_MIN_TXD 256 51#define IGB_DEFAULT_TXD 1024 52#define IGB_MAX_TXD 4096 53 54/* 55 * IGB_RXD: Maximum number of Transmit Descriptors 56 * 57 * This value is the number of receive descriptors allocated by the driver. 58 * Increasing this value allows the driver to buffer more incoming packets. 59 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 60 * descriptor. The maximum MTU size is 16110. 61 * Since TDLEN should be multiple of 128bytes, the number of transmit 62 * desscriptors should meet the following condition. 63 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 64 */ 65#define IGB_MIN_RXD 256 66#define IGB_DEFAULT_RXD 1024 67#define IGB_MAX_RXD 4096 68 69/* 70 * IGB_TIDV - Transmit Interrupt Delay Value 71 * Valid Range: 0-65535 (0=off) 72 * Default Value: 64 73 * This value delays the generation of transmit interrupts in units of 74 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 75 * efficiency if properly tuned for specific network traffic. If the 76 * system is reporting dropped transmits, this value may be set too high 77 * causing the driver to run out of available transmit descriptors. 78 */ 79#define IGB_TIDV 64 80 81/* 82 * IGB_TADV - Transmit Absolute Interrupt Delay Value 83 * Valid Range: 0-65535 (0=off) 84 * Default Value: 64 85 * This value, in units of 1.024 microseconds, limits the delay in which a 86 * transmit interrupt is generated. Useful only if IGB_TIDV is non-zero, 87 * this value ensures that an interrupt is generated after the initial 88 * packet is sent on the wire within the set amount of time. Proper tuning, 89 * along with IGB_TIDV, may improve traffic throughput in specific 90 * network conditions. 91 */ 92#define IGB_TADV 64 93 94/* 95 * IGB_RDTR - Receive Interrupt Delay Timer (Packet Timer) 96 * Valid Range: 0-65535 (0=off) 97 * Default Value: 0 98 * This value delays the generation of receive interrupts in units of 1.024 99 * microseconds. Receive interrupt reduction can improve CPU efficiency if 100 * properly tuned for specific network traffic. Increasing this value adds 101 * extra latency to frame reception and can end up decreasing the throughput 102 * of TCP traffic. If the system is reporting dropped receives, this value 103 * may be set too high, causing the driver to run out of available receive 104 * descriptors. 105 * 106 * CAUTION: When setting IGB_RDTR to a value other than 0, adapters 107 * may hang (stop transmitting) under certain network conditions. 108 * If this occurs a WATCHDOG message is logged in the system 109 * event log. In addition, the controller is automatically reset, 110 * restoring the network connection. To eliminate the potential 111 * for the hang ensure that IGB_RDTR is set to 0. 112 */ 113#define IGB_RDTR 0 114 115/* 116 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 117 * Valid Range: 0-65535 (0=off) 118 * Default Value: 64 119 * This value, in units of 1.024 microseconds, limits the delay in which a 120 * receive interrupt is generated. Useful only if IGB_RDTR is non-zero, 121 * this value ensures that an interrupt is generated after the initial 122 * packet is received within the set amount of time. Proper tuning, 123 * along with IGB_RDTR, may improve traffic throughput in specific network 124 * conditions. 125 */ 126#define IGB_RADV 64 127 128/* 129 * This parameter controls the duration of transmit watchdog timer. 130 */ 131#define IGB_WATCHDOG (10 * hz) 132 133/* 134 * This parameter controls when the driver calls the routine to reclaim 135 * transmit descriptors. 136 */ 137#define IGB_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 138#define IGB_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 139 140/* 141 * This parameter controls whether or not autonegotation is enabled. 142 * 0 - Disable autonegotiation 143 * 1 - Enable autonegotiation 144 */ 145#define DO_AUTO_NEG 1 146 147/* 148 * This parameter control whether or not the driver will wait for 149 * autonegotiation to complete. 150 * 1 - Wait for autonegotiation to complete 151 * 0 - Don't wait for autonegotiation to complete 152 */ 153#define WAIT_FOR_AUTO_NEG_DEFAULT 0 154 155/* Tunables -- End */ 156 157#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 158 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 159 ADVERTISE_1000_FULL) 160 161#define AUTO_ALL_MODES 0 162 163/* PHY master/slave setting */ 164#define IGB_MASTER_SLAVE e1000_ms_hw_default 165 166/* 167 * Micellaneous constants 168 */ 169#define IGB_VENDOR_ID 0x8086 170 171#define IGB_JUMBO_PBA 0x00000028 172#define IGB_DEFAULT_PBA 0x00000030 173#define IGB_SMARTSPEED_DOWNSHIFT 3 174#define IGB_SMARTSPEED_MAX 15 175#define IGB_MAX_LOOP 10 176 177#define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8) 178#define IGB_RX_HTHRESH 8 179#define IGB_RX_WTHRESH 1 180 181#define IGB_TX_PTHRESH 8 182#define IGB_TX_HTHRESH 1 183#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \ 184 adapter->msix_mem) ? 1 : 16) 185 186#define MAX_NUM_MULTICAST_ADDRESSES 128 187#define PCI_ANY_ID (~0U) 188#define ETHER_ALIGN 2 189#define IGB_TX_BUFFER_SIZE ((uint32_t) 1514) 190#define IGB_FC_PAUSE_TIME 0x0680 191#define IGB_EEPROM_APME 0x400; 192 193/* 194 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 195 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 196 * also optimize cache line size effect. H/W supports up to cache line size 128. 197 */ 198#define IGB_DBA_ALIGN 128 199 200#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 201 202/* PCI Config defines */ 203#define IGB_MSIX_BAR 3 204 205/* 206** This is the total number of MSIX vectors you wish 207** to use, it also controls the size of resources. 208** The 82575 has a total of 10, 82576 has 25. Set this 209** to the real amount you need to streamline data storage. 210*/ 211#define IGB_MSIX_VEC 6 /* MSIX vectors configured */ 212 213/* Defines for printing debug information */ 214#define DEBUG_INIT 0 215#define DEBUG_IOCTL 0 216#define DEBUG_HW 0 217 218#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 219#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 220#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 221#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 222#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 223#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 224#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 225#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 226#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 227 228#define IGB_MAX_SCATTER 64 229#define IGB_VFTA_SIZE 128 230#define IGB_BR_SIZE 4096 /* ring buf size */ 231#define IGB_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 232#define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */ 233#define IGB_HDR_BUF 128 234#define IGB_PKTTYPE_MASK 0x0000FFF0 235#define ETH_ZLEN 60 236#define ETH_ADDR_LEN 6 237 238/* Offload bits in mbuf flag */ 239#if __FreeBSD_version >= 800000 240#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 241#else 242#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 243#endif 244 245/* Define the starting Interrupt rate per Queue */ 246#define IGB_INTS_PER_SEC 8000 247#define IGB_DEFAULT_ITR 1000000000/(IGB_INTS_PER_SEC * 256) 248 249 250/* Header split codes for get_buf */ 251#define IGB_CLEAN_HEADER 0x01 252#define IGB_CLEAN_PAYLOAD 0x02 253#define IGB_CLEAN_BOTH (IGB_CLEAN_HEADER | IGB_CLEAN_PAYLOAD) 254 255#define IGB_LINK_ITR 2000 256 257/* Precision Time Sync (IEEE 1588) defines */ 258#define ETHERTYPE_IEEE1588 0x88F7 259#define PICOSECS_PER_TICK 20833 260#define TSYNC_PORT 319 /* UDP port for the protocol */ 261 262/* 263 * Bus dma allocation structure used by 264 * e1000_dma_malloc and e1000_dma_free. 265 */ 266struct igb_dma_alloc { 267 bus_addr_t dma_paddr; 268 caddr_t dma_vaddr; 269 bus_dma_tag_t dma_tag; 270 bus_dmamap_t dma_map; 271 bus_dma_segment_t dma_seg; 272 int dma_nseg; 273}; 274 275 276/* 277** Driver queue struct: this is the interrupt container 278** for the associated tx and rx ring. 279*/ 280struct igb_queue { 281 struct adapter *adapter; 282 u32 msix; /* This queue's MSIX vector */ 283 u32 eims; /* This queue's EIMS bit */ 284 u32 eitr_setting; 285 struct resource *res; 286 void *tag; 287 struct tx_ring *txr; 288 struct rx_ring *rxr; 289 struct task que_task; 290 struct taskqueue *tq; 291 u64 irqs; 292}; 293 294/* 295 * Transmit ring: one per queue 296 */ 297struct tx_ring { 298 struct adapter *adapter; 299 u32 me; 300 struct mtx tx_mtx; 301 char mtx_name[16]; 302 struct igb_dma_alloc txdma; 303 struct e1000_tx_desc *tx_base; 304 u32 next_avail_desc; 305 u32 next_to_clean; 306 volatile u16 tx_avail; 307 struct igb_tx_buffer *tx_buffers; 308#if __FreeBSD_version >= 800000 309 struct buf_ring *br; 310#endif 311 bus_dma_tag_t txtag; 312 313 u32 bytes; 314 u32 packets; 315 316 bool watchdog_check; 317 int watchdog_time; 318 u64 no_desc_avail; 319 u64 tx_packets; 320}; 321 322/* 323 * Receive ring: one per queue 324 */ 325struct rx_ring { 326 struct adapter *adapter; 327 u32 me; 328 struct igb_dma_alloc rxdma; 329 union e1000_adv_rx_desc *rx_base; 330 struct lro_ctrl lro; 331 bool lro_enabled; 332 bool hdr_split; 333 bool discard; 334 struct mtx rx_mtx; 335 char mtx_name[16]; 336 u32 next_to_refresh; 337 u32 next_to_check; 338 struct igb_rx_buf *rx_buffers; 339 bus_dma_tag_t htag; /* dma tag for rx head */ 340 bus_dma_tag_t ptag; /* dma tag for rx packet */ 341 /* 342 * First/last mbuf pointers, for 343 * collecting multisegment RX packets. 344 */ 345 struct mbuf *fmp; 346 struct mbuf *lmp; 347 348 u32 bytes; 349 u32 packets; 350 351 /* Soft stats */ 352 u64 rx_split_packets; 353 u64 rx_discarded; 354 u64 rx_packets; 355 u64 rx_bytes; 356}; 357 358struct adapter { 359 struct ifnet *ifp; 360 struct e1000_hw hw; 361 362 struct e1000_osdep osdep; 363 struct device *dev; 364 struct cdev *led_dev; 365 366 struct resource *pci_mem; 367 struct resource *msix_mem; 368 struct resource *res; 369 void *tag; 370 u32 eims_mask; 371 372 int linkvec; 373 int link_mask; 374 struct task link_task; 375 int link_irq; 376 377 struct ifmedia media; 378 struct callout timer; 379 int msix; /* total vectors allocated */ 380 int if_flags; 381 int max_frame_size; 382 int min_frame_size; 383 struct mtx core_mtx; 384 int igb_insert_vlan_header; 385 struct taskqueue *tq; /* adapter task queue */ 386 u16 num_queues; 387 388 eventhandler_tag vlan_attach; 389 eventhandler_tag vlan_detach; 390 u32 num_vlans; 391 392 /* Management and WOL features */ 393 int wol; 394 int has_manage; 395 396 /* Info about the board itself */ 397 u8 link_active; 398 u16 link_speed; 399 u16 link_duplex; 400 u32 smartspeed; 401 402 /* Interface queues */ 403 struct igb_queue *queues; 404 405 /* 406 * Transmit rings 407 */ 408 struct tx_ring *tx_rings; 409 u16 num_tx_desc; 410 411 /* 412 * Receive rings 413 */ 414 struct rx_ring *rx_rings; 415 bool rx_hdr_split; 416 u16 num_rx_desc; 417 int rx_process_limit; 418 u32 rx_mbuf_sz; 419 u32 rx_mask; 420 421 /* Misc stats maintained by the driver */ 422 unsigned long dropped_pkts; 423 unsigned long mbuf_defrag_failed; 424 unsigned long mbuf_header_failed; 425 unsigned long mbuf_packet_failed; 426 unsigned long no_tx_map_avail; 427 unsigned long no_tx_dma_setup; 428 unsigned long watchdog_events; 429 unsigned long rx_overruns; 430 431 boolean_t in_detach; 432 433#ifdef IGB_IEEE1588 434 /* IEEE 1588 precision time support */ 435 struct cyclecounter cycles; 436 struct nettimer clock; 437 struct nettime_compare compare; 438 struct hwtstamp_ctrl hwtstamp; 439#endif 440 441 struct e1000_hw_stats stats; 442}; 443 444/* ****************************************************************************** 445 * vendor_info_array 446 * 447 * This array contains the list of Subvendor/Subdevice IDs on which the driver 448 * should load. 449 * 450 * ******************************************************************************/ 451typedef struct _igb_vendor_info_t { 452 unsigned int vendor_id; 453 unsigned int device_id; 454 unsigned int subvendor_id; 455 unsigned int subdevice_id; 456 unsigned int index; 457} igb_vendor_info_t; 458 459 460struct igb_tx_buffer { 461 int next_eop; /* Index of the desc to watch */ 462 struct mbuf *m_head; 463 bus_dmamap_t map; /* bus_dma map for packet */ 464}; 465 466struct igb_rx_buf { 467 struct mbuf *m_head; 468 struct mbuf *m_pack; 469 bus_dmamap_t hmap; /* bus_dma map for header */ 470 bus_dmamap_t pmap; /* bus_dma map for packet */ 471}; 472 473#define IGB_CORE_LOCK_INIT(_sc, _name) \ 474 mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF) 475#define IGB_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 476#define IGB_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 477#define IGB_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 478#define IGB_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 479 480#define IGB_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 481#define IGB_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 482#define IGB_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 483#define IGB_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 484#define IGB_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 485 486#define IGB_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 487#define IGB_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 488#define IGB_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 489#define IGB_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 490 491#endif /* _IGB_H_DEFINED_ */ 492 493 494