if_igb.h revision 194865
1/****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/if_igb.h 194865 2009-06-24 17:41:29Z jfv $*/ 34 35#ifndef _IGB_H_DEFINED_ 36#define _IGB_H_DEFINED_ 37 38/* Tunables */ 39 40/* 41 * IGB_TXD: Maximum number of Transmit Descriptors 42 * 43 * This value is the number of transmit descriptors allocated by the driver. 44 * Increasing this value allows the driver to queue more transmits. Each 45 * descriptor is 16 bytes. 46 * Since TDLEN should be multiple of 128bytes, the number of transmit 47 * desscriptors should meet the following condition. 48 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 49 */ 50#define IGB_MIN_TXD 80 51#define IGB_DEFAULT_TXD 256 52#define IGB_MAX_TXD 4096 53 54/* 55 * IGB_RXD: Maximum number of Transmit Descriptors 56 * 57 * This value is the number of receive descriptors allocated by the driver. 58 * Increasing this value allows the driver to buffer more incoming packets. 59 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 60 * descriptor. The maximum MTU size is 16110. 61 * Since TDLEN should be multiple of 128bytes, the number of transmit 62 * desscriptors should meet the following condition. 63 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 64 */ 65#define IGB_MIN_RXD 80 66#define IGB_DEFAULT_RXD 256 67#define IGB_MAX_RXD 4096 68 69/* 70 * IGB_TIDV - Transmit Interrupt Delay Value 71 * Valid Range: 0-65535 (0=off) 72 * Default Value: 64 73 * This value delays the generation of transmit interrupts in units of 74 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 75 * efficiency if properly tuned for specific network traffic. If the 76 * system is reporting dropped transmits, this value may be set too high 77 * causing the driver to run out of available transmit descriptors. 78 */ 79#define IGB_TIDV 64 80 81/* 82 * IGB_TADV - Transmit Absolute Interrupt Delay Value 83 * Valid Range: 0-65535 (0=off) 84 * Default Value: 64 85 * This value, in units of 1.024 microseconds, limits the delay in which a 86 * transmit interrupt is generated. Useful only if IGB_TIDV is non-zero, 87 * this value ensures that an interrupt is generated after the initial 88 * packet is sent on the wire within the set amount of time. Proper tuning, 89 * along with IGB_TIDV, may improve traffic throughput in specific 90 * network conditions. 91 */ 92#define IGB_TADV 64 93 94/* 95 * IGB_RDTR - Receive Interrupt Delay Timer (Packet Timer) 96 * Valid Range: 0-65535 (0=off) 97 * Default Value: 0 98 * This value delays the generation of receive interrupts in units of 1.024 99 * microseconds. Receive interrupt reduction can improve CPU efficiency if 100 * properly tuned for specific network traffic. Increasing this value adds 101 * extra latency to frame reception and can end up decreasing the throughput 102 * of TCP traffic. If the system is reporting dropped receives, this value 103 * may be set too high, causing the driver to run out of available receive 104 * descriptors. 105 * 106 * CAUTION: When setting IGB_RDTR to a value other than 0, adapters 107 * may hang (stop transmitting) under certain network conditions. 108 * If this occurs a WATCHDOG message is logged in the system 109 * event log. In addition, the controller is automatically reset, 110 * restoring the network connection. To eliminate the potential 111 * for the hang ensure that IGB_RDTR is set to 0. 112 */ 113#define IGB_RDTR 0 114 115/* 116 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 117 * Valid Range: 0-65535 (0=off) 118 * Default Value: 64 119 * This value, in units of 1.024 microseconds, limits the delay in which a 120 * receive interrupt is generated. Useful only if IGB_RDTR is non-zero, 121 * this value ensures that an interrupt is generated after the initial 122 * packet is received within the set amount of time. Proper tuning, 123 * along with IGB_RDTR, may improve traffic throughput in specific network 124 * conditions. 125 */ 126#define IGB_RADV 64 127 128/* 129 * This parameter controls the duration of transmit watchdog timer. 130 */ 131#define IGB_TX_TIMEOUT 5 /* set to 5 seconds */ 132 133/* 134 * This parameter controls when the driver calls the routine to reclaim 135 * transmit descriptors. 136 */ 137#define IGB_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 138#define IGB_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 139 140/* 141 * This parameter controls whether or not autonegotation is enabled. 142 * 0 - Disable autonegotiation 143 * 1 - Enable autonegotiation 144 */ 145#define DO_AUTO_NEG 1 146 147/* 148 * This parameter control whether or not the driver will wait for 149 * autonegotiation to complete. 150 * 1 - Wait for autonegotiation to complete 151 * 0 - Don't wait for autonegotiation to complete 152 */ 153#define WAIT_FOR_AUTO_NEG_DEFAULT 0 154 155/* Tunables -- End */ 156 157#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 158 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 159 ADVERTISE_1000_FULL) 160 161#define AUTO_ALL_MODES 0 162 163/* PHY master/slave setting */ 164#define IGB_MASTER_SLAVE e1000_ms_hw_default 165 166/* 167 * Micellaneous constants 168 */ 169#define IGB_VENDOR_ID 0x8086 170 171#define IGB_JUMBO_PBA 0x00000028 172#define IGB_DEFAULT_PBA 0x00000030 173#define IGB_SMARTSPEED_DOWNSHIFT 3 174#define IGB_SMARTSPEED_MAX 15 175#define IGB_MAX_LOOP 10 176#define IGB_RX_PTHRESH 16 177#define IGB_RX_HTHRESH 8 178#define IGB_RX_WTHRESH 1 179 180#define MAX_NUM_MULTICAST_ADDRESSES 128 181#define PCI_ANY_ID (~0U) 182#define ETHER_ALIGN 2 183#define IGB_TX_BUFFER_SIZE ((uint32_t) 1514) 184#define IGB_FC_PAUSE_TIME 0x0680 185#define IGB_EEPROM_APME 0x400; 186 187/* 188 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 189 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 190 * also optimize cache line size effect. H/W supports up to cache line size 128. 191 */ 192#define IGB_DBA_ALIGN 128 193 194#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 195 196/* PCI Config defines */ 197#define IGB_MSIX_BAR 3 198 199/* 200** This is the total number of MSIX vectors you wish 201** to use, it also controls the size of resources. 202** The 82575 has a total of 10, 82576 has 25. Set this 203** to the real amount you need to streamline data storage. 204*/ 205#define IGB_MSIX_VEC 6 /* MSIX vectors configured */ 206 207/* Defines for printing debug information */ 208#define DEBUG_INIT 0 209#define DEBUG_IOCTL 0 210#define DEBUG_HW 0 211 212#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 213#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 214#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 215#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 216#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 217#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 218#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 219#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 220#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 221 222#define IGB_MAX_SCATTER 64 223#define IGB_VFTA_SIZE 128 224#define IGB_BR_SIZE 4096 /* ring buf size */ 225#define IGB_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 226#define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */ 227#define IGB_HDR_BUF 128 228#define ETH_ZLEN 60 229#define ETH_ADDR_LEN 6 230 231/* Offload bits in mbuf flag */ 232#if __FreeBSD_version >= 800000 233#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 234#else 235#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 236#endif 237 238/* Header split codes for get_buf */ 239#define IGB_CLEAN_HEADER 1 240#define IGB_CLEAN_PAYLOAD 2 241#define IGB_CLEAN_BOTH 3 242 243/* 244 * Interrupt Moderation parameters 245 */ 246#define IGB_LOW_LATENCY 128 247#define IGB_AVE_LATENCY 450 248#define IGB_BULK_LATENCY 1200 249#define IGB_LINK_ITR 2000 250 251/* Precision Time Sync (IEEE 1588) defines */ 252#define ETHERTYPE_IEEE1588 0x88F7 253#define PICOSECS_PER_TICK 20833 254#define TSYNC_PORT 319 /* UDP port for the protocol */ 255 256/* 257 * Bus dma allocation structure used by 258 * e1000_dma_malloc and e1000_dma_free. 259 */ 260struct igb_dma_alloc { 261 bus_addr_t dma_paddr; 262 caddr_t dma_vaddr; 263 bus_dma_tag_t dma_tag; 264 bus_dmamap_t dma_map; 265 bus_dma_segment_t dma_seg; 266 int dma_nseg; 267}; 268 269 270/* 271 * Transmit ring: one per tx queue 272 */ 273struct tx_ring { 274 struct adapter *adapter; 275 u32 me; 276 u32 msix; /* This ring's MSIX vector */ 277 u32 eims; /* This ring's EIMS bit */ 278 struct mtx tx_mtx; 279 char mtx_name[16]; 280 struct igb_dma_alloc txdma; /* bus_dma glue for tx desc */ 281 struct e1000_tx_desc *tx_base; 282 struct task tx_task; /* cleanup tasklet */ 283 u32 next_avail_desc; 284 u32 next_to_clean; 285 volatile u16 tx_avail; 286 struct igb_tx_buffer *tx_buffers; 287#if __FreeBSD_version >= 800000 288 struct buf_ring *br; 289#endif 290 bus_dma_tag_t txtag; /* dma tag for tx */ 291 struct resource *res; 292 void *tag; 293 294 u32 watchdog_timer; 295 u64 no_desc_avail; 296 u64 tx_irq; 297 u64 tx_packets; 298}; 299 300/* 301 * Receive ring: one per rx queue 302 */ 303struct rx_ring { 304 struct adapter *adapter; 305 u32 me; 306 u32 msix; /* This ring's MSIX vector */ 307 u32 eims; /* This ring's EIMS bit */ 308 struct igb_dma_alloc rxdma; /* bus_dma glue for tx desc */ 309 union e1000_adv_rx_desc *rx_base; 310 struct lro_ctrl lro; 311 bool lro_enabled; 312 bool hdr_split; 313 struct task rx_task; /* cleanup tasklet */ 314 struct mtx rx_mtx; 315 char mtx_name[16]; 316 u32 last_cleaned; 317 u32 next_to_check; 318 struct igb_rx_buffer *rx_buffers; 319 bus_dma_tag_t rxtag; /* dma tag for tx */ 320 bus_dmamap_t rx_spare_map; 321 /* 322 * First/last mbuf pointers, for 323 * collecting multisegment RX packets. 324 */ 325 struct mbuf *fmp; 326 struct mbuf *lmp; 327 328 u32 bytes; 329 u32 eitr_setting; 330 331 struct resource *res; 332 void *tag; 333 334 /* Soft stats */ 335 u64 rx_irq; 336 u64 rx_split_packets; 337 u64 rx_packets; 338 u64 rx_bytes; 339}; 340 341struct adapter { 342 struct ifnet *ifp; 343 struct e1000_hw hw; 344 345 /* FreeBSD operating-system-specific structures. */ 346 struct e1000_osdep osdep; 347 struct device *dev; 348 349 struct resource *pci_mem; 350 struct resource *msix_mem; 351 struct resource *res; 352 void *tag; 353 u32 eims_mask; 354 355 int linkvec; 356 int link_mask; 357 int link_irq; 358 359 struct ifmedia media; 360 struct callout timer; 361 int msix; /* total vectors allocated */ 362 int if_flags; 363 int max_frame_size; 364 int min_frame_size; 365 struct mtx core_mtx; 366 int igb_insert_vlan_header; 367 struct task link_task; 368 struct task rxtx_task; 369 struct taskqueue *tq; /* private task queue */ 370 u16 num_queues; 371 372 eventhandler_tag vlan_attach; 373 eventhandler_tag vlan_detach; 374 u32 num_vlans; 375 376 /* Management and WOL features */ 377 int wol; 378 int has_manage; 379 380 /* Info about the board itself */ 381 u8 link_active; 382 u16 link_speed; 383 u16 link_duplex; 384 u32 smartspeed; 385 386 /* 387 * Transmit rings 388 */ 389 struct tx_ring *tx_rings; 390 u16 num_tx_desc; 391 u32 txd_cmd; 392 393 /* 394 * Receive rings 395 */ 396 struct rx_ring *rx_rings; 397 bool rx_hdr_split; 398 u16 num_rx_desc; 399 int rx_process_limit; 400 u32 rx_mbuf_sz; 401 u32 rx_mask; 402 403 /* Misc stats maintained by the driver */ 404 unsigned long dropped_pkts; 405 unsigned long mbuf_defrag_failed; 406 unsigned long mbuf_header_failed; 407 unsigned long mbuf_packet_failed; 408 unsigned long no_tx_map_avail; 409 unsigned long no_tx_dma_setup; 410 unsigned long watchdog_events; 411 unsigned long rx_overruns; 412 413 boolean_t in_detach; 414 415#ifdef IGB_IEEE1588 416 /* IEEE 1588 precision time support */ 417 struct cyclecounter cycles; 418 struct nettimer clock; 419 struct nettime_compare compare; 420 struct hwtstamp_ctrl hwtstamp; 421#endif 422 423 struct e1000_hw_stats stats; 424}; 425 426/* ****************************************************************************** 427 * vendor_info_array 428 * 429 * This array contains the list of Subvendor/Subdevice IDs on which the driver 430 * should load. 431 * 432 * ******************************************************************************/ 433typedef struct _igb_vendor_info_t { 434 unsigned int vendor_id; 435 unsigned int device_id; 436 unsigned int subvendor_id; 437 unsigned int subdevice_id; 438 unsigned int index; 439} igb_vendor_info_t; 440 441 442struct igb_tx_buffer { 443 int next_eop; /* Index of the desc to watch */ 444 struct mbuf *m_head; 445 bus_dmamap_t map; /* bus_dma map for packet */ 446}; 447 448struct igb_rx_buffer { 449 struct mbuf *m_head; 450 struct mbuf *m_pack; 451 bus_dmamap_t map; /* bus_dma map for packet */ 452}; 453 454#define IGB_CORE_LOCK_INIT(_sc, _name) \ 455 mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF) 456#define IGB_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 457#define IGB_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 458#define IGB_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 459#define IGB_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 460#define IGB_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 461#define IGB_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 462#define IGB_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 463#define IGB_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 464#define IGB_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 465#define IGB_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 466#define IGB_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 467#define IGB_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 468 469#endif /* _IGB_H_DEFINED_ */ 470 471 472