if_igb.h revision 297187
1176667Sjfv/****************************************************************************** 2176667Sjfv 3286833Ssbruno Copyright (c) 2001-2015, Intel Corporation 4176667Sjfv All rights reserved. 5176667Sjfv 6176667Sjfv Redistribution and use in source and binary forms, with or without 7176667Sjfv modification, are permitted provided that the following conditions are met: 8176667Sjfv 9176667Sjfv 1. Redistributions of source code must retain the above copyright notice, 10176667Sjfv this list of conditions and the following disclaimer. 11176667Sjfv 12176667Sjfv 2. Redistributions in binary form must reproduce the above copyright 13176667Sjfv notice, this list of conditions and the following disclaimer in the 14176667Sjfv documentation and/or other materials provided with the distribution. 15176667Sjfv 16176667Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17176667Sjfv contributors may be used to endorse or promote products derived from 18176667Sjfv this software without specific prior written permission. 19176667Sjfv 20176667Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21176667Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22176667Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23176667Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24176667Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25176667Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26176667Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27176667Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28176667Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29176667Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30176667Sjfv POSSIBILITY OF SUCH DAMAGE. 31176667Sjfv 32176667Sjfv******************************************************************************/ 33176667Sjfv/*$FreeBSD: head/sys/dev/e1000/if_igb.h 297187 2016-03-22 12:40:09Z tuexen $*/ 34176667Sjfv 35287465Ssbruno#ifndef _IF_IGB_H_ 36287465Ssbruno#define _IF_IGB_H_ 37176667Sjfv 38287465Ssbruno#include <sys/param.h> 39287465Ssbruno#include <sys/systm.h> 40287465Ssbruno#ifndef IGB_LEGACY_TX 41287465Ssbruno#include <sys/buf_ring.h> 42287465Ssbruno#endif 43287465Ssbruno#include <sys/bus.h> 44287465Ssbruno#include <sys/endian.h> 45287465Ssbruno#include <sys/kernel.h> 46287465Ssbruno#include <sys/kthread.h> 47287465Ssbruno#include <sys/malloc.h> 48287465Ssbruno#include <sys/mbuf.h> 49287465Ssbruno#include <sys/module.h> 50287465Ssbruno#include <sys/rman.h> 51287465Ssbruno#include <sys/socket.h> 52287465Ssbruno#include <sys/sockio.h> 53287465Ssbruno#include <sys/sysctl.h> 54287465Ssbruno#include <sys/taskqueue.h> 55287465Ssbruno#include <sys/eventhandler.h> 56287465Ssbruno#include <sys/pcpu.h> 57287465Ssbruno#include <sys/smp.h> 58287465Ssbruno#include <machine/smp.h> 59287465Ssbruno#include <machine/bus.h> 60287465Ssbruno#include <machine/resource.h> 61287465Ssbruno 62287465Ssbruno#include <net/bpf.h> 63287465Ssbruno#include <net/ethernet.h> 64287465Ssbruno#include <net/if.h> 65287465Ssbruno#include <net/if_var.h> 66287465Ssbruno#include <net/if_arp.h> 67287465Ssbruno#include <net/if_dl.h> 68287465Ssbruno#include <net/if_media.h> 69287465Ssbruno#ifdef RSS 70287465Ssbruno#include <net/rss_config.h> 71287465Ssbruno#include <netinet/in_rss.h> 72287465Ssbruno#endif 73287465Ssbruno 74287465Ssbruno#include <net/if_types.h> 75287465Ssbruno#include <net/if_vlan_var.h> 76287465Ssbruno 77287465Ssbruno#include <netinet/in_systm.h> 78287465Ssbruno#include <netinet/in.h> 79287465Ssbruno#include <netinet/if_ether.h> 80287465Ssbruno#include <netinet/ip.h> 81287465Ssbruno#include <netinet/ip6.h> 82287465Ssbruno#include <netinet/tcp.h> 83287465Ssbruno#include <netinet/tcp_lro.h> 84287465Ssbruno#include <netinet/udp.h> 85287465Ssbruno 86287465Ssbruno#include <machine/in_cksum.h> 87287465Ssbruno#include <dev/led/led.h> 88287465Ssbruno#include <dev/pci/pcivar.h> 89287465Ssbruno#include <dev/pci/pcireg.h> 90287465Ssbruno 91287465Ssbruno#include "e1000_api.h" 92287465Ssbruno#include "e1000_82575.h" 93287465Ssbruno 94176667Sjfv/* Tunables */ 95176667Sjfv/* 96176667Sjfv * IGB_TXD: Maximum number of Transmit Descriptors 97176667Sjfv * 98176667Sjfv * This value is the number of transmit descriptors allocated by the driver. 99176667Sjfv * Increasing this value allows the driver to queue more transmits. Each 100176667Sjfv * descriptor is 16 bytes. 101176667Sjfv * Since TDLEN should be multiple of 128bytes, the number of transmit 102176667Sjfv * desscriptors should meet the following condition. 103176667Sjfv * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 104176667Sjfv */ 105205869Sjfv#define IGB_MIN_TXD 256 106205869Sjfv#define IGB_DEFAULT_TXD 1024 107176667Sjfv#define IGB_MAX_TXD 4096 108176667Sjfv 109176667Sjfv/* 110234665Semaste * IGB_RXD: Maximum number of Receive Descriptors 111176667Sjfv * 112176667Sjfv * This value is the number of receive descriptors allocated by the driver. 113176667Sjfv * Increasing this value allows the driver to buffer more incoming packets. 114176667Sjfv * Each descriptor is 16 bytes. A receive buffer is also allocated for each 115176667Sjfv * descriptor. The maximum MTU size is 16110. 116176667Sjfv * Since TDLEN should be multiple of 128bytes, the number of transmit 117176667Sjfv * desscriptors should meet the following condition. 118176667Sjfv * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 119176667Sjfv */ 120205869Sjfv#define IGB_MIN_RXD 256 121205869Sjfv#define IGB_DEFAULT_RXD 1024 122176667Sjfv#define IGB_MAX_RXD 4096 123176667Sjfv 124176667Sjfv/* 125176667Sjfv * IGB_TIDV - Transmit Interrupt Delay Value 126176667Sjfv * Valid Range: 0-65535 (0=off) 127176667Sjfv * Default Value: 64 128176667Sjfv * This value delays the generation of transmit interrupts in units of 129176667Sjfv * 1.024 microseconds. Transmit interrupt reduction can improve CPU 130176667Sjfv * efficiency if properly tuned for specific network traffic. If the 131176667Sjfv * system is reporting dropped transmits, this value may be set too high 132176667Sjfv * causing the driver to run out of available transmit descriptors. 133176667Sjfv */ 134176667Sjfv#define IGB_TIDV 64 135176667Sjfv 136176667Sjfv/* 137176667Sjfv * IGB_TADV - Transmit Absolute Interrupt Delay Value 138176667Sjfv * Valid Range: 0-65535 (0=off) 139176667Sjfv * Default Value: 64 140176667Sjfv * This value, in units of 1.024 microseconds, limits the delay in which a 141176667Sjfv * transmit interrupt is generated. Useful only if IGB_TIDV is non-zero, 142176667Sjfv * this value ensures that an interrupt is generated after the initial 143176667Sjfv * packet is sent on the wire within the set amount of time. Proper tuning, 144176667Sjfv * along with IGB_TIDV, may improve traffic throughput in specific 145176667Sjfv * network conditions. 146176667Sjfv */ 147176667Sjfv#define IGB_TADV 64 148176667Sjfv 149176667Sjfv/* 150176667Sjfv * IGB_RDTR - Receive Interrupt Delay Timer (Packet Timer) 151176667Sjfv * Valid Range: 0-65535 (0=off) 152176667Sjfv * Default Value: 0 153176667Sjfv * This value delays the generation of receive interrupts in units of 1.024 154176667Sjfv * microseconds. Receive interrupt reduction can improve CPU efficiency if 155176667Sjfv * properly tuned for specific network traffic. Increasing this value adds 156176667Sjfv * extra latency to frame reception and can end up decreasing the throughput 157176667Sjfv * of TCP traffic. If the system is reporting dropped receives, this value 158176667Sjfv * may be set too high, causing the driver to run out of available receive 159176667Sjfv * descriptors. 160176667Sjfv * 161176667Sjfv * CAUTION: When setting IGB_RDTR to a value other than 0, adapters 162176667Sjfv * may hang (stop transmitting) under certain network conditions. 163176667Sjfv * If this occurs a WATCHDOG message is logged in the system 164176667Sjfv * event log. In addition, the controller is automatically reset, 165176667Sjfv * restoring the network connection. To eliminate the potential 166176667Sjfv * for the hang ensure that IGB_RDTR is set to 0. 167176667Sjfv */ 168176667Sjfv#define IGB_RDTR 0 169176667Sjfv 170176667Sjfv/* 171176667Sjfv * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 172176667Sjfv * Valid Range: 0-65535 (0=off) 173176667Sjfv * Default Value: 64 174176667Sjfv * This value, in units of 1.024 microseconds, limits the delay in which a 175176667Sjfv * receive interrupt is generated. Useful only if IGB_RDTR is non-zero, 176176667Sjfv * this value ensures that an interrupt is generated after the initial 177176667Sjfv * packet is received within the set amount of time. Proper tuning, 178176667Sjfv * along with IGB_RDTR, may improve traffic throughput in specific network 179176667Sjfv * conditions. 180176667Sjfv */ 181176667Sjfv#define IGB_RADV 64 182176667Sjfv 183176667Sjfv/* 184176667Sjfv * This parameter controls the duration of transmit watchdog timer. 185176667Sjfv */ 186200243Sjfv#define IGB_WATCHDOG (10 * hz) 187176667Sjfv 188176667Sjfv/* 189176667Sjfv * This parameter controls when the driver calls the routine to reclaim 190220375Sjfv * transmit descriptors. Cleaning earlier seems a win. 191176667Sjfv */ 192220375Sjfv#define IGB_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 2) 193176667Sjfv 194176667Sjfv/* 195176667Sjfv * This parameter controls whether or not autonegotation is enabled. 196176667Sjfv * 0 - Disable autonegotiation 197176667Sjfv * 1 - Enable autonegotiation 198176667Sjfv */ 199176667Sjfv#define DO_AUTO_NEG 1 200176667Sjfv 201176667Sjfv/* 202176667Sjfv * This parameter control whether or not the driver will wait for 203176667Sjfv * autonegotiation to complete. 204176667Sjfv * 1 - Wait for autonegotiation to complete 205176667Sjfv * 0 - Don't wait for autonegotiation to complete 206176667Sjfv */ 207176667Sjfv#define WAIT_FOR_AUTO_NEG_DEFAULT 0 208176667Sjfv 209176667Sjfv/* Tunables -- End */ 210176667Sjfv 211176667Sjfv#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 212176667Sjfv ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 213176667Sjfv ADVERTISE_1000_FULL) 214176667Sjfv 215176667Sjfv#define AUTO_ALL_MODES 0 216176667Sjfv 217176667Sjfv/* PHY master/slave setting */ 218176667Sjfv#define IGB_MASTER_SLAVE e1000_ms_hw_default 219176667Sjfv 220256200Sjfv/* Support AutoMediaDetect for Marvell M88 PHY in i354 */ 221256200Sjfv#define IGB_MEDIA_RESET (1 << 0) 222256200Sjfv 223176667Sjfv/* 224176667Sjfv * Micellaneous constants 225176667Sjfv */ 226287465Ssbruno#define IGB_INTEL_VENDOR_ID 0x8086 227176667Sjfv 228176667Sjfv#define IGB_JUMBO_PBA 0x00000028 229176667Sjfv#define IGB_DEFAULT_PBA 0x00000030 230176667Sjfv#define IGB_SMARTSPEED_DOWNSHIFT 3 231176667Sjfv#define IGB_SMARTSPEED_MAX 15 232190872Sjfv#define IGB_MAX_LOOP 10 233203049Sjfv 234256200Sjfv#define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : \ 235256200Sjfv ((hw->mac.type <= e1000_82576) ? 16 : 8)) 236176667Sjfv#define IGB_RX_HTHRESH 8 237256200Sjfv#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ 238256200Sjfv adapter->msix_mem) ? 1 : 4) 239176667Sjfv 240256200Sjfv#define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) 241203049Sjfv#define IGB_TX_HTHRESH 1 242218530Sjfv#define IGB_TX_WTHRESH ((hw->mac.type != e1000_82575 && \ 243203049Sjfv adapter->msix_mem) ? 1 : 16) 244203049Sjfv 245176667Sjfv#define MAX_NUM_MULTICAST_ADDRESSES 128 246176667Sjfv#define PCI_ANY_ID (~0U) 247176667Sjfv#define ETHER_ALIGN 2 248176667Sjfv#define IGB_TX_BUFFER_SIZE ((uint32_t) 1514) 249176667Sjfv#define IGB_FC_PAUSE_TIME 0x0680 250176667Sjfv#define IGB_EEPROM_APME 0x400; 251228387Sjfv/* Queue minimum free for use */ 252228387Sjfv#define IGB_QUEUE_THRESHOLD (adapter->num_tx_desc / 8) 253176667Sjfv 254176667Sjfv/* 255176667Sjfv * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 256176667Sjfv * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 257176667Sjfv * also optimize cache line size effect. H/W supports up to cache line size 128. 258176667Sjfv */ 259176667Sjfv#define IGB_DBA_ALIGN 128 260176667Sjfv 261176667Sjfv#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 262176667Sjfv 263176667Sjfv/* PCI Config defines */ 264176667Sjfv#define IGB_MSIX_BAR 3 265176667Sjfv 266176667Sjfv/* Defines for printing debug information */ 267176667Sjfv#define DEBUG_INIT 0 268176667Sjfv#define DEBUG_IOCTL 0 269176667Sjfv#define DEBUG_HW 0 270176667Sjfv 271176667Sjfv#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 272176667Sjfv#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 273176667Sjfv#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 274176667Sjfv#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 275176667Sjfv#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 276176667Sjfv#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 277176667Sjfv#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 278176667Sjfv#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 279176667Sjfv#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 280176667Sjfv 281295906Smarius#define IGB_MAX_SCATTER 40 282194865Sjfv#define IGB_VFTA_SIZE 128 283194865Sjfv#define IGB_BR_SIZE 4096 /* ring buf size */ 284176667Sjfv#define IGB_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 285176667Sjfv#define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */ 286256200Sjfv#define IGB_TXPBSIZE 20408 287190872Sjfv#define IGB_HDR_BUF 128 288200243Sjfv#define IGB_PKTTYPE_MASK 0x0000FFF0 289256200Sjfv#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ 290176667Sjfv#define ETH_ZLEN 60 291176667Sjfv#define ETH_ADDR_LEN 6 292176667Sjfv 293190872Sjfv/* Offload bits in mbuf flag */ 294297187Stuexen#if __FreeBSD_version >= 1000000 295297187Stuexen#define CSUM_OFFLOAD_IPV4 (CSUM_IP|CSUM_IP_TCP|CSUM_IP_UDP|CSUM_IP_SCTP) 296297187Stuexen#define CSUM_OFFLOAD_IPV6 (CSUM_IP6_TCP|CSUM_IP6_UDP|CSUM_IP6_SCTP) 297297187Stuexen#define CSUM_OFFLOAD (CSUM_OFFLOAD_IPV4|CSUM_OFFLOAD_IPV6) 298297187Stuexen#elif __FreeBSD_version >= 800000 299190872Sjfv#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 300190872Sjfv#else 301190872Sjfv#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 302190872Sjfv#endif 303190872Sjfv 304203049Sjfv/* Define the starting Interrupt rate per Queue */ 305203049Sjfv#define IGB_INTS_PER_SEC 8000 306215781Sjfv#define IGB_DEFAULT_ITR ((1000000/IGB_INTS_PER_SEC) << 2) 307203049Sjfv 308182416Sjfv#define IGB_LINK_ITR 2000 309256200Sjfv#define I210_LINK_DELAY 1000 310182416Sjfv 311181027Sjfv/* Precision Time Sync (IEEE 1588) defines */ 312181027Sjfv#define ETHERTYPE_IEEE1588 0x88F7 313181027Sjfv#define PICOSECS_PER_TICK 20833 314181027Sjfv#define TSYNC_PORT 319 /* UDP port for the protocol */ 315176667Sjfv 316176667Sjfv/* 317176667Sjfv * Bus dma allocation structure used by 318176667Sjfv * e1000_dma_malloc and e1000_dma_free. 319176667Sjfv */ 320176667Sjfvstruct igb_dma_alloc { 321176667Sjfv bus_addr_t dma_paddr; 322176667Sjfv caddr_t dma_vaddr; 323176667Sjfv bus_dma_tag_t dma_tag; 324176667Sjfv bus_dmamap_t dma_map; 325176667Sjfv bus_dma_segment_t dma_seg; 326176667Sjfv int dma_nseg; 327176667Sjfv}; 328176667Sjfv 329176667Sjfv 330176667Sjfv/* 331203049Sjfv** Driver queue struct: this is the interrupt container 332203049Sjfv** for the associated tx and rx ring. 333203049Sjfv*/ 334203049Sjfvstruct igb_queue { 335203049Sjfv struct adapter *adapter; 336203049Sjfv u32 msix; /* This queue's MSIX vector */ 337203049Sjfv u32 eims; /* This queue's EIMS bit */ 338203049Sjfv u32 eitr_setting; 339203049Sjfv struct resource *res; 340203049Sjfv void *tag; 341203049Sjfv struct tx_ring *txr; 342203049Sjfv struct rx_ring *rxr; 343203049Sjfv struct task que_task; 344203049Sjfv struct taskqueue *tq; 345203049Sjfv u64 irqs; 346203049Sjfv}; 347203049Sjfv 348203049Sjfv/* 349256200Sjfv * The transmit ring, one per queue 350176667Sjfv */ 351176667Sjfvstruct tx_ring { 352256200Sjfv struct adapter *adapter; 353256200Sjfv struct mtx tx_mtx; 354176667Sjfv u32 me; 355256200Sjfv int watchdog_time; 356256200Sjfv union e1000_adv_tx_desc *tx_base; 357256200Sjfv struct igb_tx_buf *tx_buffers; 358203049Sjfv struct igb_dma_alloc txdma; 359176667Sjfv volatile u16 tx_avail; 360256200Sjfv u16 next_avail_desc; 361256200Sjfv u16 next_to_clean; 362256200Sjfv u16 num_desc; 363256200Sjfv enum { 364256200Sjfv IGB_QUEUE_IDLE = 1, 365256200Sjfv IGB_QUEUE_WORKING = 2, 366256200Sjfv IGB_QUEUE_HUNG = 4, 367256200Sjfv IGB_QUEUE_DEPLETED = 8, 368256200Sjfv } queue_status; 369256200Sjfv u32 txd_cmd; 370256200Sjfv bus_dma_tag_t txtag; 371256200Sjfv char mtx_name[16]; 372248908Sjfv#ifndef IGB_LEGACY_TX 373194865Sjfv struct buf_ring *br; 374240968Sjhb struct task txq_task; 375194865Sjfv#endif 376256200Sjfv u32 bytes; /* used for AIM */ 377203049Sjfv u32 packets; 378256200Sjfv /* Soft Stats */ 379256200Sjfv unsigned long tso_tx; 380256200Sjfv unsigned long no_tx_map_avail; 381256200Sjfv unsigned long no_tx_dma_setup; 382176667Sjfv u64 no_desc_avail; 383256200Sjfv u64 total_packets; 384176667Sjfv}; 385176667Sjfv 386176667Sjfv/* 387203049Sjfv * Receive ring: one per queue 388176667Sjfv */ 389176667Sjfvstruct rx_ring { 390176667Sjfv struct adapter *adapter; 391176667Sjfv u32 me; 392203049Sjfv struct igb_dma_alloc rxdma; 393176667Sjfv union e1000_adv_rx_desc *rx_base; 394181027Sjfv struct lro_ctrl lro; 395194865Sjfv bool lro_enabled; 396194865Sjfv bool hdr_split; 397176667Sjfv struct mtx rx_mtx; 398182416Sjfv char mtx_name[16]; 399205869Sjfv u32 next_to_refresh; 400176667Sjfv u32 next_to_check; 401200243Sjfv struct igb_rx_buf *rx_buffers; 402205869Sjfv bus_dma_tag_t htag; /* dma tag for rx head */ 403205869Sjfv bus_dma_tag_t ptag; /* dma tag for rx packet */ 404176667Sjfv /* 405176667Sjfv * First/last mbuf pointers, for 406176667Sjfv * collecting multisegment RX packets. 407176667Sjfv */ 408176667Sjfv struct mbuf *fmp; 409176667Sjfv struct mbuf *lmp; 410182416Sjfv 411182416Sjfv u32 bytes; 412203049Sjfv u32 packets; 413209616Sjfv int rdt; 414209616Sjfv int rdh; 415182416Sjfv 416176667Sjfv /* Soft stats */ 417190872Sjfv u64 rx_split_packets; 418203049Sjfv u64 rx_discarded; 419176667Sjfv u64 rx_packets; 420176667Sjfv u64 rx_bytes; 421176667Sjfv}; 422176667Sjfv 423176667Sjfvstruct adapter { 424256200Sjfv struct ifnet *ifp; 425256200Sjfv struct e1000_hw hw; 426176667Sjfv 427256200Sjfv struct e1000_osdep osdep; 428256200Sjfv struct device *dev; 429256200Sjfv struct cdev *led_dev; 430176667Sjfv 431256200Sjfv struct resource *pci_mem; 432256200Sjfv struct resource *msix_mem; 433256200Sjfv int memrid; 434176667Sjfv 435256200Sjfv /* 436256200Sjfv * Interrupt resources: this set is 437256200Sjfv * either used for legacy, or for Link 438256200Sjfv * when doing MSIX 439256200Sjfv */ 440256200Sjfv void *tag; 441256200Sjfv struct resource *res; 442176667Sjfv 443256200Sjfv struct ifmedia media; 444256200Sjfv struct callout timer; 445256200Sjfv int msix; 446256200Sjfv int if_flags; 447256200Sjfv int pause_frames; 448194865Sjfv 449256200Sjfv struct mtx core_mtx; 450190872Sjfv 451256200Sjfv eventhandler_tag vlan_attach; 452256200Sjfv eventhandler_tag vlan_detach; 453176667Sjfv 454256200Sjfv u16 num_vlans; 455256200Sjfv u16 num_queues; 456256200Sjfv 457215781Sjfv /* 458215781Sjfv ** Shadow VFTA table, this is needed because 459215781Sjfv ** the real vlan filter table gets cleared during 460215781Sjfv ** a soft reset and the driver needs to be able 461215781Sjfv ** to repopulate it. 462215781Sjfv */ 463256200Sjfv u32 shadow_vfta[IGB_VFTA_SIZE]; 464215781Sjfv 465215781Sjfv /* Info about the interface */ 466256200Sjfv u32 optics; 467256200Sjfv u32 fc; /* local flow ctrl setting */ 468256200Sjfv int advertise; /* link speeds */ 469256200Sjfv bool link_active; 470256200Sjfv u16 max_frame_size; 471256200Sjfv u16 num_segs; 472256200Sjfv u16 link_speed; 473256200Sjfv bool link_up; 474256200Sjfv u32 linkvec; 475256200Sjfv u16 link_duplex; 476256200Sjfv u32 dmac; 477256200Sjfv int link_mask; 478176667Sjfv 479256200Sjfv /* Flags */ 480256200Sjfv u32 flags; 481256200Sjfv 482256200Sjfv /* Mbuf cluster size */ 483256200Sjfv u32 rx_mbuf_sz; 484256200Sjfv 485256200Sjfv /* Support for pluggable optics */ 486256200Sjfv bool sfp_probe; 487256200Sjfv struct task link_task; /* Link tasklet */ 488256200Sjfv struct task mod_task; /* SFP tasklet */ 489256200Sjfv struct task msf_task; /* Multispeed Fiber */ 490256200Sjfv struct taskqueue *tq; 491256200Sjfv 492256200Sjfv /* 493256200Sjfv ** Queues: 494256200Sjfv ** This is the irq holder, it has 495256200Sjfv ** and RX/TX pair or rings associated 496256200Sjfv ** with it. 497256200Sjfv */ 498203049Sjfv struct igb_queue *queues; 499203049Sjfv 500176667Sjfv /* 501256200Sjfv * Transmit rings: 502256200Sjfv * Allocated at run time, an array of rings. 503176667Sjfv */ 504176667Sjfv struct tx_ring *tx_rings; 505256200Sjfv u32 num_tx_desc; 506176667Sjfv 507256200Sjfv /* 508256200Sjfv * Receive rings: 509256200Sjfv * Allocated at run time, an array of rings. 510176667Sjfv */ 511176667Sjfv struct rx_ring *rx_rings; 512256200Sjfv u64 que_mask; 513256200Sjfv u32 num_rx_desc; 514176667Sjfv 515256200Sjfv /* Multicast array memory */ 516256200Sjfv u8 *mta; 517256200Sjfv 518176667Sjfv /* Misc stats maintained by the driver */ 519293854Smarius unsigned long device_control; 520256200Sjfv unsigned long dropped_pkts; 521293854Smarius unsigned long eint_mask; 522293854Smarius unsigned long int_mask; 523293854Smarius unsigned long link_irq; 524256200Sjfv unsigned long mbuf_defrag_failed; 525256200Sjfv unsigned long no_tx_dma_setup; 526256200Sjfv unsigned long packet_buf_alloc_rx; 527256200Sjfv unsigned long packet_buf_alloc_tx; 528293854Smarius unsigned long rx_control; 529293854Smarius unsigned long rx_overruns; 530293854Smarius unsigned long watchdog_events; 531293854Smarius 532256200Sjfv /* Used in pf and vf */ 533256200Sjfv void *stats; 534176667Sjfv 535256200Sjfv int enable_aim; 536256200Sjfv int has_manage; 537256200Sjfv int wol; 538256200Sjfv int rx_process_limit; 539292670Ssbruno int tx_process_limit; 540256200Sjfv u16 vf_ifp; /* a VF interface */ 541256200Sjfv bool in_detach; /* Used only in igb_ioctl */ 542176667Sjfv 543176667Sjfv}; 544176667Sjfv 545176667Sjfv/* ****************************************************************************** 546176667Sjfv * vendor_info_array 547176667Sjfv * 548176667Sjfv * This array contains the list of Subvendor/Subdevice IDs on which the driver 549176667Sjfv * should load. 550176667Sjfv * 551176667Sjfv * ******************************************************************************/ 552176667Sjfvtypedef struct _igb_vendor_info_t { 553176667Sjfv unsigned int vendor_id; 554176667Sjfv unsigned int device_id; 555176667Sjfv unsigned int subvendor_id; 556176667Sjfv unsigned int subdevice_id; 557176667Sjfv unsigned int index; 558176667Sjfv} igb_vendor_info_t; 559176667Sjfv 560256200Sjfvstruct igb_tx_buf { 561256200Sjfv union e1000_adv_tx_desc *eop; 562256200Sjfv struct mbuf *m_head; 563256200Sjfv bus_dmamap_t map; 564176667Sjfv}; 565176667Sjfv 566200243Sjfvstruct igb_rx_buf { 567190872Sjfv struct mbuf *m_head; 568190872Sjfv struct mbuf *m_pack; 569205869Sjfv bus_dmamap_t hmap; /* bus_dma map for header */ 570205869Sjfv bus_dmamap_t pmap; /* bus_dma map for packet */ 571190872Sjfv}; 572190872Sjfv 573220375Sjfv/* 574220375Sjfv** Find the number of unrefreshed RX descriptors 575220375Sjfv*/ 576220375Sjfvstatic inline u16 577220375Sjfvigb_rx_unrefreshed(struct rx_ring *rxr) 578220375Sjfv{ 579220375Sjfv struct adapter *adapter = rxr->adapter; 580220375Sjfv 581220375Sjfv if (rxr->next_to_check > rxr->next_to_refresh) 582220375Sjfv return (rxr->next_to_check - rxr->next_to_refresh - 1); 583220375Sjfv else 584220375Sjfv return ((adapter->num_rx_desc + rxr->next_to_check) - 585220375Sjfv rxr->next_to_refresh - 1); 586220375Sjfv} 587220375Sjfv 588176667Sjfv#define IGB_CORE_LOCK_INIT(_sc, _name) \ 589176667Sjfv mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF) 590176667Sjfv#define IGB_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 591203049Sjfv#define IGB_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 592203049Sjfv#define IGB_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 593203049Sjfv#define IGB_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 594203049Sjfv 595200243Sjfv#define IGB_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 596200243Sjfv#define IGB_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 597203049Sjfv#define IGB_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 598200243Sjfv#define IGB_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 599203049Sjfv#define IGB_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 600203049Sjfv 601203049Sjfv#define IGB_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 602200243Sjfv#define IGB_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 603176667Sjfv#define IGB_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 604209611Sjfv#define IGB_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rx_mtx, MA_OWNED) 605176667Sjfv 606209611Sjfv#define UPDATE_VF_REG(reg, last, cur) \ 607209611Sjfv{ \ 608209611Sjfv u32 new = E1000_READ_REG(hw, reg); \ 609209611Sjfv if (new < last) \ 610209611Sjfv cur += 0x100000000LL; \ 611209611Sjfv last = new; \ 612209611Sjfv cur &= 0xFFFFFFFF00000000LL; \ 613209611Sjfv cur |= new; \ 614209611Sjfv} 615209611Sjfv 616221187Sjfv#if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504 617209616Sjfvstatic __inline int 618209616Sjfvdrbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 619209616Sjfv{ 620209616Sjfv#ifdef ALTQ 621209616Sjfv if (ALTQ_IS_ENABLED(&ifp->if_snd)) 622209616Sjfv return (1); 623209616Sjfv#endif 624209616Sjfv return (!buf_ring_empty(br)); 625209616Sjfv} 626209616Sjfv#endif 627209616Sjfv 628287465Ssbruno#endif /* _IF_IGB_H_ */ 629176667Sjfv 630176667Sjfv 631