1176667Sjfv/****************************************************************************** 2176667Sjfv 3286833Ssbruno Copyright (c) 2001-2015, Intel Corporation 4176667Sjfv All rights reserved. 5176667Sjfv 6176667Sjfv Redistribution and use in source and binary forms, with or without 7176667Sjfv modification, are permitted provided that the following conditions are met: 8176667Sjfv 9176667Sjfv 1. Redistributions of source code must retain the above copyright notice, 10176667Sjfv this list of conditions and the following disclaimer. 11176667Sjfv 12176667Sjfv 2. Redistributions in binary form must reproduce the above copyright 13176667Sjfv notice, this list of conditions and the following disclaimer in the 14176667Sjfv documentation and/or other materials provided with the distribution. 15176667Sjfv 16176667Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17176667Sjfv contributors may be used to endorse or promote products derived from 18176667Sjfv this software without specific prior written permission. 19176667Sjfv 20176667Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21176667Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22176667Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23176667Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24176667Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25176667Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26176667Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27176667Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28176667Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29176667Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30176667Sjfv POSSIBILITY OF SUCH DAMAGE. 31176667Sjfv 32176667Sjfv******************************************************************************/ 33176667Sjfv/*$FreeBSD$*/ 34176667Sjfv 35287465Ssbruno#ifndef _IF_IGB_H_ 36287465Ssbruno#define _IF_IGB_H_ 37176667Sjfv 38299182Ssbruno#ifdef ALTQ 39299182Ssbruno#define IGB_LEGACY_TX 40299182Ssbruno#endif 41299182Ssbruno 42287465Ssbruno#include <sys/param.h> 43287465Ssbruno#include <sys/systm.h> 44287465Ssbruno#ifndef IGB_LEGACY_TX 45287465Ssbruno#include <sys/buf_ring.h> 46287465Ssbruno#endif 47287465Ssbruno#include <sys/bus.h> 48287465Ssbruno#include <sys/endian.h> 49287465Ssbruno#include <sys/kernel.h> 50287465Ssbruno#include <sys/kthread.h> 51287465Ssbruno#include <sys/malloc.h> 52287465Ssbruno#include <sys/mbuf.h> 53287465Ssbruno#include <sys/module.h> 54287465Ssbruno#include <sys/rman.h> 55287465Ssbruno#include <sys/socket.h> 56287465Ssbruno#include <sys/sockio.h> 57287465Ssbruno#include <sys/sysctl.h> 58287465Ssbruno#include <sys/taskqueue.h> 59287465Ssbruno#include <sys/eventhandler.h> 60287465Ssbruno#include <sys/pcpu.h> 61287465Ssbruno#include <sys/smp.h> 62287465Ssbruno#include <machine/smp.h> 63287465Ssbruno#include <machine/bus.h> 64287465Ssbruno#include <machine/resource.h> 65287465Ssbruno 66287465Ssbruno#include <net/bpf.h> 67287465Ssbruno#include <net/ethernet.h> 68287465Ssbruno#include <net/if.h> 69287465Ssbruno#include <net/if_var.h> 70287465Ssbruno#include <net/if_arp.h> 71287465Ssbruno#include <net/if_dl.h> 72287465Ssbruno#include <net/if_media.h> 73287465Ssbruno#ifdef RSS 74287465Ssbruno#include <net/rss_config.h> 75287465Ssbruno#include <netinet/in_rss.h> 76287465Ssbruno#endif 77287465Ssbruno 78287465Ssbruno#include <net/if_types.h> 79287465Ssbruno#include <net/if_vlan_var.h> 80287465Ssbruno 81287465Ssbruno#include <netinet/in_systm.h> 82287465Ssbruno#include <netinet/in.h> 83287465Ssbruno#include <netinet/if_ether.h> 84287465Ssbruno#include <netinet/ip.h> 85287465Ssbruno#include <netinet/ip6.h> 86287465Ssbruno#include <netinet/tcp.h> 87287465Ssbruno#include <netinet/tcp_lro.h> 88287465Ssbruno#include <netinet/udp.h> 89287465Ssbruno 90287465Ssbruno#include <machine/in_cksum.h> 91287465Ssbruno#include <dev/led/led.h> 92287465Ssbruno#include <dev/pci/pcivar.h> 93287465Ssbruno#include <dev/pci/pcireg.h> 94287465Ssbruno 95287465Ssbruno#include "e1000_api.h" 96287465Ssbruno#include "e1000_82575.h" 97287465Ssbruno 98176667Sjfv/* Tunables */ 99176667Sjfv/* 100176667Sjfv * IGB_TXD: Maximum number of Transmit Descriptors 101176667Sjfv * 102176667Sjfv * This value is the number of transmit descriptors allocated by the driver. 103176667Sjfv * Increasing this value allows the driver to queue more transmits. Each 104176667Sjfv * descriptor is 16 bytes. 105176667Sjfv * Since TDLEN should be multiple of 128bytes, the number of transmit 106176667Sjfv * desscriptors should meet the following condition. 107176667Sjfv * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 108176667Sjfv */ 109205869Sjfv#define IGB_MIN_TXD 256 110205869Sjfv#define IGB_DEFAULT_TXD 1024 111176667Sjfv#define IGB_MAX_TXD 4096 112176667Sjfv 113176667Sjfv/* 114234665Semaste * IGB_RXD: Maximum number of Receive Descriptors 115176667Sjfv * 116176667Sjfv * This value is the number of receive descriptors allocated by the driver. 117176667Sjfv * Increasing this value allows the driver to buffer more incoming packets. 118176667Sjfv * Each descriptor is 16 bytes. A receive buffer is also allocated for each 119176667Sjfv * descriptor. The maximum MTU size is 16110. 120176667Sjfv * Since TDLEN should be multiple of 128bytes, the number of transmit 121176667Sjfv * desscriptors should meet the following condition. 122176667Sjfv * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 123176667Sjfv */ 124205869Sjfv#define IGB_MIN_RXD 256 125205869Sjfv#define IGB_DEFAULT_RXD 1024 126176667Sjfv#define IGB_MAX_RXD 4096 127176667Sjfv 128176667Sjfv/* 129176667Sjfv * IGB_TIDV - Transmit Interrupt Delay Value 130176667Sjfv * Valid Range: 0-65535 (0=off) 131176667Sjfv * Default Value: 64 132176667Sjfv * This value delays the generation of transmit interrupts in units of 133176667Sjfv * 1.024 microseconds. Transmit interrupt reduction can improve CPU 134176667Sjfv * efficiency if properly tuned for specific network traffic. If the 135176667Sjfv * system is reporting dropped transmits, this value may be set too high 136176667Sjfv * causing the driver to run out of available transmit descriptors. 137176667Sjfv */ 138176667Sjfv#define IGB_TIDV 64 139176667Sjfv 140176667Sjfv/* 141176667Sjfv * IGB_TADV - Transmit Absolute Interrupt Delay Value 142176667Sjfv * Valid Range: 0-65535 (0=off) 143176667Sjfv * Default Value: 64 144176667Sjfv * This value, in units of 1.024 microseconds, limits the delay in which a 145176667Sjfv * transmit interrupt is generated. Useful only if IGB_TIDV is non-zero, 146176667Sjfv * this value ensures that an interrupt is generated after the initial 147176667Sjfv * packet is sent on the wire within the set amount of time. Proper tuning, 148176667Sjfv * along with IGB_TIDV, may improve traffic throughput in specific 149176667Sjfv * network conditions. 150176667Sjfv */ 151176667Sjfv#define IGB_TADV 64 152176667Sjfv 153176667Sjfv/* 154176667Sjfv * IGB_RDTR - Receive Interrupt Delay Timer (Packet Timer) 155176667Sjfv * Valid Range: 0-65535 (0=off) 156176667Sjfv * Default Value: 0 157176667Sjfv * This value delays the generation of receive interrupts in units of 1.024 158176667Sjfv * microseconds. Receive interrupt reduction can improve CPU efficiency if 159176667Sjfv * properly tuned for specific network traffic. Increasing this value adds 160176667Sjfv * extra latency to frame reception and can end up decreasing the throughput 161176667Sjfv * of TCP traffic. If the system is reporting dropped receives, this value 162176667Sjfv * may be set too high, causing the driver to run out of available receive 163176667Sjfv * descriptors. 164176667Sjfv * 165176667Sjfv * CAUTION: When setting IGB_RDTR to a value other than 0, adapters 166176667Sjfv * may hang (stop transmitting) under certain network conditions. 167176667Sjfv * If this occurs a WATCHDOG message is logged in the system 168176667Sjfv * event log. In addition, the controller is automatically reset, 169176667Sjfv * restoring the network connection. To eliminate the potential 170176667Sjfv * for the hang ensure that IGB_RDTR is set to 0. 171176667Sjfv */ 172176667Sjfv#define IGB_RDTR 0 173176667Sjfv 174176667Sjfv/* 175176667Sjfv * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 176176667Sjfv * Valid Range: 0-65535 (0=off) 177176667Sjfv * Default Value: 64 178176667Sjfv * This value, in units of 1.024 microseconds, limits the delay in which a 179176667Sjfv * receive interrupt is generated. Useful only if IGB_RDTR is non-zero, 180176667Sjfv * this value ensures that an interrupt is generated after the initial 181176667Sjfv * packet is received within the set amount of time. Proper tuning, 182176667Sjfv * along with IGB_RDTR, may improve traffic throughput in specific network 183176667Sjfv * conditions. 184176667Sjfv */ 185176667Sjfv#define IGB_RADV 64 186176667Sjfv 187176667Sjfv/* 188176667Sjfv * This parameter controls the duration of transmit watchdog timer. 189176667Sjfv */ 190200243Sjfv#define IGB_WATCHDOG (10 * hz) 191176667Sjfv 192176667Sjfv/* 193176667Sjfv * This parameter controls when the driver calls the routine to reclaim 194220375Sjfv * transmit descriptors. Cleaning earlier seems a win. 195176667Sjfv */ 196220375Sjfv#define IGB_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 2) 197176667Sjfv 198176667Sjfv/* 199176667Sjfv * This parameter controls whether or not autonegotation is enabled. 200176667Sjfv * 0 - Disable autonegotiation 201176667Sjfv * 1 - Enable autonegotiation 202176667Sjfv */ 203176667Sjfv#define DO_AUTO_NEG 1 204176667Sjfv 205176667Sjfv/* 206176667Sjfv * This parameter control whether or not the driver will wait for 207176667Sjfv * autonegotiation to complete. 208176667Sjfv * 1 - Wait for autonegotiation to complete 209176667Sjfv * 0 - Don't wait for autonegotiation to complete 210176667Sjfv */ 211176667Sjfv#define WAIT_FOR_AUTO_NEG_DEFAULT 0 212176667Sjfv 213176667Sjfv/* Tunables -- End */ 214176667Sjfv 215176667Sjfv#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 216176667Sjfv ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 217176667Sjfv ADVERTISE_1000_FULL) 218176667Sjfv 219176667Sjfv#define AUTO_ALL_MODES 0 220176667Sjfv 221176667Sjfv/* PHY master/slave setting */ 222176667Sjfv#define IGB_MASTER_SLAVE e1000_ms_hw_default 223176667Sjfv 224256200Sjfv/* Support AutoMediaDetect for Marvell M88 PHY in i354 */ 225256200Sjfv#define IGB_MEDIA_RESET (1 << 0) 226256200Sjfv 227176667Sjfv/* 228176667Sjfv * Micellaneous constants 229176667Sjfv */ 230287465Ssbruno#define IGB_INTEL_VENDOR_ID 0x8086 231176667Sjfv 232176667Sjfv#define IGB_JUMBO_PBA 0x00000028 233176667Sjfv#define IGB_DEFAULT_PBA 0x00000030 234176667Sjfv#define IGB_SMARTSPEED_DOWNSHIFT 3 235176667Sjfv#define IGB_SMARTSPEED_MAX 15 236190872Sjfv#define IGB_MAX_LOOP 10 237203049Sjfv 238256200Sjfv#define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : \ 239256200Sjfv ((hw->mac.type <= e1000_82576) ? 16 : 8)) 240176667Sjfv#define IGB_RX_HTHRESH 8 241256200Sjfv#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ 242256200Sjfv adapter->msix_mem) ? 1 : 4) 243176667Sjfv 244256200Sjfv#define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) 245203049Sjfv#define IGB_TX_HTHRESH 1 246218530Sjfv#define IGB_TX_WTHRESH ((hw->mac.type != e1000_82575 && \ 247203049Sjfv adapter->msix_mem) ? 1 : 16) 248203049Sjfv 249176667Sjfv#define MAX_NUM_MULTICAST_ADDRESSES 128 250176667Sjfv#define PCI_ANY_ID (~0U) 251176667Sjfv#define ETHER_ALIGN 2 252176667Sjfv#define IGB_TX_BUFFER_SIZE ((uint32_t) 1514) 253176667Sjfv#define IGB_FC_PAUSE_TIME 0x0680 254176667Sjfv#define IGB_EEPROM_APME 0x400; 255228387Sjfv/* Queue minimum free for use */ 256228387Sjfv#define IGB_QUEUE_THRESHOLD (adapter->num_tx_desc / 8) 257176667Sjfv 258176667Sjfv/* 259176667Sjfv * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 260176667Sjfv * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 261176667Sjfv * also optimize cache line size effect. H/W supports up to cache line size 128. 262176667Sjfv */ 263176667Sjfv#define IGB_DBA_ALIGN 128 264176667Sjfv 265176667Sjfv#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 266176667Sjfv 267176667Sjfv/* PCI Config defines */ 268176667Sjfv#define IGB_MSIX_BAR 3 269176667Sjfv 270176667Sjfv/* Defines for printing debug information */ 271176667Sjfv#define DEBUG_INIT 0 272176667Sjfv#define DEBUG_IOCTL 0 273176667Sjfv#define DEBUG_HW 0 274176667Sjfv 275176667Sjfv#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 276176667Sjfv#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 277176667Sjfv#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 278176667Sjfv#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 279176667Sjfv#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 280176667Sjfv#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 281176667Sjfv#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 282176667Sjfv#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 283176667Sjfv#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 284176667Sjfv 285295906Smarius#define IGB_MAX_SCATTER 40 286194865Sjfv#define IGB_VFTA_SIZE 128 287194865Sjfv#define IGB_BR_SIZE 4096 /* ring buf size */ 288176667Sjfv#define IGB_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 289176667Sjfv#define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */ 290256200Sjfv#define IGB_TXPBSIZE 20408 291190872Sjfv#define IGB_HDR_BUF 128 292200243Sjfv#define IGB_PKTTYPE_MASK 0x0000FFF0 293256200Sjfv#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ 294176667Sjfv#define ETH_ZLEN 60 295176667Sjfv#define ETH_ADDR_LEN 6 296176667Sjfv 297190872Sjfv/* Offload bits in mbuf flag */ 298297187Stuexen#if __FreeBSD_version >= 1000000 299297187Stuexen#define CSUM_OFFLOAD_IPV4 (CSUM_IP|CSUM_IP_TCP|CSUM_IP_UDP|CSUM_IP_SCTP) 300297187Stuexen#define CSUM_OFFLOAD_IPV6 (CSUM_IP6_TCP|CSUM_IP6_UDP|CSUM_IP6_SCTP) 301297187Stuexen#define CSUM_OFFLOAD (CSUM_OFFLOAD_IPV4|CSUM_OFFLOAD_IPV6) 302297187Stuexen#elif __FreeBSD_version >= 800000 303190872Sjfv#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 304190872Sjfv#else 305190872Sjfv#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 306190872Sjfv#endif 307190872Sjfv 308203049Sjfv/* Define the starting Interrupt rate per Queue */ 309203049Sjfv#define IGB_INTS_PER_SEC 8000 310215781Sjfv#define IGB_DEFAULT_ITR ((1000000/IGB_INTS_PER_SEC) << 2) 311203049Sjfv 312182416Sjfv#define IGB_LINK_ITR 2000 313256200Sjfv#define I210_LINK_DELAY 1000 314182416Sjfv 315181027Sjfv/* Precision Time Sync (IEEE 1588) defines */ 316181027Sjfv#define ETHERTYPE_IEEE1588 0x88F7 317181027Sjfv#define PICOSECS_PER_TICK 20833 318181027Sjfv#define TSYNC_PORT 319 /* UDP port for the protocol */ 319176667Sjfv 320176667Sjfv/* 321176667Sjfv * Bus dma allocation structure used by 322176667Sjfv * e1000_dma_malloc and e1000_dma_free. 323176667Sjfv */ 324176667Sjfvstruct igb_dma_alloc { 325176667Sjfv bus_addr_t dma_paddr; 326176667Sjfv caddr_t dma_vaddr; 327176667Sjfv bus_dma_tag_t dma_tag; 328176667Sjfv bus_dmamap_t dma_map; 329176667Sjfv bus_dma_segment_t dma_seg; 330176667Sjfv int dma_nseg; 331176667Sjfv}; 332176667Sjfv 333176667Sjfv 334176667Sjfv/* 335203049Sjfv** Driver queue struct: this is the interrupt container 336203049Sjfv** for the associated tx and rx ring. 337203049Sjfv*/ 338203049Sjfvstruct igb_queue { 339203049Sjfv struct adapter *adapter; 340203049Sjfv u32 msix; /* This queue's MSIX vector */ 341203049Sjfv u32 eims; /* This queue's EIMS bit */ 342203049Sjfv u32 eitr_setting; 343203049Sjfv struct resource *res; 344203049Sjfv void *tag; 345203049Sjfv struct tx_ring *txr; 346203049Sjfv struct rx_ring *rxr; 347203049Sjfv struct task que_task; 348203049Sjfv struct taskqueue *tq; 349203049Sjfv u64 irqs; 350203049Sjfv}; 351203049Sjfv 352203049Sjfv/* 353256200Sjfv * The transmit ring, one per queue 354176667Sjfv */ 355176667Sjfvstruct tx_ring { 356256200Sjfv struct adapter *adapter; 357256200Sjfv struct mtx tx_mtx; 358176667Sjfv u32 me; 359256200Sjfv int watchdog_time; 360256200Sjfv union e1000_adv_tx_desc *tx_base; 361256200Sjfv struct igb_tx_buf *tx_buffers; 362203049Sjfv struct igb_dma_alloc txdma; 363176667Sjfv volatile u16 tx_avail; 364256200Sjfv u16 next_avail_desc; 365256200Sjfv u16 next_to_clean; 366256200Sjfv u16 num_desc; 367256200Sjfv enum { 368256200Sjfv IGB_QUEUE_IDLE = 1, 369256200Sjfv IGB_QUEUE_WORKING = 2, 370256200Sjfv IGB_QUEUE_HUNG = 4, 371256200Sjfv IGB_QUEUE_DEPLETED = 8, 372256200Sjfv } queue_status; 373256200Sjfv u32 txd_cmd; 374256200Sjfv bus_dma_tag_t txtag; 375256200Sjfv char mtx_name[16]; 376248908Sjfv#ifndef IGB_LEGACY_TX 377194865Sjfv struct buf_ring *br; 378240968Sjhb struct task txq_task; 379194865Sjfv#endif 380256200Sjfv u32 bytes; /* used for AIM */ 381203049Sjfv u32 packets; 382256200Sjfv /* Soft Stats */ 383256200Sjfv unsigned long tso_tx; 384256200Sjfv unsigned long no_tx_map_avail; 385256200Sjfv unsigned long no_tx_dma_setup; 386176667Sjfv u64 no_desc_avail; 387256200Sjfv u64 total_packets; 388176667Sjfv}; 389176667Sjfv 390176667Sjfv/* 391203049Sjfv * Receive ring: one per queue 392176667Sjfv */ 393176667Sjfvstruct rx_ring { 394176667Sjfv struct adapter *adapter; 395176667Sjfv u32 me; 396203049Sjfv struct igb_dma_alloc rxdma; 397176667Sjfv union e1000_adv_rx_desc *rx_base; 398181027Sjfv struct lro_ctrl lro; 399194865Sjfv bool lro_enabled; 400194865Sjfv bool hdr_split; 401176667Sjfv struct mtx rx_mtx; 402182416Sjfv char mtx_name[16]; 403205869Sjfv u32 next_to_refresh; 404176667Sjfv u32 next_to_check; 405200243Sjfv struct igb_rx_buf *rx_buffers; 406205869Sjfv bus_dma_tag_t htag; /* dma tag for rx head */ 407205869Sjfv bus_dma_tag_t ptag; /* dma tag for rx packet */ 408176667Sjfv /* 409176667Sjfv * First/last mbuf pointers, for 410176667Sjfv * collecting multisegment RX packets. 411176667Sjfv */ 412176667Sjfv struct mbuf *fmp; 413176667Sjfv struct mbuf *lmp; 414182416Sjfv 415182416Sjfv u32 bytes; 416203049Sjfv u32 packets; 417209616Sjfv int rdt; 418209616Sjfv int rdh; 419182416Sjfv 420176667Sjfv /* Soft stats */ 421190872Sjfv u64 rx_split_packets; 422203049Sjfv u64 rx_discarded; 423176667Sjfv u64 rx_packets; 424176667Sjfv u64 rx_bytes; 425176667Sjfv}; 426176667Sjfv 427176667Sjfvstruct adapter { 428256200Sjfv struct ifnet *ifp; 429256200Sjfv struct e1000_hw hw; 430176667Sjfv 431256200Sjfv struct e1000_osdep osdep; 432256200Sjfv struct device *dev; 433256200Sjfv struct cdev *led_dev; 434176667Sjfv 435256200Sjfv struct resource *pci_mem; 436256200Sjfv struct resource *msix_mem; 437256200Sjfv int memrid; 438176667Sjfv 439256200Sjfv /* 440256200Sjfv * Interrupt resources: this set is 441256200Sjfv * either used for legacy, or for Link 442256200Sjfv * when doing MSIX 443256200Sjfv */ 444256200Sjfv void *tag; 445256200Sjfv struct resource *res; 446176667Sjfv 447256200Sjfv struct ifmedia media; 448256200Sjfv struct callout timer; 449256200Sjfv int msix; 450256200Sjfv int if_flags; 451256200Sjfv int pause_frames; 452194865Sjfv 453256200Sjfv struct mtx core_mtx; 454190872Sjfv 455256200Sjfv eventhandler_tag vlan_attach; 456256200Sjfv eventhandler_tag vlan_detach; 457176667Sjfv 458256200Sjfv u16 num_vlans; 459256200Sjfv u16 num_queues; 460256200Sjfv 461215781Sjfv /* 462215781Sjfv ** Shadow VFTA table, this is needed because 463215781Sjfv ** the real vlan filter table gets cleared during 464215781Sjfv ** a soft reset and the driver needs to be able 465215781Sjfv ** to repopulate it. 466215781Sjfv */ 467256200Sjfv u32 shadow_vfta[IGB_VFTA_SIZE]; 468215781Sjfv 469215781Sjfv /* Info about the interface */ 470256200Sjfv u32 optics; 471256200Sjfv u32 fc; /* local flow ctrl setting */ 472256200Sjfv int advertise; /* link speeds */ 473256200Sjfv bool link_active; 474256200Sjfv u16 max_frame_size; 475256200Sjfv u16 num_segs; 476256200Sjfv u16 link_speed; 477256200Sjfv bool link_up; 478256200Sjfv u32 linkvec; 479256200Sjfv u16 link_duplex; 480256200Sjfv u32 dmac; 481256200Sjfv int link_mask; 482176667Sjfv 483256200Sjfv /* Flags */ 484256200Sjfv u32 flags; 485256200Sjfv 486256200Sjfv /* Mbuf cluster size */ 487256200Sjfv u32 rx_mbuf_sz; 488256200Sjfv 489256200Sjfv /* Support for pluggable optics */ 490256200Sjfv bool sfp_probe; 491256200Sjfv struct task link_task; /* Link tasklet */ 492256200Sjfv struct task mod_task; /* SFP tasklet */ 493256200Sjfv struct task msf_task; /* Multispeed Fiber */ 494256200Sjfv struct taskqueue *tq; 495256200Sjfv 496256200Sjfv /* 497256200Sjfv ** Queues: 498256200Sjfv ** This is the irq holder, it has 499256200Sjfv ** and RX/TX pair or rings associated 500256200Sjfv ** with it. 501256200Sjfv */ 502203049Sjfv struct igb_queue *queues; 503203049Sjfv 504176667Sjfv /* 505256200Sjfv * Transmit rings: 506256200Sjfv * Allocated at run time, an array of rings. 507176667Sjfv */ 508176667Sjfv struct tx_ring *tx_rings; 509256200Sjfv u32 num_tx_desc; 510176667Sjfv 511256200Sjfv /* 512256200Sjfv * Receive rings: 513256200Sjfv * Allocated at run time, an array of rings. 514176667Sjfv */ 515176667Sjfv struct rx_ring *rx_rings; 516256200Sjfv u64 que_mask; 517256200Sjfv u32 num_rx_desc; 518176667Sjfv 519256200Sjfv /* Multicast array memory */ 520256200Sjfv u8 *mta; 521256200Sjfv 522176667Sjfv /* Misc stats maintained by the driver */ 523293854Smarius unsigned long device_control; 524256200Sjfv unsigned long dropped_pkts; 525293854Smarius unsigned long eint_mask; 526293854Smarius unsigned long int_mask; 527293854Smarius unsigned long link_irq; 528256200Sjfv unsigned long mbuf_defrag_failed; 529256200Sjfv unsigned long no_tx_dma_setup; 530256200Sjfv unsigned long packet_buf_alloc_rx; 531256200Sjfv unsigned long packet_buf_alloc_tx; 532293854Smarius unsigned long rx_control; 533293854Smarius unsigned long rx_overruns; 534293854Smarius unsigned long watchdog_events; 535293854Smarius 536256200Sjfv /* Used in pf and vf */ 537256200Sjfv void *stats; 538176667Sjfv 539256200Sjfv int enable_aim; 540256200Sjfv int has_manage; 541256200Sjfv int wol; 542256200Sjfv int rx_process_limit; 543292670Ssbruno int tx_process_limit; 544256200Sjfv u16 vf_ifp; /* a VF interface */ 545256200Sjfv bool in_detach; /* Used only in igb_ioctl */ 546176667Sjfv 547176667Sjfv}; 548176667Sjfv 549176667Sjfv/* ****************************************************************************** 550176667Sjfv * vendor_info_array 551176667Sjfv * 552176667Sjfv * This array contains the list of Subvendor/Subdevice IDs on which the driver 553176667Sjfv * should load. 554176667Sjfv * 555176667Sjfv * ******************************************************************************/ 556176667Sjfvtypedef struct _igb_vendor_info_t { 557176667Sjfv unsigned int vendor_id; 558176667Sjfv unsigned int device_id; 559176667Sjfv unsigned int subvendor_id; 560176667Sjfv unsigned int subdevice_id; 561176667Sjfv unsigned int index; 562176667Sjfv} igb_vendor_info_t; 563176667Sjfv 564256200Sjfvstruct igb_tx_buf { 565256200Sjfv union e1000_adv_tx_desc *eop; 566256200Sjfv struct mbuf *m_head; 567256200Sjfv bus_dmamap_t map; 568176667Sjfv}; 569176667Sjfv 570200243Sjfvstruct igb_rx_buf { 571190872Sjfv struct mbuf *m_head; 572190872Sjfv struct mbuf *m_pack; 573205869Sjfv bus_dmamap_t hmap; /* bus_dma map for header */ 574205869Sjfv bus_dmamap_t pmap; /* bus_dma map for packet */ 575190872Sjfv}; 576190872Sjfv 577220375Sjfv/* 578220375Sjfv** Find the number of unrefreshed RX descriptors 579220375Sjfv*/ 580220375Sjfvstatic inline u16 581220375Sjfvigb_rx_unrefreshed(struct rx_ring *rxr) 582220375Sjfv{ 583220375Sjfv struct adapter *adapter = rxr->adapter; 584220375Sjfv 585220375Sjfv if (rxr->next_to_check > rxr->next_to_refresh) 586220375Sjfv return (rxr->next_to_check - rxr->next_to_refresh - 1); 587220375Sjfv else 588220375Sjfv return ((adapter->num_rx_desc + rxr->next_to_check) - 589220375Sjfv rxr->next_to_refresh - 1); 590220375Sjfv} 591220375Sjfv 592176667Sjfv#define IGB_CORE_LOCK_INIT(_sc, _name) \ 593176667Sjfv mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF) 594176667Sjfv#define IGB_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 595203049Sjfv#define IGB_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 596203049Sjfv#define IGB_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 597203049Sjfv#define IGB_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 598203049Sjfv 599200243Sjfv#define IGB_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 600200243Sjfv#define IGB_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 601203049Sjfv#define IGB_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 602200243Sjfv#define IGB_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 603203049Sjfv#define IGB_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 604203049Sjfv 605203049Sjfv#define IGB_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 606200243Sjfv#define IGB_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 607176667Sjfv#define IGB_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 608209611Sjfv#define IGB_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rx_mtx, MA_OWNED) 609176667Sjfv 610209611Sjfv#define UPDATE_VF_REG(reg, last, cur) \ 611209611Sjfv{ \ 612209611Sjfv u32 new = E1000_READ_REG(hw, reg); \ 613209611Sjfv if (new < last) \ 614209611Sjfv cur += 0x100000000LL; \ 615209611Sjfv last = new; \ 616209611Sjfv cur &= 0xFFFFFFFF00000000LL; \ 617209611Sjfv cur |= new; \ 618209611Sjfv} 619209611Sjfv 620221187Sjfv#if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504 621209616Sjfvstatic __inline int 622209616Sjfvdrbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 623209616Sjfv{ 624209616Sjfv#ifdef ALTQ 625209616Sjfv if (ALTQ_IS_ENABLED(&ifp->if_snd)) 626209616Sjfv return (1); 627209616Sjfv#endif 628209616Sjfv return (!buf_ring_empty(br)); 629209616Sjfv} 630209616Sjfv#endif 631209616Sjfv 632287465Ssbruno#endif /* _IF_IGB_H_ */ 633176667Sjfv 634176667Sjfv 635