e1000_mac.c revision 287467
1/****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/e1000_mac.c 287467 2015-09-04 16:30:48Z sbruno $*/ 34 35#include "e1000_api.h" 36 37static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 38static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 39static void e1000_config_collision_dist_generic(struct e1000_hw *hw); 40static int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index); 41 42/** 43 * e1000_init_mac_ops_generic - Initialize MAC function pointers 44 * @hw: pointer to the HW structure 45 * 46 * Setups up the function pointers to no-op functions 47 **/ 48void e1000_init_mac_ops_generic(struct e1000_hw *hw) 49{ 50 struct e1000_mac_info *mac = &hw->mac; 51 DEBUGFUNC("e1000_init_mac_ops_generic"); 52 53 /* General Setup */ 54 mac->ops.init_params = e1000_null_ops_generic; 55 mac->ops.init_hw = e1000_null_ops_generic; 56 mac->ops.reset_hw = e1000_null_ops_generic; 57 mac->ops.setup_physical_interface = e1000_null_ops_generic; 58 mac->ops.get_bus_info = e1000_null_ops_generic; 59 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 60 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 61 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 62 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 63 /* LED */ 64 mac->ops.cleanup_led = e1000_null_ops_generic; 65 mac->ops.setup_led = e1000_null_ops_generic; 66 mac->ops.blink_led = e1000_null_ops_generic; 67 mac->ops.led_on = e1000_null_ops_generic; 68 mac->ops.led_off = e1000_null_ops_generic; 69 /* LINK */ 70 mac->ops.setup_link = e1000_null_ops_generic; 71 mac->ops.get_link_up_info = e1000_null_link_info; 72 mac->ops.check_for_link = e1000_null_ops_generic; 73 /* Management */ 74 mac->ops.check_mng_mode = e1000_null_mng_mode; 75 /* VLAN, MC, etc. */ 76 mac->ops.update_mc_addr_list = e1000_null_update_mc; 77 mac->ops.clear_vfta = e1000_null_mac_generic; 78 mac->ops.write_vfta = e1000_null_write_vfta; 79 mac->ops.rar_set = e1000_rar_set_generic; 80 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 81} 82 83/** 84 * e1000_null_ops_generic - No-op function, returns 0 85 * @hw: pointer to the HW structure 86 **/ 87s32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw) 88{ 89 DEBUGFUNC("e1000_null_ops_generic"); 90 return E1000_SUCCESS; 91} 92 93/** 94 * e1000_null_mac_generic - No-op function, return void 95 * @hw: pointer to the HW structure 96 **/ 97void e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw) 98{ 99 DEBUGFUNC("e1000_null_mac_generic"); 100 return; 101} 102 103/** 104 * e1000_null_link_info - No-op function, return 0 105 * @hw: pointer to the HW structure 106 **/ 107s32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw, 108 u16 E1000_UNUSEDARG *s, u16 E1000_UNUSEDARG *d) 109{ 110 DEBUGFUNC("e1000_null_link_info"); 111 return E1000_SUCCESS; 112} 113 114/** 115 * e1000_null_mng_mode - No-op function, return FALSE 116 * @hw: pointer to the HW structure 117 **/ 118bool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw) 119{ 120 DEBUGFUNC("e1000_null_mng_mode"); 121 return FALSE; 122} 123 124/** 125 * e1000_null_update_mc - No-op function, return void 126 * @hw: pointer to the HW structure 127 **/ 128void e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw, 129 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a) 130{ 131 DEBUGFUNC("e1000_null_update_mc"); 132 return; 133} 134 135/** 136 * e1000_null_write_vfta - No-op function, return void 137 * @hw: pointer to the HW structure 138 **/ 139void e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw, 140 u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b) 141{ 142 DEBUGFUNC("e1000_null_write_vfta"); 143 return; 144} 145 146/** 147 * e1000_null_rar_set - No-op function, return 0 148 * @hw: pointer to the HW structure 149 **/ 150int e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw, 151 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a) 152{ 153 DEBUGFUNC("e1000_null_rar_set"); 154 return E1000_SUCCESS; 155} 156 157/** 158 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 159 * @hw: pointer to the HW structure 160 * 161 * Determines and stores the system bus information for a particular 162 * network interface. The following bus information is determined and stored: 163 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 164 **/ 165s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 166{ 167 struct e1000_mac_info *mac = &hw->mac; 168 struct e1000_bus_info *bus = &hw->bus; 169 u32 status = E1000_READ_REG(hw, E1000_STATUS); 170 s32 ret_val = E1000_SUCCESS; 171 172 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 173 174 /* PCI or PCI-X? */ 175 bus->type = (status & E1000_STATUS_PCIX_MODE) 176 ? e1000_bus_type_pcix 177 : e1000_bus_type_pci; 178 179 /* Bus speed */ 180 if (bus->type == e1000_bus_type_pci) { 181 bus->speed = (status & E1000_STATUS_PCI66) 182 ? e1000_bus_speed_66 183 : e1000_bus_speed_33; 184 } else { 185 switch (status & E1000_STATUS_PCIX_SPEED) { 186 case E1000_STATUS_PCIX_SPEED_66: 187 bus->speed = e1000_bus_speed_66; 188 break; 189 case E1000_STATUS_PCIX_SPEED_100: 190 bus->speed = e1000_bus_speed_100; 191 break; 192 case E1000_STATUS_PCIX_SPEED_133: 193 bus->speed = e1000_bus_speed_133; 194 break; 195 default: 196 bus->speed = e1000_bus_speed_reserved; 197 break; 198 } 199 } 200 201 /* Bus width */ 202 bus->width = (status & E1000_STATUS_BUS64) 203 ? e1000_bus_width_64 204 : e1000_bus_width_32; 205 206 /* Which PCI(-X) function? */ 207 mac->ops.set_lan_id(hw); 208 209 return ret_val; 210} 211 212/** 213 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 214 * @hw: pointer to the HW structure 215 * 216 * Determines and stores the system bus information for a particular 217 * network interface. The following bus information is determined and stored: 218 * bus speed, bus width, type (PCIe), and PCIe function. 219 **/ 220s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 221{ 222 struct e1000_mac_info *mac = &hw->mac; 223 struct e1000_bus_info *bus = &hw->bus; 224 s32 ret_val; 225 u16 pcie_link_status; 226 227 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 228 229 bus->type = e1000_bus_type_pci_express; 230 231 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS, 232 &pcie_link_status); 233 if (ret_val) { 234 bus->width = e1000_bus_width_unknown; 235 bus->speed = e1000_bus_speed_unknown; 236 } else { 237 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) { 238 case PCIE_LINK_SPEED_2500: 239 bus->speed = e1000_bus_speed_2500; 240 break; 241 case PCIE_LINK_SPEED_5000: 242 bus->speed = e1000_bus_speed_5000; 243 break; 244 default: 245 bus->speed = e1000_bus_speed_unknown; 246 break; 247 } 248 249 bus->width = (enum e1000_bus_width)((pcie_link_status & 250 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT); 251 } 252 253 mac->ops.set_lan_id(hw); 254 255 return E1000_SUCCESS; 256} 257 258/** 259 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 260 * 261 * @hw: pointer to the HW structure 262 * 263 * Determines the LAN function id by reading memory-mapped registers 264 * and swaps the port value if requested. 265 **/ 266static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 267{ 268 struct e1000_bus_info *bus = &hw->bus; 269 u32 reg; 270 271 /* The status register reports the correct function number 272 * for the device regardless of function swap state. 273 */ 274 reg = E1000_READ_REG(hw, E1000_STATUS); 275 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 276} 277 278/** 279 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 280 * @hw: pointer to the HW structure 281 * 282 * Determines the LAN function id by reading PCI config space. 283 **/ 284void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 285{ 286 struct e1000_bus_info *bus = &hw->bus; 287 u16 pci_header_type; 288 u32 status; 289 290 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 291 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 292 status = E1000_READ_REG(hw, E1000_STATUS); 293 bus->func = (status & E1000_STATUS_FUNC_MASK) 294 >> E1000_STATUS_FUNC_SHIFT; 295 } else { 296 bus->func = 0; 297 } 298} 299 300/** 301 * e1000_set_lan_id_single_port - Set LAN id for a single port device 302 * @hw: pointer to the HW structure 303 * 304 * Sets the LAN function id to zero for a single port device. 305 **/ 306void e1000_set_lan_id_single_port(struct e1000_hw *hw) 307{ 308 struct e1000_bus_info *bus = &hw->bus; 309 310 bus->func = 0; 311} 312 313/** 314 * e1000_clear_vfta_generic - Clear VLAN filter table 315 * @hw: pointer to the HW structure 316 * 317 * Clears the register array which contains the VLAN filter table by 318 * setting all the values to 0. 319 **/ 320void e1000_clear_vfta_generic(struct e1000_hw *hw) 321{ 322 u32 offset; 323 324 DEBUGFUNC("e1000_clear_vfta_generic"); 325 326 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 327 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 328 E1000_WRITE_FLUSH(hw); 329 } 330} 331 332/** 333 * e1000_write_vfta_generic - Write value to VLAN filter table 334 * @hw: pointer to the HW structure 335 * @offset: register offset in VLAN filter table 336 * @value: register value written to VLAN filter table 337 * 338 * Writes value at the given offset in the register array which stores 339 * the VLAN filter table. 340 **/ 341void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 342{ 343 DEBUGFUNC("e1000_write_vfta_generic"); 344 345 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 346 E1000_WRITE_FLUSH(hw); 347} 348 349/** 350 * e1000_init_rx_addrs_generic - Initialize receive address's 351 * @hw: pointer to the HW structure 352 * @rar_count: receive address registers 353 * 354 * Setup the receive address registers by setting the base receive address 355 * register to the devices MAC address and clearing all the other receive 356 * address registers to 0. 357 **/ 358void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 359{ 360 u32 i; 361 u8 mac_addr[ETH_ADDR_LEN] = {0}; 362 363 DEBUGFUNC("e1000_init_rx_addrs_generic"); 364 365 /* Setup the receive address */ 366 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 367 368 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 369 370 /* Zero out the other (rar_entry_count - 1) receive addresses */ 371 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 372 for (i = 1; i < rar_count; i++) 373 hw->mac.ops.rar_set(hw, mac_addr, i); 374} 375 376/** 377 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 378 * @hw: pointer to the HW structure 379 * 380 * Checks the nvm for an alternate MAC address. An alternate MAC address 381 * can be setup by pre-boot software and must be treated like a permanent 382 * address and must override the actual permanent MAC address. If an 383 * alternate MAC address is found it is programmed into RAR0, replacing 384 * the permanent address that was installed into RAR0 by the Si on reset. 385 * This function will return SUCCESS unless it encounters an error while 386 * reading the EEPROM. 387 **/ 388s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 389{ 390 u32 i; 391 s32 ret_val; 392 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 393 u8 alt_mac_addr[ETH_ADDR_LEN]; 394 395 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 396 397 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); 398 if (ret_val) 399 return ret_val; 400 401 /* not supported on older hardware or 82573 */ 402 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573)) 403 return E1000_SUCCESS; 404 405 /* Alternate MAC address is handled by the option ROM for 82580 406 * and newer. SW support not required. 407 */ 408 if (hw->mac.type >= e1000_82580) 409 return E1000_SUCCESS; 410 411 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 412 &nvm_alt_mac_addr_offset); 413 if (ret_val) { 414 DEBUGOUT("NVM Read Error\n"); 415 return ret_val; 416 } 417 418 if ((nvm_alt_mac_addr_offset == 0xFFFF) || 419 (nvm_alt_mac_addr_offset == 0x0000)) 420 /* There is no Alternate MAC Address */ 421 return E1000_SUCCESS; 422 423 if (hw->bus.func == E1000_FUNC_1) 424 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 425 if (hw->bus.func == E1000_FUNC_2) 426 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 427 428 if (hw->bus.func == E1000_FUNC_3) 429 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 430 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 431 offset = nvm_alt_mac_addr_offset + (i >> 1); 432 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 433 if (ret_val) { 434 DEBUGOUT("NVM Read Error\n"); 435 return ret_val; 436 } 437 438 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 439 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 440 } 441 442 /* if multicast bit is set, the alternate address will not be used */ 443 if (alt_mac_addr[0] & 0x01) { 444 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 445 return E1000_SUCCESS; 446 } 447 448 /* We have a valid alternate MAC address, and we want to treat it the 449 * same as the normal permanent MAC address stored by the HW into the 450 * RAR. Do this by mapping this address into RAR0. 451 */ 452 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 453 454 return E1000_SUCCESS; 455} 456 457/** 458 * e1000_rar_set_generic - Set receive address register 459 * @hw: pointer to the HW structure 460 * @addr: pointer to the receive address 461 * @index: receive address array register 462 * 463 * Sets the receive address array register at index to the address passed 464 * in by addr. 465 **/ 466static int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 467{ 468 u32 rar_low, rar_high; 469 470 DEBUGFUNC("e1000_rar_set_generic"); 471 472 /* HW expects these in little endian so we reverse the byte order 473 * from network order (big endian) to little endian 474 */ 475 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 476 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 477 478 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 479 480 /* If MAC address zero, no need to set the AV bit */ 481 if (rar_low || rar_high) 482 rar_high |= E1000_RAH_AV; 483 484 /* Some bridges will combine consecutive 32-bit writes into 485 * a single burst write, which will malfunction on some parts. 486 * The flushes avoid this. 487 */ 488 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 489 E1000_WRITE_FLUSH(hw); 490 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 491 E1000_WRITE_FLUSH(hw); 492 493 return E1000_SUCCESS; 494} 495 496/** 497 * e1000_hash_mc_addr_generic - Generate a multicast hash value 498 * @hw: pointer to the HW structure 499 * @mc_addr: pointer to a multicast address 500 * 501 * Generates a multicast address hash value which is used to determine 502 * the multicast filter table array address and new table value. 503 **/ 504u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 505{ 506 u32 hash_value, hash_mask; 507 u8 bit_shift = 0; 508 509 DEBUGFUNC("e1000_hash_mc_addr_generic"); 510 511 /* Register count multiplied by bits per register */ 512 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 513 514 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts 515 * where 0xFF would still fall within the hash mask. 516 */ 517 while (hash_mask >> bit_shift != 0xFF) 518 bit_shift++; 519 520 /* The portion of the address that is used for the hash table 521 * is determined by the mc_filter_type setting. 522 * The algorithm is such that there is a total of 8 bits of shifting. 523 * The bit_shift for a mc_filter_type of 0 represents the number of 524 * left-shifts where the MSB of mc_addr[5] would still fall within 525 * the hash_mask. Case 0 does this exactly. Since there are a total 526 * of 8 bits of shifting, then mc_addr[4] will shift right the 527 * remaining number of bits. Thus 8 - bit_shift. The rest of the 528 * cases are a variation of this algorithm...essentially raising the 529 * number of bits to shift mc_addr[5] left, while still keeping the 530 * 8-bit shifting total. 531 * 532 * For example, given the following Destination MAC Address and an 533 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 534 * we can see that the bit_shift for case 0 is 4. These are the hash 535 * values resulting from each mc_filter_type... 536 * [0] [1] [2] [3] [4] [5] 537 * 01 AA 00 12 34 56 538 * LSB MSB 539 * 540 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 541 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 542 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 543 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 544 */ 545 switch (hw->mac.mc_filter_type) { 546 default: 547 case 0: 548 break; 549 case 1: 550 bit_shift += 1; 551 break; 552 case 2: 553 bit_shift += 2; 554 break; 555 case 3: 556 bit_shift += 4; 557 break; 558 } 559 560 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 561 (((u16) mc_addr[5]) << bit_shift))); 562 563 return hash_value; 564} 565 566/** 567 * e1000_update_mc_addr_list_generic - Update Multicast addresses 568 * @hw: pointer to the HW structure 569 * @mc_addr_list: array of multicast addresses to program 570 * @mc_addr_count: number of multicast addresses to program 571 * 572 * Updates entire Multicast Table Array. 573 * The caller must have a packed mc_addr_list of multicast addresses. 574 **/ 575void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 576 u8 *mc_addr_list, u32 mc_addr_count) 577{ 578 u32 hash_value, hash_bit, hash_reg; 579 int i; 580 581 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 582 583 /* clear mta_shadow */ 584 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 585 586 /* update mta_shadow from mc_addr_list */ 587 for (i = 0; (u32) i < mc_addr_count; i++) { 588 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 589 590 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 591 hash_bit = hash_value & 0x1F; 592 593 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 594 mc_addr_list += (ETH_ADDR_LEN); 595 } 596 597 /* replace the entire MTA table */ 598 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 599 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 600 E1000_WRITE_FLUSH(hw); 601} 602 603/** 604 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 605 * @hw: pointer to the HW structure 606 * 607 * In certain situations, a system BIOS may report that the PCIx maximum 608 * memory read byte count (MMRBC) value is higher than than the actual 609 * value. We check the PCIx command register with the current PCIx status 610 * register. 611 **/ 612void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 613{ 614 u16 cmd_mmrbc; 615 u16 pcix_cmd; 616 u16 pcix_stat_hi_word; 617 u16 stat_mmrbc; 618 619 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 620 621 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 622 if (hw->bus.type != e1000_bus_type_pcix) 623 return; 624 625 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 626 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 627 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 628 PCIX_COMMAND_MMRBC_SHIFT; 629 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 630 PCIX_STATUS_HI_MMRBC_SHIFT; 631 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 632 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 633 if (cmd_mmrbc > stat_mmrbc) { 634 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 635 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 636 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 637 } 638} 639 640/** 641 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 642 * @hw: pointer to the HW structure 643 * 644 * Clears the base hardware counters by reading the counter registers. 645 **/ 646void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 647{ 648 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 649 650 E1000_READ_REG(hw, E1000_CRCERRS); 651 E1000_READ_REG(hw, E1000_SYMERRS); 652 E1000_READ_REG(hw, E1000_MPC); 653 E1000_READ_REG(hw, E1000_SCC); 654 E1000_READ_REG(hw, E1000_ECOL); 655 E1000_READ_REG(hw, E1000_MCC); 656 E1000_READ_REG(hw, E1000_LATECOL); 657 E1000_READ_REG(hw, E1000_COLC); 658 E1000_READ_REG(hw, E1000_DC); 659 E1000_READ_REG(hw, E1000_SEC); 660 E1000_READ_REG(hw, E1000_RLEC); 661 E1000_READ_REG(hw, E1000_XONRXC); 662 E1000_READ_REG(hw, E1000_XONTXC); 663 E1000_READ_REG(hw, E1000_XOFFRXC); 664 E1000_READ_REG(hw, E1000_XOFFTXC); 665 E1000_READ_REG(hw, E1000_FCRUC); 666 E1000_READ_REG(hw, E1000_GPRC); 667 E1000_READ_REG(hw, E1000_BPRC); 668 E1000_READ_REG(hw, E1000_MPRC); 669 E1000_READ_REG(hw, E1000_GPTC); 670 E1000_READ_REG(hw, E1000_GORCL); 671 E1000_READ_REG(hw, E1000_GORCH); 672 E1000_READ_REG(hw, E1000_GOTCL); 673 E1000_READ_REG(hw, E1000_GOTCH); 674 E1000_READ_REG(hw, E1000_RNBC); 675 E1000_READ_REG(hw, E1000_RUC); 676 E1000_READ_REG(hw, E1000_RFC); 677 E1000_READ_REG(hw, E1000_ROC); 678 E1000_READ_REG(hw, E1000_RJC); 679 E1000_READ_REG(hw, E1000_TORL); 680 E1000_READ_REG(hw, E1000_TORH); 681 E1000_READ_REG(hw, E1000_TOTL); 682 E1000_READ_REG(hw, E1000_TOTH); 683 E1000_READ_REG(hw, E1000_TPR); 684 E1000_READ_REG(hw, E1000_TPT); 685 E1000_READ_REG(hw, E1000_MPTC); 686 E1000_READ_REG(hw, E1000_BPTC); 687} 688 689/** 690 * e1000_check_for_copper_link_generic - Check for link (Copper) 691 * @hw: pointer to the HW structure 692 * 693 * Checks to see of the link status of the hardware has changed. If a 694 * change in link status has been detected, then we read the PHY registers 695 * to get the current speed/duplex if link exists. 696 **/ 697s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 698{ 699 struct e1000_mac_info *mac = &hw->mac; 700 s32 ret_val; 701 bool link; 702 703 DEBUGFUNC("e1000_check_for_copper_link"); 704 705 /* We only want to go out to the PHY registers to see if Auto-Neg 706 * has completed and/or if our link status has changed. The 707 * get_link_status flag is set upon receiving a Link Status 708 * Change or Rx Sequence Error interrupt. 709 */ 710 if (!mac->get_link_status) 711 return E1000_SUCCESS; 712 713 /* First we want to see if the MII Status Register reports 714 * link. If so, then we want to get the current speed/duplex 715 * of the PHY. 716 */ 717 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 718 if (ret_val) 719 return ret_val; 720 721 if (!link) 722 return E1000_SUCCESS; /* No link detected */ 723 724 mac->get_link_status = FALSE; 725 726 /* Check if there was DownShift, must be checked 727 * immediately after link-up 728 */ 729 e1000_check_downshift_generic(hw); 730 731 /* If we are forcing speed/duplex, then we simply return since 732 * we have already determined whether we have link or not. 733 */ 734 if (!mac->autoneg) 735 return -E1000_ERR_CONFIG; 736 737 /* Auto-Neg is enabled. Auto Speed Detection takes care 738 * of MAC speed/duplex configuration. So we only need to 739 * configure Collision Distance in the MAC. 740 */ 741 mac->ops.config_collision_dist(hw); 742 743 /* Configure Flow Control now that Auto-Neg has completed. 744 * First, we need to restore the desired flow control 745 * settings because we may have had to re-autoneg with a 746 * different link partner. 747 */ 748 ret_val = e1000_config_fc_after_link_up_generic(hw); 749 if (ret_val) 750 DEBUGOUT("Error configuring flow control\n"); 751 752 return ret_val; 753} 754 755/** 756 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 757 * @hw: pointer to the HW structure 758 * 759 * Checks for link up on the hardware. If link is not up and we have 760 * a signal, then we need to force link up. 761 **/ 762s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 763{ 764 struct e1000_mac_info *mac = &hw->mac; 765 u32 rxcw; 766 u32 ctrl; 767 u32 status; 768 s32 ret_val; 769 770 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 771 772 ctrl = E1000_READ_REG(hw, E1000_CTRL); 773 status = E1000_READ_REG(hw, E1000_STATUS); 774 rxcw = E1000_READ_REG(hw, E1000_RXCW); 775 776 /* If we don't have link (auto-negotiation failed or link partner 777 * cannot auto-negotiate), the cable is plugged in (we have signal), 778 * and our link partner is not trying to auto-negotiate with us (we 779 * are receiving idles or data), we need to force link up. We also 780 * need to give auto-negotiation time to complete, in case the cable 781 * was just plugged in. The autoneg_failed flag does this. 782 */ 783 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 784 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) && 785 !(rxcw & E1000_RXCW_C)) { 786 if (!mac->autoneg_failed) { 787 mac->autoneg_failed = TRUE; 788 return E1000_SUCCESS; 789 } 790 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 791 792 /* Disable auto-negotiation in the TXCW register */ 793 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 794 795 /* Force link-up and also force full-duplex. */ 796 ctrl = E1000_READ_REG(hw, E1000_CTRL); 797 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 798 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 799 800 /* Configure Flow Control after forcing link up. */ 801 ret_val = e1000_config_fc_after_link_up_generic(hw); 802 if (ret_val) { 803 DEBUGOUT("Error configuring flow control\n"); 804 return ret_val; 805 } 806 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 807 /* If we are forcing link and we are receiving /C/ ordered 808 * sets, re-enable auto-negotiation in the TXCW register 809 * and disable forced link in the Device Control register 810 * in an attempt to auto-negotiate with our link partner. 811 */ 812 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 813 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 814 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 815 816 mac->serdes_has_link = TRUE; 817 } 818 819 return E1000_SUCCESS; 820} 821 822/** 823 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 824 * @hw: pointer to the HW structure 825 * 826 * Checks for link up on the hardware. If link is not up and we have 827 * a signal, then we need to force link up. 828 **/ 829s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 830{ 831 struct e1000_mac_info *mac = &hw->mac; 832 u32 rxcw; 833 u32 ctrl; 834 u32 status; 835 s32 ret_val; 836 837 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 838 839 ctrl = E1000_READ_REG(hw, E1000_CTRL); 840 status = E1000_READ_REG(hw, E1000_STATUS); 841 rxcw = E1000_READ_REG(hw, E1000_RXCW); 842 843 /* If we don't have link (auto-negotiation failed or link partner 844 * cannot auto-negotiate), and our link partner is not trying to 845 * auto-negotiate with us (we are receiving idles or data), 846 * we need to force link up. We also need to give auto-negotiation 847 * time to complete. 848 */ 849 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 850 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) { 851 if (!mac->autoneg_failed) { 852 mac->autoneg_failed = TRUE; 853 return E1000_SUCCESS; 854 } 855 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 856 857 /* Disable auto-negotiation in the TXCW register */ 858 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 859 860 /* Force link-up and also force full-duplex. */ 861 ctrl = E1000_READ_REG(hw, E1000_CTRL); 862 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 863 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 864 865 /* Configure Flow Control after forcing link up. */ 866 ret_val = e1000_config_fc_after_link_up_generic(hw); 867 if (ret_val) { 868 DEBUGOUT("Error configuring flow control\n"); 869 return ret_val; 870 } 871 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 872 /* If we are forcing link and we are receiving /C/ ordered 873 * sets, re-enable auto-negotiation in the TXCW register 874 * and disable forced link in the Device Control register 875 * in an attempt to auto-negotiate with our link partner. 876 */ 877 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 878 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 879 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 880 881 mac->serdes_has_link = TRUE; 882 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 883 /* If we force link for non-auto-negotiation switch, check 884 * link status based on MAC synchronization for internal 885 * serdes media type. 886 */ 887 /* SYNCH bit and IV bit are sticky. */ 888 usec_delay(10); 889 rxcw = E1000_READ_REG(hw, E1000_RXCW); 890 if (rxcw & E1000_RXCW_SYNCH) { 891 if (!(rxcw & E1000_RXCW_IV)) { 892 mac->serdes_has_link = TRUE; 893 DEBUGOUT("SERDES: Link up - forced.\n"); 894 } 895 } else { 896 mac->serdes_has_link = FALSE; 897 DEBUGOUT("SERDES: Link down - force failed.\n"); 898 } 899 } 900 901 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 902 status = E1000_READ_REG(hw, E1000_STATUS); 903 if (status & E1000_STATUS_LU) { 904 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 905 usec_delay(10); 906 rxcw = E1000_READ_REG(hw, E1000_RXCW); 907 if (rxcw & E1000_RXCW_SYNCH) { 908 if (!(rxcw & E1000_RXCW_IV)) { 909 mac->serdes_has_link = TRUE; 910 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n"); 911 } else { 912 mac->serdes_has_link = FALSE; 913 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n"); 914 } 915 } else { 916 mac->serdes_has_link = FALSE; 917 DEBUGOUT("SERDES: Link down - no sync.\n"); 918 } 919 } else { 920 mac->serdes_has_link = FALSE; 921 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 922 } 923 } 924 925 return E1000_SUCCESS; 926} 927 928/** 929 * e1000_set_default_fc_generic - Set flow control default values 930 * @hw: pointer to the HW structure 931 * 932 * Read the EEPROM for the default values for flow control and store the 933 * values. 934 **/ 935s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 936{ 937 s32 ret_val; 938 u16 nvm_data; 939 u16 nvm_offset = 0; 940 941 DEBUGFUNC("e1000_set_default_fc_generic"); 942 943 /* Read and store word 0x0F of the EEPROM. This word contains bits 944 * that determine the hardware's default PAUSE (flow control) mode, 945 * a bit that determines whether the HW defaults to enabling or 946 * disabling auto-negotiation, and the direction of the 947 * SW defined pins. If there is no SW over-ride of the flow 948 * control setting, then the variable hw->fc will 949 * be initialized based on a value in the EEPROM. 950 */ 951 if (hw->mac.type == e1000_i350) { 952 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func); 953 ret_val = hw->nvm.ops.read(hw, 954 NVM_INIT_CONTROL2_REG + 955 nvm_offset, 956 1, &nvm_data); 957 } else { 958 ret_val = hw->nvm.ops.read(hw, 959 NVM_INIT_CONTROL2_REG, 960 1, &nvm_data); 961 } 962 963 964 if (ret_val) { 965 DEBUGOUT("NVM Read Error\n"); 966 return ret_val; 967 } 968 969 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK)) 970 hw->fc.requested_mode = e1000_fc_none; 971 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 972 NVM_WORD0F_ASM_DIR) 973 hw->fc.requested_mode = e1000_fc_tx_pause; 974 else 975 hw->fc.requested_mode = e1000_fc_full; 976 977 return E1000_SUCCESS; 978} 979 980/** 981 * e1000_setup_link_generic - Setup flow control and link settings 982 * @hw: pointer to the HW structure 983 * 984 * Determines which flow control settings to use, then configures flow 985 * control. Calls the appropriate media-specific link configuration 986 * function. Assuming the adapter has a valid link partner, a valid link 987 * should be established. Assumes the hardware has previously been reset 988 * and the transmitter and receiver are not enabled. 989 **/ 990s32 e1000_setup_link_generic(struct e1000_hw *hw) 991{ 992 s32 ret_val; 993 994 DEBUGFUNC("e1000_setup_link_generic"); 995 996 /* In the case of the phy reset being blocked, we already have a link. 997 * We do not need to set it up again. 998 */ 999 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 1000 return E1000_SUCCESS; 1001 1002 /* If requested flow control is set to default, set flow control 1003 * based on the EEPROM flow control settings. 1004 */ 1005 if (hw->fc.requested_mode == e1000_fc_default) { 1006 ret_val = e1000_set_default_fc_generic(hw); 1007 if (ret_val) 1008 return ret_val; 1009 } 1010 1011 /* Save off the requested flow control mode for use later. Depending 1012 * on the link partner's capabilities, we may or may not use this mode. 1013 */ 1014 hw->fc.current_mode = hw->fc.requested_mode; 1015 1016 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 1017 hw->fc.current_mode); 1018 1019 /* Call the necessary media_type subroutine to configure the link. */ 1020 ret_val = hw->mac.ops.setup_physical_interface(hw); 1021 if (ret_val) 1022 return ret_val; 1023 1024 /* Initialize the flow control address, type, and PAUSE timer 1025 * registers to their default values. This is done even if flow 1026 * control is disabled, because it does not hurt anything to 1027 * initialize these registers. 1028 */ 1029 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1030 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 1031 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1032 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 1033 1034 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 1035 1036 return e1000_set_fc_watermarks_generic(hw); 1037} 1038 1039/** 1040 * e1000_commit_fc_settings_generic - Configure flow control 1041 * @hw: pointer to the HW structure 1042 * 1043 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1044 * base on the flow control settings in e1000_mac_info. 1045 **/ 1046s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1047{ 1048 struct e1000_mac_info *mac = &hw->mac; 1049 u32 txcw; 1050 1051 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1052 1053 /* Check for a software override of the flow control settings, and 1054 * setup the device accordingly. If auto-negotiation is enabled, then 1055 * software will have to set the "PAUSE" bits to the correct value in 1056 * the Transmit Config Word Register (TXCW) and re-start auto- 1057 * negotiation. However, if auto-negotiation is disabled, then 1058 * software will have to manually configure the two flow control enable 1059 * bits in the CTRL register. 1060 * 1061 * The possible values of the "fc" parameter are: 1062 * 0: Flow control is completely disabled 1063 * 1: Rx flow control is enabled (we can receive pause frames, 1064 * but not send pause frames). 1065 * 2: Tx flow control is enabled (we can send pause frames but we 1066 * do not support receiving pause frames). 1067 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1068 */ 1069 switch (hw->fc.current_mode) { 1070 case e1000_fc_none: 1071 /* Flow control completely disabled by a software over-ride. */ 1072 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1073 break; 1074 case e1000_fc_rx_pause: 1075 /* Rx Flow control is enabled and Tx Flow control is disabled 1076 * by a software over-ride. Since there really isn't a way to 1077 * advertise that we are capable of Rx Pause ONLY, we will 1078 * advertise that we support both symmetric and asymmetric Rx 1079 * PAUSE. Later, we will disable the adapter's ability to send 1080 * PAUSE frames. 1081 */ 1082 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1083 break; 1084 case e1000_fc_tx_pause: 1085 /* Tx Flow control is enabled, and Rx Flow control is disabled, 1086 * by a software over-ride. 1087 */ 1088 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1089 break; 1090 case e1000_fc_full: 1091 /* Flow control (both Rx and Tx) is enabled by a software 1092 * over-ride. 1093 */ 1094 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1095 break; 1096 default: 1097 DEBUGOUT("Flow control param set incorrectly\n"); 1098 return -E1000_ERR_CONFIG; 1099 break; 1100 } 1101 1102 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1103 mac->txcw = txcw; 1104 1105 return E1000_SUCCESS; 1106} 1107 1108/** 1109 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1110 * @hw: pointer to the HW structure 1111 * 1112 * Polls for link up by reading the status register, if link fails to come 1113 * up with auto-negotiation, then the link is forced if a signal is detected. 1114 **/ 1115s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1116{ 1117 struct e1000_mac_info *mac = &hw->mac; 1118 u32 i, status; 1119 s32 ret_val; 1120 1121 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1122 1123 /* If we have a signal (the cable is plugged in, or assumed TRUE for 1124 * serdes media) then poll for a "Link-Up" indication in the Device 1125 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1126 * seconds (Auto-negotiation should complete in less than 500 1127 * milliseconds even if the other end is doing it in SW). 1128 */ 1129 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1130 msec_delay(10); 1131 status = E1000_READ_REG(hw, E1000_STATUS); 1132 if (status & E1000_STATUS_LU) 1133 break; 1134 } 1135 if (i == FIBER_LINK_UP_LIMIT) { 1136 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1137 mac->autoneg_failed = TRUE; 1138 /* AutoNeg failed to achieve a link, so we'll call 1139 * mac->check_for_link. This routine will force the 1140 * link up if we detect a signal. This will allow us to 1141 * communicate with non-autonegotiating link partners. 1142 */ 1143 ret_val = mac->ops.check_for_link(hw); 1144 if (ret_val) { 1145 DEBUGOUT("Error while checking for link\n"); 1146 return ret_val; 1147 } 1148 mac->autoneg_failed = FALSE; 1149 } else { 1150 mac->autoneg_failed = FALSE; 1151 DEBUGOUT("Valid Link Found\n"); 1152 } 1153 1154 return E1000_SUCCESS; 1155} 1156 1157/** 1158 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1159 * @hw: pointer to the HW structure 1160 * 1161 * Configures collision distance and flow control for fiber and serdes 1162 * links. Upon successful setup, poll for link. 1163 **/ 1164s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1165{ 1166 u32 ctrl; 1167 s32 ret_val; 1168 1169 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1170 1171 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1172 1173 /* Take the link out of reset */ 1174 ctrl &= ~E1000_CTRL_LRST; 1175 1176 hw->mac.ops.config_collision_dist(hw); 1177 1178 ret_val = e1000_commit_fc_settings_generic(hw); 1179 if (ret_val) 1180 return ret_val; 1181 1182 /* Since auto-negotiation is enabled, take the link out of reset (the 1183 * link will be in reset, because we previously reset the chip). This 1184 * will restart auto-negotiation. If auto-negotiation is successful 1185 * then the link-up status bit will be set and the flow control enable 1186 * bits (RFCE and TFCE) will be set according to their negotiated value. 1187 */ 1188 DEBUGOUT("Auto-negotiation enabled\n"); 1189 1190 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1191 E1000_WRITE_FLUSH(hw); 1192 msec_delay(1); 1193 1194 /* For these adapters, the SW definable pin 1 is set when the optics 1195 * detect a signal. If we have a signal, then poll for a "Link-Up" 1196 * indication. 1197 */ 1198 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1199 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1200 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1201 } else { 1202 DEBUGOUT("No signal detected\n"); 1203 } 1204 1205 return ret_val; 1206} 1207 1208/** 1209 * e1000_config_collision_dist_generic - Configure collision distance 1210 * @hw: pointer to the HW structure 1211 * 1212 * Configures the collision distance to the default value and is used 1213 * during link setup. 1214 **/ 1215static void e1000_config_collision_dist_generic(struct e1000_hw *hw) 1216{ 1217 u32 tctl; 1218 1219 DEBUGFUNC("e1000_config_collision_dist_generic"); 1220 1221 tctl = E1000_READ_REG(hw, E1000_TCTL); 1222 1223 tctl &= ~E1000_TCTL_COLD; 1224 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1225 1226 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1227 E1000_WRITE_FLUSH(hw); 1228} 1229 1230/** 1231 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1232 * @hw: pointer to the HW structure 1233 * 1234 * Sets the flow control high/low threshold (watermark) registers. If 1235 * flow control XON frame transmission is enabled, then set XON frame 1236 * transmission as well. 1237 **/ 1238s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1239{ 1240 u32 fcrtl = 0, fcrth = 0; 1241 1242 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1243 1244 /* Set the flow control receive threshold registers. Normally, 1245 * these registers will be set to a default threshold that may be 1246 * adjusted later by the driver's runtime code. However, if the 1247 * ability to transmit pause frames is not enabled, then these 1248 * registers will be set to 0. 1249 */ 1250 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1251 /* We need to set up the Receive Threshold high and low water 1252 * marks as well as (optionally) enabling the transmission of 1253 * XON frames. 1254 */ 1255 fcrtl = hw->fc.low_water; 1256 if (hw->fc.send_xon) 1257 fcrtl |= E1000_FCRTL_XONE; 1258 1259 fcrth = hw->fc.high_water; 1260 } 1261 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1262 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1263 1264 return E1000_SUCCESS; 1265} 1266 1267/** 1268 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1269 * @hw: pointer to the HW structure 1270 * 1271 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1272 * device control register to reflect the adapter settings. TFCE and RFCE 1273 * need to be explicitly set by software when a copper PHY is used because 1274 * autonegotiation is managed by the PHY rather than the MAC. Software must 1275 * also configure these bits when link is forced on a fiber connection. 1276 **/ 1277s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1278{ 1279 u32 ctrl; 1280 1281 DEBUGFUNC("e1000_force_mac_fc_generic"); 1282 1283 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1284 1285 /* Because we didn't get link via the internal auto-negotiation 1286 * mechanism (we either forced link or we got link via PHY 1287 * auto-neg), we have to manually enable/disable transmit an 1288 * receive flow control. 1289 * 1290 * The "Case" statement below enables/disable flow control 1291 * according to the "hw->fc.current_mode" parameter. 1292 * 1293 * The possible values of the "fc" parameter are: 1294 * 0: Flow control is completely disabled 1295 * 1: Rx flow control is enabled (we can receive pause 1296 * frames but not send pause frames). 1297 * 2: Tx flow control is enabled (we can send pause frames 1298 * frames but we do not receive pause frames). 1299 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1300 * other: No other values should be possible at this point. 1301 */ 1302 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1303 1304 switch (hw->fc.current_mode) { 1305 case e1000_fc_none: 1306 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1307 break; 1308 case e1000_fc_rx_pause: 1309 ctrl &= (~E1000_CTRL_TFCE); 1310 ctrl |= E1000_CTRL_RFCE; 1311 break; 1312 case e1000_fc_tx_pause: 1313 ctrl &= (~E1000_CTRL_RFCE); 1314 ctrl |= E1000_CTRL_TFCE; 1315 break; 1316 case e1000_fc_full: 1317 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1318 break; 1319 default: 1320 DEBUGOUT("Flow control param set incorrectly\n"); 1321 return -E1000_ERR_CONFIG; 1322 } 1323 1324 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1325 1326 return E1000_SUCCESS; 1327} 1328 1329/** 1330 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1331 * @hw: pointer to the HW structure 1332 * 1333 * Checks the status of auto-negotiation after link up to ensure that the 1334 * speed and duplex were not forced. If the link needed to be forced, then 1335 * flow control needs to be forced also. If auto-negotiation is enabled 1336 * and did not fail, then we configure flow control based on our link 1337 * partner. 1338 **/ 1339s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1340{ 1341 struct e1000_mac_info *mac = &hw->mac; 1342 s32 ret_val = E1000_SUCCESS; 1343 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg; 1344 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1345 u16 speed, duplex; 1346 1347 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1348 1349 /* Check for the case where we have fiber media and auto-neg failed 1350 * so we had to force link. In this case, we need to force the 1351 * configuration of the MAC to match the "fc" parameter. 1352 */ 1353 if (mac->autoneg_failed) { 1354 if (hw->phy.media_type == e1000_media_type_fiber || 1355 hw->phy.media_type == e1000_media_type_internal_serdes) 1356 ret_val = e1000_force_mac_fc_generic(hw); 1357 } else { 1358 if (hw->phy.media_type == e1000_media_type_copper) 1359 ret_val = e1000_force_mac_fc_generic(hw); 1360 } 1361 1362 if (ret_val) { 1363 DEBUGOUT("Error forcing flow control settings\n"); 1364 return ret_val; 1365 } 1366 1367 /* Check for the case where we have copper media and auto-neg is 1368 * enabled. In this case, we need to check and see if Auto-Neg 1369 * has completed, and if so, how the PHY and link partner has 1370 * flow control configured. 1371 */ 1372 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1373 /* Read the MII Status Register and check to see if AutoNeg 1374 * has completed. We read this twice because this reg has 1375 * some "sticky" (latched) bits. 1376 */ 1377 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1378 if (ret_val) 1379 return ret_val; 1380 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1381 if (ret_val) 1382 return ret_val; 1383 1384 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1385 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); 1386 return ret_val; 1387 } 1388 1389 /* The AutoNeg process has completed, so we now need to 1390 * read both the Auto Negotiation Advertisement 1391 * Register (Address 4) and the Auto_Negotiation Base 1392 * Page Ability Register (Address 5) to determine how 1393 * flow control was negotiated. 1394 */ 1395 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1396 &mii_nway_adv_reg); 1397 if (ret_val) 1398 return ret_val; 1399 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1400 &mii_nway_lp_ability_reg); 1401 if (ret_val) 1402 return ret_val; 1403 1404 /* Two bits in the Auto Negotiation Advertisement Register 1405 * (Address 4) and two bits in the Auto Negotiation Base 1406 * Page Ability Register (Address 5) determine flow control 1407 * for both the PHY and the link partner. The following 1408 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1409 * 1999, describes these PAUSE resolution bits and how flow 1410 * control is determined based upon these settings. 1411 * NOTE: DC = Don't Care 1412 * 1413 * LOCAL DEVICE | LINK PARTNER 1414 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1415 *-------|---------|-------|---------|-------------------- 1416 * 0 | 0 | DC | DC | e1000_fc_none 1417 * 0 | 1 | 0 | DC | e1000_fc_none 1418 * 0 | 1 | 1 | 0 | e1000_fc_none 1419 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1420 * 1 | 0 | 0 | DC | e1000_fc_none 1421 * 1 | DC | 1 | DC | e1000_fc_full 1422 * 1 | 1 | 0 | 0 | e1000_fc_none 1423 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1424 * 1425 * Are both PAUSE bits set to 1? If so, this implies 1426 * Symmetric Flow Control is enabled at both ends. The 1427 * ASM_DIR bits are irrelevant per the spec. 1428 * 1429 * For Symmetric Flow Control: 1430 * 1431 * LOCAL DEVICE | LINK PARTNER 1432 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1433 *-------|---------|-------|---------|-------------------- 1434 * 1 | DC | 1 | DC | E1000_fc_full 1435 * 1436 */ 1437 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1438 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1439 /* Now we need to check if the user selected Rx ONLY 1440 * of pause frames. In this case, we had to advertise 1441 * FULL flow control because we could not advertise Rx 1442 * ONLY. Hence, we must now check to see if we need to 1443 * turn OFF the TRANSMISSION of PAUSE frames. 1444 */ 1445 if (hw->fc.requested_mode == e1000_fc_full) { 1446 hw->fc.current_mode = e1000_fc_full; 1447 DEBUGOUT("Flow Control = FULL.\n"); 1448 } else { 1449 hw->fc.current_mode = e1000_fc_rx_pause; 1450 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1451 } 1452 } 1453 /* For receiving PAUSE frames ONLY. 1454 * 1455 * LOCAL DEVICE | LINK PARTNER 1456 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1457 *-------|---------|-------|---------|-------------------- 1458 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1459 */ 1460 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1461 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1462 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1463 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1464 hw->fc.current_mode = e1000_fc_tx_pause; 1465 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1466 } 1467 /* For transmitting PAUSE frames ONLY. 1468 * 1469 * LOCAL DEVICE | LINK PARTNER 1470 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1471 *-------|---------|-------|---------|-------------------- 1472 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1473 */ 1474 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1475 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1476 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1477 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1478 hw->fc.current_mode = e1000_fc_rx_pause; 1479 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1480 } else { 1481 /* Per the IEEE spec, at this point flow control 1482 * should be disabled. 1483 */ 1484 hw->fc.current_mode = e1000_fc_none; 1485 DEBUGOUT("Flow Control = NONE.\n"); 1486 } 1487 1488 /* Now we need to do one last check... If we auto- 1489 * negotiated to HALF DUPLEX, flow control should not be 1490 * enabled per IEEE 802.3 spec. 1491 */ 1492 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1493 if (ret_val) { 1494 DEBUGOUT("Error getting link speed and duplex\n"); 1495 return ret_val; 1496 } 1497 1498 if (duplex == HALF_DUPLEX) 1499 hw->fc.current_mode = e1000_fc_none; 1500 1501 /* Now we call a subroutine to actually force the MAC 1502 * controller to use the correct flow control settings. 1503 */ 1504 ret_val = e1000_force_mac_fc_generic(hw); 1505 if (ret_val) { 1506 DEBUGOUT("Error forcing flow control settings\n"); 1507 return ret_val; 1508 } 1509 } 1510 1511 /* Check for the case where we have SerDes media and auto-neg is 1512 * enabled. In this case, we need to check and see if Auto-Neg 1513 * has completed, and if so, how the PHY and link partner has 1514 * flow control configured. 1515 */ 1516 if ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1517 mac->autoneg) { 1518 /* Read the PCS_LSTS and check to see if AutoNeg 1519 * has completed. 1520 */ 1521 pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT); 1522 1523 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) { 1524 DEBUGOUT("PCS Auto Neg has not completed.\n"); 1525 return ret_val; 1526 } 1527 1528 /* The AutoNeg process has completed, so we now need to 1529 * read both the Auto Negotiation Advertisement 1530 * Register (PCS_ANADV) and the Auto_Negotiation Base 1531 * Page Ability Register (PCS_LPAB) to determine how 1532 * flow control was negotiated. 1533 */ 1534 pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); 1535 pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB); 1536 1537 /* Two bits in the Auto Negotiation Advertisement Register 1538 * (PCS_ANADV) and two bits in the Auto Negotiation Base 1539 * Page Ability Register (PCS_LPAB) determine flow control 1540 * for both the PHY and the link partner. The following 1541 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1542 * 1999, describes these PAUSE resolution bits and how flow 1543 * control is determined based upon these settings. 1544 * NOTE: DC = Don't Care 1545 * 1546 * LOCAL DEVICE | LINK PARTNER 1547 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1548 *-------|---------|-------|---------|-------------------- 1549 * 0 | 0 | DC | DC | e1000_fc_none 1550 * 0 | 1 | 0 | DC | e1000_fc_none 1551 * 0 | 1 | 1 | 0 | e1000_fc_none 1552 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1553 * 1 | 0 | 0 | DC | e1000_fc_none 1554 * 1 | DC | 1 | DC | e1000_fc_full 1555 * 1 | 1 | 0 | 0 | e1000_fc_none 1556 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1557 * 1558 * Are both PAUSE bits set to 1? If so, this implies 1559 * Symmetric Flow Control is enabled at both ends. The 1560 * ASM_DIR bits are irrelevant per the spec. 1561 * 1562 * For Symmetric Flow Control: 1563 * 1564 * LOCAL DEVICE | LINK PARTNER 1565 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1566 *-------|---------|-------|---------|-------------------- 1567 * 1 | DC | 1 | DC | e1000_fc_full 1568 * 1569 */ 1570 if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1571 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) { 1572 /* Now we need to check if the user selected Rx ONLY 1573 * of pause frames. In this case, we had to advertise 1574 * FULL flow control because we could not advertise Rx 1575 * ONLY. Hence, we must now check to see if we need to 1576 * turn OFF the TRANSMISSION of PAUSE frames. 1577 */ 1578 if (hw->fc.requested_mode == e1000_fc_full) { 1579 hw->fc.current_mode = e1000_fc_full; 1580 DEBUGOUT("Flow Control = FULL.\n"); 1581 } else { 1582 hw->fc.current_mode = e1000_fc_rx_pause; 1583 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1584 } 1585 } 1586 /* For receiving PAUSE frames ONLY. 1587 * 1588 * LOCAL DEVICE | LINK PARTNER 1589 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1590 *-------|---------|-------|---------|-------------------- 1591 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1592 */ 1593 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) && 1594 (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1595 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1596 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1597 hw->fc.current_mode = e1000_fc_tx_pause; 1598 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1599 } 1600 /* For transmitting PAUSE frames ONLY. 1601 * 1602 * LOCAL DEVICE | LINK PARTNER 1603 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1604 *-------|---------|-------|---------|-------------------- 1605 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1606 */ 1607 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1608 (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1609 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1610 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1611 hw->fc.current_mode = e1000_fc_rx_pause; 1612 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1613 } else { 1614 /* Per the IEEE spec, at this point flow control 1615 * should be disabled. 1616 */ 1617 hw->fc.current_mode = e1000_fc_none; 1618 DEBUGOUT("Flow Control = NONE.\n"); 1619 } 1620 1621 /* Now we call a subroutine to actually force the MAC 1622 * controller to use the correct flow control settings. 1623 */ 1624 pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1625 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1626 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg); 1627 1628 ret_val = e1000_force_mac_fc_generic(hw); 1629 if (ret_val) { 1630 DEBUGOUT("Error forcing flow control settings\n"); 1631 return ret_val; 1632 } 1633 } 1634 1635 return E1000_SUCCESS; 1636} 1637 1638/** 1639 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1640 * @hw: pointer to the HW structure 1641 * @speed: stores the current speed 1642 * @duplex: stores the current duplex 1643 * 1644 * Read the status register for the current speed/duplex and store the current 1645 * speed and duplex for copper connections. 1646 **/ 1647s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1648 u16 *duplex) 1649{ 1650 u32 status; 1651 1652 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1653 1654 status = E1000_READ_REG(hw, E1000_STATUS); 1655 if (status & E1000_STATUS_SPEED_1000) { 1656 *speed = SPEED_1000; 1657 DEBUGOUT("1000 Mbs, "); 1658 } else if (status & E1000_STATUS_SPEED_100) { 1659 *speed = SPEED_100; 1660 DEBUGOUT("100 Mbs, "); 1661 } else { 1662 *speed = SPEED_10; 1663 DEBUGOUT("10 Mbs, "); 1664 } 1665 1666 if (status & E1000_STATUS_FD) { 1667 *duplex = FULL_DUPLEX; 1668 DEBUGOUT("Full Duplex\n"); 1669 } else { 1670 *duplex = HALF_DUPLEX; 1671 DEBUGOUT("Half Duplex\n"); 1672 } 1673 1674 return E1000_SUCCESS; 1675} 1676 1677/** 1678 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1679 * @hw: pointer to the HW structure 1680 * @speed: stores the current speed 1681 * @duplex: stores the current duplex 1682 * 1683 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1684 * for fiber/serdes links. 1685 **/ 1686s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw, 1687 u16 *speed, u16 *duplex) 1688{ 1689 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1690 1691 *speed = SPEED_1000; 1692 *duplex = FULL_DUPLEX; 1693 1694 return E1000_SUCCESS; 1695} 1696 1697/** 1698 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1699 * @hw: pointer to the HW structure 1700 * 1701 * Acquire the HW semaphore to access the PHY or NVM 1702 **/ 1703s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1704{ 1705 u32 swsm; 1706 s32 timeout = hw->nvm.word_size + 1; 1707 s32 i = 0; 1708 1709 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1710 1711 /* Get the SW semaphore */ 1712 while (i < timeout) { 1713 swsm = E1000_READ_REG(hw, E1000_SWSM); 1714 if (!(swsm & E1000_SWSM_SMBI)) 1715 break; 1716 1717 usec_delay(50); 1718 i++; 1719 } 1720 1721 if (i == timeout) { 1722 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1723 return -E1000_ERR_NVM; 1724 } 1725 1726 /* Get the FW semaphore. */ 1727 for (i = 0; i < timeout; i++) { 1728 swsm = E1000_READ_REG(hw, E1000_SWSM); 1729 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1730 1731 /* Semaphore acquired if bit latched */ 1732 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1733 break; 1734 1735 usec_delay(50); 1736 } 1737 1738 if (i == timeout) { 1739 /* Release semaphores */ 1740 e1000_put_hw_semaphore_generic(hw); 1741 DEBUGOUT("Driver can't access the NVM\n"); 1742 return -E1000_ERR_NVM; 1743 } 1744 1745 return E1000_SUCCESS; 1746} 1747 1748/** 1749 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1750 * @hw: pointer to the HW structure 1751 * 1752 * Release hardware semaphore used to access the PHY or NVM 1753 **/ 1754void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1755{ 1756 u32 swsm; 1757 1758 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1759 1760 swsm = E1000_READ_REG(hw, E1000_SWSM); 1761 1762 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1763 1764 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1765} 1766 1767/** 1768 * e1000_get_auto_rd_done_generic - Check for auto read completion 1769 * @hw: pointer to the HW structure 1770 * 1771 * Check EEPROM for Auto Read done bit. 1772 **/ 1773s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1774{ 1775 s32 i = 0; 1776 1777 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1778 1779 while (i < AUTO_READ_DONE_TIMEOUT) { 1780 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1781 break; 1782 msec_delay(1); 1783 i++; 1784 } 1785 1786 if (i == AUTO_READ_DONE_TIMEOUT) { 1787 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1788 return -E1000_ERR_RESET; 1789 } 1790 1791 return E1000_SUCCESS; 1792} 1793 1794/** 1795 * e1000_valid_led_default_generic - Verify a valid default LED config 1796 * @hw: pointer to the HW structure 1797 * @data: pointer to the NVM (EEPROM) 1798 * 1799 * Read the EEPROM for the current default LED configuration. If the 1800 * LED configuration is not valid, set to a valid LED configuration. 1801 **/ 1802s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1803{ 1804 s32 ret_val; 1805 1806 DEBUGFUNC("e1000_valid_led_default_generic"); 1807 1808 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1809 if (ret_val) { 1810 DEBUGOUT("NVM Read Error\n"); 1811 return ret_val; 1812 } 1813 1814 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1815 *data = ID_LED_DEFAULT; 1816 1817 return E1000_SUCCESS; 1818} 1819 1820/** 1821 * e1000_id_led_init_generic - 1822 * @hw: pointer to the HW structure 1823 * 1824 **/ 1825s32 e1000_id_led_init_generic(struct e1000_hw *hw) 1826{ 1827 struct e1000_mac_info *mac = &hw->mac; 1828 s32 ret_val; 1829 const u32 ledctl_mask = 0x000000FF; 1830 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1831 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1832 u16 data, i, temp; 1833 const u16 led_mask = 0x0F; 1834 1835 DEBUGFUNC("e1000_id_led_init_generic"); 1836 1837 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1838 if (ret_val) 1839 return ret_val; 1840 1841 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1842 mac->ledctl_mode1 = mac->ledctl_default; 1843 mac->ledctl_mode2 = mac->ledctl_default; 1844 1845 for (i = 0; i < 4; i++) { 1846 temp = (data >> (i << 2)) & led_mask; 1847 switch (temp) { 1848 case ID_LED_ON1_DEF2: 1849 case ID_LED_ON1_ON2: 1850 case ID_LED_ON1_OFF2: 1851 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1852 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1853 break; 1854 case ID_LED_OFF1_DEF2: 1855 case ID_LED_OFF1_ON2: 1856 case ID_LED_OFF1_OFF2: 1857 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1858 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1859 break; 1860 default: 1861 /* Do nothing */ 1862 break; 1863 } 1864 switch (temp) { 1865 case ID_LED_DEF1_ON2: 1866 case ID_LED_ON1_ON2: 1867 case ID_LED_OFF1_ON2: 1868 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1869 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1870 break; 1871 case ID_LED_DEF1_OFF2: 1872 case ID_LED_ON1_OFF2: 1873 case ID_LED_OFF1_OFF2: 1874 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1875 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1876 break; 1877 default: 1878 /* Do nothing */ 1879 break; 1880 } 1881 } 1882 1883 return E1000_SUCCESS; 1884} 1885 1886/** 1887 * e1000_setup_led_generic - Configures SW controllable LED 1888 * @hw: pointer to the HW structure 1889 * 1890 * This prepares the SW controllable LED for use and saves the current state 1891 * of the LED so it can be later restored. 1892 **/ 1893s32 e1000_setup_led_generic(struct e1000_hw *hw) 1894{ 1895 u32 ledctl; 1896 1897 DEBUGFUNC("e1000_setup_led_generic"); 1898 1899 if (hw->mac.ops.setup_led != e1000_setup_led_generic) 1900 return -E1000_ERR_CONFIG; 1901 1902 if (hw->phy.media_type == e1000_media_type_fiber) { 1903 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1904 hw->mac.ledctl_default = ledctl; 1905 /* Turn off LED0 */ 1906 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | 1907 E1000_LEDCTL_LED0_MODE_MASK); 1908 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1909 E1000_LEDCTL_LED0_MODE_SHIFT); 1910 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1911 } else if (hw->phy.media_type == e1000_media_type_copper) { 1912 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1913 } 1914 1915 return E1000_SUCCESS; 1916} 1917 1918/** 1919 * e1000_cleanup_led_generic - Set LED config to default operation 1920 * @hw: pointer to the HW structure 1921 * 1922 * Remove the current LED configuration and set the LED configuration 1923 * to the default value, saved from the EEPROM. 1924 **/ 1925s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1926{ 1927 DEBUGFUNC("e1000_cleanup_led_generic"); 1928 1929 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1930 return E1000_SUCCESS; 1931} 1932 1933/** 1934 * e1000_blink_led_generic - Blink LED 1935 * @hw: pointer to the HW structure 1936 * 1937 * Blink the LEDs which are set to be on. 1938 **/ 1939s32 e1000_blink_led_generic(struct e1000_hw *hw) 1940{ 1941 u32 ledctl_blink = 0; 1942 u32 i; 1943 1944 DEBUGFUNC("e1000_blink_led_generic"); 1945 1946 if (hw->phy.media_type == e1000_media_type_fiber) { 1947 /* always blink LED0 for PCI-E fiber */ 1948 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1949 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1950 } else { 1951 /* Set the blink bit for each LED that's "on" (0x0E) 1952 * (or "off" if inverted) in ledctl_mode2. The blink 1953 * logic in hardware only works when mode is set to "on" 1954 * so it must be changed accordingly when the mode is 1955 * "off" and inverted. 1956 */ 1957 ledctl_blink = hw->mac.ledctl_mode2; 1958 for (i = 0; i < 32; i += 8) { 1959 u32 mode = (hw->mac.ledctl_mode2 >> i) & 1960 E1000_LEDCTL_LED0_MODE_MASK; 1961 u32 led_default = hw->mac.ledctl_default >> i; 1962 1963 if ((!(led_default & E1000_LEDCTL_LED0_IVRT) && 1964 (mode == E1000_LEDCTL_MODE_LED_ON)) || 1965 ((led_default & E1000_LEDCTL_LED0_IVRT) && 1966 (mode == E1000_LEDCTL_MODE_LED_OFF))) { 1967 ledctl_blink &= 1968 ~(E1000_LEDCTL_LED0_MODE_MASK << i); 1969 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK | 1970 E1000_LEDCTL_MODE_LED_ON) << i; 1971 } 1972 } 1973 } 1974 1975 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1976 1977 return E1000_SUCCESS; 1978} 1979 1980/** 1981 * e1000_led_on_generic - Turn LED on 1982 * @hw: pointer to the HW structure 1983 * 1984 * Turn LED on. 1985 **/ 1986s32 e1000_led_on_generic(struct e1000_hw *hw) 1987{ 1988 u32 ctrl; 1989 1990 DEBUGFUNC("e1000_led_on_generic"); 1991 1992 switch (hw->phy.media_type) { 1993 case e1000_media_type_fiber: 1994 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1995 ctrl &= ~E1000_CTRL_SWDPIN0; 1996 ctrl |= E1000_CTRL_SWDPIO0; 1997 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1998 break; 1999 case e1000_media_type_copper: 2000 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 2001 break; 2002 default: 2003 break; 2004 } 2005 2006 return E1000_SUCCESS; 2007} 2008 2009/** 2010 * e1000_led_off_generic - Turn LED off 2011 * @hw: pointer to the HW structure 2012 * 2013 * Turn LED off. 2014 **/ 2015s32 e1000_led_off_generic(struct e1000_hw *hw) 2016{ 2017 u32 ctrl; 2018 2019 DEBUGFUNC("e1000_led_off_generic"); 2020 2021 switch (hw->phy.media_type) { 2022 case e1000_media_type_fiber: 2023 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2024 ctrl |= E1000_CTRL_SWDPIN0; 2025 ctrl |= E1000_CTRL_SWDPIO0; 2026 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2027 break; 2028 case e1000_media_type_copper: 2029 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 2030 break; 2031 default: 2032 break; 2033 } 2034 2035 return E1000_SUCCESS; 2036} 2037 2038/** 2039 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 2040 * @hw: pointer to the HW structure 2041 * @no_snoop: bitmap of snoop events 2042 * 2043 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 2044 **/ 2045void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 2046{ 2047 u32 gcr; 2048 2049 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 2050 2051 if (hw->bus.type != e1000_bus_type_pci_express) 2052 return; 2053 2054 if (no_snoop) { 2055 gcr = E1000_READ_REG(hw, E1000_GCR); 2056 gcr &= ~(PCIE_NO_SNOOP_ALL); 2057 gcr |= no_snoop; 2058 E1000_WRITE_REG(hw, E1000_GCR, gcr); 2059 } 2060} 2061 2062/** 2063 * e1000_disable_pcie_master_generic - Disables PCI-express master access 2064 * @hw: pointer to the HW structure 2065 * 2066 * Returns E1000_SUCCESS if successful, else returns -10 2067 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 2068 * the master requests to be disabled. 2069 * 2070 * Disables PCI-Express master access and verifies there are no pending 2071 * requests. 2072 **/ 2073s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 2074{ 2075 u32 ctrl; 2076 s32 timeout = MASTER_DISABLE_TIMEOUT; 2077 2078 DEBUGFUNC("e1000_disable_pcie_master_generic"); 2079 2080 if (hw->bus.type != e1000_bus_type_pci_express) 2081 return E1000_SUCCESS; 2082 2083 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2084 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2085 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2086 2087 while (timeout) { 2088 if (!(E1000_READ_REG(hw, E1000_STATUS) & 2089 E1000_STATUS_GIO_MASTER_ENABLE) || 2090 E1000_REMOVED(hw->hw_addr)) 2091 break; 2092 usec_delay(100); 2093 timeout--; 2094 } 2095 2096 if (!timeout) { 2097 DEBUGOUT("Master requests are pending.\n"); 2098 return -E1000_ERR_MASTER_REQUESTS_PENDING; 2099 } 2100 2101 return E1000_SUCCESS; 2102} 2103 2104/** 2105 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2106 * @hw: pointer to the HW structure 2107 * 2108 * Reset the Adaptive Interframe Spacing throttle to default values. 2109 **/ 2110void e1000_reset_adaptive_generic(struct e1000_hw *hw) 2111{ 2112 struct e1000_mac_info *mac = &hw->mac; 2113 2114 DEBUGFUNC("e1000_reset_adaptive_generic"); 2115 2116 if (!mac->adaptive_ifs) { 2117 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2118 return; 2119 } 2120 2121 mac->current_ifs_val = 0; 2122 mac->ifs_min_val = IFS_MIN; 2123 mac->ifs_max_val = IFS_MAX; 2124 mac->ifs_step_size = IFS_STEP; 2125 mac->ifs_ratio = IFS_RATIO; 2126 2127 mac->in_ifs_mode = FALSE; 2128 E1000_WRITE_REG(hw, E1000_AIT, 0); 2129} 2130 2131/** 2132 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2133 * @hw: pointer to the HW structure 2134 * 2135 * Update the Adaptive Interframe Spacing Throttle value based on the 2136 * time between transmitted packets and time between collisions. 2137 **/ 2138void e1000_update_adaptive_generic(struct e1000_hw *hw) 2139{ 2140 struct e1000_mac_info *mac = &hw->mac; 2141 2142 DEBUGFUNC("e1000_update_adaptive_generic"); 2143 2144 if (!mac->adaptive_ifs) { 2145 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2146 return; 2147 } 2148 2149 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2150 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2151 mac->in_ifs_mode = TRUE; 2152 if (mac->current_ifs_val < mac->ifs_max_val) { 2153 if (!mac->current_ifs_val) 2154 mac->current_ifs_val = mac->ifs_min_val; 2155 else 2156 mac->current_ifs_val += 2157 mac->ifs_step_size; 2158 E1000_WRITE_REG(hw, E1000_AIT, 2159 mac->current_ifs_val); 2160 } 2161 } 2162 } else { 2163 if (mac->in_ifs_mode && 2164 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2165 mac->current_ifs_val = 0; 2166 mac->in_ifs_mode = FALSE; 2167 E1000_WRITE_REG(hw, E1000_AIT, 0); 2168 } 2169 } 2170} 2171 2172/** 2173 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2174 * @hw: pointer to the HW structure 2175 * 2176 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2177 * set, which is forced to MDI mode only. 2178 **/ 2179static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2180{ 2181 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2182 2183 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2184 DEBUGOUT("Invalid MDI setting detected\n"); 2185 hw->phy.mdix = 1; 2186 return -E1000_ERR_CONFIG; 2187 } 2188 2189 return E1000_SUCCESS; 2190} 2191 2192/** 2193 * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings 2194 * @hw: pointer to the HW structure 2195 * 2196 * Validate the MDI/MDIx setting, allowing for auto-crossover during forced 2197 * operation. 2198 **/ 2199s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw) 2200{ 2201 DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic"); 2202 2203 return E1000_SUCCESS; 2204} 2205 2206/** 2207 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2208 * @hw: pointer to the HW structure 2209 * @reg: 32bit register offset such as E1000_SCTL 2210 * @offset: register offset to write to 2211 * @data: data to write at register offset 2212 * 2213 * Writes an address/data control type register. There are several of these 2214 * and they all have the format address << 8 | data and bit 31 is polled for 2215 * completion. 2216 **/ 2217s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2218 u32 offset, u8 data) 2219{ 2220 u32 i, regvalue = 0; 2221 2222 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2223 2224 /* Set up the address and data */ 2225 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2226 E1000_WRITE_REG(hw, reg, regvalue); 2227 2228 /* Poll the ready bit to see if the MDI read completed */ 2229 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2230 usec_delay(5); 2231 regvalue = E1000_READ_REG(hw, reg); 2232 if (regvalue & E1000_GEN_CTL_READY) 2233 break; 2234 } 2235 if (!(regvalue & E1000_GEN_CTL_READY)) { 2236 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2237 return -E1000_ERR_PHY; 2238 } 2239 2240 return E1000_SUCCESS; 2241} 2242