e1000_mac.c revision 213234
1/****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/e1000_mac.c 213234 2010-09-28 00:13:15Z jfv $*/ 34 35#include "e1000_api.h" 36 37static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 38static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 39 40/** 41 * e1000_init_mac_ops_generic - Initialize MAC function pointers 42 * @hw: pointer to the HW structure 43 * 44 * Setups up the function pointers to no-op functions 45 **/ 46void e1000_init_mac_ops_generic(struct e1000_hw *hw) 47{ 48 struct e1000_mac_info *mac = &hw->mac; 49 DEBUGFUNC("e1000_init_mac_ops_generic"); 50 51 /* General Setup */ 52 mac->ops.init_params = e1000_null_ops_generic; 53 mac->ops.init_hw = e1000_null_ops_generic; 54 mac->ops.reset_hw = e1000_null_ops_generic; 55 mac->ops.setup_physical_interface = e1000_null_ops_generic; 56 mac->ops.get_bus_info = e1000_null_ops_generic; 57 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 58 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 59 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 60 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 61 /* LED */ 62 mac->ops.cleanup_led = e1000_null_ops_generic; 63 mac->ops.setup_led = e1000_null_ops_generic; 64 mac->ops.blink_led = e1000_null_ops_generic; 65 mac->ops.led_on = e1000_null_ops_generic; 66 mac->ops.led_off = e1000_null_ops_generic; 67 /* LINK */ 68 mac->ops.setup_link = e1000_null_ops_generic; 69 mac->ops.get_link_up_info = e1000_null_link_info; 70 mac->ops.check_for_link = e1000_null_ops_generic; 71 mac->ops.wait_autoneg = e1000_wait_autoneg_generic; 72 /* Management */ 73 mac->ops.check_mng_mode = e1000_null_mng_mode; 74 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; 75 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; 76 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; 77 /* VLAN, MC, etc. */ 78 mac->ops.update_mc_addr_list = e1000_null_update_mc; 79 mac->ops.clear_vfta = e1000_null_mac_generic; 80 mac->ops.write_vfta = e1000_null_write_vfta; 81 mac->ops.rar_set = e1000_rar_set_generic; 82 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 83} 84 85/** 86 * e1000_null_ops_generic - No-op function, returns 0 87 * @hw: pointer to the HW structure 88 **/ 89s32 e1000_null_ops_generic(struct e1000_hw *hw) 90{ 91 DEBUGFUNC("e1000_null_ops_generic"); 92 return E1000_SUCCESS; 93} 94 95/** 96 * e1000_null_mac_generic - No-op function, return void 97 * @hw: pointer to the HW structure 98 **/ 99void e1000_null_mac_generic(struct e1000_hw *hw) 100{ 101 DEBUGFUNC("e1000_null_mac_generic"); 102 return; 103} 104 105/** 106 * e1000_null_link_info - No-op function, return 0 107 * @hw: pointer to the HW structure 108 **/ 109s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) 110{ 111 DEBUGFUNC("e1000_null_link_info"); 112 return E1000_SUCCESS; 113} 114 115/** 116 * e1000_null_mng_mode - No-op function, return FALSE 117 * @hw: pointer to the HW structure 118 **/ 119bool e1000_null_mng_mode(struct e1000_hw *hw) 120{ 121 DEBUGFUNC("e1000_null_mng_mode"); 122 return FALSE; 123} 124 125/** 126 * e1000_null_update_mc - No-op function, return void 127 * @hw: pointer to the HW structure 128 **/ 129void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a) 130{ 131 DEBUGFUNC("e1000_null_update_mc"); 132 return; 133} 134 135/** 136 * e1000_null_write_vfta - No-op function, return void 137 * @hw: pointer to the HW structure 138 **/ 139void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b) 140{ 141 DEBUGFUNC("e1000_null_write_vfta"); 142 return; 143} 144 145/** 146 * e1000_null_rar_set - No-op function, return void 147 * @hw: pointer to the HW structure 148 **/ 149void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a) 150{ 151 DEBUGFUNC("e1000_null_rar_set"); 152 return; 153} 154 155/** 156 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 157 * @hw: pointer to the HW structure 158 * 159 * Determines and stores the system bus information for a particular 160 * network interface. The following bus information is determined and stored: 161 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 162 **/ 163s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 164{ 165 struct e1000_mac_info *mac = &hw->mac; 166 struct e1000_bus_info *bus = &hw->bus; 167 u32 status = E1000_READ_REG(hw, E1000_STATUS); 168 s32 ret_val = E1000_SUCCESS; 169 170 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 171 172 /* PCI or PCI-X? */ 173 bus->type = (status & E1000_STATUS_PCIX_MODE) 174 ? e1000_bus_type_pcix 175 : e1000_bus_type_pci; 176 177 /* Bus speed */ 178 if (bus->type == e1000_bus_type_pci) { 179 bus->speed = (status & E1000_STATUS_PCI66) 180 ? e1000_bus_speed_66 181 : e1000_bus_speed_33; 182 } else { 183 switch (status & E1000_STATUS_PCIX_SPEED) { 184 case E1000_STATUS_PCIX_SPEED_66: 185 bus->speed = e1000_bus_speed_66; 186 break; 187 case E1000_STATUS_PCIX_SPEED_100: 188 bus->speed = e1000_bus_speed_100; 189 break; 190 case E1000_STATUS_PCIX_SPEED_133: 191 bus->speed = e1000_bus_speed_133; 192 break; 193 default: 194 bus->speed = e1000_bus_speed_reserved; 195 break; 196 } 197 } 198 199 /* Bus width */ 200 bus->width = (status & E1000_STATUS_BUS64) 201 ? e1000_bus_width_64 202 : e1000_bus_width_32; 203 204 /* Which PCI(-X) function? */ 205 mac->ops.set_lan_id(hw); 206 207 return ret_val; 208} 209 210/** 211 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 212 * @hw: pointer to the HW structure 213 * 214 * Determines and stores the system bus information for a particular 215 * network interface. The following bus information is determined and stored: 216 * bus speed, bus width, type (PCIe), and PCIe function. 217 **/ 218s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 219{ 220 struct e1000_mac_info *mac = &hw->mac; 221 struct e1000_bus_info *bus = &hw->bus; 222 s32 ret_val; 223 u16 pcie_link_status; 224 225 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 226 227 bus->type = e1000_bus_type_pci_express; 228 229 ret_val = e1000_read_pcie_cap_reg(hw, 230 PCIE_LINK_STATUS, 231 &pcie_link_status); 232 if (ret_val) { 233 bus->width = e1000_bus_width_unknown; 234 bus->speed = e1000_bus_speed_unknown; 235 } else { 236 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) { 237 case PCIE_LINK_SPEED_2500: 238 bus->speed = e1000_bus_speed_2500; 239 break; 240 case PCIE_LINK_SPEED_5000: 241 bus->speed = e1000_bus_speed_5000; 242 break; 243 default: 244 bus->speed = e1000_bus_speed_unknown; 245 break; 246 } 247 248 bus->width = (enum e1000_bus_width)((pcie_link_status & 249 PCIE_LINK_WIDTH_MASK) >> 250 PCIE_LINK_WIDTH_SHIFT); 251 } 252 253 mac->ops.set_lan_id(hw); 254 255 return E1000_SUCCESS; 256} 257 258/** 259 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 260 * 261 * @hw: pointer to the HW structure 262 * 263 * Determines the LAN function id by reading memory-mapped registers 264 * and swaps the port value if requested. 265 **/ 266static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 267{ 268 struct e1000_bus_info *bus = &hw->bus; 269 u32 reg; 270 271 /* 272 * The status register reports the correct function number 273 * for the device regardless of function swap state. 274 */ 275 reg = E1000_READ_REG(hw, E1000_STATUS); 276 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 277} 278 279/** 280 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 281 * @hw: pointer to the HW structure 282 * 283 * Determines the LAN function id by reading PCI config space. 284 **/ 285void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 286{ 287 struct e1000_bus_info *bus = &hw->bus; 288 u16 pci_header_type; 289 u32 status; 290 291 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 292 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 293 status = E1000_READ_REG(hw, E1000_STATUS); 294 bus->func = (status & E1000_STATUS_FUNC_MASK) 295 >> E1000_STATUS_FUNC_SHIFT; 296 } else { 297 bus->func = 0; 298 } 299} 300 301/** 302 * e1000_set_lan_id_single_port - Set LAN id for a single port device 303 * @hw: pointer to the HW structure 304 * 305 * Sets the LAN function id to zero for a single port device. 306 **/ 307void e1000_set_lan_id_single_port(struct e1000_hw *hw) 308{ 309 struct e1000_bus_info *bus = &hw->bus; 310 311 bus->func = 0; 312} 313 314/** 315 * e1000_clear_vfta_generic - Clear VLAN filter table 316 * @hw: pointer to the HW structure 317 * 318 * Clears the register array which contains the VLAN filter table by 319 * setting all the values to 0. 320 **/ 321void e1000_clear_vfta_generic(struct e1000_hw *hw) 322{ 323 u32 offset; 324 325 DEBUGFUNC("e1000_clear_vfta_generic"); 326 327 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 328 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 329 E1000_WRITE_FLUSH(hw); 330 } 331} 332 333/** 334 * e1000_write_vfta_generic - Write value to VLAN filter table 335 * @hw: pointer to the HW structure 336 * @offset: register offset in VLAN filter table 337 * @value: register value written to VLAN filter table 338 * 339 * Writes value at the given offset in the register array which stores 340 * the VLAN filter table. 341 **/ 342void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 343{ 344 DEBUGFUNC("e1000_write_vfta_generic"); 345 346 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 347 E1000_WRITE_FLUSH(hw); 348} 349 350/** 351 * e1000_init_rx_addrs_generic - Initialize receive address's 352 * @hw: pointer to the HW structure 353 * @rar_count: receive address registers 354 * 355 * Setups the receive address registers by setting the base receive address 356 * register to the devices MAC address and clearing all the other receive 357 * address registers to 0. 358 **/ 359void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 360{ 361 u32 i; 362 u8 mac_addr[ETH_ADDR_LEN] = {0}; 363 364 DEBUGFUNC("e1000_init_rx_addrs_generic"); 365 366 /* Setup the receive address */ 367 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 368 369 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 370 371 /* Zero out the other (rar_entry_count - 1) receive addresses */ 372 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 373 for (i = 1; i < rar_count; i++) 374 hw->mac.ops.rar_set(hw, mac_addr, i); 375} 376 377/** 378 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 379 * @hw: pointer to the HW structure 380 * 381 * Checks the nvm for an alternate MAC address. An alternate MAC address 382 * can be setup by pre-boot software and must be treated like a permanent 383 * address and must override the actual permanent MAC address. If an 384 * alternate MAC address is found it is programmed into RAR0, replacing 385 * the permanent address that was installed into RAR0 by the Si on reset. 386 * This function will return SUCCESS unless it encounters an error while 387 * reading the EEPROM. 388 **/ 389s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 390{ 391 u32 i; 392 s32 ret_val = E1000_SUCCESS; 393 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 394 u8 alt_mac_addr[ETH_ADDR_LEN]; 395 396 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 397 398 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); 399 if (ret_val) 400 goto out; 401 402 /* Check for LOM (vs. NIC) or one of two valid mezzanine cards */ 403 if (!((nvm_data & NVM_COMPAT_LOM) || 404 (hw->device_id == E1000_DEV_ID_82571EB_SERDES_DUAL) || 405 (hw->device_id == E1000_DEV_ID_82571EB_SERDES_QUAD))) 406 goto out; 407 408 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 409 &nvm_alt_mac_addr_offset); 410 if (ret_val) { 411 DEBUGOUT("NVM Read Error\n"); 412 goto out; 413 } 414 415 if (nvm_alt_mac_addr_offset == 0xFFFF) { 416 /* There is no Alternate MAC Address */ 417 goto out; 418 } 419 420 if (hw->bus.func == E1000_FUNC_1) 421 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 422 if (hw->bus.func == E1000_FUNC_2) 423 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 424 425 if (hw->bus.func == E1000_FUNC_3) 426 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 427 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 428 offset = nvm_alt_mac_addr_offset + (i >> 1); 429 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 430 if (ret_val) { 431 DEBUGOUT("NVM Read Error\n"); 432 goto out; 433 } 434 435 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 436 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 437 } 438 439 /* if multicast bit is set, the alternate address will not be used */ 440 if (alt_mac_addr[0] & 0x01) { 441 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 442 goto out; 443 } 444 445 /* 446 * We have a valid alternate MAC address, and we want to treat it the 447 * same as the normal permanent MAC address stored by the HW into the 448 * RAR. Do this by mapping this address into RAR0. 449 */ 450 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 451 452out: 453 return ret_val; 454} 455 456/** 457 * e1000_rar_set_generic - Set receive address register 458 * @hw: pointer to the HW structure 459 * @addr: pointer to the receive address 460 * @index: receive address array register 461 * 462 * Sets the receive address array register at index to the address passed 463 * in by addr. 464 **/ 465void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 466{ 467 u32 rar_low, rar_high; 468 469 DEBUGFUNC("e1000_rar_set_generic"); 470 471 /* 472 * HW expects these in little endian so we reverse the byte order 473 * from network order (big endian) to little endian 474 */ 475 rar_low = ((u32) addr[0] | 476 ((u32) addr[1] << 8) | 477 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 478 479 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 480 481 /* If MAC address zero, no need to set the AV bit */ 482 if (rar_low || rar_high) 483 rar_high |= E1000_RAH_AV; 484 485 /* 486 * Some bridges will combine consecutive 32-bit writes into 487 * a single burst write, which will malfunction on some parts. 488 * The flushes avoid this. 489 */ 490 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 491 E1000_WRITE_FLUSH(hw); 492 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 493 E1000_WRITE_FLUSH(hw); 494} 495 496/** 497 * e1000_update_mc_addr_list_generic - Update Multicast addresses 498 * @hw: pointer to the HW structure 499 * @mc_addr_list: array of multicast addresses to program 500 * @mc_addr_count: number of multicast addresses to program 501 * 502 * Updates entire Multicast Table Array. 503 * The caller must have a packed mc_addr_list of multicast addresses. 504 **/ 505void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 506 u8 *mc_addr_list, u32 mc_addr_count) 507{ 508 u32 hash_value, hash_bit, hash_reg; 509 int i; 510 511 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 512 513 /* clear mta_shadow */ 514 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 515 516 /* update mta_shadow from mc_addr_list */ 517 for (i = 0; (u32) i < mc_addr_count; i++) { 518 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 519 520 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 521 hash_bit = hash_value & 0x1F; 522 523 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 524 mc_addr_list += (ETH_ADDR_LEN); 525 } 526 527 /* replace the entire MTA table */ 528 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 529 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 530 E1000_WRITE_FLUSH(hw); 531} 532 533/** 534 * e1000_hash_mc_addr_generic - Generate a multicast hash value 535 * @hw: pointer to the HW structure 536 * @mc_addr: pointer to a multicast address 537 * 538 * Generates a multicast address hash value which is used to determine 539 * the multicast filter table array address and new table value. 540 **/ 541u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 542{ 543 u32 hash_value, hash_mask; 544 u8 bit_shift = 0; 545 546 DEBUGFUNC("e1000_hash_mc_addr_generic"); 547 548 /* Register count multiplied by bits per register */ 549 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 550 551 /* 552 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 553 * where 0xFF would still fall within the hash mask. 554 */ 555 while (hash_mask >> bit_shift != 0xFF) 556 bit_shift++; 557 558 /* 559 * The portion of the address that is used for the hash table 560 * is determined by the mc_filter_type setting. 561 * The algorithm is such that there is a total of 8 bits of shifting. 562 * The bit_shift for a mc_filter_type of 0 represents the number of 563 * left-shifts where the MSB of mc_addr[5] would still fall within 564 * the hash_mask. Case 0 does this exactly. Since there are a total 565 * of 8 bits of shifting, then mc_addr[4] will shift right the 566 * remaining number of bits. Thus 8 - bit_shift. The rest of the 567 * cases are a variation of this algorithm...essentially raising the 568 * number of bits to shift mc_addr[5] left, while still keeping the 569 * 8-bit shifting total. 570 * 571 * For example, given the following Destination MAC Address and an 572 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 573 * we can see that the bit_shift for case 0 is 4. These are the hash 574 * values resulting from each mc_filter_type... 575 * [0] [1] [2] [3] [4] [5] 576 * 01 AA 00 12 34 56 577 * LSB MSB 578 * 579 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 580 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 581 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 582 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 583 */ 584 switch (hw->mac.mc_filter_type) { 585 default: 586 case 0: 587 break; 588 case 1: 589 bit_shift += 1; 590 break; 591 case 2: 592 bit_shift += 2; 593 break; 594 case 3: 595 bit_shift += 4; 596 break; 597 } 598 599 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 600 (((u16) mc_addr[5]) << bit_shift))); 601 602 return hash_value; 603} 604 605/** 606 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 607 * @hw: pointer to the HW structure 608 * 609 * In certain situations, a system BIOS may report that the PCIx maximum 610 * memory read byte count (MMRBC) value is higher than than the actual 611 * value. We check the PCIx command register with the current PCIx status 612 * register. 613 **/ 614void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 615{ 616 u16 cmd_mmrbc; 617 u16 pcix_cmd; 618 u16 pcix_stat_hi_word; 619 u16 stat_mmrbc; 620 621 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 622 623 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 624 if (hw->bus.type != e1000_bus_type_pcix) 625 return; 626 627 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 628 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 629 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 630 PCIX_COMMAND_MMRBC_SHIFT; 631 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 632 PCIX_STATUS_HI_MMRBC_SHIFT; 633 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 634 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 635 if (cmd_mmrbc > stat_mmrbc) { 636 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 637 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 638 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 639 } 640} 641 642/** 643 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 644 * @hw: pointer to the HW structure 645 * 646 * Clears the base hardware counters by reading the counter registers. 647 **/ 648void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 649{ 650 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 651 652 E1000_READ_REG(hw, E1000_CRCERRS); 653 E1000_READ_REG(hw, E1000_SYMERRS); 654 E1000_READ_REG(hw, E1000_MPC); 655 E1000_READ_REG(hw, E1000_SCC); 656 E1000_READ_REG(hw, E1000_ECOL); 657 E1000_READ_REG(hw, E1000_MCC); 658 E1000_READ_REG(hw, E1000_LATECOL); 659 E1000_READ_REG(hw, E1000_COLC); 660 E1000_READ_REG(hw, E1000_DC); 661 E1000_READ_REG(hw, E1000_SEC); 662 E1000_READ_REG(hw, E1000_RLEC); 663 E1000_READ_REG(hw, E1000_XONRXC); 664 E1000_READ_REG(hw, E1000_XONTXC); 665 E1000_READ_REG(hw, E1000_XOFFRXC); 666 E1000_READ_REG(hw, E1000_XOFFTXC); 667 E1000_READ_REG(hw, E1000_FCRUC); 668 E1000_READ_REG(hw, E1000_GPRC); 669 E1000_READ_REG(hw, E1000_BPRC); 670 E1000_READ_REG(hw, E1000_MPRC); 671 E1000_READ_REG(hw, E1000_GPTC); 672 E1000_READ_REG(hw, E1000_GORCL); 673 E1000_READ_REG(hw, E1000_GORCH); 674 E1000_READ_REG(hw, E1000_GOTCL); 675 E1000_READ_REG(hw, E1000_GOTCH); 676 E1000_READ_REG(hw, E1000_RNBC); 677 E1000_READ_REG(hw, E1000_RUC); 678 E1000_READ_REG(hw, E1000_RFC); 679 E1000_READ_REG(hw, E1000_ROC); 680 E1000_READ_REG(hw, E1000_RJC); 681 E1000_READ_REG(hw, E1000_TORL); 682 E1000_READ_REG(hw, E1000_TORH); 683 E1000_READ_REG(hw, E1000_TOTL); 684 E1000_READ_REG(hw, E1000_TOTH); 685 E1000_READ_REG(hw, E1000_TPR); 686 E1000_READ_REG(hw, E1000_TPT); 687 E1000_READ_REG(hw, E1000_MPTC); 688 E1000_READ_REG(hw, E1000_BPTC); 689} 690 691/** 692 * e1000_check_for_copper_link_generic - Check for link (Copper) 693 * @hw: pointer to the HW structure 694 * 695 * Checks to see of the link status of the hardware has changed. If a 696 * change in link status has been detected, then we read the PHY registers 697 * to get the current speed/duplex if link exists. 698 **/ 699s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 700{ 701 struct e1000_mac_info *mac = &hw->mac; 702 s32 ret_val; 703 bool link; 704 705 DEBUGFUNC("e1000_check_for_copper_link"); 706 707 /* 708 * We only want to go out to the PHY registers to see if Auto-Neg 709 * has completed and/or if our link status has changed. The 710 * get_link_status flag is set upon receiving a Link Status 711 * Change or Rx Sequence Error interrupt. 712 */ 713 if (!mac->get_link_status) { 714 ret_val = E1000_SUCCESS; 715 goto out; 716 } 717 718 /* 719 * First we want to see if the MII Status Register reports 720 * link. If so, then we want to get the current speed/duplex 721 * of the PHY. 722 */ 723 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 724 if (ret_val) 725 goto out; 726 727 if (!link) 728 goto out; /* No link detected */ 729 730 mac->get_link_status = FALSE; 731 732 /* 733 * Check if there was DownShift, must be checked 734 * immediately after link-up 735 */ 736 e1000_check_downshift_generic(hw); 737 738 /* 739 * If we are forcing speed/duplex, then we simply return since 740 * we have already determined whether we have link or not. 741 */ 742 if (!mac->autoneg) { 743 ret_val = -E1000_ERR_CONFIG; 744 goto out; 745 } 746 747 /* 748 * Auto-Neg is enabled. Auto Speed Detection takes care 749 * of MAC speed/duplex configuration. So we only need to 750 * configure Collision Distance in the MAC. 751 */ 752 mac->ops.config_collision_dist(hw); 753 754 /* 755 * Configure Flow Control now that Auto-Neg has completed. 756 * First, we need to restore the desired flow control 757 * settings because we may have had to re-autoneg with a 758 * different link partner. 759 */ 760 ret_val = e1000_config_fc_after_link_up_generic(hw); 761 if (ret_val) 762 DEBUGOUT("Error configuring flow control\n"); 763 764out: 765 return ret_val; 766} 767 768/** 769 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 770 * @hw: pointer to the HW structure 771 * 772 * Checks for link up on the hardware. If link is not up and we have 773 * a signal, then we need to force link up. 774 **/ 775s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 776{ 777 struct e1000_mac_info *mac = &hw->mac; 778 u32 rxcw; 779 u32 ctrl; 780 u32 status; 781 s32 ret_val = E1000_SUCCESS; 782 783 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 784 785 ctrl = E1000_READ_REG(hw, E1000_CTRL); 786 status = E1000_READ_REG(hw, E1000_STATUS); 787 rxcw = E1000_READ_REG(hw, E1000_RXCW); 788 789 /* 790 * If we don't have link (auto-negotiation failed or link partner 791 * cannot auto-negotiate), the cable is plugged in (we have signal), 792 * and our link partner is not trying to auto-negotiate with us (we 793 * are receiving idles or data), we need to force link up. We also 794 * need to give auto-negotiation time to complete, in case the cable 795 * was just plugged in. The autoneg_failed flag does this. 796 */ 797 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 798 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 799 (!(rxcw & E1000_RXCW_C))) { 800 if (mac->autoneg_failed == 0) { 801 mac->autoneg_failed = 1; 802 goto out; 803 } 804 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 805 806 /* Disable auto-negotiation in the TXCW register */ 807 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 808 809 /* Force link-up and also force full-duplex. */ 810 ctrl = E1000_READ_REG(hw, E1000_CTRL); 811 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 812 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 813 814 /* Configure Flow Control after forcing link up. */ 815 ret_val = e1000_config_fc_after_link_up_generic(hw); 816 if (ret_val) { 817 DEBUGOUT("Error configuring flow control\n"); 818 goto out; 819 } 820 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 821 /* 822 * If we are forcing link and we are receiving /C/ ordered 823 * sets, re-enable auto-negotiation in the TXCW register 824 * and disable forced link in the Device Control register 825 * in an attempt to auto-negotiate with our link partner. 826 */ 827 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 828 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 829 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 830 831 mac->serdes_has_link = TRUE; 832 } 833 834out: 835 return ret_val; 836} 837 838/** 839 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 840 * @hw: pointer to the HW structure 841 * 842 * Checks for link up on the hardware. If link is not up and we have 843 * a signal, then we need to force link up. 844 **/ 845s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 846{ 847 struct e1000_mac_info *mac = &hw->mac; 848 u32 rxcw; 849 u32 ctrl; 850 u32 status; 851 s32 ret_val = E1000_SUCCESS; 852 853 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 854 855 ctrl = E1000_READ_REG(hw, E1000_CTRL); 856 status = E1000_READ_REG(hw, E1000_STATUS); 857 rxcw = E1000_READ_REG(hw, E1000_RXCW); 858 859 /* 860 * If we don't have link (auto-negotiation failed or link partner 861 * cannot auto-negotiate), and our link partner is not trying to 862 * auto-negotiate with us (we are receiving idles or data), 863 * we need to force link up. We also need to give auto-negotiation 864 * time to complete. 865 */ 866 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 867 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 868 if (mac->autoneg_failed == 0) { 869 mac->autoneg_failed = 1; 870 goto out; 871 } 872 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 873 874 /* Disable auto-negotiation in the TXCW register */ 875 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 876 877 /* Force link-up and also force full-duplex. */ 878 ctrl = E1000_READ_REG(hw, E1000_CTRL); 879 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 880 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 881 882 /* Configure Flow Control after forcing link up. */ 883 ret_val = e1000_config_fc_after_link_up_generic(hw); 884 if (ret_val) { 885 DEBUGOUT("Error configuring flow control\n"); 886 goto out; 887 } 888 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 889 /* 890 * If we are forcing link and we are receiving /C/ ordered 891 * sets, re-enable auto-negotiation in the TXCW register 892 * and disable forced link in the Device Control register 893 * in an attempt to auto-negotiate with our link partner. 894 */ 895 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 896 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 897 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 898 899 mac->serdes_has_link = TRUE; 900 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 901 /* 902 * If we force link for non-auto-negotiation switch, check 903 * link status based on MAC synchronization for internal 904 * serdes media type. 905 */ 906 /* SYNCH bit and IV bit are sticky. */ 907 usec_delay(10); 908 rxcw = E1000_READ_REG(hw, E1000_RXCW); 909 if (rxcw & E1000_RXCW_SYNCH) { 910 if (!(rxcw & E1000_RXCW_IV)) { 911 mac->serdes_has_link = TRUE; 912 DEBUGOUT("SERDES: Link up - forced.\n"); 913 } 914 } else { 915 mac->serdes_has_link = FALSE; 916 DEBUGOUT("SERDES: Link down - force failed.\n"); 917 } 918 } 919 920 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 921 status = E1000_READ_REG(hw, E1000_STATUS); 922 if (status & E1000_STATUS_LU) { 923 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 924 usec_delay(10); 925 rxcw = E1000_READ_REG(hw, E1000_RXCW); 926 if (rxcw & E1000_RXCW_SYNCH) { 927 if (!(rxcw & E1000_RXCW_IV)) { 928 mac->serdes_has_link = TRUE; 929 DEBUGOUT("SERDES: Link up - autoneg " 930 "completed sucessfully.\n"); 931 } else { 932 mac->serdes_has_link = FALSE; 933 DEBUGOUT("SERDES: Link down - invalid" 934 "codewords detected in autoneg.\n"); 935 } 936 } else { 937 mac->serdes_has_link = FALSE; 938 DEBUGOUT("SERDES: Link down - no sync.\n"); 939 } 940 } else { 941 mac->serdes_has_link = FALSE; 942 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 943 } 944 } 945 946out: 947 return ret_val; 948} 949 950/** 951 * e1000_setup_link_generic - Setup flow control and link settings 952 * @hw: pointer to the HW structure 953 * 954 * Determines which flow control settings to use, then configures flow 955 * control. Calls the appropriate media-specific link configuration 956 * function. Assuming the adapter has a valid link partner, a valid link 957 * should be established. Assumes the hardware has previously been reset 958 * and the transmitter and receiver are not enabled. 959 **/ 960s32 e1000_setup_link_generic(struct e1000_hw *hw) 961{ 962 s32 ret_val = E1000_SUCCESS; 963 964 DEBUGFUNC("e1000_setup_link_generic"); 965 966 /* 967 * In the case of the phy reset being blocked, we already have a link. 968 * We do not need to set it up again. 969 */ 970 if (e1000_check_reset_block(hw)) 971 goto out; 972 973 /* 974 * If requested flow control is set to default, set flow control 975 * based on the EEPROM flow control settings. 976 */ 977 if (hw->fc.requested_mode == e1000_fc_default) { 978 ret_val = e1000_set_default_fc_generic(hw); 979 if (ret_val) 980 goto out; 981 } 982 983 /* 984 * Save off the requested flow control mode for use later. Depending 985 * on the link partner's capabilities, we may or may not use this mode. 986 */ 987 hw->fc.current_mode = hw->fc.requested_mode; 988 989 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 990 hw->fc.current_mode); 991 992 /* Call the necessary media_type subroutine to configure the link. */ 993 ret_val = hw->mac.ops.setup_physical_interface(hw); 994 if (ret_val) 995 goto out; 996 997 /* 998 * Initialize the flow control address, type, and PAUSE timer 999 * registers to their default values. This is done even if flow 1000 * control is disabled, because it does not hurt anything to 1001 * initialize these registers. 1002 */ 1003 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1004 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 1005 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1006 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 1007 1008 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 1009 1010 ret_val = e1000_set_fc_watermarks_generic(hw); 1011 1012out: 1013 return ret_val; 1014} 1015 1016/** 1017 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1018 * @hw: pointer to the HW structure 1019 * 1020 * Configures collision distance and flow control for fiber and serdes 1021 * links. Upon successful setup, poll for link. 1022 **/ 1023s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1024{ 1025 struct e1000_mac_info *mac = &hw->mac; 1026 u32 ctrl; 1027 s32 ret_val = E1000_SUCCESS; 1028 1029 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1030 1031 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1032 1033 /* Take the link out of reset */ 1034 ctrl &= ~E1000_CTRL_LRST; 1035 1036 mac->ops.config_collision_dist(hw); 1037 1038 ret_val = e1000_commit_fc_settings_generic(hw); 1039 if (ret_val) 1040 goto out; 1041 1042 /* 1043 * Since auto-negotiation is enabled, take the link out of reset (the 1044 * link will be in reset, because we previously reset the chip). This 1045 * will restart auto-negotiation. If auto-negotiation is successful 1046 * then the link-up status bit will be set and the flow control enable 1047 * bits (RFCE and TFCE) will be set according to their negotiated value. 1048 */ 1049 DEBUGOUT("Auto-negotiation enabled\n"); 1050 1051 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1052 E1000_WRITE_FLUSH(hw); 1053 msec_delay(1); 1054 1055 /* 1056 * For these adapters, the SW definable pin 1 is set when the optics 1057 * detect a signal. If we have a signal, then poll for a "Link-Up" 1058 * indication. 1059 */ 1060 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1061 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1062 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1063 } else { 1064 DEBUGOUT("No signal detected\n"); 1065 } 1066 1067out: 1068 return ret_val; 1069} 1070 1071/** 1072 * e1000_config_collision_dist_generic - Configure collision distance 1073 * @hw: pointer to the HW structure 1074 * 1075 * Configures the collision distance to the default value and is used 1076 * during link setup. 1077 **/ 1078void e1000_config_collision_dist_generic(struct e1000_hw *hw) 1079{ 1080 u32 tctl; 1081 1082 DEBUGFUNC("e1000_config_collision_dist_generic"); 1083 1084 tctl = E1000_READ_REG(hw, E1000_TCTL); 1085 1086 tctl &= ~E1000_TCTL_COLD; 1087 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1088 1089 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1090 E1000_WRITE_FLUSH(hw); 1091} 1092 1093/** 1094 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1095 * @hw: pointer to the HW structure 1096 * 1097 * Polls for link up by reading the status register, if link fails to come 1098 * up with auto-negotiation, then the link is forced if a signal is detected. 1099 **/ 1100s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1101{ 1102 struct e1000_mac_info *mac = &hw->mac; 1103 u32 i, status; 1104 s32 ret_val = E1000_SUCCESS; 1105 1106 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1107 1108 /* 1109 * If we have a signal (the cable is plugged in, or assumed TRUE for 1110 * serdes media) then poll for a "Link-Up" indication in the Device 1111 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1112 * seconds (Auto-negotiation should complete in less than 500 1113 * milliseconds even if the other end is doing it in SW). 1114 */ 1115 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1116 msec_delay(10); 1117 status = E1000_READ_REG(hw, E1000_STATUS); 1118 if (status & E1000_STATUS_LU) 1119 break; 1120 } 1121 if (i == FIBER_LINK_UP_LIMIT) { 1122 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1123 mac->autoneg_failed = 1; 1124 /* 1125 * AutoNeg failed to achieve a link, so we'll call 1126 * mac->check_for_link. This routine will force the 1127 * link up if we detect a signal. This will allow us to 1128 * communicate with non-autonegotiating link partners. 1129 */ 1130 ret_val = mac->ops.check_for_link(hw); 1131 if (ret_val) { 1132 DEBUGOUT("Error while checking for link\n"); 1133 goto out; 1134 } 1135 mac->autoneg_failed = 0; 1136 } else { 1137 mac->autoneg_failed = 0; 1138 DEBUGOUT("Valid Link Found\n"); 1139 } 1140 1141out: 1142 return ret_val; 1143} 1144 1145/** 1146 * e1000_commit_fc_settings_generic - Configure flow control 1147 * @hw: pointer to the HW structure 1148 * 1149 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1150 * base on the flow control settings in e1000_mac_info. 1151 **/ 1152s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1153{ 1154 struct e1000_mac_info *mac = &hw->mac; 1155 u32 txcw; 1156 s32 ret_val = E1000_SUCCESS; 1157 1158 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1159 1160 /* 1161 * Check for a software override of the flow control settings, and 1162 * setup the device accordingly. If auto-negotiation is enabled, then 1163 * software will have to set the "PAUSE" bits to the correct value in 1164 * the Transmit Config Word Register (TXCW) and re-start auto- 1165 * negotiation. However, if auto-negotiation is disabled, then 1166 * software will have to manually configure the two flow control enable 1167 * bits in the CTRL register. 1168 * 1169 * The possible values of the "fc" parameter are: 1170 * 0: Flow control is completely disabled 1171 * 1: Rx flow control is enabled (we can receive pause frames, 1172 * but not send pause frames). 1173 * 2: Tx flow control is enabled (we can send pause frames but we 1174 * do not support receiving pause frames). 1175 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1176 */ 1177 switch (hw->fc.current_mode) { 1178 case e1000_fc_none: 1179 /* Flow control completely disabled by a software over-ride. */ 1180 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1181 break; 1182 case e1000_fc_rx_pause: 1183 /* 1184 * Rx Flow control is enabled and Tx Flow control is disabled 1185 * by a software over-ride. Since there really isn't a way to 1186 * advertise that we are capable of Rx Pause ONLY, we will 1187 * advertise that we support both symmetric and asymmetric Rx 1188 * PAUSE. Later, we will disable the adapter's ability to send 1189 * PAUSE frames. 1190 */ 1191 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1192 break; 1193 case e1000_fc_tx_pause: 1194 /* 1195 * Tx Flow control is enabled, and Rx Flow control is disabled, 1196 * by a software over-ride. 1197 */ 1198 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1199 break; 1200 case e1000_fc_full: 1201 /* 1202 * Flow control (both Rx and Tx) is enabled by a software 1203 * over-ride. 1204 */ 1205 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1206 break; 1207 default: 1208 DEBUGOUT("Flow control param set incorrectly\n"); 1209 ret_val = -E1000_ERR_CONFIG; 1210 goto out; 1211 break; 1212 } 1213 1214 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1215 mac->txcw = txcw; 1216 1217out: 1218 return ret_val; 1219} 1220 1221/** 1222 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1223 * @hw: pointer to the HW structure 1224 * 1225 * Sets the flow control high/low threshold (watermark) registers. If 1226 * flow control XON frame transmission is enabled, then set XON frame 1227 * transmission as well. 1228 **/ 1229s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1230{ 1231 u32 fcrtl = 0, fcrth = 0; 1232 1233 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1234 1235 /* 1236 * Set the flow control receive threshold registers. Normally, 1237 * these registers will be set to a default threshold that may be 1238 * adjusted later by the driver's runtime code. However, if the 1239 * ability to transmit pause frames is not enabled, then these 1240 * registers will be set to 0. 1241 */ 1242 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1243 /* 1244 * We need to set up the Receive Threshold high and low water 1245 * marks as well as (optionally) enabling the transmission of 1246 * XON frames. 1247 */ 1248 fcrtl = hw->fc.low_water; 1249 if (hw->fc.send_xon) 1250 fcrtl |= E1000_FCRTL_XONE; 1251 1252 fcrth = hw->fc.high_water; 1253 } 1254 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1255 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1256 1257 return E1000_SUCCESS; 1258} 1259 1260/** 1261 * e1000_set_default_fc_generic - Set flow control default values 1262 * @hw: pointer to the HW structure 1263 * 1264 * Read the EEPROM for the default values for flow control and store the 1265 * values. 1266 **/ 1267s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 1268{ 1269 s32 ret_val = E1000_SUCCESS; 1270 u16 nvm_data; 1271 1272 DEBUGFUNC("e1000_set_default_fc_generic"); 1273 1274 /* 1275 * Read and store word 0x0F of the EEPROM. This word contains bits 1276 * that determine the hardware's default PAUSE (flow control) mode, 1277 * a bit that determines whether the HW defaults to enabling or 1278 * disabling auto-negotiation, and the direction of the 1279 * SW defined pins. If there is no SW over-ride of the flow 1280 * control setting, then the variable hw->fc will 1281 * be initialized based on a value in the EEPROM. 1282 */ 1283 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 1284 1285 if (ret_val) { 1286 DEBUGOUT("NVM Read Error\n"); 1287 goto out; 1288 } 1289 1290 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 1291 hw->fc.requested_mode = e1000_fc_none; 1292 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 1293 NVM_WORD0F_ASM_DIR) 1294 hw->fc.requested_mode = e1000_fc_tx_pause; 1295 else 1296 hw->fc.requested_mode = e1000_fc_full; 1297 1298out: 1299 return ret_val; 1300} 1301 1302/** 1303 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1304 * @hw: pointer to the HW structure 1305 * 1306 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1307 * device control register to reflect the adapter settings. TFCE and RFCE 1308 * need to be explicitly set by software when a copper PHY is used because 1309 * autonegotiation is managed by the PHY rather than the MAC. Software must 1310 * also configure these bits when link is forced on a fiber connection. 1311 **/ 1312s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1313{ 1314 u32 ctrl; 1315 s32 ret_val = E1000_SUCCESS; 1316 1317 DEBUGFUNC("e1000_force_mac_fc_generic"); 1318 1319 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1320 1321 /* 1322 * Because we didn't get link via the internal auto-negotiation 1323 * mechanism (we either forced link or we got link via PHY 1324 * auto-neg), we have to manually enable/disable transmit an 1325 * receive flow control. 1326 * 1327 * The "Case" statement below enables/disable flow control 1328 * according to the "hw->fc.current_mode" parameter. 1329 * 1330 * The possible values of the "fc" parameter are: 1331 * 0: Flow control is completely disabled 1332 * 1: Rx flow control is enabled (we can receive pause 1333 * frames but not send pause frames). 1334 * 2: Tx flow control is enabled (we can send pause frames 1335 * frames but we do not receive pause frames). 1336 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1337 * other: No other values should be possible at this point. 1338 */ 1339 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1340 1341 switch (hw->fc.current_mode) { 1342 case e1000_fc_none: 1343 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1344 break; 1345 case e1000_fc_rx_pause: 1346 ctrl &= (~E1000_CTRL_TFCE); 1347 ctrl |= E1000_CTRL_RFCE; 1348 break; 1349 case e1000_fc_tx_pause: 1350 ctrl &= (~E1000_CTRL_RFCE); 1351 ctrl |= E1000_CTRL_TFCE; 1352 break; 1353 case e1000_fc_full: 1354 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1355 break; 1356 default: 1357 DEBUGOUT("Flow control param set incorrectly\n"); 1358 ret_val = -E1000_ERR_CONFIG; 1359 goto out; 1360 } 1361 1362 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1363 1364out: 1365 return ret_val; 1366} 1367 1368/** 1369 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1370 * @hw: pointer to the HW structure 1371 * 1372 * Checks the status of auto-negotiation after link up to ensure that the 1373 * speed and duplex were not forced. If the link needed to be forced, then 1374 * flow control needs to be forced also. If auto-negotiation is enabled 1375 * and did not fail, then we configure flow control based on our link 1376 * partner. 1377 **/ 1378s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1379{ 1380 struct e1000_mac_info *mac = &hw->mac; 1381 s32 ret_val = E1000_SUCCESS; 1382 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1383 u16 speed, duplex; 1384 1385 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1386 1387 /* 1388 * Check for the case where we have fiber media and auto-neg failed 1389 * so we had to force link. In this case, we need to force the 1390 * configuration of the MAC to match the "fc" parameter. 1391 */ 1392 if (mac->autoneg_failed) { 1393 if (hw->phy.media_type == e1000_media_type_fiber || 1394 hw->phy.media_type == e1000_media_type_internal_serdes) 1395 ret_val = e1000_force_mac_fc_generic(hw); 1396 } else { 1397 if (hw->phy.media_type == e1000_media_type_copper) 1398 ret_val = e1000_force_mac_fc_generic(hw); 1399 } 1400 1401 if (ret_val) { 1402 DEBUGOUT("Error forcing flow control settings\n"); 1403 goto out; 1404 } 1405 1406 /* 1407 * Check for the case where we have copper media and auto-neg is 1408 * enabled. In this case, we need to check and see if Auto-Neg 1409 * has completed, and if so, how the PHY and link partner has 1410 * flow control configured. 1411 */ 1412 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1413 /* 1414 * Read the MII Status Register and check to see if AutoNeg 1415 * has completed. We read this twice because this reg has 1416 * some "sticky" (latched) bits. 1417 */ 1418 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1419 if (ret_val) 1420 goto out; 1421 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1422 if (ret_val) 1423 goto out; 1424 1425 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1426 DEBUGOUT("Copper PHY and Auto Neg " 1427 "has not completed.\n"); 1428 goto out; 1429 } 1430 1431 /* 1432 * The AutoNeg process has completed, so we now need to 1433 * read both the Auto Negotiation Advertisement 1434 * Register (Address 4) and the Auto_Negotiation Base 1435 * Page Ability Register (Address 5) to determine how 1436 * flow control was negotiated. 1437 */ 1438 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1439 &mii_nway_adv_reg); 1440 if (ret_val) 1441 goto out; 1442 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1443 &mii_nway_lp_ability_reg); 1444 if (ret_val) 1445 goto out; 1446 1447 /* 1448 * Two bits in the Auto Negotiation Advertisement Register 1449 * (Address 4) and two bits in the Auto Negotiation Base 1450 * Page Ability Register (Address 5) determine flow control 1451 * for both the PHY and the link partner. The following 1452 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1453 * 1999, describes these PAUSE resolution bits and how flow 1454 * control is determined based upon these settings. 1455 * NOTE: DC = Don't Care 1456 * 1457 * LOCAL DEVICE | LINK PARTNER 1458 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1459 *-------|---------|-------|---------|-------------------- 1460 * 0 | 0 | DC | DC | e1000_fc_none 1461 * 0 | 1 | 0 | DC | e1000_fc_none 1462 * 0 | 1 | 1 | 0 | e1000_fc_none 1463 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1464 * 1 | 0 | 0 | DC | e1000_fc_none 1465 * 1 | DC | 1 | DC | e1000_fc_full 1466 * 1 | 1 | 0 | 0 | e1000_fc_none 1467 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1468 * 1469 * Are both PAUSE bits set to 1? If so, this implies 1470 * Symmetric Flow Control is enabled at both ends. The 1471 * ASM_DIR bits are irrelevant per the spec. 1472 * 1473 * For Symmetric Flow Control: 1474 * 1475 * LOCAL DEVICE | LINK PARTNER 1476 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1477 *-------|---------|-------|---------|-------------------- 1478 * 1 | DC | 1 | DC | E1000_fc_full 1479 * 1480 */ 1481 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1482 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1483 /* 1484 * Now we need to check if the user selected Rx ONLY 1485 * of pause frames. In this case, we had to advertise 1486 * FULL flow control because we could not advertise Rx 1487 * ONLY. Hence, we must now check to see if we need to 1488 * turn OFF the TRANSMISSION of PAUSE frames. 1489 */ 1490 if (hw->fc.requested_mode == e1000_fc_full) { 1491 hw->fc.current_mode = e1000_fc_full; 1492 DEBUGOUT("Flow Control = FULL.\r\n"); 1493 } else { 1494 hw->fc.current_mode = e1000_fc_rx_pause; 1495 DEBUGOUT("Flow Control = " 1496 "Rx PAUSE frames only.\r\n"); 1497 } 1498 } 1499 /* 1500 * For receiving PAUSE frames ONLY. 1501 * 1502 * LOCAL DEVICE | LINK PARTNER 1503 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1504 *-------|---------|-------|---------|-------------------- 1505 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1506 */ 1507 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1508 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1509 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1510 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1511 hw->fc.current_mode = e1000_fc_tx_pause; 1512 DEBUGOUT("Flow Control = Tx PAUSE frames only.\r\n"); 1513 } 1514 /* 1515 * For transmitting PAUSE frames ONLY. 1516 * 1517 * LOCAL DEVICE | LINK PARTNER 1518 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1519 *-------|---------|-------|---------|-------------------- 1520 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1521 */ 1522 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1523 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1524 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1525 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1526 hw->fc.current_mode = e1000_fc_rx_pause; 1527 DEBUGOUT("Flow Control = Rx PAUSE frames only.\r\n"); 1528 } else { 1529 /* 1530 * Per the IEEE spec, at this point flow control 1531 * should be disabled. 1532 */ 1533 hw->fc.current_mode = e1000_fc_none; 1534 DEBUGOUT("Flow Control = NONE.\r\n"); 1535 } 1536 1537 /* 1538 * Now we need to do one last check... If we auto- 1539 * negotiated to HALF DUPLEX, flow control should not be 1540 * enabled per IEEE 802.3 spec. 1541 */ 1542 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1543 if (ret_val) { 1544 DEBUGOUT("Error getting link speed and duplex\n"); 1545 goto out; 1546 } 1547 1548 if (duplex == HALF_DUPLEX) 1549 hw->fc.current_mode = e1000_fc_none; 1550 1551 /* 1552 * Now we call a subroutine to actually force the MAC 1553 * controller to use the correct flow control settings. 1554 */ 1555 ret_val = e1000_force_mac_fc_generic(hw); 1556 if (ret_val) { 1557 DEBUGOUT("Error forcing flow control settings\n"); 1558 goto out; 1559 } 1560 } 1561 1562out: 1563 return ret_val; 1564} 1565 1566/** 1567 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1568 * @hw: pointer to the HW structure 1569 * @speed: stores the current speed 1570 * @duplex: stores the current duplex 1571 * 1572 * Read the status register for the current speed/duplex and store the current 1573 * speed and duplex for copper connections. 1574 **/ 1575s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1576 u16 *duplex) 1577{ 1578 u32 status; 1579 1580 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1581 1582 status = E1000_READ_REG(hw, E1000_STATUS); 1583 if (status & E1000_STATUS_SPEED_1000) { 1584 *speed = SPEED_1000; 1585 DEBUGOUT("1000 Mbs, "); 1586 } else if (status & E1000_STATUS_SPEED_100) { 1587 *speed = SPEED_100; 1588 DEBUGOUT("100 Mbs, "); 1589 } else { 1590 *speed = SPEED_10; 1591 DEBUGOUT("10 Mbs, "); 1592 } 1593 1594 if (status & E1000_STATUS_FD) { 1595 *duplex = FULL_DUPLEX; 1596 DEBUGOUT("Full Duplex\n"); 1597 } else { 1598 *duplex = HALF_DUPLEX; 1599 DEBUGOUT("Half Duplex\n"); 1600 } 1601 1602 return E1000_SUCCESS; 1603} 1604 1605/** 1606 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1607 * @hw: pointer to the HW structure 1608 * @speed: stores the current speed 1609 * @duplex: stores the current duplex 1610 * 1611 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1612 * for fiber/serdes links. 1613 **/ 1614s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, 1615 u16 *speed, u16 *duplex) 1616{ 1617 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1618 1619 *speed = SPEED_1000; 1620 *duplex = FULL_DUPLEX; 1621 1622 return E1000_SUCCESS; 1623} 1624 1625/** 1626 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1627 * @hw: pointer to the HW structure 1628 * 1629 * Acquire the HW semaphore to access the PHY or NVM 1630 **/ 1631s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1632{ 1633 u32 swsm; 1634 s32 ret_val = E1000_SUCCESS; 1635 s32 timeout = hw->nvm.word_size + 1; 1636 s32 i = 0; 1637 1638 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1639 1640 /* Get the SW semaphore */ 1641 while (i < timeout) { 1642 swsm = E1000_READ_REG(hw, E1000_SWSM); 1643 if (!(swsm & E1000_SWSM_SMBI)) 1644 break; 1645 1646 usec_delay(50); 1647 i++; 1648 } 1649 1650 if (i == timeout) { 1651 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1652 ret_val = -E1000_ERR_NVM; 1653 goto out; 1654 } 1655 1656 /* Get the FW semaphore. */ 1657 for (i = 0; i < timeout; i++) { 1658 swsm = E1000_READ_REG(hw, E1000_SWSM); 1659 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1660 1661 /* Semaphore acquired if bit latched */ 1662 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1663 break; 1664 1665 usec_delay(50); 1666 } 1667 1668 if (i == timeout) { 1669 /* Release semaphores */ 1670 e1000_put_hw_semaphore_generic(hw); 1671 DEBUGOUT("Driver can't access the NVM\n"); 1672 ret_val = -E1000_ERR_NVM; 1673 goto out; 1674 } 1675 1676out: 1677 return ret_val; 1678} 1679 1680/** 1681 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1682 * @hw: pointer to the HW structure 1683 * 1684 * Release hardware semaphore used to access the PHY or NVM 1685 **/ 1686void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1687{ 1688 u32 swsm; 1689 1690 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1691 1692 swsm = E1000_READ_REG(hw, E1000_SWSM); 1693 1694 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1695 1696 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1697} 1698 1699/** 1700 * e1000_get_auto_rd_done_generic - Check for auto read completion 1701 * @hw: pointer to the HW structure 1702 * 1703 * Check EEPROM for Auto Read done bit. 1704 **/ 1705s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1706{ 1707 s32 i = 0; 1708 s32 ret_val = E1000_SUCCESS; 1709 1710 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1711 1712 while (i < AUTO_READ_DONE_TIMEOUT) { 1713 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1714 break; 1715 msec_delay(1); 1716 i++; 1717 } 1718 1719 if (i == AUTO_READ_DONE_TIMEOUT) { 1720 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1721 ret_val = -E1000_ERR_RESET; 1722 goto out; 1723 } 1724 1725out: 1726 return ret_val; 1727} 1728 1729/** 1730 * e1000_valid_led_default_generic - Verify a valid default LED config 1731 * @hw: pointer to the HW structure 1732 * @data: pointer to the NVM (EEPROM) 1733 * 1734 * Read the EEPROM for the current default LED configuration. If the 1735 * LED configuration is not valid, set to a valid LED configuration. 1736 **/ 1737s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1738{ 1739 s32 ret_val; 1740 1741 DEBUGFUNC("e1000_valid_led_default_generic"); 1742 1743 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1744 if (ret_val) { 1745 DEBUGOUT("NVM Read Error\n"); 1746 goto out; 1747 } 1748 1749 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1750 *data = ID_LED_DEFAULT; 1751 1752out: 1753 return ret_val; 1754} 1755 1756/** 1757 * e1000_id_led_init_generic - 1758 * @hw: pointer to the HW structure 1759 * 1760 **/ 1761s32 e1000_id_led_init_generic(struct e1000_hw *hw) 1762{ 1763 struct e1000_mac_info *mac = &hw->mac; 1764 s32 ret_val; 1765 const u32 ledctl_mask = 0x000000FF; 1766 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1767 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1768 u16 data, i, temp; 1769 const u16 led_mask = 0x0F; 1770 1771 DEBUGFUNC("e1000_id_led_init_generic"); 1772 1773 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1774 if (ret_val) 1775 goto out; 1776 1777 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1778 mac->ledctl_mode1 = mac->ledctl_default; 1779 mac->ledctl_mode2 = mac->ledctl_default; 1780 1781 for (i = 0; i < 4; i++) { 1782 temp = (data >> (i << 2)) & led_mask; 1783 switch (temp) { 1784 case ID_LED_ON1_DEF2: 1785 case ID_LED_ON1_ON2: 1786 case ID_LED_ON1_OFF2: 1787 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1788 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1789 break; 1790 case ID_LED_OFF1_DEF2: 1791 case ID_LED_OFF1_ON2: 1792 case ID_LED_OFF1_OFF2: 1793 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1794 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1795 break; 1796 default: 1797 /* Do nothing */ 1798 break; 1799 } 1800 switch (temp) { 1801 case ID_LED_DEF1_ON2: 1802 case ID_LED_ON1_ON2: 1803 case ID_LED_OFF1_ON2: 1804 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1805 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1806 break; 1807 case ID_LED_DEF1_OFF2: 1808 case ID_LED_ON1_OFF2: 1809 case ID_LED_OFF1_OFF2: 1810 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1811 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1812 break; 1813 default: 1814 /* Do nothing */ 1815 break; 1816 } 1817 } 1818 1819out: 1820 return ret_val; 1821} 1822 1823/** 1824 * e1000_setup_led_generic - Configures SW controllable LED 1825 * @hw: pointer to the HW structure 1826 * 1827 * This prepares the SW controllable LED for use and saves the current state 1828 * of the LED so it can be later restored. 1829 **/ 1830s32 e1000_setup_led_generic(struct e1000_hw *hw) 1831{ 1832 u32 ledctl; 1833 s32 ret_val = E1000_SUCCESS; 1834 1835 DEBUGFUNC("e1000_setup_led_generic"); 1836 1837 if (hw->mac.ops.setup_led != e1000_setup_led_generic) { 1838 ret_val = -E1000_ERR_CONFIG; 1839 goto out; 1840 } 1841 1842 if (hw->phy.media_type == e1000_media_type_fiber) { 1843 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1844 hw->mac.ledctl_default = ledctl; 1845 /* Turn off LED0 */ 1846 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 1847 E1000_LEDCTL_LED0_BLINK | 1848 E1000_LEDCTL_LED0_MODE_MASK); 1849 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1850 E1000_LEDCTL_LED0_MODE_SHIFT); 1851 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1852 } else if (hw->phy.media_type == e1000_media_type_copper) { 1853 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1854 } 1855 1856out: 1857 return ret_val; 1858} 1859 1860/** 1861 * e1000_cleanup_led_generic - Set LED config to default operation 1862 * @hw: pointer to the HW structure 1863 * 1864 * Remove the current LED configuration and set the LED configuration 1865 * to the default value, saved from the EEPROM. 1866 **/ 1867s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1868{ 1869 DEBUGFUNC("e1000_cleanup_led_generic"); 1870 1871 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1872 return E1000_SUCCESS; 1873} 1874 1875/** 1876 * e1000_blink_led_generic - Blink LED 1877 * @hw: pointer to the HW structure 1878 * 1879 * Blink the LEDs which are set to be on. 1880 **/ 1881s32 e1000_blink_led_generic(struct e1000_hw *hw) 1882{ 1883 u32 ledctl_blink = 0; 1884 u32 i; 1885 1886 DEBUGFUNC("e1000_blink_led_generic"); 1887 1888 if (hw->phy.media_type == e1000_media_type_fiber) { 1889 /* always blink LED0 for PCI-E fiber */ 1890 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1891 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1892 } else { 1893 /* 1894 * set the blink bit for each LED that's "on" (0x0E) 1895 * in ledctl_mode2 1896 */ 1897 ledctl_blink = hw->mac.ledctl_mode2; 1898 for (i = 0; i < 4; i++) 1899 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1900 E1000_LEDCTL_MODE_LED_ON) 1901 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1902 (i * 8)); 1903 } 1904 1905 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1906 1907 return E1000_SUCCESS; 1908} 1909 1910/** 1911 * e1000_led_on_generic - Turn LED on 1912 * @hw: pointer to the HW structure 1913 * 1914 * Turn LED on. 1915 **/ 1916s32 e1000_led_on_generic(struct e1000_hw *hw) 1917{ 1918 u32 ctrl; 1919 1920 DEBUGFUNC("e1000_led_on_generic"); 1921 1922 switch (hw->phy.media_type) { 1923 case e1000_media_type_fiber: 1924 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1925 ctrl &= ~E1000_CTRL_SWDPIN0; 1926 ctrl |= E1000_CTRL_SWDPIO0; 1927 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1928 break; 1929 case e1000_media_type_copper: 1930 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1931 break; 1932 default: 1933 break; 1934 } 1935 1936 return E1000_SUCCESS; 1937} 1938 1939/** 1940 * e1000_led_off_generic - Turn LED off 1941 * @hw: pointer to the HW structure 1942 * 1943 * Turn LED off. 1944 **/ 1945s32 e1000_led_off_generic(struct e1000_hw *hw) 1946{ 1947 u32 ctrl; 1948 1949 DEBUGFUNC("e1000_led_off_generic"); 1950 1951 switch (hw->phy.media_type) { 1952 case e1000_media_type_fiber: 1953 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1954 ctrl |= E1000_CTRL_SWDPIN0; 1955 ctrl |= E1000_CTRL_SWDPIO0; 1956 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1957 break; 1958 case e1000_media_type_copper: 1959 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1960 break; 1961 default: 1962 break; 1963 } 1964 1965 return E1000_SUCCESS; 1966} 1967 1968/** 1969 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 1970 * @hw: pointer to the HW structure 1971 * @no_snoop: bitmap of snoop events 1972 * 1973 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 1974 **/ 1975void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 1976{ 1977 u32 gcr; 1978 1979 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 1980 1981 if (hw->bus.type != e1000_bus_type_pci_express) 1982 goto out; 1983 1984 if (no_snoop) { 1985 gcr = E1000_READ_REG(hw, E1000_GCR); 1986 gcr &= ~(PCIE_NO_SNOOP_ALL); 1987 gcr |= no_snoop; 1988 E1000_WRITE_REG(hw, E1000_GCR, gcr); 1989 } 1990out: 1991 return; 1992} 1993 1994/** 1995 * e1000_disable_pcie_master_generic - Disables PCI-express master access 1996 * @hw: pointer to the HW structure 1997 * 1998 * Returns E1000_SUCCESS if successful, else returns -10 1999 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 2000 * the master requests to be disabled. 2001 * 2002 * Disables PCI-Express master access and verifies there are no pending 2003 * requests. 2004 **/ 2005s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 2006{ 2007 u32 ctrl; 2008 s32 timeout = MASTER_DISABLE_TIMEOUT; 2009 s32 ret_val = E1000_SUCCESS; 2010 2011 DEBUGFUNC("e1000_disable_pcie_master_generic"); 2012 2013 if (hw->bus.type != e1000_bus_type_pci_express) 2014 goto out; 2015 2016 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2017 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2018 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2019 2020 while (timeout) { 2021 if (!(E1000_READ_REG(hw, E1000_STATUS) & 2022 E1000_STATUS_GIO_MASTER_ENABLE)) 2023 break; 2024 usec_delay(100); 2025 timeout--; 2026 } 2027 2028 if (!timeout) { 2029 DEBUGOUT("Master requests are pending.\n"); 2030 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 2031 } 2032 2033out: 2034 return ret_val; 2035} 2036 2037/** 2038 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2039 * @hw: pointer to the HW structure 2040 * 2041 * Reset the Adaptive Interframe Spacing throttle to default values. 2042 **/ 2043void e1000_reset_adaptive_generic(struct e1000_hw *hw) 2044{ 2045 struct e1000_mac_info *mac = &hw->mac; 2046 2047 DEBUGFUNC("e1000_reset_adaptive_generic"); 2048 2049 if (!mac->adaptive_ifs) { 2050 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2051 goto out; 2052 } 2053 2054 mac->current_ifs_val = 0; 2055 mac->ifs_min_val = IFS_MIN; 2056 mac->ifs_max_val = IFS_MAX; 2057 mac->ifs_step_size = IFS_STEP; 2058 mac->ifs_ratio = IFS_RATIO; 2059 2060 mac->in_ifs_mode = FALSE; 2061 E1000_WRITE_REG(hw, E1000_AIT, 0); 2062out: 2063 return; 2064} 2065 2066/** 2067 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2068 * @hw: pointer to the HW structure 2069 * 2070 * Update the Adaptive Interframe Spacing Throttle value based on the 2071 * time between transmitted packets and time between collisions. 2072 **/ 2073void e1000_update_adaptive_generic(struct e1000_hw *hw) 2074{ 2075 struct e1000_mac_info *mac = &hw->mac; 2076 2077 DEBUGFUNC("e1000_update_adaptive_generic"); 2078 2079 if (!mac->adaptive_ifs) { 2080 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2081 goto out; 2082 } 2083 2084 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2085 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2086 mac->in_ifs_mode = TRUE; 2087 if (mac->current_ifs_val < mac->ifs_max_val) { 2088 if (!mac->current_ifs_val) 2089 mac->current_ifs_val = mac->ifs_min_val; 2090 else 2091 mac->current_ifs_val += 2092 mac->ifs_step_size; 2093 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val); 2094 } 2095 } 2096 } else { 2097 if (mac->in_ifs_mode && 2098 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2099 mac->current_ifs_val = 0; 2100 mac->in_ifs_mode = FALSE; 2101 E1000_WRITE_REG(hw, E1000_AIT, 0); 2102 } 2103 } 2104out: 2105 return; 2106} 2107 2108/** 2109 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2110 * @hw: pointer to the HW structure 2111 * 2112 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2113 * set, which is forced to MDI mode only. 2114 **/ 2115static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2116{ 2117 s32 ret_val = E1000_SUCCESS; 2118 2119 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2120 2121 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2122 DEBUGOUT("Invalid MDI setting detected\n"); 2123 hw->phy.mdix = 1; 2124 ret_val = -E1000_ERR_CONFIG; 2125 goto out; 2126 } 2127 2128out: 2129 return ret_val; 2130} 2131 2132/** 2133 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2134 * @hw: pointer to the HW structure 2135 * @reg: 32bit register offset such as E1000_SCTL 2136 * @offset: register offset to write to 2137 * @data: data to write at register offset 2138 * 2139 * Writes an address/data control type register. There are several of these 2140 * and they all have the format address << 8 | data and bit 31 is polled for 2141 * completion. 2142 **/ 2143s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2144 u32 offset, u8 data) 2145{ 2146 u32 i, regvalue = 0; 2147 s32 ret_val = E1000_SUCCESS; 2148 2149 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2150 2151 /* Set up the address and data */ 2152 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2153 E1000_WRITE_REG(hw, reg, regvalue); 2154 2155 /* Poll the ready bit to see if the MDI read completed */ 2156 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2157 usec_delay(5); 2158 regvalue = E1000_READ_REG(hw, reg); 2159 if (regvalue & E1000_GEN_CTL_READY) 2160 break; 2161 } 2162 if (!(regvalue & E1000_GEN_CTL_READY)) { 2163 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2164 ret_val = -E1000_ERR_PHY; 2165 goto out; 2166 } 2167 2168out: 2169 return ret_val; 2170} 2171