e1000_mac.c revision 256200
1177867Sjfv/****************************************************************************** 2169240Sjfv 3247064Sjfv Copyright (c) 2001-2013, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD: head/sys/dev/e1000/e1000_mac.c 256200 2013-10-09 17:32:52Z jfv $*/ 34169240Sjfv 35169589Sjfv#include "e1000_api.h" 36169240Sjfv 37185353Sjfvstatic s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 38190872Sjfvstatic void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 39238148Sjfvstatic void e1000_config_collision_dist_generic(struct e1000_hw *hw); 40238148Sjfvstatic void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index); 41185353Sjfv 42169240Sjfv/** 43177867Sjfv * e1000_init_mac_ops_generic - Initialize MAC function pointers 44177867Sjfv * @hw: pointer to the HW structure 45177867Sjfv * 46177867Sjfv * Setups up the function pointers to no-op functions 47177867Sjfv **/ 48177867Sjfvvoid e1000_init_mac_ops_generic(struct e1000_hw *hw) 49177867Sjfv{ 50177867Sjfv struct e1000_mac_info *mac = &hw->mac; 51177867Sjfv DEBUGFUNC("e1000_init_mac_ops_generic"); 52177867Sjfv 53177867Sjfv /* General Setup */ 54177867Sjfv mac->ops.init_params = e1000_null_ops_generic; 55177867Sjfv mac->ops.init_hw = e1000_null_ops_generic; 56177867Sjfv mac->ops.reset_hw = e1000_null_ops_generic; 57177867Sjfv mac->ops.setup_physical_interface = e1000_null_ops_generic; 58177867Sjfv mac->ops.get_bus_info = e1000_null_ops_generic; 59185353Sjfv mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 60177867Sjfv mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 61177867Sjfv mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 62177867Sjfv mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 63177867Sjfv /* LED */ 64177867Sjfv mac->ops.cleanup_led = e1000_null_ops_generic; 65177867Sjfv mac->ops.setup_led = e1000_null_ops_generic; 66177867Sjfv mac->ops.blink_led = e1000_null_ops_generic; 67177867Sjfv mac->ops.led_on = e1000_null_ops_generic; 68177867Sjfv mac->ops.led_off = e1000_null_ops_generic; 69177867Sjfv /* LINK */ 70177867Sjfv mac->ops.setup_link = e1000_null_ops_generic; 71177867Sjfv mac->ops.get_link_up_info = e1000_null_link_info; 72177867Sjfv mac->ops.check_for_link = e1000_null_ops_generic; 73247064Sjfv mac->ops.set_obff_timer = e1000_null_set_obff_timer; 74177867Sjfv /* Management */ 75177867Sjfv mac->ops.check_mng_mode = e1000_null_mng_mode; 76177867Sjfv /* VLAN, MC, etc. */ 77177867Sjfv mac->ops.update_mc_addr_list = e1000_null_update_mc; 78177867Sjfv mac->ops.clear_vfta = e1000_null_mac_generic; 79177867Sjfv mac->ops.write_vfta = e1000_null_write_vfta; 80177867Sjfv mac->ops.rar_set = e1000_rar_set_generic; 81177867Sjfv mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 82177867Sjfv} 83177867Sjfv 84177867Sjfv/** 85177867Sjfv * e1000_null_ops_generic - No-op function, returns 0 86177867Sjfv * @hw: pointer to the HW structure 87177867Sjfv **/ 88256200Sjfvs32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw) 89177867Sjfv{ 90177867Sjfv DEBUGFUNC("e1000_null_ops_generic"); 91177867Sjfv return E1000_SUCCESS; 92177867Sjfv} 93177867Sjfv 94177867Sjfv/** 95177867Sjfv * e1000_null_mac_generic - No-op function, return void 96177867Sjfv * @hw: pointer to the HW structure 97177867Sjfv **/ 98256200Sjfvvoid e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw) 99177867Sjfv{ 100177867Sjfv DEBUGFUNC("e1000_null_mac_generic"); 101177867Sjfv return; 102177867Sjfv} 103177867Sjfv 104177867Sjfv/** 105177867Sjfv * e1000_null_link_info - No-op function, return 0 106177867Sjfv * @hw: pointer to the HW structure 107177867Sjfv **/ 108256200Sjfvs32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw, 109256200Sjfv u16 E1000_UNUSEDARG *s, u16 E1000_UNUSEDARG *d) 110177867Sjfv{ 111177867Sjfv DEBUGFUNC("e1000_null_link_info"); 112177867Sjfv return E1000_SUCCESS; 113177867Sjfv} 114177867Sjfv 115177867Sjfv/** 116177867Sjfv * e1000_null_mng_mode - No-op function, return FALSE 117177867Sjfv * @hw: pointer to the HW structure 118177867Sjfv **/ 119256200Sjfvbool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw) 120256200Sjfv{ 121177867Sjfv DEBUGFUNC("e1000_null_mng_mode"); 122177867Sjfv return FALSE; 123177867Sjfv} 124177867Sjfv 125177867Sjfv/** 126177867Sjfv * e1000_null_update_mc - No-op function, return void 127177867Sjfv * @hw: pointer to the HW structure 128177867Sjfv **/ 129256200Sjfvvoid e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw, 130256200Sjfv u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a) 131177867Sjfv{ 132177867Sjfv DEBUGFUNC("e1000_null_update_mc"); 133177867Sjfv return; 134177867Sjfv} 135177867Sjfv 136177867Sjfv/** 137177867Sjfv * e1000_null_write_vfta - No-op function, return void 138177867Sjfv * @hw: pointer to the HW structure 139177867Sjfv **/ 140256200Sjfvvoid e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw, 141256200Sjfv u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b) 142177867Sjfv{ 143177867Sjfv DEBUGFUNC("e1000_null_write_vfta"); 144177867Sjfv return; 145177867Sjfv} 146177867Sjfv 147177867Sjfv/** 148177867Sjfv * e1000_null_rar_set - No-op function, return void 149177867Sjfv * @hw: pointer to the HW structure 150177867Sjfv **/ 151256200Sjfvvoid e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw, 152256200Sjfv u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a) 153177867Sjfv{ 154177867Sjfv DEBUGFUNC("e1000_null_rar_set"); 155177867Sjfv return; 156177867Sjfv} 157177867Sjfv 158177867Sjfv/** 159247064Sjfv * e1000_null_set_obff_timer - No-op function, return 0 160247064Sjfv * @hw: pointer to the HW structure 161247064Sjfv **/ 162256200Sjfvs32 e1000_null_set_obff_timer(struct e1000_hw E1000_UNUSEDARG *hw, 163256200Sjfv u32 E1000_UNUSEDARG a) 164247064Sjfv{ 165247064Sjfv DEBUGFUNC("e1000_null_set_obff_timer"); 166247064Sjfv return E1000_SUCCESS; 167247064Sjfv} 168247064Sjfv 169247064Sjfv/** 170169240Sjfv * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 171169589Sjfv * @hw: pointer to the HW structure 172169240Sjfv * 173169240Sjfv * Determines and stores the system bus information for a particular 174169240Sjfv * network interface. The following bus information is determined and stored: 175169240Sjfv * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 176169240Sjfv **/ 177173788Sjfvs32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 178169240Sjfv{ 179185353Sjfv struct e1000_mac_info *mac = &hw->mac; 180169240Sjfv struct e1000_bus_info *bus = &hw->bus; 181169240Sjfv u32 status = E1000_READ_REG(hw, E1000_STATUS); 182169240Sjfv s32 ret_val = E1000_SUCCESS; 183169240Sjfv 184169240Sjfv DEBUGFUNC("e1000_get_bus_info_pci_generic"); 185169240Sjfv 186169240Sjfv /* PCI or PCI-X? */ 187169240Sjfv bus->type = (status & E1000_STATUS_PCIX_MODE) 188169240Sjfv ? e1000_bus_type_pcix 189169240Sjfv : e1000_bus_type_pci; 190169240Sjfv 191169240Sjfv /* Bus speed */ 192169240Sjfv if (bus->type == e1000_bus_type_pci) { 193169240Sjfv bus->speed = (status & E1000_STATUS_PCI66) 194228386Sjfv ? e1000_bus_speed_66 195228386Sjfv : e1000_bus_speed_33; 196169240Sjfv } else { 197169240Sjfv switch (status & E1000_STATUS_PCIX_SPEED) { 198169240Sjfv case E1000_STATUS_PCIX_SPEED_66: 199169240Sjfv bus->speed = e1000_bus_speed_66; 200169240Sjfv break; 201169240Sjfv case E1000_STATUS_PCIX_SPEED_100: 202169240Sjfv bus->speed = e1000_bus_speed_100; 203169240Sjfv break; 204169240Sjfv case E1000_STATUS_PCIX_SPEED_133: 205169240Sjfv bus->speed = e1000_bus_speed_133; 206169240Sjfv break; 207169240Sjfv default: 208169240Sjfv bus->speed = e1000_bus_speed_reserved; 209169240Sjfv break; 210169240Sjfv } 211169240Sjfv } 212169240Sjfv 213169240Sjfv /* Bus width */ 214169240Sjfv bus->width = (status & E1000_STATUS_BUS64) 215228386Sjfv ? e1000_bus_width_64 216228386Sjfv : e1000_bus_width_32; 217169240Sjfv 218169240Sjfv /* Which PCI(-X) function? */ 219185353Sjfv mac->ops.set_lan_id(hw); 220169240Sjfv 221169240Sjfv return ret_val; 222169240Sjfv} 223169240Sjfv 224169240Sjfv/** 225169240Sjfv * e1000_get_bus_info_pcie_generic - Get PCIe bus information 226169589Sjfv * @hw: pointer to the HW structure 227169240Sjfv * 228169240Sjfv * Determines and stores the system bus information for a particular 229169240Sjfv * network interface. The following bus information is determined and stored: 230169240Sjfv * bus speed, bus width, type (PCIe), and PCIe function. 231169240Sjfv **/ 232173788Sjfvs32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 233169240Sjfv{ 234185353Sjfv struct e1000_mac_info *mac = &hw->mac; 235169240Sjfv struct e1000_bus_info *bus = &hw->bus; 236169240Sjfv s32 ret_val; 237185353Sjfv u16 pcie_link_status; 238169240Sjfv 239169240Sjfv DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 240169240Sjfv 241169240Sjfv bus->type = e1000_bus_type_pci_express; 242169240Sjfv 243228386Sjfv ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS, 244228386Sjfv &pcie_link_status); 245205869Sjfv if (ret_val) { 246169240Sjfv bus->width = e1000_bus_width_unknown; 247205869Sjfv bus->speed = e1000_bus_speed_unknown; 248205869Sjfv } else { 249205869Sjfv switch (pcie_link_status & PCIE_LINK_SPEED_MASK) { 250205869Sjfv case PCIE_LINK_SPEED_2500: 251205869Sjfv bus->speed = e1000_bus_speed_2500; 252205869Sjfv break; 253205869Sjfv case PCIE_LINK_SPEED_5000: 254205869Sjfv bus->speed = e1000_bus_speed_5000; 255205869Sjfv break; 256205869Sjfv default: 257205869Sjfv bus->speed = e1000_bus_speed_unknown; 258205869Sjfv break; 259205869Sjfv } 260218530Sjfv 261181027Sjfv bus->width = (enum e1000_bus_width)((pcie_link_status & 262228386Sjfv PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT); 263205869Sjfv } 264169240Sjfv 265185353Sjfv mac->ops.set_lan_id(hw); 266185353Sjfv 267185353Sjfv return E1000_SUCCESS; 268185353Sjfv} 269185353Sjfv 270185353Sjfv/** 271185353Sjfv * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 272185353Sjfv * 273185353Sjfv * @hw: pointer to the HW structure 274185353Sjfv * 275185353Sjfv * Determines the LAN function id by reading memory-mapped registers 276185353Sjfv * and swaps the port value if requested. 277185353Sjfv **/ 278190872Sjfvstatic void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 279185353Sjfv{ 280185353Sjfv struct e1000_bus_info *bus = &hw->bus; 281185353Sjfv u32 reg; 282185353Sjfv 283247064Sjfv /* The status register reports the correct function number 284190872Sjfv * for the device regardless of function swap state. 285190872Sjfv */ 286185353Sjfv reg = E1000_READ_REG(hw, E1000_STATUS); 287185353Sjfv bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 288185353Sjfv} 289185353Sjfv 290185353Sjfv/** 291185353Sjfv * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 292185353Sjfv * @hw: pointer to the HW structure 293185353Sjfv * 294185353Sjfv * Determines the LAN function id by reading PCI config space. 295185353Sjfv **/ 296185353Sjfvvoid e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 297185353Sjfv{ 298185353Sjfv struct e1000_bus_info *bus = &hw->bus; 299185353Sjfv u16 pci_header_type; 300185353Sjfv u32 status; 301185353Sjfv 302169240Sjfv e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 303169240Sjfv if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 304169240Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 305169240Sjfv bus->func = (status & E1000_STATUS_FUNC_MASK) 306228386Sjfv >> E1000_STATUS_FUNC_SHIFT; 307173788Sjfv } else { 308169240Sjfv bus->func = 0; 309173788Sjfv } 310185353Sjfv} 311169240Sjfv 312185353Sjfv/** 313185353Sjfv * e1000_set_lan_id_single_port - Set LAN id for a single port device 314185353Sjfv * @hw: pointer to the HW structure 315185353Sjfv * 316185353Sjfv * Sets the LAN function id to zero for a single port device. 317185353Sjfv **/ 318185353Sjfvvoid e1000_set_lan_id_single_port(struct e1000_hw *hw) 319185353Sjfv{ 320185353Sjfv struct e1000_bus_info *bus = &hw->bus; 321185353Sjfv 322185353Sjfv bus->func = 0; 323169240Sjfv} 324169240Sjfv 325169240Sjfv/** 326169240Sjfv * e1000_clear_vfta_generic - Clear VLAN filter table 327169589Sjfv * @hw: pointer to the HW structure 328169240Sjfv * 329169240Sjfv * Clears the register array which contains the VLAN filter table by 330169240Sjfv * setting all the values to 0. 331169240Sjfv **/ 332173788Sjfvvoid e1000_clear_vfta_generic(struct e1000_hw *hw) 333169240Sjfv{ 334169240Sjfv u32 offset; 335169240Sjfv 336169240Sjfv DEBUGFUNC("e1000_clear_vfta_generic"); 337169240Sjfv 338169240Sjfv for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 339169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 340169240Sjfv E1000_WRITE_FLUSH(hw); 341169240Sjfv } 342169240Sjfv} 343169240Sjfv 344169240Sjfv/** 345169240Sjfv * e1000_write_vfta_generic - Write value to VLAN filter table 346169589Sjfv * @hw: pointer to the HW structure 347169589Sjfv * @offset: register offset in VLAN filter table 348169589Sjfv * @value: register value written to VLAN filter table 349169240Sjfv * 350169240Sjfv * Writes value at the given offset in the register array which stores 351169240Sjfv * the VLAN filter table. 352169240Sjfv **/ 353173788Sjfvvoid e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 354169240Sjfv{ 355169240Sjfv DEBUGFUNC("e1000_write_vfta_generic"); 356169240Sjfv 357169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 358169240Sjfv E1000_WRITE_FLUSH(hw); 359169240Sjfv} 360169240Sjfv 361169240Sjfv/** 362169240Sjfv * e1000_init_rx_addrs_generic - Initialize receive address's 363169589Sjfv * @hw: pointer to the HW structure 364169589Sjfv * @rar_count: receive address registers 365169240Sjfv * 366228386Sjfv * Setup the receive address registers by setting the base receive address 367169240Sjfv * register to the devices MAC address and clearing all the other receive 368169240Sjfv * address registers to 0. 369169240Sjfv **/ 370173788Sjfvvoid e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 371169240Sjfv{ 372169240Sjfv u32 i; 373190872Sjfv u8 mac_addr[ETH_ADDR_LEN] = {0}; 374169240Sjfv 375169240Sjfv DEBUGFUNC("e1000_init_rx_addrs_generic"); 376169240Sjfv 377169240Sjfv /* Setup the receive address */ 378169240Sjfv DEBUGOUT("Programming MAC Address into RAR[0]\n"); 379169240Sjfv 380177867Sjfv hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 381169240Sjfv 382169240Sjfv /* Zero out the other (rar_entry_count - 1) receive addresses */ 383169240Sjfv DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 384190872Sjfv for (i = 1; i < rar_count; i++) 385190872Sjfv hw->mac.ops.rar_set(hw, mac_addr, i); 386169240Sjfv} 387169240Sjfv 388169240Sjfv/** 389173788Sjfv * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 390173788Sjfv * @hw: pointer to the HW structure 391173788Sjfv * 392173788Sjfv * Checks the nvm for an alternate MAC address. An alternate MAC address 393173788Sjfv * can be setup by pre-boot software and must be treated like a permanent 394190872Sjfv * address and must override the actual permanent MAC address. If an 395190872Sjfv * alternate MAC address is found it is programmed into RAR0, replacing 396190872Sjfv * the permanent address that was installed into RAR0 by the Si on reset. 397190872Sjfv * This function will return SUCCESS unless it encounters an error while 398190872Sjfv * reading the EEPROM. 399173788Sjfv **/ 400173788Sjfvs32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 401173788Sjfv{ 402173788Sjfv u32 i; 403247064Sjfv s32 ret_val; 404173788Sjfv u16 offset, nvm_alt_mac_addr_offset, nvm_data; 405173788Sjfv u8 alt_mac_addr[ETH_ADDR_LEN]; 406173788Sjfv 407173788Sjfv DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 408173788Sjfv 409213234Sjfv ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); 410213234Sjfv if (ret_val) 411238148Sjfv return ret_val; 412213234Sjfv 413228386Sjfv /* not supported on older hardware or 82573 */ 414228386Sjfv if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573)) 415238148Sjfv return E1000_SUCCESS; 416213234Sjfv 417247064Sjfv /* Alternate MAC address is handled by the option ROM for 82580 418228386Sjfv * and newer. SW support not required. 419228386Sjfv */ 420228386Sjfv if (hw->mac.type >= e1000_82580) 421238148Sjfv return E1000_SUCCESS; 422228386Sjfv 423177867Sjfv ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 424228386Sjfv &nvm_alt_mac_addr_offset); 425173788Sjfv if (ret_val) { 426173788Sjfv DEBUGOUT("NVM Read Error\n"); 427238148Sjfv return ret_val; 428173788Sjfv } 429173788Sjfv 430228386Sjfv if ((nvm_alt_mac_addr_offset == 0xFFFF) || 431228386Sjfv (nvm_alt_mac_addr_offset == 0x0000)) 432190872Sjfv /* There is no Alternate MAC Address */ 433238148Sjfv return E1000_SUCCESS; 434173788Sjfv 435173788Sjfv if (hw->bus.func == E1000_FUNC_1) 436190872Sjfv nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 437200243Sjfv if (hw->bus.func == E1000_FUNC_2) 438200243Sjfv nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 439200243Sjfv 440200243Sjfv if (hw->bus.func == E1000_FUNC_3) 441200243Sjfv nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 442173788Sjfv for (i = 0; i < ETH_ADDR_LEN; i += 2) { 443173788Sjfv offset = nvm_alt_mac_addr_offset + (i >> 1); 444177867Sjfv ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 445173788Sjfv if (ret_val) { 446173788Sjfv DEBUGOUT("NVM Read Error\n"); 447238148Sjfv return ret_val; 448173788Sjfv } 449173788Sjfv 450173788Sjfv alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 451173788Sjfv alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 452173788Sjfv } 453173788Sjfv 454173788Sjfv /* if multicast bit is set, the alternate address will not be used */ 455173788Sjfv if (alt_mac_addr[0] & 0x01) { 456190872Sjfv DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 457238148Sjfv return E1000_SUCCESS; 458173788Sjfv } 459173788Sjfv 460247064Sjfv /* We have a valid alternate MAC address, and we want to treat it the 461190872Sjfv * same as the normal permanent MAC address stored by the HW into the 462190872Sjfv * RAR. Do this by mapping this address into RAR0. 463190872Sjfv */ 464190872Sjfv hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 465173788Sjfv 466238148Sjfv return E1000_SUCCESS; 467173788Sjfv} 468173788Sjfv 469173788Sjfv/** 470169240Sjfv * e1000_rar_set_generic - Set receive address register 471169589Sjfv * @hw: pointer to the HW structure 472169589Sjfv * @addr: pointer to the receive address 473169589Sjfv * @index: receive address array register 474169240Sjfv * 475169240Sjfv * Sets the receive address array register at index to the address passed 476169240Sjfv * in by addr. 477169240Sjfv **/ 478238148Sjfvstatic void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 479169240Sjfv{ 480169240Sjfv u32 rar_low, rar_high; 481169240Sjfv 482169240Sjfv DEBUGFUNC("e1000_rar_set_generic"); 483169240Sjfv 484247064Sjfv /* HW expects these in little endian so we reverse the byte order 485169240Sjfv * from network order (big endian) to little endian 486169240Sjfv */ 487228386Sjfv rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 488228386Sjfv ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 489169240Sjfv 490169240Sjfv rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 491169240Sjfv 492173788Sjfv /* If MAC address zero, no need to set the AV bit */ 493185353Sjfv if (rar_low || rar_high) 494185353Sjfv rar_high |= E1000_RAH_AV; 495169240Sjfv 496247064Sjfv /* Some bridges will combine consecutive 32-bit writes into 497190872Sjfv * a single burst write, which will malfunction on some parts. 498190872Sjfv * The flushes avoid this. 499190872Sjfv */ 500176667Sjfv E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 501190872Sjfv E1000_WRITE_FLUSH(hw); 502176667Sjfv E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 503190872Sjfv E1000_WRITE_FLUSH(hw); 504169240Sjfv} 505169240Sjfv 506169240Sjfv/** 507169240Sjfv * e1000_hash_mc_addr_generic - Generate a multicast hash value 508169589Sjfv * @hw: pointer to the HW structure 509169589Sjfv * @mc_addr: pointer to a multicast address 510169240Sjfv * 511169240Sjfv * Generates a multicast address hash value which is used to determine 512203049Sjfv * the multicast filter table array address and new table value. 513169240Sjfv **/ 514173788Sjfvu32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 515169240Sjfv{ 516169240Sjfv u32 hash_value, hash_mask; 517169240Sjfv u8 bit_shift = 0; 518169240Sjfv 519169240Sjfv DEBUGFUNC("e1000_hash_mc_addr_generic"); 520169240Sjfv 521169240Sjfv /* Register count multiplied by bits per register */ 522169240Sjfv hash_mask = (hw->mac.mta_reg_count * 32) - 1; 523169240Sjfv 524247064Sjfv /* For a mc_filter_type of 0, bit_shift is the number of left-shifts 525173788Sjfv * where 0xFF would still fall within the hash mask. 526173788Sjfv */ 527169240Sjfv while (hash_mask >> bit_shift != 0xFF) 528169240Sjfv bit_shift++; 529169240Sjfv 530247064Sjfv /* The portion of the address that is used for the hash table 531169240Sjfv * is determined by the mc_filter_type setting. 532169240Sjfv * The algorithm is such that there is a total of 8 bits of shifting. 533169240Sjfv * The bit_shift for a mc_filter_type of 0 represents the number of 534169240Sjfv * left-shifts where the MSB of mc_addr[5] would still fall within 535169240Sjfv * the hash_mask. Case 0 does this exactly. Since there are a total 536169240Sjfv * of 8 bits of shifting, then mc_addr[4] will shift right the 537169240Sjfv * remaining number of bits. Thus 8 - bit_shift. The rest of the 538169240Sjfv * cases are a variation of this algorithm...essentially raising the 539169240Sjfv * number of bits to shift mc_addr[5] left, while still keeping the 540169240Sjfv * 8-bit shifting total. 541173788Sjfv * 542173788Sjfv * For example, given the following Destination MAC Address and an 543169240Sjfv * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 544169240Sjfv * we can see that the bit_shift for case 0 is 4. These are the hash 545169240Sjfv * values resulting from each mc_filter_type... 546169240Sjfv * [0] [1] [2] [3] [4] [5] 547169240Sjfv * 01 AA 00 12 34 56 548228386Sjfv * LSB MSB 549169240Sjfv * 550169240Sjfv * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 551169240Sjfv * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 552169240Sjfv * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 553169240Sjfv * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 554169240Sjfv */ 555169240Sjfv switch (hw->mac.mc_filter_type) { 556185353Sjfv default: 557185353Sjfv case 0: 558185353Sjfv break; 559185353Sjfv case 1: 560185353Sjfv bit_shift += 1; 561185353Sjfv break; 562185353Sjfv case 2: 563185353Sjfv bit_shift += 2; 564185353Sjfv break; 565185353Sjfv case 3: 566185353Sjfv bit_shift += 4; 567185353Sjfv break; 568169240Sjfv } 569169240Sjfv 570169240Sjfv hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 571228386Sjfv (((u16) mc_addr[5]) << bit_shift))); 572169240Sjfv 573169240Sjfv return hash_value; 574169240Sjfv} 575169240Sjfv 576169240Sjfv/** 577238148Sjfv * e1000_update_mc_addr_list_generic - Update Multicast addresses 578238148Sjfv * @hw: pointer to the HW structure 579238148Sjfv * @mc_addr_list: array of multicast addresses to program 580238148Sjfv * @mc_addr_count: number of multicast addresses to program 581238148Sjfv * 582238148Sjfv * Updates entire Multicast Table Array. 583238148Sjfv * The caller must have a packed mc_addr_list of multicast addresses. 584238148Sjfv **/ 585238148Sjfvvoid e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 586238148Sjfv u8 *mc_addr_list, u32 mc_addr_count) 587238148Sjfv{ 588238148Sjfv u32 hash_value, hash_bit, hash_reg; 589238148Sjfv int i; 590238148Sjfv 591238148Sjfv DEBUGFUNC("e1000_update_mc_addr_list_generic"); 592238148Sjfv 593238148Sjfv /* clear mta_shadow */ 594238148Sjfv memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 595238148Sjfv 596238148Sjfv /* update mta_shadow from mc_addr_list */ 597238148Sjfv for (i = 0; (u32) i < mc_addr_count; i++) { 598238148Sjfv hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 599238148Sjfv 600238148Sjfv hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 601238148Sjfv hash_bit = hash_value & 0x1F; 602238148Sjfv 603238148Sjfv hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 604238148Sjfv mc_addr_list += (ETH_ADDR_LEN); 605238148Sjfv } 606238148Sjfv 607238148Sjfv /* replace the entire MTA table */ 608238148Sjfv for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 609238148Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 610238148Sjfv E1000_WRITE_FLUSH(hw); 611238148Sjfv} 612238148Sjfv 613238148Sjfv/** 614169240Sjfv * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 615169589Sjfv * @hw: pointer to the HW structure 616169240Sjfv * 617169240Sjfv * In certain situations, a system BIOS may report that the PCIx maximum 618169240Sjfv * memory read byte count (MMRBC) value is higher than than the actual 619176667Sjfv * value. We check the PCIx command register with the current PCIx status 620176667Sjfv * register. 621169240Sjfv **/ 622173788Sjfvvoid e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 623169240Sjfv{ 624169240Sjfv u16 cmd_mmrbc; 625169240Sjfv u16 pcix_cmd; 626169240Sjfv u16 pcix_stat_hi_word; 627169240Sjfv u16 stat_mmrbc; 628169240Sjfv 629169240Sjfv DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 630169240Sjfv 631169240Sjfv /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 632169240Sjfv if (hw->bus.type != e1000_bus_type_pcix) 633169240Sjfv return; 634169240Sjfv 635169240Sjfv e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 636169240Sjfv e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 637169240Sjfv cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 638228386Sjfv PCIX_COMMAND_MMRBC_SHIFT; 639169240Sjfv stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 640228386Sjfv PCIX_STATUS_HI_MMRBC_SHIFT; 641169240Sjfv if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 642169240Sjfv stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 643169240Sjfv if (cmd_mmrbc > stat_mmrbc) { 644169240Sjfv pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 645169240Sjfv pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 646169240Sjfv e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 647169240Sjfv } 648169240Sjfv} 649169240Sjfv 650169240Sjfv/** 651169240Sjfv * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 652169589Sjfv * @hw: pointer to the HW structure 653169240Sjfv * 654169240Sjfv * Clears the base hardware counters by reading the counter registers. 655169240Sjfv **/ 656173788Sjfvvoid e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 657169240Sjfv{ 658169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 659169240Sjfv 660185353Sjfv E1000_READ_REG(hw, E1000_CRCERRS); 661185353Sjfv E1000_READ_REG(hw, E1000_SYMERRS); 662185353Sjfv E1000_READ_REG(hw, E1000_MPC); 663185353Sjfv E1000_READ_REG(hw, E1000_SCC); 664185353Sjfv E1000_READ_REG(hw, E1000_ECOL); 665185353Sjfv E1000_READ_REG(hw, E1000_MCC); 666185353Sjfv E1000_READ_REG(hw, E1000_LATECOL); 667185353Sjfv E1000_READ_REG(hw, E1000_COLC); 668185353Sjfv E1000_READ_REG(hw, E1000_DC); 669185353Sjfv E1000_READ_REG(hw, E1000_SEC); 670185353Sjfv E1000_READ_REG(hw, E1000_RLEC); 671185353Sjfv E1000_READ_REG(hw, E1000_XONRXC); 672185353Sjfv E1000_READ_REG(hw, E1000_XONTXC); 673185353Sjfv E1000_READ_REG(hw, E1000_XOFFRXC); 674185353Sjfv E1000_READ_REG(hw, E1000_XOFFTXC); 675185353Sjfv E1000_READ_REG(hw, E1000_FCRUC); 676185353Sjfv E1000_READ_REG(hw, E1000_GPRC); 677185353Sjfv E1000_READ_REG(hw, E1000_BPRC); 678185353Sjfv E1000_READ_REG(hw, E1000_MPRC); 679185353Sjfv E1000_READ_REG(hw, E1000_GPTC); 680185353Sjfv E1000_READ_REG(hw, E1000_GORCL); 681185353Sjfv E1000_READ_REG(hw, E1000_GORCH); 682185353Sjfv E1000_READ_REG(hw, E1000_GOTCL); 683185353Sjfv E1000_READ_REG(hw, E1000_GOTCH); 684185353Sjfv E1000_READ_REG(hw, E1000_RNBC); 685185353Sjfv E1000_READ_REG(hw, E1000_RUC); 686185353Sjfv E1000_READ_REG(hw, E1000_RFC); 687185353Sjfv E1000_READ_REG(hw, E1000_ROC); 688185353Sjfv E1000_READ_REG(hw, E1000_RJC); 689185353Sjfv E1000_READ_REG(hw, E1000_TORL); 690185353Sjfv E1000_READ_REG(hw, E1000_TORH); 691185353Sjfv E1000_READ_REG(hw, E1000_TOTL); 692185353Sjfv E1000_READ_REG(hw, E1000_TOTH); 693185353Sjfv E1000_READ_REG(hw, E1000_TPR); 694185353Sjfv E1000_READ_REG(hw, E1000_TPT); 695185353Sjfv E1000_READ_REG(hw, E1000_MPTC); 696185353Sjfv E1000_READ_REG(hw, E1000_BPTC); 697169240Sjfv} 698169240Sjfv 699169240Sjfv/** 700169240Sjfv * e1000_check_for_copper_link_generic - Check for link (Copper) 701169589Sjfv * @hw: pointer to the HW structure 702169240Sjfv * 703169240Sjfv * Checks to see of the link status of the hardware has changed. If a 704169240Sjfv * change in link status has been detected, then we read the PHY registers 705169240Sjfv * to get the current speed/duplex if link exists. 706169240Sjfv **/ 707173788Sjfvs32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 708169240Sjfv{ 709169240Sjfv struct e1000_mac_info *mac = &hw->mac; 710169240Sjfv s32 ret_val; 711173788Sjfv bool link; 712169240Sjfv 713169240Sjfv DEBUGFUNC("e1000_check_for_copper_link"); 714169240Sjfv 715247064Sjfv /* We only want to go out to the PHY registers to see if Auto-Neg 716169240Sjfv * has completed and/or if our link status has changed. The 717169240Sjfv * get_link_status flag is set upon receiving a Link Status 718169240Sjfv * Change or Rx Sequence Error interrupt. 719169240Sjfv */ 720238148Sjfv if (!mac->get_link_status) 721238148Sjfv return E1000_SUCCESS; 722169240Sjfv 723247064Sjfv /* First we want to see if the MII Status Register reports 724169240Sjfv * link. If so, then we want to get the current speed/duplex 725169240Sjfv * of the PHY. 726169240Sjfv */ 727169240Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 728169240Sjfv if (ret_val) 729238148Sjfv return ret_val; 730169240Sjfv 731169240Sjfv if (!link) 732238148Sjfv return E1000_SUCCESS; /* No link detected */ 733169240Sjfv 734169240Sjfv mac->get_link_status = FALSE; 735169240Sjfv 736247064Sjfv /* Check if there was DownShift, must be checked 737173788Sjfv * immediately after link-up 738173788Sjfv */ 739169240Sjfv e1000_check_downshift_generic(hw); 740169240Sjfv 741247064Sjfv /* If we are forcing speed/duplex, then we simply return since 742169240Sjfv * we have already determined whether we have link or not. 743169240Sjfv */ 744238148Sjfv if (!mac->autoneg) 745238148Sjfv return -E1000_ERR_CONFIG; 746169240Sjfv 747247064Sjfv /* Auto-Neg is enabled. Auto Speed Detection takes care 748169240Sjfv * of MAC speed/duplex configuration. So we only need to 749169240Sjfv * configure Collision Distance in the MAC. 750169240Sjfv */ 751203049Sjfv mac->ops.config_collision_dist(hw); 752169240Sjfv 753247064Sjfv /* Configure Flow Control now that Auto-Neg has completed. 754169240Sjfv * First, we need to restore the desired flow control 755169240Sjfv * settings because we may have had to re-autoneg with a 756169240Sjfv * different link partner. 757169240Sjfv */ 758169240Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 759185353Sjfv if (ret_val) 760169240Sjfv DEBUGOUT("Error configuring flow control\n"); 761169240Sjfv 762169240Sjfv return ret_val; 763169240Sjfv} 764169240Sjfv 765169240Sjfv/** 766169240Sjfv * e1000_check_for_fiber_link_generic - Check for link (Fiber) 767169589Sjfv * @hw: pointer to the HW structure 768169240Sjfv * 769169240Sjfv * Checks for link up on the hardware. If link is not up and we have 770169240Sjfv * a signal, then we need to force link up. 771169240Sjfv **/ 772173788Sjfvs32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 773169240Sjfv{ 774169240Sjfv struct e1000_mac_info *mac = &hw->mac; 775169240Sjfv u32 rxcw; 776169240Sjfv u32 ctrl; 777169240Sjfv u32 status; 778238148Sjfv s32 ret_val; 779169240Sjfv 780169240Sjfv DEBUGFUNC("e1000_check_for_fiber_link_generic"); 781169240Sjfv 782169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 783169240Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 784169240Sjfv rxcw = E1000_READ_REG(hw, E1000_RXCW); 785169240Sjfv 786247064Sjfv /* If we don't have link (auto-negotiation failed or link partner 787169240Sjfv * cannot auto-negotiate), the cable is plugged in (we have signal), 788169240Sjfv * and our link partner is not trying to auto-negotiate with us (we 789169240Sjfv * are receiving idles or data), we need to force link up. We also 790169240Sjfv * need to give auto-negotiation time to complete, in case the cable 791169240Sjfv * was just plugged in. The autoneg_failed flag does this. 792169240Sjfv */ 793169240Sjfv /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 794238148Sjfv if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) && 795238148Sjfv !(rxcw & E1000_RXCW_C)) { 796238148Sjfv if (!mac->autoneg_failed) { 797238148Sjfv mac->autoneg_failed = TRUE; 798238148Sjfv return E1000_SUCCESS; 799169240Sjfv } 800218530Sjfv DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 801169240Sjfv 802169240Sjfv /* Disable auto-negotiation in the TXCW register */ 803169240Sjfv E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 804169240Sjfv 805169240Sjfv /* Force link-up and also force full-duplex. */ 806169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 807169240Sjfv ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 808169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 809169240Sjfv 810169240Sjfv /* Configure Flow Control after forcing link up. */ 811169240Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 812169240Sjfv if (ret_val) { 813169240Sjfv DEBUGOUT("Error configuring flow control\n"); 814238148Sjfv return ret_val; 815169240Sjfv } 816169240Sjfv } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 817247064Sjfv /* If we are forcing link and we are receiving /C/ ordered 818169240Sjfv * sets, re-enable auto-negotiation in the TXCW register 819169240Sjfv * and disable forced link in the Device Control register 820169240Sjfv * in an attempt to auto-negotiate with our link partner. 821169240Sjfv */ 822218530Sjfv DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 823169240Sjfv E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 824169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 825169240Sjfv 826169240Sjfv mac->serdes_has_link = TRUE; 827169240Sjfv } 828169240Sjfv 829238148Sjfv return E1000_SUCCESS; 830169240Sjfv} 831169240Sjfv 832169240Sjfv/** 833169240Sjfv * e1000_check_for_serdes_link_generic - Check for link (Serdes) 834169589Sjfv * @hw: pointer to the HW structure 835169240Sjfv * 836169240Sjfv * Checks for link up on the hardware. If link is not up and we have 837169240Sjfv * a signal, then we need to force link up. 838169240Sjfv **/ 839173788Sjfvs32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 840169240Sjfv{ 841169240Sjfv struct e1000_mac_info *mac = &hw->mac; 842169240Sjfv u32 rxcw; 843169240Sjfv u32 ctrl; 844169240Sjfv u32 status; 845238148Sjfv s32 ret_val; 846169240Sjfv 847169240Sjfv DEBUGFUNC("e1000_check_for_serdes_link_generic"); 848169240Sjfv 849169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 850169240Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 851169240Sjfv rxcw = E1000_READ_REG(hw, E1000_RXCW); 852169240Sjfv 853247064Sjfv /* If we don't have link (auto-negotiation failed or link partner 854169240Sjfv * cannot auto-negotiate), and our link partner is not trying to 855169240Sjfv * auto-negotiate with us (we are receiving idles or data), 856169240Sjfv * we need to force link up. We also need to give auto-negotiation 857169240Sjfv * time to complete. 858169240Sjfv */ 859169240Sjfv /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 860238148Sjfv if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) { 861238148Sjfv if (!mac->autoneg_failed) { 862238148Sjfv mac->autoneg_failed = TRUE; 863238148Sjfv return E1000_SUCCESS; 864169240Sjfv } 865218530Sjfv DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 866169240Sjfv 867169240Sjfv /* Disable auto-negotiation in the TXCW register */ 868169240Sjfv E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 869169240Sjfv 870169240Sjfv /* Force link-up and also force full-duplex. */ 871169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 872169240Sjfv ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 873169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 874169240Sjfv 875169240Sjfv /* Configure Flow Control after forcing link up. */ 876169240Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 877169240Sjfv if (ret_val) { 878169240Sjfv DEBUGOUT("Error configuring flow control\n"); 879238148Sjfv return ret_val; 880169240Sjfv } 881169240Sjfv } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 882247064Sjfv /* If we are forcing link and we are receiving /C/ ordered 883169240Sjfv * sets, re-enable auto-negotiation in the TXCW register 884169240Sjfv * and disable forced link in the Device Control register 885169240Sjfv * in an attempt to auto-negotiate with our link partner. 886169240Sjfv */ 887218530Sjfv DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 888169240Sjfv E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 889169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 890169240Sjfv 891169240Sjfv mac->serdes_has_link = TRUE; 892169240Sjfv } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 893247064Sjfv /* If we force link for non-auto-negotiation switch, check 894169240Sjfv * link status based on MAC synchronization for internal 895169240Sjfv * serdes media type. 896169240Sjfv */ 897169240Sjfv /* SYNCH bit and IV bit are sticky. */ 898169240Sjfv usec_delay(10); 899181027Sjfv rxcw = E1000_READ_REG(hw, E1000_RXCW); 900181027Sjfv if (rxcw & E1000_RXCW_SYNCH) { 901169240Sjfv if (!(rxcw & E1000_RXCW_IV)) { 902169240Sjfv mac->serdes_has_link = TRUE; 903181027Sjfv DEBUGOUT("SERDES: Link up - forced.\n"); 904169240Sjfv } 905169240Sjfv } else { 906169240Sjfv mac->serdes_has_link = FALSE; 907181027Sjfv DEBUGOUT("SERDES: Link down - force failed.\n"); 908169240Sjfv } 909169240Sjfv } 910169240Sjfv 911169240Sjfv if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 912169240Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 913181027Sjfv if (status & E1000_STATUS_LU) { 914181027Sjfv /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 915181027Sjfv usec_delay(10); 916181027Sjfv rxcw = E1000_READ_REG(hw, E1000_RXCW); 917181027Sjfv if (rxcw & E1000_RXCW_SYNCH) { 918181027Sjfv if (!(rxcw & E1000_RXCW_IV)) { 919181027Sjfv mac->serdes_has_link = TRUE; 920228386Sjfv DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n"); 921181027Sjfv } else { 922181027Sjfv mac->serdes_has_link = FALSE; 923228386Sjfv DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n"); 924181027Sjfv } 925181027Sjfv } else { 926181027Sjfv mac->serdes_has_link = FALSE; 927181027Sjfv DEBUGOUT("SERDES: Link down - no sync.\n"); 928181027Sjfv } 929181027Sjfv } else { 930181027Sjfv mac->serdes_has_link = FALSE; 931181027Sjfv DEBUGOUT("SERDES: Link down - autoneg failed\n"); 932181027Sjfv } 933169240Sjfv } 934169240Sjfv 935238148Sjfv return E1000_SUCCESS; 936169240Sjfv} 937169240Sjfv 938169240Sjfv/** 939238148Sjfv * e1000_set_default_fc_generic - Set flow control default values 940238148Sjfv * @hw: pointer to the HW structure 941238148Sjfv * 942238148Sjfv * Read the EEPROM for the default values for flow control and store the 943238148Sjfv * values. 944238148Sjfv **/ 945238148Sjfvs32 e1000_set_default_fc_generic(struct e1000_hw *hw) 946238148Sjfv{ 947238148Sjfv s32 ret_val; 948238148Sjfv u16 nvm_data; 949256200Sjfv u16 nvm_offset = 0; 950238148Sjfv 951238148Sjfv DEBUGFUNC("e1000_set_default_fc_generic"); 952238148Sjfv 953247064Sjfv /* Read and store word 0x0F of the EEPROM. This word contains bits 954238148Sjfv * that determine the hardware's default PAUSE (flow control) mode, 955238148Sjfv * a bit that determines whether the HW defaults to enabling or 956238148Sjfv * disabling auto-negotiation, and the direction of the 957238148Sjfv * SW defined pins. If there is no SW over-ride of the flow 958238148Sjfv * control setting, then the variable hw->fc will 959238148Sjfv * be initialized based on a value in the EEPROM. 960238148Sjfv */ 961256200Sjfv if (hw->mac.type == e1000_i350) { 962256200Sjfv nvm_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func); 963256200Sjfv ret_val = hw->nvm.ops.read(hw, 964256200Sjfv NVM_INIT_CONTROL2_REG + 965256200Sjfv nvm_offset, 966256200Sjfv 1, &nvm_data); 967256200Sjfv } else { 968256200Sjfv ret_val = hw->nvm.ops.read(hw, 969256200Sjfv NVM_INIT_CONTROL2_REG, 970256200Sjfv 1, &nvm_data); 971256200Sjfv } 972238148Sjfv 973256200Sjfv 974238148Sjfv if (ret_val) { 975238148Sjfv DEBUGOUT("NVM Read Error\n"); 976238148Sjfv return ret_val; 977238148Sjfv } 978238148Sjfv 979238148Sjfv if (!(nvm_data & NVM_WORD0F_PAUSE_MASK)) 980238148Sjfv hw->fc.requested_mode = e1000_fc_none; 981238148Sjfv else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 982238148Sjfv NVM_WORD0F_ASM_DIR) 983238148Sjfv hw->fc.requested_mode = e1000_fc_tx_pause; 984238148Sjfv else 985238148Sjfv hw->fc.requested_mode = e1000_fc_full; 986238148Sjfv 987238148Sjfv return E1000_SUCCESS; 988238148Sjfv} 989238148Sjfv 990238148Sjfv/** 991169240Sjfv * e1000_setup_link_generic - Setup flow control and link settings 992169589Sjfv * @hw: pointer to the HW structure 993169240Sjfv * 994169240Sjfv * Determines which flow control settings to use, then configures flow 995169240Sjfv * control. Calls the appropriate media-specific link configuration 996169240Sjfv * function. Assuming the adapter has a valid link partner, a valid link 997169240Sjfv * should be established. Assumes the hardware has previously been reset 998169240Sjfv * and the transmitter and receiver are not enabled. 999169240Sjfv **/ 1000173788Sjfvs32 e1000_setup_link_generic(struct e1000_hw *hw) 1001169240Sjfv{ 1002238148Sjfv s32 ret_val; 1003169240Sjfv 1004169240Sjfv DEBUGFUNC("e1000_setup_link_generic"); 1005169240Sjfv 1006247064Sjfv /* In the case of the phy reset being blocked, we already have a link. 1007169240Sjfv * We do not need to set it up again. 1008169240Sjfv */ 1009238148Sjfv if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 1010238148Sjfv return E1000_SUCCESS; 1011169240Sjfv 1012247064Sjfv /* If requested flow control is set to default, set flow control 1013185353Sjfv * based on the EEPROM flow control settings. 1014173788Sjfv */ 1015185353Sjfv if (hw->fc.requested_mode == e1000_fc_default) { 1016173788Sjfv ret_val = e1000_set_default_fc_generic(hw); 1017173788Sjfv if (ret_val) 1018238148Sjfv return ret_val; 1019173788Sjfv } 1020169240Sjfv 1021247064Sjfv /* Save off the requested flow control mode for use later. Depending 1022185353Sjfv * on the link partner's capabilities, we may or may not use this mode. 1023169240Sjfv */ 1024185353Sjfv hw->fc.current_mode = hw->fc.requested_mode; 1025169240Sjfv 1026185353Sjfv DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 1027190872Sjfv hw->fc.current_mode); 1028169240Sjfv 1029169240Sjfv /* Call the necessary media_type subroutine to configure the link. */ 1030177867Sjfv ret_val = hw->mac.ops.setup_physical_interface(hw); 1031169240Sjfv if (ret_val) 1032238148Sjfv return ret_val; 1033169240Sjfv 1034247064Sjfv /* Initialize the flow control address, type, and PAUSE timer 1035169240Sjfv * registers to their default values. This is done even if flow 1036169240Sjfv * control is disabled, because it does not hurt anything to 1037169240Sjfv * initialize these registers. 1038169240Sjfv */ 1039169240Sjfv DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1040169240Sjfv E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 1041169240Sjfv E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1042169240Sjfv E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 1043169240Sjfv 1044173788Sjfv E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 1045169240Sjfv 1046238148Sjfv return e1000_set_fc_watermarks_generic(hw); 1047169240Sjfv} 1048169240Sjfv 1049169240Sjfv/** 1050238148Sjfv * e1000_commit_fc_settings_generic - Configure flow control 1051169589Sjfv * @hw: pointer to the HW structure 1052169240Sjfv * 1053238148Sjfv * Write the flow control settings to the Transmit Config Word Register (TXCW) 1054238148Sjfv * base on the flow control settings in e1000_mac_info. 1055169240Sjfv **/ 1056238148Sjfvs32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1057169240Sjfv{ 1058203049Sjfv struct e1000_mac_info *mac = &hw->mac; 1059238148Sjfv u32 txcw; 1060169240Sjfv 1061238148Sjfv DEBUGFUNC("e1000_commit_fc_settings_generic"); 1062169240Sjfv 1063247064Sjfv /* Check for a software override of the flow control settings, and 1064238148Sjfv * setup the device accordingly. If auto-negotiation is enabled, then 1065238148Sjfv * software will have to set the "PAUSE" bits to the correct value in 1066238148Sjfv * the Transmit Config Word Register (TXCW) and re-start auto- 1067238148Sjfv * negotiation. However, if auto-negotiation is disabled, then 1068238148Sjfv * software will have to manually configure the two flow control enable 1069238148Sjfv * bits in the CTRL register. 1070238148Sjfv * 1071238148Sjfv * The possible values of the "fc" parameter are: 1072238148Sjfv * 0: Flow control is completely disabled 1073238148Sjfv * 1: Rx flow control is enabled (we can receive pause frames, 1074238148Sjfv * but not send pause frames). 1075238148Sjfv * 2: Tx flow control is enabled (we can send pause frames but we 1076238148Sjfv * do not support receiving pause frames). 1077238148Sjfv * 3: Both Rx and Tx flow control (symmetric) are enabled. 1078169240Sjfv */ 1079238148Sjfv switch (hw->fc.current_mode) { 1080238148Sjfv case e1000_fc_none: 1081238148Sjfv /* Flow control completely disabled by a software over-ride. */ 1082238148Sjfv txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1083238148Sjfv break; 1084238148Sjfv case e1000_fc_rx_pause: 1085247064Sjfv /* Rx Flow control is enabled and Tx Flow control is disabled 1086238148Sjfv * by a software over-ride. Since there really isn't a way to 1087238148Sjfv * advertise that we are capable of Rx Pause ONLY, we will 1088238148Sjfv * advertise that we support both symmetric and asymmetric Rx 1089238148Sjfv * PAUSE. Later, we will disable the adapter's ability to send 1090238148Sjfv * PAUSE frames. 1091238148Sjfv */ 1092238148Sjfv txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1093238148Sjfv break; 1094238148Sjfv case e1000_fc_tx_pause: 1095247064Sjfv /* Tx Flow control is enabled, and Rx Flow control is disabled, 1096238148Sjfv * by a software over-ride. 1097238148Sjfv */ 1098238148Sjfv txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1099238148Sjfv break; 1100238148Sjfv case e1000_fc_full: 1101247064Sjfv /* Flow control (both Rx and Tx) is enabled by a software 1102238148Sjfv * over-ride. 1103238148Sjfv */ 1104238148Sjfv txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1105238148Sjfv break; 1106238148Sjfv default: 1107238148Sjfv DEBUGOUT("Flow control param set incorrectly\n"); 1108238148Sjfv return -E1000_ERR_CONFIG; 1109238148Sjfv break; 1110169240Sjfv } 1111169240Sjfv 1112238148Sjfv E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1113238148Sjfv mac->txcw = txcw; 1114169240Sjfv 1115238148Sjfv return E1000_SUCCESS; 1116169240Sjfv} 1117169240Sjfv 1118169240Sjfv/** 1119169240Sjfv * e1000_poll_fiber_serdes_link_generic - Poll for link up 1120169589Sjfv * @hw: pointer to the HW structure 1121169240Sjfv * 1122169240Sjfv * Polls for link up by reading the status register, if link fails to come 1123169240Sjfv * up with auto-negotiation, then the link is forced if a signal is detected. 1124169240Sjfv **/ 1125218548Sbzs32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1126169240Sjfv{ 1127169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1128169240Sjfv u32 i, status; 1129238148Sjfv s32 ret_val; 1130169240Sjfv 1131169240Sjfv DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1132169240Sjfv 1133247064Sjfv /* If we have a signal (the cable is plugged in, or assumed TRUE for 1134169240Sjfv * serdes media) then poll for a "Link-Up" indication in the Device 1135169240Sjfv * Status Register. Time-out if a link isn't seen in 500 milliseconds 1136169240Sjfv * seconds (Auto-negotiation should complete in less than 500 1137169240Sjfv * milliseconds even if the other end is doing it in SW). 1138169240Sjfv */ 1139169240Sjfv for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1140169240Sjfv msec_delay(10); 1141169240Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 1142169240Sjfv if (status & E1000_STATUS_LU) 1143169240Sjfv break; 1144169240Sjfv } 1145169240Sjfv if (i == FIBER_LINK_UP_LIMIT) { 1146169240Sjfv DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1147238148Sjfv mac->autoneg_failed = TRUE; 1148247064Sjfv /* AutoNeg failed to achieve a link, so we'll call 1149169240Sjfv * mac->check_for_link. This routine will force the 1150169240Sjfv * link up if we detect a signal. This will allow us to 1151169240Sjfv * communicate with non-autonegotiating link partners. 1152169240Sjfv */ 1153203049Sjfv ret_val = mac->ops.check_for_link(hw); 1154169240Sjfv if (ret_val) { 1155169240Sjfv DEBUGOUT("Error while checking for link\n"); 1156238148Sjfv return ret_val; 1157169240Sjfv } 1158238148Sjfv mac->autoneg_failed = FALSE; 1159169240Sjfv } else { 1160238148Sjfv mac->autoneg_failed = FALSE; 1161169240Sjfv DEBUGOUT("Valid Link Found\n"); 1162169240Sjfv } 1163169240Sjfv 1164238148Sjfv return E1000_SUCCESS; 1165169240Sjfv} 1166169240Sjfv 1167169240Sjfv/** 1168238148Sjfv * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1169169589Sjfv * @hw: pointer to the HW structure 1170169240Sjfv * 1171238148Sjfv * Configures collision distance and flow control for fiber and serdes 1172238148Sjfv * links. Upon successful setup, poll for link. 1173169240Sjfv **/ 1174238148Sjfvs32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1175169240Sjfv{ 1176238148Sjfv u32 ctrl; 1177238148Sjfv s32 ret_val; 1178169240Sjfv 1179238148Sjfv DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1180169240Sjfv 1181238148Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1182238148Sjfv 1183238148Sjfv /* Take the link out of reset */ 1184238148Sjfv ctrl &= ~E1000_CTRL_LRST; 1185238148Sjfv 1186238148Sjfv hw->mac.ops.config_collision_dist(hw); 1187238148Sjfv 1188238148Sjfv ret_val = e1000_commit_fc_settings_generic(hw); 1189238148Sjfv if (ret_val) 1190238148Sjfv return ret_val; 1191238148Sjfv 1192247064Sjfv /* Since auto-negotiation is enabled, take the link out of reset (the 1193238148Sjfv * link will be in reset, because we previously reset the chip). This 1194238148Sjfv * will restart auto-negotiation. If auto-negotiation is successful 1195238148Sjfv * then the link-up status bit will be set and the flow control enable 1196238148Sjfv * bits (RFCE and TFCE) will be set according to their negotiated value. 1197169240Sjfv */ 1198238148Sjfv DEBUGOUT("Auto-negotiation enabled\n"); 1199238148Sjfv 1200238148Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1201238148Sjfv E1000_WRITE_FLUSH(hw); 1202238148Sjfv msec_delay(1); 1203238148Sjfv 1204247064Sjfv /* For these adapters, the SW definable pin 1 is set when the optics 1205238148Sjfv * detect a signal. If we have a signal, then poll for a "Link-Up" 1206238148Sjfv * indication. 1207238148Sjfv */ 1208238148Sjfv if (hw->phy.media_type == e1000_media_type_internal_serdes || 1209238148Sjfv (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1210238148Sjfv ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1211238148Sjfv } else { 1212238148Sjfv DEBUGOUT("No signal detected\n"); 1213169240Sjfv } 1214169240Sjfv 1215169240Sjfv return ret_val; 1216169240Sjfv} 1217169240Sjfv 1218169240Sjfv/** 1219238148Sjfv * e1000_config_collision_dist_generic - Configure collision distance 1220238148Sjfv * @hw: pointer to the HW structure 1221238148Sjfv * 1222238148Sjfv * Configures the collision distance to the default value and is used 1223238148Sjfv * during link setup. 1224238148Sjfv **/ 1225238148Sjfvstatic void e1000_config_collision_dist_generic(struct e1000_hw *hw) 1226238148Sjfv{ 1227238148Sjfv u32 tctl; 1228238148Sjfv 1229238148Sjfv DEBUGFUNC("e1000_config_collision_dist_generic"); 1230238148Sjfv 1231238148Sjfv tctl = E1000_READ_REG(hw, E1000_TCTL); 1232238148Sjfv 1233238148Sjfv tctl &= ~E1000_TCTL_COLD; 1234238148Sjfv tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1235238148Sjfv 1236238148Sjfv E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1237238148Sjfv E1000_WRITE_FLUSH(hw); 1238238148Sjfv} 1239238148Sjfv 1240238148Sjfv/** 1241169240Sjfv * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1242169589Sjfv * @hw: pointer to the HW structure 1243169240Sjfv * 1244169240Sjfv * Sets the flow control high/low threshold (watermark) registers. If 1245169240Sjfv * flow control XON frame transmission is enabled, then set XON frame 1246176667Sjfv * transmission as well. 1247169240Sjfv **/ 1248173788Sjfvs32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1249169240Sjfv{ 1250169240Sjfv u32 fcrtl = 0, fcrth = 0; 1251169240Sjfv 1252169240Sjfv DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1253169240Sjfv 1254247064Sjfv /* Set the flow control receive threshold registers. Normally, 1255169240Sjfv * these registers will be set to a default threshold that may be 1256169240Sjfv * adjusted later by the driver's runtime code. However, if the 1257169240Sjfv * ability to transmit pause frames is not enabled, then these 1258169240Sjfv * registers will be set to 0. 1259169240Sjfv */ 1260185353Sjfv if (hw->fc.current_mode & e1000_fc_tx_pause) { 1261247064Sjfv /* We need to set up the Receive Threshold high and low water 1262169240Sjfv * marks as well as (optionally) enabling the transmission of 1263169240Sjfv * XON frames. 1264169240Sjfv */ 1265173788Sjfv fcrtl = hw->fc.low_water; 1266173788Sjfv if (hw->fc.send_xon) 1267169240Sjfv fcrtl |= E1000_FCRTL_XONE; 1268169240Sjfv 1269173788Sjfv fcrth = hw->fc.high_water; 1270169240Sjfv } 1271169240Sjfv E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1272169240Sjfv E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1273169240Sjfv 1274203049Sjfv return E1000_SUCCESS; 1275169240Sjfv} 1276169240Sjfv 1277169240Sjfv/** 1278169240Sjfv * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1279169589Sjfv * @hw: pointer to the HW structure 1280169240Sjfv * 1281169240Sjfv * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1282169240Sjfv * device control register to reflect the adapter settings. TFCE and RFCE 1283169240Sjfv * need to be explicitly set by software when a copper PHY is used because 1284169240Sjfv * autonegotiation is managed by the PHY rather than the MAC. Software must 1285169240Sjfv * also configure these bits when link is forced on a fiber connection. 1286169240Sjfv **/ 1287173788Sjfvs32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1288169240Sjfv{ 1289169240Sjfv u32 ctrl; 1290169240Sjfv 1291169240Sjfv DEBUGFUNC("e1000_force_mac_fc_generic"); 1292169240Sjfv 1293169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1294169240Sjfv 1295247064Sjfv /* Because we didn't get link via the internal auto-negotiation 1296169240Sjfv * mechanism (we either forced link or we got link via PHY 1297169240Sjfv * auto-neg), we have to manually enable/disable transmit an 1298169240Sjfv * receive flow control. 1299169240Sjfv * 1300169240Sjfv * The "Case" statement below enables/disable flow control 1301185353Sjfv * according to the "hw->fc.current_mode" parameter. 1302169240Sjfv * 1303169240Sjfv * The possible values of the "fc" parameter are: 1304169240Sjfv * 0: Flow control is completely disabled 1305169240Sjfv * 1: Rx flow control is enabled (we can receive pause 1306169240Sjfv * frames but not send pause frames). 1307169240Sjfv * 2: Tx flow control is enabled (we can send pause frames 1308169240Sjfv * frames but we do not receive pause frames). 1309173788Sjfv * 3: Both Rx and Tx flow control (symmetric) is enabled. 1310169240Sjfv * other: No other values should be possible at this point. 1311169240Sjfv */ 1312185353Sjfv DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1313169240Sjfv 1314185353Sjfv switch (hw->fc.current_mode) { 1315169240Sjfv case e1000_fc_none: 1316169240Sjfv ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1317169240Sjfv break; 1318169240Sjfv case e1000_fc_rx_pause: 1319169240Sjfv ctrl &= (~E1000_CTRL_TFCE); 1320169240Sjfv ctrl |= E1000_CTRL_RFCE; 1321169240Sjfv break; 1322169240Sjfv case e1000_fc_tx_pause: 1323169240Sjfv ctrl &= (~E1000_CTRL_RFCE); 1324169240Sjfv ctrl |= E1000_CTRL_TFCE; 1325169240Sjfv break; 1326169240Sjfv case e1000_fc_full: 1327169240Sjfv ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1328169240Sjfv break; 1329169240Sjfv default: 1330169240Sjfv DEBUGOUT("Flow control param set incorrectly\n"); 1331238148Sjfv return -E1000_ERR_CONFIG; 1332169240Sjfv } 1333169240Sjfv 1334169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1335169240Sjfv 1336238148Sjfv return E1000_SUCCESS; 1337169240Sjfv} 1338169240Sjfv 1339169240Sjfv/** 1340169240Sjfv * e1000_config_fc_after_link_up_generic - Configures flow control after link 1341169589Sjfv * @hw: pointer to the HW structure 1342169240Sjfv * 1343169240Sjfv * Checks the status of auto-negotiation after link up to ensure that the 1344169240Sjfv * speed and duplex were not forced. If the link needed to be forced, then 1345169240Sjfv * flow control needs to be forced also. If auto-negotiation is enabled 1346169240Sjfv * and did not fail, then we configure flow control based on our link 1347169240Sjfv * partner. 1348169240Sjfv **/ 1349173788Sjfvs32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1350169240Sjfv{ 1351169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1352169240Sjfv s32 ret_val = E1000_SUCCESS; 1353247064Sjfv u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg; 1354169240Sjfv u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1355169240Sjfv u16 speed, duplex; 1356169240Sjfv 1357169240Sjfv DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1358169240Sjfv 1359247064Sjfv /* Check for the case where we have fiber media and auto-neg failed 1360169240Sjfv * so we had to force link. In this case, we need to force the 1361169240Sjfv * configuration of the MAC to match the "fc" parameter. 1362169240Sjfv */ 1363169240Sjfv if (mac->autoneg_failed) { 1364173788Sjfv if (hw->phy.media_type == e1000_media_type_fiber || 1365173788Sjfv hw->phy.media_type == e1000_media_type_internal_serdes) 1366169240Sjfv ret_val = e1000_force_mac_fc_generic(hw); 1367169240Sjfv } else { 1368173788Sjfv if (hw->phy.media_type == e1000_media_type_copper) 1369169240Sjfv ret_val = e1000_force_mac_fc_generic(hw); 1370169240Sjfv } 1371169240Sjfv 1372169240Sjfv if (ret_val) { 1373169240Sjfv DEBUGOUT("Error forcing flow control settings\n"); 1374238148Sjfv return ret_val; 1375169240Sjfv } 1376169240Sjfv 1377247064Sjfv /* Check for the case where we have copper media and auto-neg is 1378169240Sjfv * enabled. In this case, we need to check and see if Auto-Neg 1379169240Sjfv * has completed, and if so, how the PHY and link partner has 1380169240Sjfv * flow control configured. 1381169240Sjfv */ 1382173788Sjfv if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1383247064Sjfv /* Read the MII Status Register and check to see if AutoNeg 1384169240Sjfv * has completed. We read this twice because this reg has 1385169240Sjfv * some "sticky" (latched) bits. 1386169240Sjfv */ 1387185353Sjfv ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1388169240Sjfv if (ret_val) 1389238148Sjfv return ret_val; 1390185353Sjfv ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1391169240Sjfv if (ret_val) 1392238148Sjfv return ret_val; 1393169240Sjfv 1394169240Sjfv if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1395228386Sjfv DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); 1396238148Sjfv return ret_val; 1397169240Sjfv } 1398169240Sjfv 1399247064Sjfv /* The AutoNeg process has completed, so we now need to 1400169240Sjfv * read both the Auto Negotiation Advertisement 1401169240Sjfv * Register (Address 4) and the Auto_Negotiation Base 1402169240Sjfv * Page Ability Register (Address 5) to determine how 1403169240Sjfv * flow control was negotiated. 1404169240Sjfv */ 1405185353Sjfv ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1406228386Sjfv &mii_nway_adv_reg); 1407169240Sjfv if (ret_val) 1408238148Sjfv return ret_val; 1409185353Sjfv ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1410228386Sjfv &mii_nway_lp_ability_reg); 1411169240Sjfv if (ret_val) 1412238148Sjfv return ret_val; 1413169240Sjfv 1414247064Sjfv /* Two bits in the Auto Negotiation Advertisement Register 1415169240Sjfv * (Address 4) and two bits in the Auto Negotiation Base 1416169240Sjfv * Page Ability Register (Address 5) determine flow control 1417169240Sjfv * for both the PHY and the link partner. The following 1418169240Sjfv * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1419169240Sjfv * 1999, describes these PAUSE resolution bits and how flow 1420169240Sjfv * control is determined based upon these settings. 1421169240Sjfv * NOTE: DC = Don't Care 1422169240Sjfv * 1423169240Sjfv * LOCAL DEVICE | LINK PARTNER 1424169240Sjfv * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1425169240Sjfv *-------|---------|-------|---------|-------------------- 1426169240Sjfv * 0 | 0 | DC | DC | e1000_fc_none 1427169240Sjfv * 0 | 1 | 0 | DC | e1000_fc_none 1428169240Sjfv * 0 | 1 | 1 | 0 | e1000_fc_none 1429169240Sjfv * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1430169240Sjfv * 1 | 0 | 0 | DC | e1000_fc_none 1431169240Sjfv * 1 | DC | 1 | DC | e1000_fc_full 1432169240Sjfv * 1 | 1 | 0 | 0 | e1000_fc_none 1433169240Sjfv * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1434169240Sjfv * 1435173788Sjfv * Are both PAUSE bits set to 1? If so, this implies 1436169240Sjfv * Symmetric Flow Control is enabled at both ends. The 1437169240Sjfv * ASM_DIR bits are irrelevant per the spec. 1438169240Sjfv * 1439169240Sjfv * For Symmetric Flow Control: 1440169240Sjfv * 1441169240Sjfv * LOCAL DEVICE | LINK PARTNER 1442169240Sjfv * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1443169240Sjfv *-------|---------|-------|---------|-------------------- 1444169240Sjfv * 1 | DC | 1 | DC | E1000_fc_full 1445169240Sjfv * 1446169240Sjfv */ 1447169240Sjfv if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1448169240Sjfv (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1449247064Sjfv /* Now we need to check if the user selected Rx ONLY 1450169240Sjfv * of pause frames. In this case, we had to advertise 1451200243Sjfv * FULL flow control because we could not advertise Rx 1452169240Sjfv * ONLY. Hence, we must now check to see if we need to 1453228386Sjfv * turn OFF the TRANSMISSION of PAUSE frames. 1454169240Sjfv */ 1455185353Sjfv if (hw->fc.requested_mode == e1000_fc_full) { 1456185353Sjfv hw->fc.current_mode = e1000_fc_full; 1457228386Sjfv DEBUGOUT("Flow Control = FULL.\n"); 1458169240Sjfv } else { 1459185353Sjfv hw->fc.current_mode = e1000_fc_rx_pause; 1460228386Sjfv DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1461169240Sjfv } 1462169240Sjfv } 1463247064Sjfv /* For receiving PAUSE frames ONLY. 1464169240Sjfv * 1465169240Sjfv * LOCAL DEVICE | LINK PARTNER 1466169240Sjfv * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1467169240Sjfv *-------|---------|-------|---------|-------------------- 1468169240Sjfv * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1469169240Sjfv */ 1470169240Sjfv else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1471228386Sjfv (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1472228386Sjfv (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1473228386Sjfv (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1474185353Sjfv hw->fc.current_mode = e1000_fc_tx_pause; 1475228386Sjfv DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1476169240Sjfv } 1477247064Sjfv /* For transmitting PAUSE frames ONLY. 1478169240Sjfv * 1479169240Sjfv * LOCAL DEVICE | LINK PARTNER 1480169240Sjfv * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1481169240Sjfv *-------|---------|-------|---------|-------------------- 1482169240Sjfv * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1483169240Sjfv */ 1484169240Sjfv else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1485228386Sjfv (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1486228386Sjfv !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1487228386Sjfv (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1488185353Sjfv hw->fc.current_mode = e1000_fc_rx_pause; 1489228386Sjfv DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1490173788Sjfv } else { 1491247064Sjfv /* Per the IEEE spec, at this point flow control 1492173788Sjfv * should be disabled. 1493173788Sjfv */ 1494185353Sjfv hw->fc.current_mode = e1000_fc_none; 1495228386Sjfv DEBUGOUT("Flow Control = NONE.\n"); 1496169240Sjfv } 1497169240Sjfv 1498247064Sjfv /* Now we need to do one last check... If we auto- 1499169240Sjfv * negotiated to HALF DUPLEX, flow control should not be 1500169240Sjfv * enabled per IEEE 802.3 spec. 1501169240Sjfv */ 1502177867Sjfv ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1503169240Sjfv if (ret_val) { 1504169240Sjfv DEBUGOUT("Error getting link speed and duplex\n"); 1505238148Sjfv return ret_val; 1506169240Sjfv } 1507169240Sjfv 1508169240Sjfv if (duplex == HALF_DUPLEX) 1509185353Sjfv hw->fc.current_mode = e1000_fc_none; 1510169240Sjfv 1511247064Sjfv /* Now we call a subroutine to actually force the MAC 1512169240Sjfv * controller to use the correct flow control settings. 1513169240Sjfv */ 1514169240Sjfv ret_val = e1000_force_mac_fc_generic(hw); 1515169240Sjfv if (ret_val) { 1516169240Sjfv DEBUGOUT("Error forcing flow control settings\n"); 1517238148Sjfv return ret_val; 1518169240Sjfv } 1519169240Sjfv } 1520169240Sjfv 1521247064Sjfv /* Check for the case where we have SerDes media and auto-neg is 1522247064Sjfv * enabled. In this case, we need to check and see if Auto-Neg 1523247064Sjfv * has completed, and if so, how the PHY and link partner has 1524247064Sjfv * flow control configured. 1525247064Sjfv */ 1526247064Sjfv if ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1527247064Sjfv mac->autoneg) { 1528247064Sjfv /* Read the PCS_LSTS and check to see if AutoNeg 1529247064Sjfv * has completed. 1530247064Sjfv */ 1531247064Sjfv pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT); 1532247064Sjfv 1533247064Sjfv if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) { 1534247064Sjfv DEBUGOUT("PCS Auto Neg has not completed.\n"); 1535247064Sjfv return ret_val; 1536247064Sjfv } 1537247064Sjfv 1538247064Sjfv /* The AutoNeg process has completed, so we now need to 1539247064Sjfv * read both the Auto Negotiation Advertisement 1540247064Sjfv * Register (PCS_ANADV) and the Auto_Negotiation Base 1541247064Sjfv * Page Ability Register (PCS_LPAB) to determine how 1542247064Sjfv * flow control was negotiated. 1543247064Sjfv */ 1544247064Sjfv pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); 1545247064Sjfv pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB); 1546247064Sjfv 1547247064Sjfv /* Two bits in the Auto Negotiation Advertisement Register 1548247064Sjfv * (PCS_ANADV) and two bits in the Auto Negotiation Base 1549247064Sjfv * Page Ability Register (PCS_LPAB) determine flow control 1550247064Sjfv * for both the PHY and the link partner. The following 1551247064Sjfv * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1552247064Sjfv * 1999, describes these PAUSE resolution bits and how flow 1553247064Sjfv * control is determined based upon these settings. 1554247064Sjfv * NOTE: DC = Don't Care 1555247064Sjfv * 1556247064Sjfv * LOCAL DEVICE | LINK PARTNER 1557247064Sjfv * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1558247064Sjfv *-------|---------|-------|---------|-------------------- 1559247064Sjfv * 0 | 0 | DC | DC | e1000_fc_none 1560247064Sjfv * 0 | 1 | 0 | DC | e1000_fc_none 1561247064Sjfv * 0 | 1 | 1 | 0 | e1000_fc_none 1562247064Sjfv * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1563247064Sjfv * 1 | 0 | 0 | DC | e1000_fc_none 1564247064Sjfv * 1 | DC | 1 | DC | e1000_fc_full 1565247064Sjfv * 1 | 1 | 0 | 0 | e1000_fc_none 1566247064Sjfv * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1567247064Sjfv * 1568247064Sjfv * Are both PAUSE bits set to 1? If so, this implies 1569247064Sjfv * Symmetric Flow Control is enabled at both ends. The 1570247064Sjfv * ASM_DIR bits are irrelevant per the spec. 1571247064Sjfv * 1572247064Sjfv * For Symmetric Flow Control: 1573247064Sjfv * 1574247064Sjfv * LOCAL DEVICE | LINK PARTNER 1575247064Sjfv * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1576247064Sjfv *-------|---------|-------|---------|-------------------- 1577247064Sjfv * 1 | DC | 1 | DC | e1000_fc_full 1578247064Sjfv * 1579247064Sjfv */ 1580247064Sjfv if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1581247064Sjfv (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) { 1582247064Sjfv /* Now we need to check if the user selected Rx ONLY 1583247064Sjfv * of pause frames. In this case, we had to advertise 1584247064Sjfv * FULL flow control because we could not advertise Rx 1585247064Sjfv * ONLY. Hence, we must now check to see if we need to 1586247064Sjfv * turn OFF the TRANSMISSION of PAUSE frames. 1587247064Sjfv */ 1588247064Sjfv if (hw->fc.requested_mode == e1000_fc_full) { 1589247064Sjfv hw->fc.current_mode = e1000_fc_full; 1590247064Sjfv DEBUGOUT("Flow Control = FULL.\n"); 1591247064Sjfv } else { 1592247064Sjfv hw->fc.current_mode = e1000_fc_rx_pause; 1593247064Sjfv DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1594247064Sjfv } 1595247064Sjfv } 1596247064Sjfv /* For receiving PAUSE frames ONLY. 1597247064Sjfv * 1598247064Sjfv * LOCAL DEVICE | LINK PARTNER 1599247064Sjfv * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1600247064Sjfv *-------|---------|-------|---------|-------------------- 1601247064Sjfv * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1602247064Sjfv */ 1603247064Sjfv else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) && 1604247064Sjfv (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1605247064Sjfv (pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1606247064Sjfv (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1607247064Sjfv hw->fc.current_mode = e1000_fc_tx_pause; 1608247064Sjfv DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1609247064Sjfv } 1610247064Sjfv /* For transmitting PAUSE frames ONLY. 1611247064Sjfv * 1612247064Sjfv * LOCAL DEVICE | LINK PARTNER 1613247064Sjfv * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1614247064Sjfv *-------|---------|-------|---------|-------------------- 1615247064Sjfv * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1616247064Sjfv */ 1617247064Sjfv else if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1618247064Sjfv (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1619247064Sjfv !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1620247064Sjfv (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1621247064Sjfv hw->fc.current_mode = e1000_fc_rx_pause; 1622247064Sjfv DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1623247064Sjfv } else { 1624247064Sjfv /* Per the IEEE spec, at this point flow control 1625247064Sjfv * should be disabled. 1626247064Sjfv */ 1627247064Sjfv hw->fc.current_mode = e1000_fc_none; 1628247064Sjfv DEBUGOUT("Flow Control = NONE.\n"); 1629247064Sjfv } 1630247064Sjfv 1631247064Sjfv /* Now we call a subroutine to actually force the MAC 1632247064Sjfv * controller to use the correct flow control settings. 1633247064Sjfv */ 1634247064Sjfv pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1635247064Sjfv pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1636247064Sjfv E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg); 1637247064Sjfv 1638247064Sjfv ret_val = e1000_force_mac_fc_generic(hw); 1639247064Sjfv if (ret_val) { 1640247064Sjfv DEBUGOUT("Error forcing flow control settings\n"); 1641247064Sjfv return ret_val; 1642247064Sjfv } 1643247064Sjfv } 1644247064Sjfv 1645238148Sjfv return E1000_SUCCESS; 1646169240Sjfv} 1647169240Sjfv 1648169240Sjfv/** 1649176667Sjfv * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1650169589Sjfv * @hw: pointer to the HW structure 1651169589Sjfv * @speed: stores the current speed 1652169589Sjfv * @duplex: stores the current duplex 1653169240Sjfv * 1654169240Sjfv * Read the status register for the current speed/duplex and store the current 1655169240Sjfv * speed and duplex for copper connections. 1656169240Sjfv **/ 1657173788Sjfvs32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1658228386Sjfv u16 *duplex) 1659169240Sjfv{ 1660169240Sjfv u32 status; 1661169240Sjfv 1662169240Sjfv DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1663169240Sjfv 1664169240Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 1665169240Sjfv if (status & E1000_STATUS_SPEED_1000) { 1666169240Sjfv *speed = SPEED_1000; 1667169240Sjfv DEBUGOUT("1000 Mbs, "); 1668169240Sjfv } else if (status & E1000_STATUS_SPEED_100) { 1669169240Sjfv *speed = SPEED_100; 1670169240Sjfv DEBUGOUT("100 Mbs, "); 1671169240Sjfv } else { 1672169240Sjfv *speed = SPEED_10; 1673169240Sjfv DEBUGOUT("10 Mbs, "); 1674169240Sjfv } 1675169240Sjfv 1676169240Sjfv if (status & E1000_STATUS_FD) { 1677169240Sjfv *duplex = FULL_DUPLEX; 1678169240Sjfv DEBUGOUT("Full Duplex\n"); 1679169240Sjfv } else { 1680169240Sjfv *duplex = HALF_DUPLEX; 1681169240Sjfv DEBUGOUT("Half Duplex\n"); 1682169240Sjfv } 1683169240Sjfv 1684169240Sjfv return E1000_SUCCESS; 1685169240Sjfv} 1686169240Sjfv 1687169240Sjfv/** 1688176667Sjfv * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1689169589Sjfv * @hw: pointer to the HW structure 1690169589Sjfv * @speed: stores the current speed 1691169589Sjfv * @duplex: stores the current duplex 1692169240Sjfv * 1693169240Sjfv * Sets the speed and duplex to gigabit full duplex (the only possible option) 1694169240Sjfv * for fiber/serdes links. 1695169240Sjfv **/ 1696256200Sjfvs32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw, 1697228386Sjfv u16 *speed, u16 *duplex) 1698169240Sjfv{ 1699169240Sjfv DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1700169240Sjfv 1701169240Sjfv *speed = SPEED_1000; 1702169240Sjfv *duplex = FULL_DUPLEX; 1703169240Sjfv 1704169240Sjfv return E1000_SUCCESS; 1705169240Sjfv} 1706169240Sjfv 1707169240Sjfv/** 1708169240Sjfv * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1709169589Sjfv * @hw: pointer to the HW structure 1710169240Sjfv * 1711169589Sjfv * Acquire the HW semaphore to access the PHY or NVM 1712169240Sjfv **/ 1713173788Sjfvs32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1714169240Sjfv{ 1715169240Sjfv u32 swsm; 1716169240Sjfv s32 timeout = hw->nvm.word_size + 1; 1717169240Sjfv s32 i = 0; 1718169240Sjfv 1719169240Sjfv DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1720169240Sjfv 1721169589Sjfv /* Get the SW semaphore */ 1722169589Sjfv while (i < timeout) { 1723169589Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 1724169589Sjfv if (!(swsm & E1000_SWSM_SMBI)) 1725169589Sjfv break; 1726169589Sjfv 1727169589Sjfv usec_delay(50); 1728169589Sjfv i++; 1729169589Sjfv } 1730169589Sjfv 1731169589Sjfv if (i == timeout) { 1732169589Sjfv DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1733238148Sjfv return -E1000_ERR_NVM; 1734169589Sjfv } 1735169589Sjfv 1736169240Sjfv /* Get the FW semaphore. */ 1737169240Sjfv for (i = 0; i < timeout; i++) { 1738169240Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 1739169240Sjfv E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1740169240Sjfv 1741169240Sjfv /* Semaphore acquired if bit latched */ 1742169240Sjfv if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1743169240Sjfv break; 1744169240Sjfv 1745169240Sjfv usec_delay(50); 1746169240Sjfv } 1747169240Sjfv 1748169240Sjfv if (i == timeout) { 1749169240Sjfv /* Release semaphores */ 1750169240Sjfv e1000_put_hw_semaphore_generic(hw); 1751169240Sjfv DEBUGOUT("Driver can't access the NVM\n"); 1752238148Sjfv return -E1000_ERR_NVM; 1753169240Sjfv } 1754169240Sjfv 1755238148Sjfv return E1000_SUCCESS; 1756169240Sjfv} 1757169240Sjfv 1758169240Sjfv/** 1759169240Sjfv * e1000_put_hw_semaphore_generic - Release hardware semaphore 1760169589Sjfv * @hw: pointer to the HW structure 1761169240Sjfv * 1762169589Sjfv * Release hardware semaphore used to access the PHY or NVM 1763169240Sjfv **/ 1764173788Sjfvvoid e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1765169240Sjfv{ 1766169240Sjfv u32 swsm; 1767169240Sjfv 1768169240Sjfv DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1769169240Sjfv 1770169240Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 1771169240Sjfv 1772169589Sjfv swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1773169240Sjfv 1774169240Sjfv E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1775169240Sjfv} 1776169240Sjfv 1777169240Sjfv/** 1778169240Sjfv * e1000_get_auto_rd_done_generic - Check for auto read completion 1779169589Sjfv * @hw: pointer to the HW structure 1780169240Sjfv * 1781169240Sjfv * Check EEPROM for Auto Read done bit. 1782169240Sjfv **/ 1783173788Sjfvs32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1784169240Sjfv{ 1785169240Sjfv s32 i = 0; 1786169240Sjfv 1787169240Sjfv DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1788169240Sjfv 1789169240Sjfv while (i < AUTO_READ_DONE_TIMEOUT) { 1790169240Sjfv if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1791169240Sjfv break; 1792169240Sjfv msec_delay(1); 1793169240Sjfv i++; 1794169240Sjfv } 1795169240Sjfv 1796169240Sjfv if (i == AUTO_READ_DONE_TIMEOUT) { 1797169240Sjfv DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1798238148Sjfv return -E1000_ERR_RESET; 1799169240Sjfv } 1800169240Sjfv 1801238148Sjfv return E1000_SUCCESS; 1802169240Sjfv} 1803169240Sjfv 1804169240Sjfv/** 1805169240Sjfv * e1000_valid_led_default_generic - Verify a valid default LED config 1806169589Sjfv * @hw: pointer to the HW structure 1807169589Sjfv * @data: pointer to the NVM (EEPROM) 1808169240Sjfv * 1809169240Sjfv * Read the EEPROM for the current default LED configuration. If the 1810169240Sjfv * LED configuration is not valid, set to a valid LED configuration. 1811169240Sjfv **/ 1812173788Sjfvs32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1813169240Sjfv{ 1814169240Sjfv s32 ret_val; 1815169240Sjfv 1816169240Sjfv DEBUGFUNC("e1000_valid_led_default_generic"); 1817169240Sjfv 1818177867Sjfv ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1819169240Sjfv if (ret_val) { 1820169240Sjfv DEBUGOUT("NVM Read Error\n"); 1821238148Sjfv return ret_val; 1822169240Sjfv } 1823169240Sjfv 1824169240Sjfv if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1825169240Sjfv *data = ID_LED_DEFAULT; 1826169240Sjfv 1827238148Sjfv return E1000_SUCCESS; 1828169240Sjfv} 1829169240Sjfv 1830169240Sjfv/** 1831169240Sjfv * e1000_id_led_init_generic - 1832169589Sjfv * @hw: pointer to the HW structure 1833169240Sjfv * 1834169240Sjfv **/ 1835185353Sjfvs32 e1000_id_led_init_generic(struct e1000_hw *hw) 1836169240Sjfv{ 1837169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1838169240Sjfv s32 ret_val; 1839169240Sjfv const u32 ledctl_mask = 0x000000FF; 1840169240Sjfv const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1841169240Sjfv const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1842169240Sjfv u16 data, i, temp; 1843169240Sjfv const u16 led_mask = 0x0F; 1844169240Sjfv 1845169240Sjfv DEBUGFUNC("e1000_id_led_init_generic"); 1846169240Sjfv 1847177867Sjfv ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1848169240Sjfv if (ret_val) 1849238148Sjfv return ret_val; 1850169240Sjfv 1851169240Sjfv mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1852169240Sjfv mac->ledctl_mode1 = mac->ledctl_default; 1853169240Sjfv mac->ledctl_mode2 = mac->ledctl_default; 1854169240Sjfv 1855169240Sjfv for (i = 0; i < 4; i++) { 1856169240Sjfv temp = (data >> (i << 2)) & led_mask; 1857169240Sjfv switch (temp) { 1858169240Sjfv case ID_LED_ON1_DEF2: 1859169240Sjfv case ID_LED_ON1_ON2: 1860169240Sjfv case ID_LED_ON1_OFF2: 1861169240Sjfv mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1862169240Sjfv mac->ledctl_mode1 |= ledctl_on << (i << 3); 1863169240Sjfv break; 1864169240Sjfv case ID_LED_OFF1_DEF2: 1865169240Sjfv case ID_LED_OFF1_ON2: 1866169240Sjfv case ID_LED_OFF1_OFF2: 1867169240Sjfv mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1868169240Sjfv mac->ledctl_mode1 |= ledctl_off << (i << 3); 1869169240Sjfv break; 1870169240Sjfv default: 1871169240Sjfv /* Do nothing */ 1872169240Sjfv break; 1873169240Sjfv } 1874169240Sjfv switch (temp) { 1875169240Sjfv case ID_LED_DEF1_ON2: 1876169240Sjfv case ID_LED_ON1_ON2: 1877169240Sjfv case ID_LED_OFF1_ON2: 1878169240Sjfv mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1879169240Sjfv mac->ledctl_mode2 |= ledctl_on << (i << 3); 1880169240Sjfv break; 1881169240Sjfv case ID_LED_DEF1_OFF2: 1882169240Sjfv case ID_LED_ON1_OFF2: 1883169240Sjfv case ID_LED_OFF1_OFF2: 1884169240Sjfv mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1885169240Sjfv mac->ledctl_mode2 |= ledctl_off << (i << 3); 1886169240Sjfv break; 1887169240Sjfv default: 1888169240Sjfv /* Do nothing */ 1889169240Sjfv break; 1890169240Sjfv } 1891169240Sjfv } 1892169240Sjfv 1893238148Sjfv return E1000_SUCCESS; 1894169240Sjfv} 1895169240Sjfv 1896169240Sjfv/** 1897169240Sjfv * e1000_setup_led_generic - Configures SW controllable LED 1898169589Sjfv * @hw: pointer to the HW structure 1899169240Sjfv * 1900169240Sjfv * This prepares the SW controllable LED for use and saves the current state 1901169240Sjfv * of the LED so it can be later restored. 1902169240Sjfv **/ 1903173788Sjfvs32 e1000_setup_led_generic(struct e1000_hw *hw) 1904169240Sjfv{ 1905169240Sjfv u32 ledctl; 1906169240Sjfv 1907169240Sjfv DEBUGFUNC("e1000_setup_led_generic"); 1908169240Sjfv 1909238148Sjfv if (hw->mac.ops.setup_led != e1000_setup_led_generic) 1910238148Sjfv return -E1000_ERR_CONFIG; 1911169240Sjfv 1912173788Sjfv if (hw->phy.media_type == e1000_media_type_fiber) { 1913169240Sjfv ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1914169240Sjfv hw->mac.ledctl_default = ledctl; 1915169240Sjfv /* Turn off LED0 */ 1916228386Sjfv ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | 1917228386Sjfv E1000_LEDCTL_LED0_MODE_MASK); 1918169240Sjfv ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1919228386Sjfv E1000_LEDCTL_LED0_MODE_SHIFT); 1920169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1921173788Sjfv } else if (hw->phy.media_type == e1000_media_type_copper) { 1922169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1923169240Sjfv } 1924169240Sjfv 1925238148Sjfv return E1000_SUCCESS; 1926169240Sjfv} 1927169240Sjfv 1928169240Sjfv/** 1929169240Sjfv * e1000_cleanup_led_generic - Set LED config to default operation 1930169589Sjfv * @hw: pointer to the HW structure 1931169240Sjfv * 1932169240Sjfv * Remove the current LED configuration and set the LED configuration 1933169240Sjfv * to the default value, saved from the EEPROM. 1934169240Sjfv **/ 1935173788Sjfvs32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1936169240Sjfv{ 1937169240Sjfv DEBUGFUNC("e1000_cleanup_led_generic"); 1938169240Sjfv 1939169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1940203049Sjfv return E1000_SUCCESS; 1941169240Sjfv} 1942169240Sjfv 1943169240Sjfv/** 1944169240Sjfv * e1000_blink_led_generic - Blink LED 1945169589Sjfv * @hw: pointer to the HW structure 1946169240Sjfv * 1947176667Sjfv * Blink the LEDs which are set to be on. 1948169240Sjfv **/ 1949173788Sjfvs32 e1000_blink_led_generic(struct e1000_hw *hw) 1950169240Sjfv{ 1951169240Sjfv u32 ledctl_blink = 0; 1952169240Sjfv u32 i; 1953169240Sjfv 1954169240Sjfv DEBUGFUNC("e1000_blink_led_generic"); 1955169240Sjfv 1956173788Sjfv if (hw->phy.media_type == e1000_media_type_fiber) { 1957169240Sjfv /* always blink LED0 for PCI-E fiber */ 1958169240Sjfv ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1959169240Sjfv (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1960169240Sjfv } else { 1961247064Sjfv /* Set the blink bit for each LED that's "on" (0x0E) 1962247064Sjfv * (or "off" if inverted) in ledctl_mode2. The blink 1963247064Sjfv * logic in hardware only works when mode is set to "on" 1964247064Sjfv * so it must be changed accordingly when the mode is 1965247064Sjfv * "off" and inverted. 1966173788Sjfv */ 1967169240Sjfv ledctl_blink = hw->mac.ledctl_mode2; 1968247064Sjfv for (i = 0; i < 32; i += 8) { 1969247064Sjfv u32 mode = (hw->mac.ledctl_mode2 >> i) & 1970247064Sjfv E1000_LEDCTL_LED0_MODE_MASK; 1971247064Sjfv u32 led_default = hw->mac.ledctl_default >> i; 1972247064Sjfv 1973247064Sjfv if ((!(led_default & E1000_LEDCTL_LED0_IVRT) && 1974247064Sjfv (mode == E1000_LEDCTL_MODE_LED_ON)) || 1975247064Sjfv ((led_default & E1000_LEDCTL_LED0_IVRT) && 1976247064Sjfv (mode == E1000_LEDCTL_MODE_LED_OFF))) { 1977247064Sjfv ledctl_blink &= 1978247064Sjfv ~(E1000_LEDCTL_LED0_MODE_MASK << i); 1979247064Sjfv ledctl_blink |= (E1000_LEDCTL_LED0_BLINK | 1980247064Sjfv E1000_LEDCTL_MODE_LED_ON) << i; 1981247064Sjfv } 1982247064Sjfv } 1983169240Sjfv } 1984169240Sjfv 1985169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1986169240Sjfv 1987169240Sjfv return E1000_SUCCESS; 1988169240Sjfv} 1989169240Sjfv 1990169240Sjfv/** 1991169240Sjfv * e1000_led_on_generic - Turn LED on 1992169589Sjfv * @hw: pointer to the HW structure 1993169240Sjfv * 1994169240Sjfv * Turn LED on. 1995169240Sjfv **/ 1996173788Sjfvs32 e1000_led_on_generic(struct e1000_hw *hw) 1997169240Sjfv{ 1998169240Sjfv u32 ctrl; 1999169240Sjfv 2000169240Sjfv DEBUGFUNC("e1000_led_on_generic"); 2001169240Sjfv 2002173788Sjfv switch (hw->phy.media_type) { 2003169240Sjfv case e1000_media_type_fiber: 2004169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 2005169240Sjfv ctrl &= ~E1000_CTRL_SWDPIN0; 2006169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 2007169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2008169240Sjfv break; 2009169240Sjfv case e1000_media_type_copper: 2010169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 2011169240Sjfv break; 2012169240Sjfv default: 2013169240Sjfv break; 2014169240Sjfv } 2015169240Sjfv 2016169240Sjfv return E1000_SUCCESS; 2017169240Sjfv} 2018169240Sjfv 2019169240Sjfv/** 2020169240Sjfv * e1000_led_off_generic - Turn LED off 2021169589Sjfv * @hw: pointer to the HW structure 2022169240Sjfv * 2023169240Sjfv * Turn LED off. 2024169240Sjfv **/ 2025173788Sjfvs32 e1000_led_off_generic(struct e1000_hw *hw) 2026169240Sjfv{ 2027169240Sjfv u32 ctrl; 2028169240Sjfv 2029169240Sjfv DEBUGFUNC("e1000_led_off_generic"); 2030169240Sjfv 2031173788Sjfv switch (hw->phy.media_type) { 2032169240Sjfv case e1000_media_type_fiber: 2033169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 2034169240Sjfv ctrl |= E1000_CTRL_SWDPIN0; 2035169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 2036169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2037169240Sjfv break; 2038169240Sjfv case e1000_media_type_copper: 2039169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 2040169240Sjfv break; 2041169240Sjfv default: 2042169240Sjfv break; 2043169240Sjfv } 2044169240Sjfv 2045169240Sjfv return E1000_SUCCESS; 2046169240Sjfv} 2047169240Sjfv 2048169240Sjfv/** 2049169240Sjfv * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 2050169589Sjfv * @hw: pointer to the HW structure 2051169589Sjfv * @no_snoop: bitmap of snoop events 2052169240Sjfv * 2053169240Sjfv * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 2054169240Sjfv **/ 2055173788Sjfvvoid e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 2056169240Sjfv{ 2057169240Sjfv u32 gcr; 2058169240Sjfv 2059169240Sjfv DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 2060169240Sjfv 2061169240Sjfv if (hw->bus.type != e1000_bus_type_pci_express) 2062238148Sjfv return; 2063169240Sjfv 2064169240Sjfv if (no_snoop) { 2065169240Sjfv gcr = E1000_READ_REG(hw, E1000_GCR); 2066169240Sjfv gcr &= ~(PCIE_NO_SNOOP_ALL); 2067169240Sjfv gcr |= no_snoop; 2068169240Sjfv E1000_WRITE_REG(hw, E1000_GCR, gcr); 2069169240Sjfv } 2070169240Sjfv} 2071169240Sjfv 2072169240Sjfv/** 2073169240Sjfv * e1000_disable_pcie_master_generic - Disables PCI-express master access 2074169589Sjfv * @hw: pointer to the HW structure 2075169240Sjfv * 2076200243Sjfv * Returns E1000_SUCCESS if successful, else returns -10 2077176667Sjfv * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 2078169240Sjfv * the master requests to be disabled. 2079169240Sjfv * 2080169240Sjfv * Disables PCI-Express master access and verifies there are no pending 2081169240Sjfv * requests. 2082169240Sjfv **/ 2083173788Sjfvs32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 2084169240Sjfv{ 2085169240Sjfv u32 ctrl; 2086169240Sjfv s32 timeout = MASTER_DISABLE_TIMEOUT; 2087169240Sjfv 2088169240Sjfv DEBUGFUNC("e1000_disable_pcie_master_generic"); 2089169240Sjfv 2090169240Sjfv if (hw->bus.type != e1000_bus_type_pci_express) 2091238148Sjfv return E1000_SUCCESS; 2092169240Sjfv 2093169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 2094169240Sjfv ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2095169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2096169240Sjfv 2097169240Sjfv while (timeout) { 2098169240Sjfv if (!(E1000_READ_REG(hw, E1000_STATUS) & 2099169240Sjfv E1000_STATUS_GIO_MASTER_ENABLE)) 2100169240Sjfv break; 2101169240Sjfv usec_delay(100); 2102169240Sjfv timeout--; 2103169240Sjfv } 2104169240Sjfv 2105169240Sjfv if (!timeout) { 2106169240Sjfv DEBUGOUT("Master requests are pending.\n"); 2107238148Sjfv return -E1000_ERR_MASTER_REQUESTS_PENDING; 2108169240Sjfv } 2109169240Sjfv 2110238148Sjfv return E1000_SUCCESS; 2111169240Sjfv} 2112169240Sjfv 2113169240Sjfv/** 2114169240Sjfv * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2115169589Sjfv * @hw: pointer to the HW structure 2116169240Sjfv * 2117169240Sjfv * Reset the Adaptive Interframe Spacing throttle to default values. 2118169240Sjfv **/ 2119173788Sjfvvoid e1000_reset_adaptive_generic(struct e1000_hw *hw) 2120169240Sjfv{ 2121169240Sjfv struct e1000_mac_info *mac = &hw->mac; 2122169240Sjfv 2123169240Sjfv DEBUGFUNC("e1000_reset_adaptive_generic"); 2124169240Sjfv 2125169240Sjfv if (!mac->adaptive_ifs) { 2126169240Sjfv DEBUGOUT("Not in Adaptive IFS mode!\n"); 2127238148Sjfv return; 2128169240Sjfv } 2129169240Sjfv 2130185353Sjfv mac->current_ifs_val = 0; 2131185353Sjfv mac->ifs_min_val = IFS_MIN; 2132185353Sjfv mac->ifs_max_val = IFS_MAX; 2133185353Sjfv mac->ifs_step_size = IFS_STEP; 2134185353Sjfv mac->ifs_ratio = IFS_RATIO; 2135169240Sjfv 2136169240Sjfv mac->in_ifs_mode = FALSE; 2137169240Sjfv E1000_WRITE_REG(hw, E1000_AIT, 0); 2138169240Sjfv} 2139169240Sjfv 2140169240Sjfv/** 2141169240Sjfv * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2142169589Sjfv * @hw: pointer to the HW structure 2143169240Sjfv * 2144169240Sjfv * Update the Adaptive Interframe Spacing Throttle value based on the 2145169240Sjfv * time between transmitted packets and time between collisions. 2146169240Sjfv **/ 2147173788Sjfvvoid e1000_update_adaptive_generic(struct e1000_hw *hw) 2148169240Sjfv{ 2149169240Sjfv struct e1000_mac_info *mac = &hw->mac; 2150169240Sjfv 2151169240Sjfv DEBUGFUNC("e1000_update_adaptive_generic"); 2152169240Sjfv 2153169240Sjfv if (!mac->adaptive_ifs) { 2154169240Sjfv DEBUGOUT("Not in Adaptive IFS mode!\n"); 2155238148Sjfv return; 2156169240Sjfv } 2157169240Sjfv 2158169240Sjfv if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2159169240Sjfv if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2160169240Sjfv mac->in_ifs_mode = TRUE; 2161169240Sjfv if (mac->current_ifs_val < mac->ifs_max_val) { 2162169240Sjfv if (!mac->current_ifs_val) 2163169240Sjfv mac->current_ifs_val = mac->ifs_min_val; 2164169240Sjfv else 2165169240Sjfv mac->current_ifs_val += 2166169240Sjfv mac->ifs_step_size; 2167228386Sjfv E1000_WRITE_REG(hw, E1000_AIT, 2168228386Sjfv mac->current_ifs_val); 2169169240Sjfv } 2170169240Sjfv } 2171169240Sjfv } else { 2172169240Sjfv if (mac->in_ifs_mode && 2173169240Sjfv (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2174169240Sjfv mac->current_ifs_val = 0; 2175169240Sjfv mac->in_ifs_mode = FALSE; 2176169240Sjfv E1000_WRITE_REG(hw, E1000_AIT, 0); 2177169240Sjfv } 2178169240Sjfv } 2179169240Sjfv} 2180169240Sjfv 2181169240Sjfv/** 2182169240Sjfv * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2183169589Sjfv * @hw: pointer to the HW structure 2184169240Sjfv * 2185176667Sjfv * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2186169240Sjfv * set, which is forced to MDI mode only. 2187169240Sjfv **/ 2188200243Sjfvstatic s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2189169240Sjfv{ 2190169240Sjfv DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2191169240Sjfv 2192169240Sjfv if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2193169240Sjfv DEBUGOUT("Invalid MDI setting detected\n"); 2194169240Sjfv hw->phy.mdix = 1; 2195238148Sjfv return -E1000_ERR_CONFIG; 2196169240Sjfv } 2197169240Sjfv 2198238148Sjfv return E1000_SUCCESS; 2199169240Sjfv} 2200169240Sjfv 2201169240Sjfv/** 2202247064Sjfv * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings 2203247064Sjfv * @hw: pointer to the HW structure 2204247064Sjfv * 2205247064Sjfv * Validate the MDI/MDIx setting, allowing for auto-crossover during forced 2206247064Sjfv * operation. 2207247064Sjfv **/ 2208256200Sjfvs32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw) 2209247064Sjfv{ 2210247064Sjfv DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic"); 2211247064Sjfv 2212247064Sjfv return E1000_SUCCESS; 2213247064Sjfv} 2214247064Sjfv 2215247064Sjfv/** 2216169240Sjfv * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2217169589Sjfv * @hw: pointer to the HW structure 2218169589Sjfv * @reg: 32bit register offset such as E1000_SCTL 2219169589Sjfv * @offset: register offset to write to 2220169589Sjfv * @data: data to write at register offset 2221169240Sjfv * 2222169240Sjfv * Writes an address/data control type register. There are several of these 2223169240Sjfv * and they all have the format address << 8 | data and bit 31 is polled for 2224169240Sjfv * completion. 2225169240Sjfv **/ 2226173788Sjfvs32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2227228386Sjfv u32 offset, u8 data) 2228169240Sjfv{ 2229169240Sjfv u32 i, regvalue = 0; 2230169240Sjfv 2231169240Sjfv DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2232169240Sjfv 2233169240Sjfv /* Set up the address and data */ 2234169240Sjfv regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2235169240Sjfv E1000_WRITE_REG(hw, reg, regvalue); 2236169240Sjfv 2237169240Sjfv /* Poll the ready bit to see if the MDI read completed */ 2238169240Sjfv for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2239169240Sjfv usec_delay(5); 2240169240Sjfv regvalue = E1000_READ_REG(hw, reg); 2241169240Sjfv if (regvalue & E1000_GEN_CTL_READY) 2242169240Sjfv break; 2243169240Sjfv } 2244169240Sjfv if (!(regvalue & E1000_GEN_CTL_READY)) { 2245169240Sjfv DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2246238148Sjfv return -E1000_ERR_PHY; 2247169240Sjfv } 2248169240Sjfv 2249238148Sjfv return E1000_SUCCESS; 2250169240Sjfv} 2251