e1000_mac.c revision 177867
1177867Sjfv/****************************************************************************** 2169240Sjfv 3176667Sjfv Copyright (c) 2001-2008, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD: head/sys/dev/em/e1000_mac.c 177867 2008-04-02 22:00:36Z jfv $*/ 34169240Sjfv 35169589Sjfv#include "e1000_api.h" 36169240Sjfv#include "e1000_mac.h" 37169240Sjfv 38169240Sjfv/** 39177867Sjfv * e1000_init_mac_ops_generic - Initialize MAC function pointers 40177867Sjfv * @hw: pointer to the HW structure 41177867Sjfv * 42177867Sjfv * Setups up the function pointers to no-op functions 43177867Sjfv **/ 44177867Sjfvvoid e1000_init_mac_ops_generic(struct e1000_hw *hw) 45177867Sjfv{ 46177867Sjfv struct e1000_mac_info *mac = &hw->mac; 47177867Sjfv DEBUGFUNC("e1000_init_mac_ops_generic"); 48177867Sjfv 49177867Sjfv /* General Setup */ 50177867Sjfv mac->ops.init_params = e1000_null_ops_generic; 51177867Sjfv mac->ops.init_hw = e1000_null_ops_generic; 52177867Sjfv mac->ops.reset_hw = e1000_null_ops_generic; 53177867Sjfv mac->ops.setup_physical_interface = e1000_null_ops_generic; 54177867Sjfv mac->ops.get_bus_info = e1000_null_ops_generic; 55177867Sjfv mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 56177867Sjfv mac->ops.remove_device = e1000_remove_device_generic; 57177867Sjfv mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 58177867Sjfv mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 59177867Sjfv /* LED */ 60177867Sjfv mac->ops.cleanup_led = e1000_null_ops_generic; 61177867Sjfv mac->ops.setup_led = e1000_null_ops_generic; 62177867Sjfv mac->ops.blink_led = e1000_null_ops_generic; 63177867Sjfv mac->ops.led_on = e1000_null_ops_generic; 64177867Sjfv mac->ops.led_off = e1000_null_ops_generic; 65177867Sjfv /* LINK */ 66177867Sjfv mac->ops.setup_link = e1000_null_ops_generic; 67177867Sjfv mac->ops.get_link_up_info = e1000_null_link_info; 68177867Sjfv mac->ops.check_for_link = e1000_null_ops_generic; 69177867Sjfv mac->ops.wait_autoneg = e1000_wait_autoneg_generic; 70177867Sjfv /* Management */ 71177867Sjfv mac->ops.check_mng_mode = e1000_null_mng_mode; 72177867Sjfv mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; 73177867Sjfv mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; 74177867Sjfv mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; 75177867Sjfv /* VLAN, MC, etc. */ 76177867Sjfv mac->ops.update_mc_addr_list = e1000_null_update_mc; 77177867Sjfv mac->ops.clear_vfta = e1000_null_mac_generic; 78177867Sjfv mac->ops.write_vfta = e1000_null_write_vfta; 79177867Sjfv mac->ops.mta_set = e1000_null_mta_set; 80177867Sjfv mac->ops.rar_set = e1000_rar_set_generic; 81177867Sjfv mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 82177867Sjfv} 83177867Sjfv 84177867Sjfv/** 85177867Sjfv * e1000_null_ops_generic - No-op function, returns 0 86177867Sjfv * @hw: pointer to the HW structure 87177867Sjfv **/ 88177867Sjfvs32 e1000_null_ops_generic(struct e1000_hw *hw) 89177867Sjfv{ 90177867Sjfv DEBUGFUNC("e1000_null_ops_generic"); 91177867Sjfv return E1000_SUCCESS; 92177867Sjfv} 93177867Sjfv 94177867Sjfv/** 95177867Sjfv * e1000_null_mac_generic - No-op function, return void 96177867Sjfv * @hw: pointer to the HW structure 97177867Sjfv **/ 98177867Sjfvvoid e1000_null_mac_generic(struct e1000_hw *hw) 99177867Sjfv{ 100177867Sjfv DEBUGFUNC("e1000_null_mac_generic"); 101177867Sjfv return; 102177867Sjfv} 103177867Sjfv 104177867Sjfv/** 105177867Sjfv * e1000_null_link_info - No-op function, return 0 106177867Sjfv * @hw: pointer to the HW structure 107177867Sjfv **/ 108177867Sjfvs32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) 109177867Sjfv{ 110177867Sjfv DEBUGFUNC("e1000_null_link_info"); 111177867Sjfv return E1000_SUCCESS; 112177867Sjfv} 113177867Sjfv 114177867Sjfv/** 115177867Sjfv * e1000_null_mng_mode - No-op function, return FALSE 116177867Sjfv * @hw: pointer to the HW structure 117177867Sjfv **/ 118177867Sjfvbool e1000_null_mng_mode(struct e1000_hw *hw) 119177867Sjfv{ 120177867Sjfv DEBUGFUNC("e1000_null_mng_mode"); 121177867Sjfv return FALSE; 122177867Sjfv} 123177867Sjfv 124177867Sjfv/** 125177867Sjfv * e1000_null_update_mc - No-op function, return void 126177867Sjfv * @hw: pointer to the HW structure 127177867Sjfv **/ 128177867Sjfvvoid e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a, u32 b, u32 c) 129177867Sjfv{ 130177867Sjfv DEBUGFUNC("e1000_null_update_mc"); 131177867Sjfv return; 132177867Sjfv} 133177867Sjfv 134177867Sjfv/** 135177867Sjfv * e1000_null_write_vfta - No-op function, return void 136177867Sjfv * @hw: pointer to the HW structure 137177867Sjfv **/ 138177867Sjfvvoid e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b) 139177867Sjfv{ 140177867Sjfv DEBUGFUNC("e1000_null_write_vfta"); 141177867Sjfv return; 142177867Sjfv} 143177867Sjfv 144177867Sjfv/** 145177867Sjfv * e1000_null_set_mta - No-op function, return void 146177867Sjfv * @hw: pointer to the HW structure 147177867Sjfv **/ 148177867Sjfvvoid e1000_null_mta_set(struct e1000_hw *hw, u32 a) 149177867Sjfv{ 150177867Sjfv DEBUGFUNC("e1000_null_mta_set"); 151177867Sjfv return; 152177867Sjfv} 153177867Sjfv 154177867Sjfv/** 155177867Sjfv * e1000_null_rar_set - No-op function, return void 156177867Sjfv * @hw: pointer to the HW structure 157177867Sjfv **/ 158177867Sjfvvoid e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a) 159177867Sjfv{ 160177867Sjfv DEBUGFUNC("e1000_null_rar_set"); 161177867Sjfv return; 162177867Sjfv} 163177867Sjfv 164177867Sjfv/** 165169240Sjfv * e1000_remove_device_generic - Free device specific structure 166169589Sjfv * @hw: pointer to the HW structure 167169240Sjfv * 168169240Sjfv * If a device specific structure was allocated, this function will 169169240Sjfv * free it. 170169240Sjfv **/ 171173788Sjfvvoid e1000_remove_device_generic(struct e1000_hw *hw) 172169240Sjfv{ 173169240Sjfv DEBUGFUNC("e1000_remove_device_generic"); 174169240Sjfv 175169240Sjfv /* Freeing the dev_spec member of e1000_hw structure */ 176169240Sjfv e1000_free_dev_spec_struct(hw); 177169240Sjfv} 178169240Sjfv 179169240Sjfv/** 180169240Sjfv * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 181169589Sjfv * @hw: pointer to the HW structure 182169240Sjfv * 183169240Sjfv * Determines and stores the system bus information for a particular 184169240Sjfv * network interface. The following bus information is determined and stored: 185169240Sjfv * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 186169240Sjfv **/ 187173788Sjfvs32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 188169240Sjfv{ 189169240Sjfv struct e1000_bus_info *bus = &hw->bus; 190169240Sjfv u32 status = E1000_READ_REG(hw, E1000_STATUS); 191169240Sjfv s32 ret_val = E1000_SUCCESS; 192169240Sjfv u16 pci_header_type; 193169240Sjfv 194169240Sjfv DEBUGFUNC("e1000_get_bus_info_pci_generic"); 195169240Sjfv 196169240Sjfv /* PCI or PCI-X? */ 197169240Sjfv bus->type = (status & E1000_STATUS_PCIX_MODE) 198169240Sjfv ? e1000_bus_type_pcix 199169240Sjfv : e1000_bus_type_pci; 200169240Sjfv 201169240Sjfv /* Bus speed */ 202169240Sjfv if (bus->type == e1000_bus_type_pci) { 203169240Sjfv bus->speed = (status & E1000_STATUS_PCI66) 204169240Sjfv ? e1000_bus_speed_66 205169240Sjfv : e1000_bus_speed_33; 206169240Sjfv } else { 207169240Sjfv switch (status & E1000_STATUS_PCIX_SPEED) { 208169240Sjfv case E1000_STATUS_PCIX_SPEED_66: 209169240Sjfv bus->speed = e1000_bus_speed_66; 210169240Sjfv break; 211169240Sjfv case E1000_STATUS_PCIX_SPEED_100: 212169240Sjfv bus->speed = e1000_bus_speed_100; 213169240Sjfv break; 214169240Sjfv case E1000_STATUS_PCIX_SPEED_133: 215169240Sjfv bus->speed = e1000_bus_speed_133; 216169240Sjfv break; 217169240Sjfv default: 218169240Sjfv bus->speed = e1000_bus_speed_reserved; 219169240Sjfv break; 220169240Sjfv } 221169240Sjfv } 222169240Sjfv 223169240Sjfv /* Bus width */ 224169240Sjfv bus->width = (status & E1000_STATUS_BUS64) 225169240Sjfv ? e1000_bus_width_64 226169240Sjfv : e1000_bus_width_32; 227169240Sjfv 228169240Sjfv /* Which PCI(-X) function? */ 229169240Sjfv e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 230169240Sjfv if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) 231169240Sjfv bus->func = (status & E1000_STATUS_FUNC_MASK) 232169240Sjfv >> E1000_STATUS_FUNC_SHIFT; 233169240Sjfv else 234169240Sjfv bus->func = 0; 235169240Sjfv 236169240Sjfv return ret_val; 237169240Sjfv} 238169240Sjfv 239169240Sjfv/** 240169240Sjfv * e1000_get_bus_info_pcie_generic - Get PCIe bus information 241169589Sjfv * @hw: pointer to the HW structure 242169240Sjfv * 243169240Sjfv * Determines and stores the system bus information for a particular 244169240Sjfv * network interface. The following bus information is determined and stored: 245169240Sjfv * bus speed, bus width, type (PCIe), and PCIe function. 246169240Sjfv **/ 247173788Sjfvs32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 248169240Sjfv{ 249169240Sjfv struct e1000_bus_info *bus = &hw->bus; 250169240Sjfv s32 ret_val; 251169240Sjfv u32 status; 252169240Sjfv u16 pcie_link_status, pci_header_type; 253169240Sjfv 254169240Sjfv DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 255169240Sjfv 256169240Sjfv bus->type = e1000_bus_type_pci_express; 257169240Sjfv bus->speed = e1000_bus_speed_2500; 258169240Sjfv 259169240Sjfv ret_val = e1000_read_pcie_cap_reg(hw, 260169240Sjfv PCIE_LINK_STATUS, 261169240Sjfv &pcie_link_status); 262169240Sjfv if (ret_val) 263169240Sjfv bus->width = e1000_bus_width_unknown; 264169240Sjfv else 265169240Sjfv bus->width = (e1000_bus_width)((pcie_link_status & 266169240Sjfv PCIE_LINK_WIDTH_MASK) >> 267169240Sjfv PCIE_LINK_WIDTH_SHIFT); 268169240Sjfv 269169240Sjfv e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 270169240Sjfv if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 271169240Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 272169240Sjfv bus->func = (status & E1000_STATUS_FUNC_MASK) 273169240Sjfv >> E1000_STATUS_FUNC_SHIFT; 274173788Sjfv } else { 275169240Sjfv bus->func = 0; 276173788Sjfv } 277169240Sjfv 278169240Sjfv return E1000_SUCCESS; 279169240Sjfv} 280169240Sjfv 281169240Sjfv/** 282169240Sjfv * e1000_clear_vfta_generic - Clear VLAN filter table 283169589Sjfv * @hw: pointer to the HW structure 284169240Sjfv * 285169240Sjfv * Clears the register array which contains the VLAN filter table by 286169240Sjfv * setting all the values to 0. 287169240Sjfv **/ 288173788Sjfvvoid e1000_clear_vfta_generic(struct e1000_hw *hw) 289169240Sjfv{ 290169240Sjfv u32 offset; 291169240Sjfv 292169240Sjfv DEBUGFUNC("e1000_clear_vfta_generic"); 293169240Sjfv 294169240Sjfv for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 295169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 296169240Sjfv E1000_WRITE_FLUSH(hw); 297169240Sjfv } 298169240Sjfv} 299169240Sjfv 300169240Sjfv/** 301169240Sjfv * e1000_write_vfta_generic - Write value to VLAN filter table 302169589Sjfv * @hw: pointer to the HW structure 303169589Sjfv * @offset: register offset in VLAN filter table 304169589Sjfv * @value: register value written to VLAN filter table 305169240Sjfv * 306169240Sjfv * Writes value at the given offset in the register array which stores 307169240Sjfv * the VLAN filter table. 308169240Sjfv **/ 309173788Sjfvvoid e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 310169240Sjfv{ 311169240Sjfv DEBUGFUNC("e1000_write_vfta_generic"); 312169240Sjfv 313169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 314169240Sjfv E1000_WRITE_FLUSH(hw); 315169240Sjfv} 316169240Sjfv 317169240Sjfv/** 318169240Sjfv * e1000_init_rx_addrs_generic - Initialize receive address's 319169589Sjfv * @hw: pointer to the HW structure 320169589Sjfv * @rar_count: receive address registers 321169240Sjfv * 322169240Sjfv * Setups the receive address registers by setting the base receive address 323169240Sjfv * register to the devices MAC address and clearing all the other receive 324169240Sjfv * address registers to 0. 325169240Sjfv **/ 326173788Sjfvvoid e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 327169240Sjfv{ 328169240Sjfv u32 i; 329169240Sjfv 330169240Sjfv DEBUGFUNC("e1000_init_rx_addrs_generic"); 331169240Sjfv 332169240Sjfv /* Setup the receive address */ 333169240Sjfv DEBUGOUT("Programming MAC Address into RAR[0]\n"); 334169240Sjfv 335177867Sjfv hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 336169240Sjfv 337169240Sjfv /* Zero out the other (rar_entry_count - 1) receive addresses */ 338169240Sjfv DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 339169240Sjfv for (i = 1; i < rar_count; i++) { 340169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0); 341169240Sjfv E1000_WRITE_FLUSH(hw); 342169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0); 343169240Sjfv E1000_WRITE_FLUSH(hw); 344169240Sjfv } 345169240Sjfv} 346169240Sjfv 347169240Sjfv/** 348173788Sjfv * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 349173788Sjfv * @hw: pointer to the HW structure 350173788Sjfv * 351173788Sjfv * Checks the nvm for an alternate MAC address. An alternate MAC address 352173788Sjfv * can be setup by pre-boot software and must be treated like a permanent 353173788Sjfv * address and must override the actual permanent MAC address. If an 354173788Sjfv * alternate MAC address is found it is saved in the hw struct and 355173788Sjfv * programmed into RAR0 and the function returns success, otherwise the 356173788Sjfv * function returns an error. 357173788Sjfv **/ 358173788Sjfvs32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 359173788Sjfv{ 360173788Sjfv u32 i; 361173788Sjfv s32 ret_val = E1000_SUCCESS; 362173788Sjfv u16 offset, nvm_alt_mac_addr_offset, nvm_data; 363173788Sjfv u8 alt_mac_addr[ETH_ADDR_LEN]; 364173788Sjfv 365173788Sjfv DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 366173788Sjfv 367177867Sjfv ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 368176667Sjfv &nvm_alt_mac_addr_offset); 369173788Sjfv if (ret_val) { 370173788Sjfv DEBUGOUT("NVM Read Error\n"); 371173788Sjfv goto out; 372173788Sjfv } 373173788Sjfv 374173788Sjfv if (nvm_alt_mac_addr_offset == 0xFFFF) { 375173788Sjfv ret_val = -(E1000_NOT_IMPLEMENTED); 376173788Sjfv goto out; 377173788Sjfv } 378173788Sjfv 379173788Sjfv if (hw->bus.func == E1000_FUNC_1) 380173788Sjfv nvm_alt_mac_addr_offset += ETH_ADDR_LEN/sizeof(u16); 381173788Sjfv 382173788Sjfv for (i = 0; i < ETH_ADDR_LEN; i += 2) { 383173788Sjfv offset = nvm_alt_mac_addr_offset + (i >> 1); 384177867Sjfv ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 385173788Sjfv if (ret_val) { 386173788Sjfv DEBUGOUT("NVM Read Error\n"); 387173788Sjfv goto out; 388173788Sjfv } 389173788Sjfv 390173788Sjfv alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 391173788Sjfv alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 392173788Sjfv } 393173788Sjfv 394173788Sjfv /* if multicast bit is set, the alternate address will not be used */ 395173788Sjfv if (alt_mac_addr[0] & 0x01) { 396173788Sjfv ret_val = -(E1000_NOT_IMPLEMENTED); 397173788Sjfv goto out; 398173788Sjfv } 399173788Sjfv 400173788Sjfv for (i = 0; i < ETH_ADDR_LEN; i++) 401173788Sjfv hw->mac.addr[i] = hw->mac.perm_addr[i] = alt_mac_addr[i]; 402173788Sjfv 403177867Sjfv hw->mac.ops.rar_set(hw, hw->mac.perm_addr, 0); 404173788Sjfv 405173788Sjfvout: 406173788Sjfv return ret_val; 407173788Sjfv} 408173788Sjfv 409173788Sjfv/** 410169240Sjfv * e1000_rar_set_generic - Set receive address register 411169589Sjfv * @hw: pointer to the HW structure 412169589Sjfv * @addr: pointer to the receive address 413169589Sjfv * @index: receive address array register 414169240Sjfv * 415169240Sjfv * Sets the receive address array register at index to the address passed 416169240Sjfv * in by addr. 417169240Sjfv **/ 418173788Sjfvvoid e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 419169240Sjfv{ 420169240Sjfv u32 rar_low, rar_high; 421169240Sjfv 422169240Sjfv DEBUGFUNC("e1000_rar_set_generic"); 423169240Sjfv 424173788Sjfv /* 425173788Sjfv * HW expects these in little endian so we reverse the byte order 426169240Sjfv * from network order (big endian) to little endian 427169240Sjfv */ 428169240Sjfv rar_low = ((u32) addr[0] | 429176667Sjfv ((u32) addr[1] << 8) | 430176667Sjfv ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 431169240Sjfv 432169240Sjfv rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 433169240Sjfv 434173788Sjfv /* If MAC address zero, no need to set the AV bit */ 435173788Sjfv if (rar_low || rar_high) { 436173788Sjfv if (!hw->mac.disable_av) 437173788Sjfv rar_high |= E1000_RAH_AV; 438173788Sjfv } 439169240Sjfv 440176667Sjfv E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 441176667Sjfv E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 442169240Sjfv} 443169240Sjfv 444169240Sjfv/** 445169240Sjfv * e1000_mta_set_generic - Set multicast filter table address 446169589Sjfv * @hw: pointer to the HW structure 447169589Sjfv * @hash_value: determines the MTA register and bit to set 448169240Sjfv * 449169240Sjfv * The multicast table address is a register array of 32-bit registers. 450169240Sjfv * The hash_value is used to determine what register the bit is in, the 451169240Sjfv * current value is read, the new bit is OR'd in and the new value is 452169240Sjfv * written back into the register. 453169240Sjfv **/ 454173788Sjfvvoid e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value) 455169240Sjfv{ 456169240Sjfv u32 hash_bit, hash_reg, mta; 457169240Sjfv 458169240Sjfv DEBUGFUNC("e1000_mta_set_generic"); 459173788Sjfv /* 460173788Sjfv * The MTA is a register array of 32-bit registers. It is 461169240Sjfv * treated like an array of (32*mta_reg_count) bits. We want to 462169240Sjfv * set bit BitArray[hash_value]. So we figure out what register 463169240Sjfv * the bit is in, read it, OR in the new bit, then write 464169240Sjfv * back the new value. The (hw->mac.mta_reg_count - 1) serves as a 465169240Sjfv * mask to bits 31:5 of the hash value which gives us the 466169240Sjfv * register we're modifying. The hash bit within that register 467169240Sjfv * is determined by the lower 5 bits of the hash value. 468169240Sjfv */ 469169240Sjfv hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 470169240Sjfv hash_bit = hash_value & 0x1F; 471169240Sjfv 472169240Sjfv mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 473169240Sjfv 474169240Sjfv mta |= (1 << hash_bit); 475169240Sjfv 476169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 477169240Sjfv E1000_WRITE_FLUSH(hw); 478169240Sjfv} 479169240Sjfv 480169240Sjfv/** 481173788Sjfv * e1000_update_mc_addr_list_generic - Update Multicast addresses 482169589Sjfv * @hw: pointer to the HW structure 483169589Sjfv * @mc_addr_list: array of multicast addresses to program 484169589Sjfv * @mc_addr_count: number of multicast addresses to program 485169589Sjfv * @rar_used_count: the first RAR register free to program 486169589Sjfv * @rar_count: total number of supported Receive Address Registers 487169240Sjfv * 488169240Sjfv * Updates the Receive Address Registers and Multicast Table Array. 489169240Sjfv * The caller must have a packed mc_addr_list of multicast addresses. 490169240Sjfv * The parameter rar_count will usually be hw->mac.rar_entry_count 491169240Sjfv * unless there are workarounds that change this. 492169240Sjfv **/ 493173788Sjfvvoid e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 494173788Sjfv u8 *mc_addr_list, u32 mc_addr_count, 495173788Sjfv u32 rar_used_count, u32 rar_count) 496169240Sjfv{ 497169240Sjfv u32 hash_value; 498169240Sjfv u32 i; 499169240Sjfv 500173788Sjfv DEBUGFUNC("e1000_update_mc_addr_list_generic"); 501169240Sjfv 502173788Sjfv /* 503173788Sjfv * Load the first set of multicast addresses into the exact 504169240Sjfv * filters (RAR). If there are not enough to fill the RAR 505169240Sjfv * array, clear the filters. 506169240Sjfv */ 507169240Sjfv for (i = rar_used_count; i < rar_count; i++) { 508169240Sjfv if (mc_addr_count) { 509177867Sjfv hw->mac.ops.rar_set(hw, mc_addr_list, i); 510169240Sjfv mc_addr_count--; 511169240Sjfv mc_addr_list += ETH_ADDR_LEN; 512169240Sjfv } else { 513169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0); 514169240Sjfv E1000_WRITE_FLUSH(hw); 515169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0); 516169240Sjfv E1000_WRITE_FLUSH(hw); 517169240Sjfv } 518169240Sjfv } 519169240Sjfv 520169240Sjfv /* Clear the old settings from the MTA */ 521169240Sjfv DEBUGOUT("Clearing MTA\n"); 522169240Sjfv for (i = 0; i < hw->mac.mta_reg_count; i++) { 523169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 524169240Sjfv E1000_WRITE_FLUSH(hw); 525169240Sjfv } 526169240Sjfv 527169240Sjfv /* Load any remaining multicast addresses into the hash table. */ 528169240Sjfv for (; mc_addr_count > 0; mc_addr_count--) { 529169240Sjfv hash_value = e1000_hash_mc_addr(hw, mc_addr_list); 530169240Sjfv DEBUGOUT1("Hash value = 0x%03X\n", hash_value); 531177867Sjfv hw->mac.ops.mta_set(hw, hash_value); 532169240Sjfv mc_addr_list += ETH_ADDR_LEN; 533169240Sjfv } 534169240Sjfv} 535169240Sjfv 536169240Sjfv/** 537169240Sjfv * e1000_hash_mc_addr_generic - Generate a multicast hash value 538169589Sjfv * @hw: pointer to the HW structure 539169589Sjfv * @mc_addr: pointer to a multicast address 540169240Sjfv * 541169240Sjfv * Generates a multicast address hash value which is used to determine 542169240Sjfv * the multicast filter table array address and new table value. See 543169240Sjfv * e1000_mta_set_generic() 544169240Sjfv **/ 545173788Sjfvu32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 546169240Sjfv{ 547169240Sjfv u32 hash_value, hash_mask; 548169240Sjfv u8 bit_shift = 0; 549169240Sjfv 550169240Sjfv DEBUGFUNC("e1000_hash_mc_addr_generic"); 551169240Sjfv 552169240Sjfv /* Register count multiplied by bits per register */ 553169240Sjfv hash_mask = (hw->mac.mta_reg_count * 32) - 1; 554169240Sjfv 555173788Sjfv /* 556173788Sjfv * For a mc_filter_type of 0, bit_shift is the number of left-shifts 557173788Sjfv * where 0xFF would still fall within the hash mask. 558173788Sjfv */ 559169240Sjfv while (hash_mask >> bit_shift != 0xFF) 560169240Sjfv bit_shift++; 561169240Sjfv 562173788Sjfv /* 563173788Sjfv * The portion of the address that is used for the hash table 564169240Sjfv * is determined by the mc_filter_type setting. 565169240Sjfv * The algorithm is such that there is a total of 8 bits of shifting. 566169240Sjfv * The bit_shift for a mc_filter_type of 0 represents the number of 567169240Sjfv * left-shifts where the MSB of mc_addr[5] would still fall within 568169240Sjfv * the hash_mask. Case 0 does this exactly. Since there are a total 569169240Sjfv * of 8 bits of shifting, then mc_addr[4] will shift right the 570169240Sjfv * remaining number of bits. Thus 8 - bit_shift. The rest of the 571169240Sjfv * cases are a variation of this algorithm...essentially raising the 572169240Sjfv * number of bits to shift mc_addr[5] left, while still keeping the 573169240Sjfv * 8-bit shifting total. 574173788Sjfv * 575173788Sjfv * For example, given the following Destination MAC Address and an 576169240Sjfv * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 577169240Sjfv * we can see that the bit_shift for case 0 is 4. These are the hash 578169240Sjfv * values resulting from each mc_filter_type... 579169240Sjfv * [0] [1] [2] [3] [4] [5] 580169240Sjfv * 01 AA 00 12 34 56 581169240Sjfv * LSB MSB 582169240Sjfv * 583169240Sjfv * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 584169240Sjfv * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 585169240Sjfv * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 586169240Sjfv * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 587169240Sjfv */ 588169240Sjfv switch (hw->mac.mc_filter_type) { 589169240Sjfv default: 590169240Sjfv case 0: 591169240Sjfv break; 592169240Sjfv case 1: 593169240Sjfv bit_shift += 1; 594169240Sjfv break; 595169240Sjfv case 2: 596169240Sjfv bit_shift += 2; 597169240Sjfv break; 598169240Sjfv case 3: 599169240Sjfv bit_shift += 4; 600169240Sjfv break; 601169240Sjfv } 602169240Sjfv 603169240Sjfv hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 604169240Sjfv (((u16) mc_addr[5]) << bit_shift))); 605169240Sjfv 606169240Sjfv return hash_value; 607169240Sjfv} 608169240Sjfv 609169240Sjfv/** 610169240Sjfv * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 611169589Sjfv * @hw: pointer to the HW structure 612169240Sjfv * 613169240Sjfv * In certain situations, a system BIOS may report that the PCIx maximum 614169240Sjfv * memory read byte count (MMRBC) value is higher than than the actual 615176667Sjfv * value. We check the PCIx command register with the current PCIx status 616176667Sjfv * register. 617169240Sjfv **/ 618173788Sjfvvoid e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 619169240Sjfv{ 620169240Sjfv u16 cmd_mmrbc; 621169240Sjfv u16 pcix_cmd; 622169240Sjfv u16 pcix_stat_hi_word; 623169240Sjfv u16 stat_mmrbc; 624169240Sjfv 625169240Sjfv DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 626169240Sjfv 627169240Sjfv /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 628169240Sjfv if (hw->bus.type != e1000_bus_type_pcix) 629169240Sjfv return; 630169240Sjfv 631169240Sjfv e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 632169240Sjfv e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 633169240Sjfv cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 634176667Sjfv PCIX_COMMAND_MMRBC_SHIFT; 635169240Sjfv stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 636176667Sjfv PCIX_STATUS_HI_MMRBC_SHIFT; 637169240Sjfv if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 638169240Sjfv stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 639169240Sjfv if (cmd_mmrbc > stat_mmrbc) { 640169240Sjfv pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 641169240Sjfv pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 642169240Sjfv e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 643169240Sjfv } 644169240Sjfv} 645169240Sjfv 646169240Sjfv/** 647169240Sjfv * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 648169589Sjfv * @hw: pointer to the HW structure 649169240Sjfv * 650169240Sjfv * Clears the base hardware counters by reading the counter registers. 651169240Sjfv **/ 652173788Sjfvvoid e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 653169240Sjfv{ 654169240Sjfv volatile u32 temp; 655169240Sjfv 656169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 657169240Sjfv 658169240Sjfv temp = E1000_READ_REG(hw, E1000_CRCERRS); 659169240Sjfv temp = E1000_READ_REG(hw, E1000_SYMERRS); 660169240Sjfv temp = E1000_READ_REG(hw, E1000_MPC); 661169240Sjfv temp = E1000_READ_REG(hw, E1000_SCC); 662169240Sjfv temp = E1000_READ_REG(hw, E1000_ECOL); 663169240Sjfv temp = E1000_READ_REG(hw, E1000_MCC); 664169240Sjfv temp = E1000_READ_REG(hw, E1000_LATECOL); 665169240Sjfv temp = E1000_READ_REG(hw, E1000_COLC); 666169240Sjfv temp = E1000_READ_REG(hw, E1000_DC); 667169240Sjfv temp = E1000_READ_REG(hw, E1000_SEC); 668169240Sjfv temp = E1000_READ_REG(hw, E1000_RLEC); 669169240Sjfv temp = E1000_READ_REG(hw, E1000_XONRXC); 670169240Sjfv temp = E1000_READ_REG(hw, E1000_XONTXC); 671169240Sjfv temp = E1000_READ_REG(hw, E1000_XOFFRXC); 672169240Sjfv temp = E1000_READ_REG(hw, E1000_XOFFTXC); 673169240Sjfv temp = E1000_READ_REG(hw, E1000_FCRUC); 674169240Sjfv temp = E1000_READ_REG(hw, E1000_GPRC); 675169240Sjfv temp = E1000_READ_REG(hw, E1000_BPRC); 676169240Sjfv temp = E1000_READ_REG(hw, E1000_MPRC); 677169240Sjfv temp = E1000_READ_REG(hw, E1000_GPTC); 678169240Sjfv temp = E1000_READ_REG(hw, E1000_GORCL); 679169240Sjfv temp = E1000_READ_REG(hw, E1000_GORCH); 680169240Sjfv temp = E1000_READ_REG(hw, E1000_GOTCL); 681169240Sjfv temp = E1000_READ_REG(hw, E1000_GOTCH); 682169240Sjfv temp = E1000_READ_REG(hw, E1000_RNBC); 683169240Sjfv temp = E1000_READ_REG(hw, E1000_RUC); 684169240Sjfv temp = E1000_READ_REG(hw, E1000_RFC); 685169240Sjfv temp = E1000_READ_REG(hw, E1000_ROC); 686169240Sjfv temp = E1000_READ_REG(hw, E1000_RJC); 687169240Sjfv temp = E1000_READ_REG(hw, E1000_TORL); 688169240Sjfv temp = E1000_READ_REG(hw, E1000_TORH); 689169240Sjfv temp = E1000_READ_REG(hw, E1000_TOTL); 690169240Sjfv temp = E1000_READ_REG(hw, E1000_TOTH); 691169240Sjfv temp = E1000_READ_REG(hw, E1000_TPR); 692169240Sjfv temp = E1000_READ_REG(hw, E1000_TPT); 693169240Sjfv temp = E1000_READ_REG(hw, E1000_MPTC); 694169240Sjfv temp = E1000_READ_REG(hw, E1000_BPTC); 695169240Sjfv} 696169240Sjfv 697169240Sjfv/** 698169240Sjfv * e1000_check_for_copper_link_generic - Check for link (Copper) 699169589Sjfv * @hw: pointer to the HW structure 700169240Sjfv * 701169240Sjfv * Checks to see of the link status of the hardware has changed. If a 702169240Sjfv * change in link status has been detected, then we read the PHY registers 703169240Sjfv * to get the current speed/duplex if link exists. 704169240Sjfv **/ 705173788Sjfvs32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 706169240Sjfv{ 707169240Sjfv struct e1000_mac_info *mac = &hw->mac; 708169240Sjfv s32 ret_val; 709173788Sjfv bool link; 710169240Sjfv 711169240Sjfv DEBUGFUNC("e1000_check_for_copper_link"); 712169240Sjfv 713173788Sjfv /* 714173788Sjfv * We only want to go out to the PHY registers to see if Auto-Neg 715169240Sjfv * has completed and/or if our link status has changed. The 716169240Sjfv * get_link_status flag is set upon receiving a Link Status 717169240Sjfv * Change or Rx Sequence Error interrupt. 718169240Sjfv */ 719169240Sjfv if (!mac->get_link_status) { 720169240Sjfv ret_val = E1000_SUCCESS; 721169240Sjfv goto out; 722169240Sjfv } 723169240Sjfv 724173788Sjfv /* 725173788Sjfv * First we want to see if the MII Status Register reports 726169240Sjfv * link. If so, then we want to get the current speed/duplex 727169240Sjfv * of the PHY. 728169240Sjfv */ 729169240Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 730169240Sjfv if (ret_val) 731169240Sjfv goto out; 732169240Sjfv 733169240Sjfv if (!link) 734169240Sjfv goto out; /* No link detected */ 735169240Sjfv 736169240Sjfv mac->get_link_status = FALSE; 737169240Sjfv 738173788Sjfv /* 739173788Sjfv * Check if there was DownShift, must be checked 740173788Sjfv * immediately after link-up 741173788Sjfv */ 742169240Sjfv e1000_check_downshift_generic(hw); 743169240Sjfv 744173788Sjfv /* 745173788Sjfv * If we are forcing speed/duplex, then we simply return since 746169240Sjfv * we have already determined whether we have link or not. 747169240Sjfv */ 748169240Sjfv if (!mac->autoneg) { 749169240Sjfv ret_val = -E1000_ERR_CONFIG; 750169240Sjfv goto out; 751169240Sjfv } 752169240Sjfv 753173788Sjfv /* 754173788Sjfv * Auto-Neg is enabled. Auto Speed Detection takes care 755169240Sjfv * of MAC speed/duplex configuration. So we only need to 756169240Sjfv * configure Collision Distance in the MAC. 757169240Sjfv */ 758169240Sjfv e1000_config_collision_dist_generic(hw); 759169240Sjfv 760173788Sjfv /* 761173788Sjfv * Configure Flow Control now that Auto-Neg has completed. 762169240Sjfv * First, we need to restore the desired flow control 763169240Sjfv * settings because we may have had to re-autoneg with a 764169240Sjfv * different link partner. 765169240Sjfv */ 766169240Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 767169240Sjfv if (ret_val) { 768169240Sjfv DEBUGOUT("Error configuring flow control\n"); 769169240Sjfv } 770169240Sjfv 771169240Sjfvout: 772169240Sjfv return ret_val; 773169240Sjfv} 774169240Sjfv 775169240Sjfv/** 776169240Sjfv * e1000_check_for_fiber_link_generic - Check for link (Fiber) 777169589Sjfv * @hw: pointer to the HW structure 778169240Sjfv * 779169240Sjfv * Checks for link up on the hardware. If link is not up and we have 780169240Sjfv * a signal, then we need to force link up. 781169240Sjfv **/ 782173788Sjfvs32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 783169240Sjfv{ 784169240Sjfv struct e1000_mac_info *mac = &hw->mac; 785169240Sjfv u32 rxcw; 786169240Sjfv u32 ctrl; 787169240Sjfv u32 status; 788169240Sjfv s32 ret_val = E1000_SUCCESS; 789169240Sjfv 790169240Sjfv DEBUGFUNC("e1000_check_for_fiber_link_generic"); 791169240Sjfv 792169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 793169240Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 794169240Sjfv rxcw = E1000_READ_REG(hw, E1000_RXCW); 795169240Sjfv 796173788Sjfv /* 797173788Sjfv * If we don't have link (auto-negotiation failed or link partner 798169240Sjfv * cannot auto-negotiate), the cable is plugged in (we have signal), 799169240Sjfv * and our link partner is not trying to auto-negotiate with us (we 800169240Sjfv * are receiving idles or data), we need to force link up. We also 801169240Sjfv * need to give auto-negotiation time to complete, in case the cable 802169240Sjfv * was just plugged in. The autoneg_failed flag does this. 803169240Sjfv */ 804169240Sjfv /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 805169240Sjfv if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 806169240Sjfv (!(rxcw & E1000_RXCW_C))) { 807169240Sjfv if (mac->autoneg_failed == 0) { 808169240Sjfv mac->autoneg_failed = 1; 809169240Sjfv goto out; 810169240Sjfv } 811169240Sjfv DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 812169240Sjfv 813169240Sjfv /* Disable auto-negotiation in the TXCW register */ 814169240Sjfv E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 815169240Sjfv 816169240Sjfv /* Force link-up and also force full-duplex. */ 817169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 818169240Sjfv ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 819169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 820169240Sjfv 821169240Sjfv /* Configure Flow Control after forcing link up. */ 822169240Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 823169240Sjfv if (ret_val) { 824169240Sjfv DEBUGOUT("Error configuring flow control\n"); 825169240Sjfv goto out; 826169240Sjfv } 827169240Sjfv } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 828173788Sjfv /* 829173788Sjfv * If we are forcing link and we are receiving /C/ ordered 830169240Sjfv * sets, re-enable auto-negotiation in the TXCW register 831169240Sjfv * and disable forced link in the Device Control register 832169240Sjfv * in an attempt to auto-negotiate with our link partner. 833169240Sjfv */ 834169240Sjfv DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 835169240Sjfv E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 836169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 837169240Sjfv 838169240Sjfv mac->serdes_has_link = TRUE; 839169240Sjfv } 840169240Sjfv 841169240Sjfvout: 842169240Sjfv return ret_val; 843169240Sjfv} 844169240Sjfv 845169240Sjfv/** 846169240Sjfv * e1000_check_for_serdes_link_generic - Check for link (Serdes) 847169589Sjfv * @hw: pointer to the HW structure 848169240Sjfv * 849169240Sjfv * Checks for link up on the hardware. If link is not up and we have 850169240Sjfv * a signal, then we need to force link up. 851169240Sjfv **/ 852173788Sjfvs32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 853169240Sjfv{ 854169240Sjfv struct e1000_mac_info *mac = &hw->mac; 855169240Sjfv u32 rxcw; 856169240Sjfv u32 ctrl; 857169240Sjfv u32 status; 858169240Sjfv s32 ret_val = E1000_SUCCESS; 859169240Sjfv 860169240Sjfv DEBUGFUNC("e1000_check_for_serdes_link_generic"); 861169240Sjfv 862169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 863169240Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 864169240Sjfv rxcw = E1000_READ_REG(hw, E1000_RXCW); 865169240Sjfv 866173788Sjfv /* 867173788Sjfv * If we don't have link (auto-negotiation failed or link partner 868169240Sjfv * cannot auto-negotiate), and our link partner is not trying to 869169240Sjfv * auto-negotiate with us (we are receiving idles or data), 870169240Sjfv * we need to force link up. We also need to give auto-negotiation 871169240Sjfv * time to complete. 872169240Sjfv */ 873169240Sjfv /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 874169240Sjfv if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 875169240Sjfv if (mac->autoneg_failed == 0) { 876169240Sjfv mac->autoneg_failed = 1; 877169240Sjfv goto out; 878169240Sjfv } 879169240Sjfv DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 880169240Sjfv 881169240Sjfv /* Disable auto-negotiation in the TXCW register */ 882169240Sjfv E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 883169240Sjfv 884169240Sjfv /* Force link-up and also force full-duplex. */ 885169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 886169240Sjfv ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 887169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 888169240Sjfv 889169240Sjfv /* Configure Flow Control after forcing link up. */ 890169240Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 891169240Sjfv if (ret_val) { 892169240Sjfv DEBUGOUT("Error configuring flow control\n"); 893169240Sjfv goto out; 894169240Sjfv } 895169240Sjfv } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 896173788Sjfv /* 897173788Sjfv * If we are forcing link and we are receiving /C/ ordered 898169240Sjfv * sets, re-enable auto-negotiation in the TXCW register 899169240Sjfv * and disable forced link in the Device Control register 900169240Sjfv * in an attempt to auto-negotiate with our link partner. 901169240Sjfv */ 902169240Sjfv DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 903169240Sjfv E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 904169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 905169240Sjfv 906169240Sjfv mac->serdes_has_link = TRUE; 907169240Sjfv } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 908173788Sjfv /* 909173788Sjfv * If we force link for non-auto-negotiation switch, check 910169240Sjfv * link status based on MAC synchronization for internal 911169240Sjfv * serdes media type. 912169240Sjfv */ 913169240Sjfv /* SYNCH bit and IV bit are sticky. */ 914169240Sjfv usec_delay(10); 915169240Sjfv if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, E1000_RXCW)) { 916169240Sjfv if (!(rxcw & E1000_RXCW_IV)) { 917169240Sjfv mac->serdes_has_link = TRUE; 918169240Sjfv DEBUGOUT("SERDES: Link is up.\n"); 919169240Sjfv } 920169240Sjfv } else { 921169240Sjfv mac->serdes_has_link = FALSE; 922169240Sjfv DEBUGOUT("SERDES: Link is down.\n"); 923169240Sjfv } 924169240Sjfv } 925169240Sjfv 926169240Sjfv if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 927169240Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 928169240Sjfv mac->serdes_has_link = (status & E1000_STATUS_LU) 929169240Sjfv ? TRUE 930169240Sjfv : FALSE; 931169240Sjfv } 932169240Sjfv 933169240Sjfvout: 934169240Sjfv return ret_val; 935169240Sjfv} 936169240Sjfv 937169240Sjfv/** 938169240Sjfv * e1000_setup_link_generic - Setup flow control and link settings 939169589Sjfv * @hw: pointer to the HW structure 940169240Sjfv * 941169240Sjfv * Determines which flow control settings to use, then configures flow 942169240Sjfv * control. Calls the appropriate media-specific link configuration 943169240Sjfv * function. Assuming the adapter has a valid link partner, a valid link 944169240Sjfv * should be established. Assumes the hardware has previously been reset 945169240Sjfv * and the transmitter and receiver are not enabled. 946169240Sjfv **/ 947173788Sjfvs32 e1000_setup_link_generic(struct e1000_hw *hw) 948169240Sjfv{ 949169240Sjfv s32 ret_val = E1000_SUCCESS; 950169240Sjfv 951169240Sjfv DEBUGFUNC("e1000_setup_link_generic"); 952169240Sjfv 953173788Sjfv /* 954173788Sjfv * In the case of the phy reset being blocked, we already have a link. 955169240Sjfv * We do not need to set it up again. 956169240Sjfv */ 957177867Sjfv if (hw->phy.ops.check_reset_block) 958177867Sjfv if (hw->phy.ops.check_reset_block(hw)) 959177867Sjfv goto out; 960169240Sjfv 961173788Sjfv /* 962173788Sjfv * If flow control is set to default, set flow control based on 963173788Sjfv * the EEPROM flow control settings. 964173788Sjfv */ 965173788Sjfv if (hw->fc.type == e1000_fc_default) { 966173788Sjfv ret_val = e1000_set_default_fc_generic(hw); 967173788Sjfv if (ret_val) 968173788Sjfv goto out; 969173788Sjfv } 970169240Sjfv 971173788Sjfv /* 972173788Sjfv * We want to save off the original Flow Control configuration just 973169240Sjfv * in case we get disconnected and then reconnected into a different 974169240Sjfv * hub or switch with different Flow Control capabilities. 975169240Sjfv */ 976173788Sjfv hw->fc.original_type = hw->fc.type; 977169240Sjfv 978173788Sjfv DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc.type); 979169240Sjfv 980169240Sjfv /* Call the necessary media_type subroutine to configure the link. */ 981177867Sjfv ret_val = hw->mac.ops.setup_physical_interface(hw); 982169240Sjfv if (ret_val) 983169240Sjfv goto out; 984169240Sjfv 985173788Sjfv /* 986173788Sjfv * Initialize the flow control address, type, and PAUSE timer 987169240Sjfv * registers to their default values. This is done even if flow 988169240Sjfv * control is disabled, because it does not hurt anything to 989169240Sjfv * initialize these registers. 990169240Sjfv */ 991169240Sjfv DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 992169240Sjfv E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 993169240Sjfv E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 994169240Sjfv E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 995169240Sjfv 996173788Sjfv E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 997169240Sjfv 998169240Sjfv ret_val = e1000_set_fc_watermarks_generic(hw); 999169240Sjfv 1000169240Sjfvout: 1001169240Sjfv return ret_val; 1002169240Sjfv} 1003169240Sjfv 1004169240Sjfv/** 1005169240Sjfv * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1006169589Sjfv * @hw: pointer to the HW structure 1007169240Sjfv * 1008169240Sjfv * Configures collision distance and flow control for fiber and serdes 1009169240Sjfv * links. Upon successful setup, poll for link. 1010169240Sjfv **/ 1011173788Sjfvs32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1012169240Sjfv{ 1013169240Sjfv u32 ctrl; 1014169240Sjfv s32 ret_val = E1000_SUCCESS; 1015169240Sjfv 1016169240Sjfv DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1017169240Sjfv 1018169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1019169240Sjfv 1020169240Sjfv /* Take the link out of reset */ 1021169240Sjfv ctrl &= ~E1000_CTRL_LRST; 1022169240Sjfv 1023169240Sjfv e1000_config_collision_dist_generic(hw); 1024169240Sjfv 1025169240Sjfv ret_val = e1000_commit_fc_settings_generic(hw); 1026169240Sjfv if (ret_val) 1027169240Sjfv goto out; 1028169240Sjfv 1029173788Sjfv /* 1030173788Sjfv * Since auto-negotiation is enabled, take the link out of reset (the 1031169240Sjfv * link will be in reset, because we previously reset the chip). This 1032169240Sjfv * will restart auto-negotiation. If auto-negotiation is successful 1033169240Sjfv * then the link-up status bit will be set and the flow control enable 1034169240Sjfv * bits (RFCE and TFCE) will be set according to their negotiated value. 1035169240Sjfv */ 1036169240Sjfv DEBUGOUT("Auto-negotiation enabled\n"); 1037169240Sjfv 1038169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1039169240Sjfv E1000_WRITE_FLUSH(hw); 1040169240Sjfv msec_delay(1); 1041169240Sjfv 1042173788Sjfv /* 1043176667Sjfv * For these adapters, the SW definable pin 1 is set when the optics 1044169240Sjfv * detect a signal. If we have a signal, then poll for a "Link-Up" 1045169240Sjfv * indication. 1046169240Sjfv */ 1047173788Sjfv if (hw->phy.media_type == e1000_media_type_internal_serdes || 1048169240Sjfv (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1049169240Sjfv ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1050169240Sjfv } else { 1051169240Sjfv DEBUGOUT("No signal detected\n"); 1052169240Sjfv } 1053169240Sjfv 1054169240Sjfvout: 1055169240Sjfv return ret_val; 1056169240Sjfv} 1057169240Sjfv 1058169240Sjfv/** 1059169240Sjfv * e1000_config_collision_dist_generic - Configure collision distance 1060169589Sjfv * @hw: pointer to the HW structure 1061169240Sjfv * 1062169240Sjfv * Configures the collision distance to the default value and is used 1063169240Sjfv * during link setup. Currently no func pointer exists and all 1064169240Sjfv * implementations are handled in the generic version of this function. 1065169240Sjfv **/ 1066173788Sjfvvoid e1000_config_collision_dist_generic(struct e1000_hw *hw) 1067169240Sjfv{ 1068169240Sjfv u32 tctl; 1069169240Sjfv 1070169240Sjfv DEBUGFUNC("e1000_config_collision_dist_generic"); 1071169240Sjfv 1072169240Sjfv tctl = E1000_READ_REG(hw, E1000_TCTL); 1073169240Sjfv 1074169240Sjfv tctl &= ~E1000_TCTL_COLD; 1075169240Sjfv tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1076169240Sjfv 1077169240Sjfv E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1078169240Sjfv E1000_WRITE_FLUSH(hw); 1079169240Sjfv} 1080169240Sjfv 1081169240Sjfv/** 1082169240Sjfv * e1000_poll_fiber_serdes_link_generic - Poll for link up 1083169589Sjfv * @hw: pointer to the HW structure 1084169240Sjfv * 1085169240Sjfv * Polls for link up by reading the status register, if link fails to come 1086169240Sjfv * up with auto-negotiation, then the link is forced if a signal is detected. 1087169240Sjfv **/ 1088173788Sjfvs32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1089169240Sjfv{ 1090169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1091169240Sjfv u32 i, status; 1092169240Sjfv s32 ret_val = E1000_SUCCESS; 1093169240Sjfv 1094169240Sjfv DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1095169240Sjfv 1096173788Sjfv /* 1097177867Sjfv * If we have a signal (the cable is plugged in, or assumed TRUE for 1098169240Sjfv * serdes media) then poll for a "Link-Up" indication in the Device 1099169240Sjfv * Status Register. Time-out if a link isn't seen in 500 milliseconds 1100169240Sjfv * seconds (Auto-negotiation should complete in less than 500 1101169240Sjfv * milliseconds even if the other end is doing it in SW). 1102169240Sjfv */ 1103169240Sjfv for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1104169240Sjfv msec_delay(10); 1105169240Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 1106169240Sjfv if (status & E1000_STATUS_LU) 1107169240Sjfv break; 1108169240Sjfv } 1109169240Sjfv if (i == FIBER_LINK_UP_LIMIT) { 1110169240Sjfv DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1111169240Sjfv mac->autoneg_failed = 1; 1112173788Sjfv /* 1113173788Sjfv * AutoNeg failed to achieve a link, so we'll call 1114169240Sjfv * mac->check_for_link. This routine will force the 1115169240Sjfv * link up if we detect a signal. This will allow us to 1116169240Sjfv * communicate with non-autonegotiating link partners. 1117169240Sjfv */ 1118177867Sjfv ret_val = hw->mac.ops.check_for_link(hw); 1119169240Sjfv if (ret_val) { 1120169240Sjfv DEBUGOUT("Error while checking for link\n"); 1121169240Sjfv goto out; 1122169240Sjfv } 1123169240Sjfv mac->autoneg_failed = 0; 1124169240Sjfv } else { 1125169240Sjfv mac->autoneg_failed = 0; 1126169240Sjfv DEBUGOUT("Valid Link Found\n"); 1127169240Sjfv } 1128169240Sjfv 1129169240Sjfvout: 1130169240Sjfv return ret_val; 1131169240Sjfv} 1132169240Sjfv 1133169240Sjfv/** 1134169240Sjfv * e1000_commit_fc_settings_generic - Configure flow control 1135169589Sjfv * @hw: pointer to the HW structure 1136169240Sjfv * 1137169240Sjfv * Write the flow control settings to the Transmit Config Word Register (TXCW) 1138169240Sjfv * base on the flow control settings in e1000_mac_info. 1139169240Sjfv **/ 1140173788Sjfvs32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1141169240Sjfv{ 1142169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1143169240Sjfv u32 txcw; 1144169240Sjfv s32 ret_val = E1000_SUCCESS; 1145169240Sjfv 1146169240Sjfv DEBUGFUNC("e1000_commit_fc_settings_generic"); 1147169240Sjfv 1148173788Sjfv /* 1149173788Sjfv * Check for a software override of the flow control settings, and 1150169240Sjfv * setup the device accordingly. If auto-negotiation is enabled, then 1151169240Sjfv * software will have to set the "PAUSE" bits to the correct value in 1152169240Sjfv * the Transmit Config Word Register (TXCW) and re-start auto- 1153169240Sjfv * negotiation. However, if auto-negotiation is disabled, then 1154169240Sjfv * software will have to manually configure the two flow control enable 1155169240Sjfv * bits in the CTRL register. 1156169240Sjfv * 1157169240Sjfv * The possible values of the "fc" parameter are: 1158169240Sjfv * 0: Flow control is completely disabled 1159169240Sjfv * 1: Rx flow control is enabled (we can receive pause frames, 1160169240Sjfv * but not send pause frames). 1161169240Sjfv * 2: Tx flow control is enabled (we can send pause frames but we 1162169240Sjfv * do not support receiving pause frames). 1163173788Sjfv * 3: Both Rx and Tx flow control (symmetric) are enabled. 1164169240Sjfv */ 1165173788Sjfv switch (hw->fc.type) { 1166169240Sjfv case e1000_fc_none: 1167169240Sjfv /* Flow control completely disabled by a software over-ride. */ 1168169240Sjfv txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1169169240Sjfv break; 1170169240Sjfv case e1000_fc_rx_pause: 1171173788Sjfv /* 1172173788Sjfv * Rx Flow control is enabled and Tx Flow control is disabled 1173169240Sjfv * by a software over-ride. Since there really isn't a way to 1174173788Sjfv * advertise that we are capable of Rx Pause ONLY, we will 1175169240Sjfv * advertise that we support both symmetric and asymmetric RX 1176169240Sjfv * PAUSE. Later, we will disable the adapter's ability to send 1177169240Sjfv * PAUSE frames. 1178169240Sjfv */ 1179169240Sjfv txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1180169240Sjfv break; 1181169240Sjfv case e1000_fc_tx_pause: 1182173788Sjfv /* 1183173788Sjfv * Tx Flow control is enabled, and Rx Flow control is disabled, 1184169240Sjfv * by a software over-ride. 1185169240Sjfv */ 1186169240Sjfv txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1187169240Sjfv break; 1188169240Sjfv case e1000_fc_full: 1189173788Sjfv /* 1190173788Sjfv * Flow control (both Rx and Tx) is enabled by a software 1191169240Sjfv * over-ride. 1192169240Sjfv */ 1193169240Sjfv txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1194169240Sjfv break; 1195169240Sjfv default: 1196169240Sjfv DEBUGOUT("Flow control param set incorrectly\n"); 1197169240Sjfv ret_val = -E1000_ERR_CONFIG; 1198169240Sjfv goto out; 1199169240Sjfv break; 1200169240Sjfv } 1201169240Sjfv 1202169240Sjfv E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1203169240Sjfv mac->txcw = txcw; 1204169240Sjfv 1205169240Sjfvout: 1206169240Sjfv return ret_val; 1207169240Sjfv} 1208169240Sjfv 1209169240Sjfv/** 1210169240Sjfv * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1211169589Sjfv * @hw: pointer to the HW structure 1212169240Sjfv * 1213169240Sjfv * Sets the flow control high/low threshold (watermark) registers. If 1214169240Sjfv * flow control XON frame transmission is enabled, then set XON frame 1215176667Sjfv * transmission as well. 1216169240Sjfv **/ 1217173788Sjfvs32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1218169240Sjfv{ 1219169240Sjfv s32 ret_val = E1000_SUCCESS; 1220169240Sjfv u32 fcrtl = 0, fcrth = 0; 1221169240Sjfv 1222169240Sjfv DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1223169240Sjfv 1224173788Sjfv /* 1225173788Sjfv * Set the flow control receive threshold registers. Normally, 1226169240Sjfv * these registers will be set to a default threshold that may be 1227169240Sjfv * adjusted later by the driver's runtime code. However, if the 1228169240Sjfv * ability to transmit pause frames is not enabled, then these 1229169240Sjfv * registers will be set to 0. 1230169240Sjfv */ 1231173788Sjfv if (hw->fc.type & e1000_fc_tx_pause) { 1232173788Sjfv /* 1233173788Sjfv * We need to set up the Receive Threshold high and low water 1234169240Sjfv * marks as well as (optionally) enabling the transmission of 1235169240Sjfv * XON frames. 1236169240Sjfv */ 1237173788Sjfv fcrtl = hw->fc.low_water; 1238173788Sjfv if (hw->fc.send_xon) 1239169240Sjfv fcrtl |= E1000_FCRTL_XONE; 1240169240Sjfv 1241173788Sjfv fcrth = hw->fc.high_water; 1242169240Sjfv } 1243169240Sjfv E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1244169240Sjfv E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1245169240Sjfv 1246169240Sjfv return ret_val; 1247169240Sjfv} 1248169240Sjfv 1249169240Sjfv/** 1250169240Sjfv * e1000_set_default_fc_generic - Set flow control default values 1251169589Sjfv * @hw: pointer to the HW structure 1252169240Sjfv * 1253169240Sjfv * Read the EEPROM for the default values for flow control and store the 1254169240Sjfv * values. 1255169240Sjfv **/ 1256173788Sjfvs32 e1000_set_default_fc_generic(struct e1000_hw *hw) 1257169240Sjfv{ 1258169240Sjfv s32 ret_val = E1000_SUCCESS; 1259169240Sjfv u16 nvm_data; 1260169240Sjfv 1261169240Sjfv DEBUGFUNC("e1000_set_default_fc_generic"); 1262169240Sjfv 1263173788Sjfv /* 1264173788Sjfv * Read and store word 0x0F of the EEPROM. This word contains bits 1265169240Sjfv * that determine the hardware's default PAUSE (flow control) mode, 1266169240Sjfv * a bit that determines whether the HW defaults to enabling or 1267169240Sjfv * disabling auto-negotiation, and the direction of the 1268169240Sjfv * SW defined pins. If there is no SW over-ride of the flow 1269169240Sjfv * control setting, then the variable hw->fc will 1270169240Sjfv * be initialized based on a value in the EEPROM. 1271169240Sjfv */ 1272177867Sjfv ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 1273169240Sjfv 1274169240Sjfv if (ret_val) { 1275169240Sjfv DEBUGOUT("NVM Read Error\n"); 1276169240Sjfv goto out; 1277169240Sjfv } 1278169240Sjfv 1279169240Sjfv if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 1280173788Sjfv hw->fc.type = e1000_fc_none; 1281169240Sjfv else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 1282169240Sjfv NVM_WORD0F_ASM_DIR) 1283173788Sjfv hw->fc.type = e1000_fc_tx_pause; 1284169240Sjfv else 1285173788Sjfv hw->fc.type = e1000_fc_full; 1286169240Sjfv 1287169240Sjfvout: 1288169240Sjfv return ret_val; 1289169240Sjfv} 1290169240Sjfv 1291169240Sjfv/** 1292169240Sjfv * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1293169589Sjfv * @hw: pointer to the HW structure 1294169240Sjfv * 1295169240Sjfv * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1296169240Sjfv * device control register to reflect the adapter settings. TFCE and RFCE 1297169240Sjfv * need to be explicitly set by software when a copper PHY is used because 1298169240Sjfv * autonegotiation is managed by the PHY rather than the MAC. Software must 1299169240Sjfv * also configure these bits when link is forced on a fiber connection. 1300169240Sjfv **/ 1301173788Sjfvs32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1302169240Sjfv{ 1303169240Sjfv u32 ctrl; 1304169240Sjfv s32 ret_val = E1000_SUCCESS; 1305169240Sjfv 1306169240Sjfv DEBUGFUNC("e1000_force_mac_fc_generic"); 1307169240Sjfv 1308169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1309169240Sjfv 1310173788Sjfv /* 1311173788Sjfv * Because we didn't get link via the internal auto-negotiation 1312169240Sjfv * mechanism (we either forced link or we got link via PHY 1313169240Sjfv * auto-neg), we have to manually enable/disable transmit an 1314169240Sjfv * receive flow control. 1315169240Sjfv * 1316169240Sjfv * The "Case" statement below enables/disable flow control 1317173788Sjfv * according to the "hw->fc.type" parameter. 1318169240Sjfv * 1319169240Sjfv * The possible values of the "fc" parameter are: 1320169240Sjfv * 0: Flow control is completely disabled 1321169240Sjfv * 1: Rx flow control is enabled (we can receive pause 1322169240Sjfv * frames but not send pause frames). 1323169240Sjfv * 2: Tx flow control is enabled (we can send pause frames 1324169240Sjfv * frames but we do not receive pause frames). 1325173788Sjfv * 3: Both Rx and Tx flow control (symmetric) is enabled. 1326169240Sjfv * other: No other values should be possible at this point. 1327169240Sjfv */ 1328173788Sjfv DEBUGOUT1("hw->fc.type = %u\n", hw->fc.type); 1329169240Sjfv 1330173788Sjfv switch (hw->fc.type) { 1331169240Sjfv case e1000_fc_none: 1332169240Sjfv ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1333169240Sjfv break; 1334169240Sjfv case e1000_fc_rx_pause: 1335169240Sjfv ctrl &= (~E1000_CTRL_TFCE); 1336169240Sjfv ctrl |= E1000_CTRL_RFCE; 1337169240Sjfv break; 1338169240Sjfv case e1000_fc_tx_pause: 1339169240Sjfv ctrl &= (~E1000_CTRL_RFCE); 1340169240Sjfv ctrl |= E1000_CTRL_TFCE; 1341169240Sjfv break; 1342169240Sjfv case e1000_fc_full: 1343169240Sjfv ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1344169240Sjfv break; 1345169240Sjfv default: 1346169240Sjfv DEBUGOUT("Flow control param set incorrectly\n"); 1347169240Sjfv ret_val = -E1000_ERR_CONFIG; 1348169240Sjfv goto out; 1349169240Sjfv } 1350169240Sjfv 1351169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1352169240Sjfv 1353169240Sjfvout: 1354169240Sjfv return ret_val; 1355169240Sjfv} 1356169240Sjfv 1357169240Sjfv/** 1358169240Sjfv * e1000_config_fc_after_link_up_generic - Configures flow control after link 1359169589Sjfv * @hw: pointer to the HW structure 1360169240Sjfv * 1361169240Sjfv * Checks the status of auto-negotiation after link up to ensure that the 1362169240Sjfv * speed and duplex were not forced. If the link needed to be forced, then 1363169240Sjfv * flow control needs to be forced also. If auto-negotiation is enabled 1364169240Sjfv * and did not fail, then we configure flow control based on our link 1365169240Sjfv * partner. 1366169240Sjfv **/ 1367173788Sjfvs32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1368169240Sjfv{ 1369169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1370177867Sjfv struct e1000_phy_info *phy = &hw->phy; 1371169240Sjfv s32 ret_val = E1000_SUCCESS; 1372169240Sjfv u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1373169240Sjfv u16 speed, duplex; 1374169240Sjfv 1375169240Sjfv DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1376169240Sjfv 1377173788Sjfv /* 1378173788Sjfv * Check for the case where we have fiber media and auto-neg failed 1379169240Sjfv * so we had to force link. In this case, we need to force the 1380169240Sjfv * configuration of the MAC to match the "fc" parameter. 1381169240Sjfv */ 1382169240Sjfv if (mac->autoneg_failed) { 1383173788Sjfv if (hw->phy.media_type == e1000_media_type_fiber || 1384173788Sjfv hw->phy.media_type == e1000_media_type_internal_serdes) 1385169240Sjfv ret_val = e1000_force_mac_fc_generic(hw); 1386169240Sjfv } else { 1387173788Sjfv if (hw->phy.media_type == e1000_media_type_copper) 1388169240Sjfv ret_val = e1000_force_mac_fc_generic(hw); 1389169240Sjfv } 1390169240Sjfv 1391169240Sjfv if (ret_val) { 1392169240Sjfv DEBUGOUT("Error forcing flow control settings\n"); 1393169240Sjfv goto out; 1394169240Sjfv } 1395169240Sjfv 1396173788Sjfv /* 1397173788Sjfv * Check for the case where we have copper media and auto-neg is 1398169240Sjfv * enabled. In this case, we need to check and see if Auto-Neg 1399169240Sjfv * has completed, and if so, how the PHY and link partner has 1400169240Sjfv * flow control configured. 1401169240Sjfv */ 1402173788Sjfv if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1403173788Sjfv /* 1404173788Sjfv * Read the MII Status Register and check to see if AutoNeg 1405169240Sjfv * has completed. We read this twice because this reg has 1406169240Sjfv * some "sticky" (latched) bits. 1407169240Sjfv */ 1408177867Sjfv ret_val = phy->ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1409169240Sjfv if (ret_val) 1410169240Sjfv goto out; 1411177867Sjfv ret_val = phy->ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1412169240Sjfv if (ret_val) 1413169240Sjfv goto out; 1414169240Sjfv 1415169240Sjfv if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1416169240Sjfv DEBUGOUT("Copper PHY and Auto Neg " 1417169240Sjfv "has not completed.\n"); 1418169240Sjfv goto out; 1419169240Sjfv } 1420169240Sjfv 1421173788Sjfv /* 1422173788Sjfv * The AutoNeg process has completed, so we now need to 1423169240Sjfv * read both the Auto Negotiation Advertisement 1424169240Sjfv * Register (Address 4) and the Auto_Negotiation Base 1425169240Sjfv * Page Ability Register (Address 5) to determine how 1426169240Sjfv * flow control was negotiated. 1427169240Sjfv */ 1428177867Sjfv ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, 1429176667Sjfv &mii_nway_adv_reg); 1430169240Sjfv if (ret_val) 1431169240Sjfv goto out; 1432177867Sjfv ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, 1433176667Sjfv &mii_nway_lp_ability_reg); 1434169240Sjfv if (ret_val) 1435169240Sjfv goto out; 1436169240Sjfv 1437173788Sjfv /* 1438173788Sjfv * Two bits in the Auto Negotiation Advertisement Register 1439169240Sjfv * (Address 4) and two bits in the Auto Negotiation Base 1440169240Sjfv * Page Ability Register (Address 5) determine flow control 1441169240Sjfv * for both the PHY and the link partner. The following 1442169240Sjfv * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1443169240Sjfv * 1999, describes these PAUSE resolution bits and how flow 1444169240Sjfv * control is determined based upon these settings. 1445169240Sjfv * NOTE: DC = Don't Care 1446169240Sjfv * 1447169240Sjfv * LOCAL DEVICE | LINK PARTNER 1448169240Sjfv * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1449169240Sjfv *-------|---------|-------|---------|-------------------- 1450169240Sjfv * 0 | 0 | DC | DC | e1000_fc_none 1451169240Sjfv * 0 | 1 | 0 | DC | e1000_fc_none 1452169240Sjfv * 0 | 1 | 1 | 0 | e1000_fc_none 1453169240Sjfv * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1454169240Sjfv * 1 | 0 | 0 | DC | e1000_fc_none 1455169240Sjfv * 1 | DC | 1 | DC | e1000_fc_full 1456169240Sjfv * 1 | 1 | 0 | 0 | e1000_fc_none 1457169240Sjfv * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1458169240Sjfv * 1459173788Sjfv * Are both PAUSE bits set to 1? If so, this implies 1460169240Sjfv * Symmetric Flow Control is enabled at both ends. The 1461169240Sjfv * ASM_DIR bits are irrelevant per the spec. 1462169240Sjfv * 1463169240Sjfv * For Symmetric Flow Control: 1464169240Sjfv * 1465169240Sjfv * LOCAL DEVICE | LINK PARTNER 1466169240Sjfv * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1467169240Sjfv *-------|---------|-------|---------|-------------------- 1468169240Sjfv * 1 | DC | 1 | DC | E1000_fc_full 1469169240Sjfv * 1470169240Sjfv */ 1471169240Sjfv if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1472169240Sjfv (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1473173788Sjfv /* 1474173788Sjfv * Now we need to check if the user selected Rx ONLY 1475169240Sjfv * of pause frames. In this case, we had to advertise 1476169240Sjfv * FULL flow control because we could not advertise RX 1477169240Sjfv * ONLY. Hence, we must now check to see if we need to 1478169240Sjfv * turn OFF the TRANSMISSION of PAUSE frames. 1479169240Sjfv */ 1480173788Sjfv if (hw->fc.original_type == e1000_fc_full) { 1481173788Sjfv hw->fc.type = e1000_fc_full; 1482169240Sjfv DEBUGOUT("Flow Control = FULL.\r\n"); 1483169240Sjfv } else { 1484173788Sjfv hw->fc.type = e1000_fc_rx_pause; 1485169240Sjfv DEBUGOUT("Flow Control = " 1486169240Sjfv "RX PAUSE frames only.\r\n"); 1487169240Sjfv } 1488169240Sjfv } 1489173788Sjfv /* 1490173788Sjfv * For receiving PAUSE frames ONLY. 1491169240Sjfv * 1492169240Sjfv * LOCAL DEVICE | LINK PARTNER 1493169240Sjfv * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1494169240Sjfv *-------|---------|-------|---------|-------------------- 1495169240Sjfv * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1496169240Sjfv */ 1497169240Sjfv else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1498169240Sjfv (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1499169240Sjfv (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1500169240Sjfv (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1501173788Sjfv hw->fc.type = e1000_fc_tx_pause; 1502169240Sjfv DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); 1503169240Sjfv } 1504173788Sjfv /* 1505173788Sjfv * For transmitting PAUSE frames ONLY. 1506169240Sjfv * 1507169240Sjfv * LOCAL DEVICE | LINK PARTNER 1508169240Sjfv * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1509169240Sjfv *-------|---------|-------|---------|-------------------- 1510169240Sjfv * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1511169240Sjfv */ 1512169240Sjfv else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1513169240Sjfv (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1514169240Sjfv !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1515169240Sjfv (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1516173788Sjfv hw->fc.type = e1000_fc_rx_pause; 1517169240Sjfv DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 1518173788Sjfv } else { 1519173788Sjfv /* 1520173788Sjfv * Per the IEEE spec, at this point flow control 1521173788Sjfv * should be disabled. 1522173788Sjfv */ 1523173788Sjfv hw->fc.type = e1000_fc_none; 1524169240Sjfv DEBUGOUT("Flow Control = NONE.\r\n"); 1525169240Sjfv } 1526169240Sjfv 1527173788Sjfv /* 1528173788Sjfv * Now we need to do one last check... If we auto- 1529169240Sjfv * negotiated to HALF DUPLEX, flow control should not be 1530169240Sjfv * enabled per IEEE 802.3 spec. 1531169240Sjfv */ 1532177867Sjfv ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1533169240Sjfv if (ret_val) { 1534169240Sjfv DEBUGOUT("Error getting link speed and duplex\n"); 1535169240Sjfv goto out; 1536169240Sjfv } 1537169240Sjfv 1538169240Sjfv if (duplex == HALF_DUPLEX) 1539173788Sjfv hw->fc.type = e1000_fc_none; 1540169240Sjfv 1541173788Sjfv /* 1542173788Sjfv * Now we call a subroutine to actually force the MAC 1543169240Sjfv * controller to use the correct flow control settings. 1544169240Sjfv */ 1545169240Sjfv ret_val = e1000_force_mac_fc_generic(hw); 1546169240Sjfv if (ret_val) { 1547169240Sjfv DEBUGOUT("Error forcing flow control settings\n"); 1548169240Sjfv goto out; 1549169240Sjfv } 1550169240Sjfv } 1551169240Sjfv 1552169240Sjfvout: 1553169240Sjfv return ret_val; 1554169240Sjfv} 1555169240Sjfv 1556169240Sjfv/** 1557176667Sjfv * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1558169589Sjfv * @hw: pointer to the HW structure 1559169589Sjfv * @speed: stores the current speed 1560169589Sjfv * @duplex: stores the current duplex 1561169240Sjfv * 1562169240Sjfv * Read the status register for the current speed/duplex and store the current 1563169240Sjfv * speed and duplex for copper connections. 1564169240Sjfv **/ 1565173788Sjfvs32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1566173788Sjfv u16 *duplex) 1567169240Sjfv{ 1568169240Sjfv u32 status; 1569169240Sjfv 1570169240Sjfv DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1571169240Sjfv 1572169240Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 1573169240Sjfv if (status & E1000_STATUS_SPEED_1000) { 1574169240Sjfv *speed = SPEED_1000; 1575169240Sjfv DEBUGOUT("1000 Mbs, "); 1576169240Sjfv } else if (status & E1000_STATUS_SPEED_100) { 1577169240Sjfv *speed = SPEED_100; 1578169240Sjfv DEBUGOUT("100 Mbs, "); 1579169240Sjfv } else { 1580169240Sjfv *speed = SPEED_10; 1581169240Sjfv DEBUGOUT("10 Mbs, "); 1582169240Sjfv } 1583169240Sjfv 1584169240Sjfv if (status & E1000_STATUS_FD) { 1585169240Sjfv *duplex = FULL_DUPLEX; 1586169240Sjfv DEBUGOUT("Full Duplex\n"); 1587169240Sjfv } else { 1588169240Sjfv *duplex = HALF_DUPLEX; 1589169240Sjfv DEBUGOUT("Half Duplex\n"); 1590169240Sjfv } 1591169240Sjfv 1592169240Sjfv return E1000_SUCCESS; 1593169240Sjfv} 1594169240Sjfv 1595169240Sjfv/** 1596176667Sjfv * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1597169589Sjfv * @hw: pointer to the HW structure 1598169589Sjfv * @speed: stores the current speed 1599169589Sjfv * @duplex: stores the current duplex 1600169240Sjfv * 1601169240Sjfv * Sets the speed and duplex to gigabit full duplex (the only possible option) 1602169240Sjfv * for fiber/serdes links. 1603169240Sjfv **/ 1604173788Sjfvs32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, 1605173788Sjfv u16 *speed, u16 *duplex) 1606169240Sjfv{ 1607169240Sjfv DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1608169240Sjfv 1609169240Sjfv *speed = SPEED_1000; 1610169240Sjfv *duplex = FULL_DUPLEX; 1611169240Sjfv 1612169240Sjfv return E1000_SUCCESS; 1613169240Sjfv} 1614169240Sjfv 1615169240Sjfv/** 1616169240Sjfv * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1617169589Sjfv * @hw: pointer to the HW structure 1618169240Sjfv * 1619169589Sjfv * Acquire the HW semaphore to access the PHY or NVM 1620169240Sjfv **/ 1621173788Sjfvs32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1622169240Sjfv{ 1623169240Sjfv u32 swsm; 1624169240Sjfv s32 ret_val = E1000_SUCCESS; 1625169240Sjfv s32 timeout = hw->nvm.word_size + 1; 1626169240Sjfv s32 i = 0; 1627169240Sjfv 1628169240Sjfv DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1629169240Sjfv 1630169589Sjfv /* Get the SW semaphore */ 1631169589Sjfv while (i < timeout) { 1632169589Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 1633169589Sjfv if (!(swsm & E1000_SWSM_SMBI)) 1634169589Sjfv break; 1635169589Sjfv 1636169589Sjfv usec_delay(50); 1637169589Sjfv i++; 1638169589Sjfv } 1639169589Sjfv 1640169589Sjfv if (i == timeout) { 1641169589Sjfv DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1642169589Sjfv ret_val = -E1000_ERR_NVM; 1643169589Sjfv goto out; 1644169589Sjfv } 1645169589Sjfv 1646169240Sjfv /* Get the FW semaphore. */ 1647169240Sjfv for (i = 0; i < timeout; i++) { 1648169240Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 1649169240Sjfv E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1650169240Sjfv 1651169240Sjfv /* Semaphore acquired if bit latched */ 1652169240Sjfv if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1653169240Sjfv break; 1654169240Sjfv 1655169240Sjfv usec_delay(50); 1656169240Sjfv } 1657169240Sjfv 1658169240Sjfv if (i == timeout) { 1659169240Sjfv /* Release semaphores */ 1660169240Sjfv e1000_put_hw_semaphore_generic(hw); 1661169240Sjfv DEBUGOUT("Driver can't access the NVM\n"); 1662169240Sjfv ret_val = -E1000_ERR_NVM; 1663169240Sjfv goto out; 1664169240Sjfv } 1665169240Sjfv 1666169240Sjfvout: 1667169240Sjfv return ret_val; 1668169240Sjfv} 1669169240Sjfv 1670169240Sjfv/** 1671169240Sjfv * e1000_put_hw_semaphore_generic - Release hardware semaphore 1672169589Sjfv * @hw: pointer to the HW structure 1673169240Sjfv * 1674169589Sjfv * Release hardware semaphore used to access the PHY or NVM 1675169240Sjfv **/ 1676173788Sjfvvoid e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1677169240Sjfv{ 1678169240Sjfv u32 swsm; 1679169240Sjfv 1680169240Sjfv DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1681169240Sjfv 1682169240Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 1683169240Sjfv 1684169589Sjfv swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1685169240Sjfv 1686169240Sjfv E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1687169240Sjfv} 1688169240Sjfv 1689169240Sjfv/** 1690169240Sjfv * e1000_get_auto_rd_done_generic - Check for auto read completion 1691169589Sjfv * @hw: pointer to the HW structure 1692169240Sjfv * 1693169240Sjfv * Check EEPROM for Auto Read done bit. 1694169240Sjfv **/ 1695173788Sjfvs32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1696169240Sjfv{ 1697169240Sjfv s32 i = 0; 1698169240Sjfv s32 ret_val = E1000_SUCCESS; 1699169240Sjfv 1700169240Sjfv DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1701169240Sjfv 1702169240Sjfv while (i < AUTO_READ_DONE_TIMEOUT) { 1703169240Sjfv if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1704169240Sjfv break; 1705169240Sjfv msec_delay(1); 1706169240Sjfv i++; 1707169240Sjfv } 1708169240Sjfv 1709169240Sjfv if (i == AUTO_READ_DONE_TIMEOUT) { 1710169240Sjfv DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1711169240Sjfv ret_val = -E1000_ERR_RESET; 1712169240Sjfv goto out; 1713169240Sjfv } 1714169240Sjfv 1715169240Sjfvout: 1716169240Sjfv return ret_val; 1717169240Sjfv} 1718169240Sjfv 1719169240Sjfv/** 1720169240Sjfv * e1000_valid_led_default_generic - Verify a valid default LED config 1721169589Sjfv * @hw: pointer to the HW structure 1722169589Sjfv * @data: pointer to the NVM (EEPROM) 1723169240Sjfv * 1724169240Sjfv * Read the EEPROM for the current default LED configuration. If the 1725169240Sjfv * LED configuration is not valid, set to a valid LED configuration. 1726169240Sjfv **/ 1727173788Sjfvs32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1728169240Sjfv{ 1729169240Sjfv s32 ret_val; 1730169240Sjfv 1731169240Sjfv DEBUGFUNC("e1000_valid_led_default_generic"); 1732169240Sjfv 1733177867Sjfv ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1734169240Sjfv if (ret_val) { 1735169240Sjfv DEBUGOUT("NVM Read Error\n"); 1736169240Sjfv goto out; 1737169240Sjfv } 1738169240Sjfv 1739169240Sjfv if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1740169240Sjfv *data = ID_LED_DEFAULT; 1741169240Sjfv 1742169240Sjfvout: 1743169240Sjfv return ret_val; 1744169240Sjfv} 1745169240Sjfv 1746169240Sjfv/** 1747169240Sjfv * e1000_id_led_init_generic - 1748169589Sjfv * @hw: pointer to the HW structure 1749169240Sjfv * 1750169240Sjfv **/ 1751173788Sjfvs32 e1000_id_led_init_generic(struct e1000_hw * hw) 1752169240Sjfv{ 1753169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1754169240Sjfv s32 ret_val; 1755169240Sjfv const u32 ledctl_mask = 0x000000FF; 1756169240Sjfv const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1757169240Sjfv const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1758169240Sjfv u16 data, i, temp; 1759169240Sjfv const u16 led_mask = 0x0F; 1760169240Sjfv 1761169240Sjfv DEBUGFUNC("e1000_id_led_init_generic"); 1762169240Sjfv 1763177867Sjfv ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1764169240Sjfv if (ret_val) 1765169240Sjfv goto out; 1766169240Sjfv 1767169240Sjfv mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1768169240Sjfv mac->ledctl_mode1 = mac->ledctl_default; 1769169240Sjfv mac->ledctl_mode2 = mac->ledctl_default; 1770169240Sjfv 1771169240Sjfv for (i = 0; i < 4; i++) { 1772169240Sjfv temp = (data >> (i << 2)) & led_mask; 1773169240Sjfv switch (temp) { 1774169240Sjfv case ID_LED_ON1_DEF2: 1775169240Sjfv case ID_LED_ON1_ON2: 1776169240Sjfv case ID_LED_ON1_OFF2: 1777169240Sjfv mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1778169240Sjfv mac->ledctl_mode1 |= ledctl_on << (i << 3); 1779169240Sjfv break; 1780169240Sjfv case ID_LED_OFF1_DEF2: 1781169240Sjfv case ID_LED_OFF1_ON2: 1782169240Sjfv case ID_LED_OFF1_OFF2: 1783169240Sjfv mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1784169240Sjfv mac->ledctl_mode1 |= ledctl_off << (i << 3); 1785169240Sjfv break; 1786169240Sjfv default: 1787169240Sjfv /* Do nothing */ 1788169240Sjfv break; 1789169240Sjfv } 1790169240Sjfv switch (temp) { 1791169240Sjfv case ID_LED_DEF1_ON2: 1792169240Sjfv case ID_LED_ON1_ON2: 1793169240Sjfv case ID_LED_OFF1_ON2: 1794169240Sjfv mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1795169240Sjfv mac->ledctl_mode2 |= ledctl_on << (i << 3); 1796169240Sjfv break; 1797169240Sjfv case ID_LED_DEF1_OFF2: 1798169240Sjfv case ID_LED_ON1_OFF2: 1799169240Sjfv case ID_LED_OFF1_OFF2: 1800169240Sjfv mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1801169240Sjfv mac->ledctl_mode2 |= ledctl_off << (i << 3); 1802169240Sjfv break; 1803169240Sjfv default: 1804169240Sjfv /* Do nothing */ 1805169240Sjfv break; 1806169240Sjfv } 1807169240Sjfv } 1808169240Sjfv 1809169240Sjfvout: 1810169240Sjfv return ret_val; 1811169240Sjfv} 1812169240Sjfv 1813169240Sjfv/** 1814169240Sjfv * e1000_setup_led_generic - Configures SW controllable LED 1815169589Sjfv * @hw: pointer to the HW structure 1816169240Sjfv * 1817169240Sjfv * This prepares the SW controllable LED for use and saves the current state 1818169240Sjfv * of the LED so it can be later restored. 1819169240Sjfv **/ 1820173788Sjfvs32 e1000_setup_led_generic(struct e1000_hw *hw) 1821169240Sjfv{ 1822169240Sjfv u32 ledctl; 1823169240Sjfv s32 ret_val = E1000_SUCCESS; 1824169240Sjfv 1825169240Sjfv DEBUGFUNC("e1000_setup_led_generic"); 1826169240Sjfv 1827177867Sjfv if (hw->mac.ops.setup_led != e1000_setup_led_generic) { 1828169240Sjfv ret_val = -E1000_ERR_CONFIG; 1829169240Sjfv goto out; 1830169240Sjfv } 1831169240Sjfv 1832173788Sjfv if (hw->phy.media_type == e1000_media_type_fiber) { 1833169240Sjfv ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1834169240Sjfv hw->mac.ledctl_default = ledctl; 1835169240Sjfv /* Turn off LED0 */ 1836169240Sjfv ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 1837169240Sjfv E1000_LEDCTL_LED0_BLINK | 1838169240Sjfv E1000_LEDCTL_LED0_MODE_MASK); 1839169240Sjfv ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1840169240Sjfv E1000_LEDCTL_LED0_MODE_SHIFT); 1841169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1842173788Sjfv } else if (hw->phy.media_type == e1000_media_type_copper) { 1843169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1844169240Sjfv } 1845169240Sjfv 1846169240Sjfvout: 1847169240Sjfv return ret_val; 1848169240Sjfv} 1849169240Sjfv 1850169240Sjfv/** 1851169240Sjfv * e1000_cleanup_led_generic - Set LED config to default operation 1852169589Sjfv * @hw: pointer to the HW structure 1853169240Sjfv * 1854169240Sjfv * Remove the current LED configuration and set the LED configuration 1855169240Sjfv * to the default value, saved from the EEPROM. 1856169240Sjfv **/ 1857173788Sjfvs32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1858169240Sjfv{ 1859169240Sjfv s32 ret_val = E1000_SUCCESS; 1860169240Sjfv 1861169240Sjfv DEBUGFUNC("e1000_cleanup_led_generic"); 1862169240Sjfv 1863177867Sjfv if (hw->mac.ops.cleanup_led != e1000_cleanup_led_generic) { 1864169240Sjfv ret_val = -E1000_ERR_CONFIG; 1865169240Sjfv goto out; 1866169240Sjfv } 1867169240Sjfv 1868169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1869169240Sjfv 1870169240Sjfvout: 1871169240Sjfv return ret_val; 1872169240Sjfv} 1873169240Sjfv 1874169240Sjfv/** 1875169240Sjfv * e1000_blink_led_generic - Blink LED 1876169589Sjfv * @hw: pointer to the HW structure 1877169240Sjfv * 1878176667Sjfv * Blink the LEDs which are set to be on. 1879169240Sjfv **/ 1880173788Sjfvs32 e1000_blink_led_generic(struct e1000_hw *hw) 1881169240Sjfv{ 1882169240Sjfv u32 ledctl_blink = 0; 1883169240Sjfv u32 i; 1884169240Sjfv 1885169240Sjfv DEBUGFUNC("e1000_blink_led_generic"); 1886169240Sjfv 1887173788Sjfv if (hw->phy.media_type == e1000_media_type_fiber) { 1888169240Sjfv /* always blink LED0 for PCI-E fiber */ 1889169240Sjfv ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1890169240Sjfv (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1891169240Sjfv } else { 1892173788Sjfv /* 1893173788Sjfv * set the blink bit for each LED that's "on" (0x0E) 1894173788Sjfv * in ledctl_mode2 1895173788Sjfv */ 1896169240Sjfv ledctl_blink = hw->mac.ledctl_mode2; 1897169240Sjfv for (i = 0; i < 4; i++) 1898169240Sjfv if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1899169240Sjfv E1000_LEDCTL_MODE_LED_ON) 1900169240Sjfv ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1901169240Sjfv (i * 8)); 1902169240Sjfv } 1903169240Sjfv 1904169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1905169240Sjfv 1906169240Sjfv return E1000_SUCCESS; 1907169240Sjfv} 1908169240Sjfv 1909169240Sjfv/** 1910169240Sjfv * e1000_led_on_generic - Turn LED on 1911169589Sjfv * @hw: pointer to the HW structure 1912169240Sjfv * 1913169240Sjfv * Turn LED on. 1914169240Sjfv **/ 1915173788Sjfvs32 e1000_led_on_generic(struct e1000_hw *hw) 1916169240Sjfv{ 1917169240Sjfv u32 ctrl; 1918169240Sjfv 1919169240Sjfv DEBUGFUNC("e1000_led_on_generic"); 1920169240Sjfv 1921173788Sjfv switch (hw->phy.media_type) { 1922169240Sjfv case e1000_media_type_fiber: 1923169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1924169240Sjfv ctrl &= ~E1000_CTRL_SWDPIN0; 1925169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 1926169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1927169240Sjfv break; 1928169240Sjfv case e1000_media_type_copper: 1929169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1930169240Sjfv break; 1931169240Sjfv default: 1932169240Sjfv break; 1933169240Sjfv } 1934169240Sjfv 1935169240Sjfv return E1000_SUCCESS; 1936169240Sjfv} 1937169240Sjfv 1938169240Sjfv/** 1939169240Sjfv * e1000_led_off_generic - Turn LED off 1940169589Sjfv * @hw: pointer to the HW structure 1941169240Sjfv * 1942169240Sjfv * Turn LED off. 1943169240Sjfv **/ 1944173788Sjfvs32 e1000_led_off_generic(struct e1000_hw *hw) 1945169240Sjfv{ 1946169240Sjfv u32 ctrl; 1947169240Sjfv 1948169240Sjfv DEBUGFUNC("e1000_led_off_generic"); 1949169240Sjfv 1950173788Sjfv switch (hw->phy.media_type) { 1951169240Sjfv case e1000_media_type_fiber: 1952169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1953169240Sjfv ctrl |= E1000_CTRL_SWDPIN0; 1954169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 1955169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1956169240Sjfv break; 1957169240Sjfv case e1000_media_type_copper: 1958169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1959169240Sjfv break; 1960169240Sjfv default: 1961169240Sjfv break; 1962169240Sjfv } 1963169240Sjfv 1964169240Sjfv return E1000_SUCCESS; 1965169240Sjfv} 1966169240Sjfv 1967169240Sjfv/** 1968169240Sjfv * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 1969169589Sjfv * @hw: pointer to the HW structure 1970169589Sjfv * @no_snoop: bitmap of snoop events 1971169240Sjfv * 1972169240Sjfv * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 1973169240Sjfv **/ 1974173788Sjfvvoid e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 1975169240Sjfv{ 1976169240Sjfv u32 gcr; 1977169240Sjfv 1978169240Sjfv DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 1979169240Sjfv 1980169240Sjfv if (hw->bus.type != e1000_bus_type_pci_express) 1981169240Sjfv goto out; 1982169240Sjfv 1983169240Sjfv if (no_snoop) { 1984169240Sjfv gcr = E1000_READ_REG(hw, E1000_GCR); 1985169240Sjfv gcr &= ~(PCIE_NO_SNOOP_ALL); 1986169240Sjfv gcr |= no_snoop; 1987169240Sjfv E1000_WRITE_REG(hw, E1000_GCR, gcr); 1988169240Sjfv } 1989169240Sjfvout: 1990169240Sjfv return; 1991169240Sjfv} 1992169240Sjfv 1993169240Sjfv/** 1994169240Sjfv * e1000_disable_pcie_master_generic - Disables PCI-express master access 1995169589Sjfv * @hw: pointer to the HW structure 1996169240Sjfv * 1997169240Sjfv * Returns 0 (E1000_SUCCESS) if successful, else returns -10 1998176667Sjfv * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 1999169240Sjfv * the master requests to be disabled. 2000169240Sjfv * 2001169240Sjfv * Disables PCI-Express master access and verifies there are no pending 2002169240Sjfv * requests. 2003169240Sjfv **/ 2004173788Sjfvs32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 2005169240Sjfv{ 2006169240Sjfv u32 ctrl; 2007169240Sjfv s32 timeout = MASTER_DISABLE_TIMEOUT; 2008169240Sjfv s32 ret_val = E1000_SUCCESS; 2009169240Sjfv 2010169240Sjfv DEBUGFUNC("e1000_disable_pcie_master_generic"); 2011169240Sjfv 2012169240Sjfv if (hw->bus.type != e1000_bus_type_pci_express) 2013169240Sjfv goto out; 2014169240Sjfv 2015169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 2016169240Sjfv ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2017169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2018169240Sjfv 2019169240Sjfv while (timeout) { 2020169240Sjfv if (!(E1000_READ_REG(hw, E1000_STATUS) & 2021169240Sjfv E1000_STATUS_GIO_MASTER_ENABLE)) 2022169240Sjfv break; 2023169240Sjfv usec_delay(100); 2024169240Sjfv timeout--; 2025169240Sjfv } 2026169240Sjfv 2027169240Sjfv if (!timeout) { 2028169240Sjfv DEBUGOUT("Master requests are pending.\n"); 2029169240Sjfv ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 2030169240Sjfv goto out; 2031169240Sjfv } 2032169240Sjfv 2033169240Sjfvout: 2034169240Sjfv return ret_val; 2035169240Sjfv} 2036169240Sjfv 2037169240Sjfv/** 2038169240Sjfv * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2039169589Sjfv * @hw: pointer to the HW structure 2040169240Sjfv * 2041169240Sjfv * Reset the Adaptive Interframe Spacing throttle to default values. 2042169240Sjfv **/ 2043173788Sjfvvoid e1000_reset_adaptive_generic(struct e1000_hw *hw) 2044169240Sjfv{ 2045169240Sjfv struct e1000_mac_info *mac = &hw->mac; 2046169240Sjfv 2047169240Sjfv DEBUGFUNC("e1000_reset_adaptive_generic"); 2048169240Sjfv 2049169240Sjfv if (!mac->adaptive_ifs) { 2050169240Sjfv DEBUGOUT("Not in Adaptive IFS mode!\n"); 2051169240Sjfv goto out; 2052169240Sjfv } 2053169240Sjfv 2054169240Sjfv if (!mac->ifs_params_forced) { 2055169240Sjfv mac->current_ifs_val = 0; 2056169240Sjfv mac->ifs_min_val = IFS_MIN; 2057169240Sjfv mac->ifs_max_val = IFS_MAX; 2058169240Sjfv mac->ifs_step_size = IFS_STEP; 2059169240Sjfv mac->ifs_ratio = IFS_RATIO; 2060169240Sjfv } 2061169240Sjfv 2062169240Sjfv mac->in_ifs_mode = FALSE; 2063169240Sjfv E1000_WRITE_REG(hw, E1000_AIT, 0); 2064169240Sjfvout: 2065169240Sjfv return; 2066169240Sjfv} 2067169240Sjfv 2068169240Sjfv/** 2069169240Sjfv * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2070169589Sjfv * @hw: pointer to the HW structure 2071169240Sjfv * 2072169240Sjfv * Update the Adaptive Interframe Spacing Throttle value based on the 2073169240Sjfv * time between transmitted packets and time between collisions. 2074169240Sjfv **/ 2075173788Sjfvvoid e1000_update_adaptive_generic(struct e1000_hw *hw) 2076169240Sjfv{ 2077169240Sjfv struct e1000_mac_info *mac = &hw->mac; 2078169240Sjfv 2079169240Sjfv DEBUGFUNC("e1000_update_adaptive_generic"); 2080169240Sjfv 2081169240Sjfv if (!mac->adaptive_ifs) { 2082169240Sjfv DEBUGOUT("Not in Adaptive IFS mode!\n"); 2083169240Sjfv goto out; 2084169240Sjfv } 2085169240Sjfv 2086169240Sjfv if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2087169240Sjfv if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2088169240Sjfv mac->in_ifs_mode = TRUE; 2089169240Sjfv if (mac->current_ifs_val < mac->ifs_max_val) { 2090169240Sjfv if (!mac->current_ifs_val) 2091169240Sjfv mac->current_ifs_val = mac->ifs_min_val; 2092169240Sjfv else 2093169240Sjfv mac->current_ifs_val += 2094169240Sjfv mac->ifs_step_size; 2095169240Sjfv E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val); 2096169240Sjfv } 2097169240Sjfv } 2098169240Sjfv } else { 2099169240Sjfv if (mac->in_ifs_mode && 2100169240Sjfv (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2101169240Sjfv mac->current_ifs_val = 0; 2102169240Sjfv mac->in_ifs_mode = FALSE; 2103169240Sjfv E1000_WRITE_REG(hw, E1000_AIT, 0); 2104169240Sjfv } 2105169240Sjfv } 2106169240Sjfvout: 2107169240Sjfv return; 2108169240Sjfv} 2109169240Sjfv 2110169240Sjfv/** 2111169240Sjfv * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2112169589Sjfv * @hw: pointer to the HW structure 2113169240Sjfv * 2114176667Sjfv * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2115169240Sjfv * set, which is forced to MDI mode only. 2116169240Sjfv **/ 2117173788Sjfvs32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2118169240Sjfv{ 2119169240Sjfv s32 ret_val = E1000_SUCCESS; 2120169240Sjfv 2121169240Sjfv DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2122169240Sjfv 2123169240Sjfv if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2124169240Sjfv DEBUGOUT("Invalid MDI setting detected\n"); 2125169240Sjfv hw->phy.mdix = 1; 2126169240Sjfv ret_val = -E1000_ERR_CONFIG; 2127169240Sjfv goto out; 2128169240Sjfv } 2129169240Sjfv 2130169240Sjfvout: 2131169240Sjfv return ret_val; 2132169240Sjfv} 2133169240Sjfv 2134169240Sjfv/** 2135169240Sjfv * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2136169589Sjfv * @hw: pointer to the HW structure 2137169589Sjfv * @reg: 32bit register offset such as E1000_SCTL 2138169589Sjfv * @offset: register offset to write to 2139169589Sjfv * @data: data to write at register offset 2140169240Sjfv * 2141169240Sjfv * Writes an address/data control type register. There are several of these 2142169240Sjfv * and they all have the format address << 8 | data and bit 31 is polled for 2143169240Sjfv * completion. 2144169240Sjfv **/ 2145173788Sjfvs32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2146173788Sjfv u32 offset, u8 data) 2147169240Sjfv{ 2148169240Sjfv u32 i, regvalue = 0; 2149169240Sjfv s32 ret_val = E1000_SUCCESS; 2150169240Sjfv 2151169240Sjfv DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2152169240Sjfv 2153169240Sjfv /* Set up the address and data */ 2154169240Sjfv regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2155169240Sjfv E1000_WRITE_REG(hw, reg, regvalue); 2156169240Sjfv 2157169240Sjfv /* Poll the ready bit to see if the MDI read completed */ 2158169240Sjfv for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2159169240Sjfv usec_delay(5); 2160169240Sjfv regvalue = E1000_READ_REG(hw, reg); 2161169240Sjfv if (regvalue & E1000_GEN_CTL_READY) 2162169240Sjfv break; 2163169240Sjfv } 2164169240Sjfv if (!(regvalue & E1000_GEN_CTL_READY)) { 2165169240Sjfv DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2166169240Sjfv ret_val = -E1000_ERR_PHY; 2167169240Sjfv goto out; 2168169240Sjfv } 2169169240Sjfv 2170169240Sjfvout: 2171169240Sjfv return ret_val; 2172169240Sjfv} 2173