1177867Sjfv/****************************************************************************** 2169240Sjfv 3286833Ssbruno Copyright (c) 2001-2015, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD$*/ 34169240Sjfv 35169589Sjfv#include "e1000_api.h" 36169240Sjfv 37185353Sjfvstatic s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 38190872Sjfvstatic void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 39238148Sjfvstatic void e1000_config_collision_dist_generic(struct e1000_hw *hw); 40267935Sjfvstatic int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index); 41185353Sjfv 42169240Sjfv/** 43177867Sjfv * e1000_init_mac_ops_generic - Initialize MAC function pointers 44177867Sjfv * @hw: pointer to the HW structure 45177867Sjfv * 46177867Sjfv * Setups up the function pointers to no-op functions 47177867Sjfv **/ 48177867Sjfvvoid e1000_init_mac_ops_generic(struct e1000_hw *hw) 49177867Sjfv{ 50177867Sjfv struct e1000_mac_info *mac = &hw->mac; 51177867Sjfv DEBUGFUNC("e1000_init_mac_ops_generic"); 52177867Sjfv 53177867Sjfv /* General Setup */ 54177867Sjfv mac->ops.init_params = e1000_null_ops_generic; 55177867Sjfv mac->ops.init_hw = e1000_null_ops_generic; 56177867Sjfv mac->ops.reset_hw = e1000_null_ops_generic; 57177867Sjfv mac->ops.setup_physical_interface = e1000_null_ops_generic; 58177867Sjfv mac->ops.get_bus_info = e1000_null_ops_generic; 59185353Sjfv mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 60177867Sjfv mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 61177867Sjfv mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 62177867Sjfv mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 63177867Sjfv /* LED */ 64177867Sjfv mac->ops.cleanup_led = e1000_null_ops_generic; 65177867Sjfv mac->ops.setup_led = e1000_null_ops_generic; 66177867Sjfv mac->ops.blink_led = e1000_null_ops_generic; 67177867Sjfv mac->ops.led_on = e1000_null_ops_generic; 68177867Sjfv mac->ops.led_off = e1000_null_ops_generic; 69177867Sjfv /* LINK */ 70177867Sjfv mac->ops.setup_link = e1000_null_ops_generic; 71177867Sjfv mac->ops.get_link_up_info = e1000_null_link_info; 72177867Sjfv mac->ops.check_for_link = e1000_null_ops_generic; 73287990Ssbruno mac->ops.set_obff_timer = e1000_null_set_obff_timer; 74177867Sjfv /* Management */ 75177867Sjfv mac->ops.check_mng_mode = e1000_null_mng_mode; 76177867Sjfv /* VLAN, MC, etc. */ 77177867Sjfv mac->ops.update_mc_addr_list = e1000_null_update_mc; 78177867Sjfv mac->ops.clear_vfta = e1000_null_mac_generic; 79177867Sjfv mac->ops.write_vfta = e1000_null_write_vfta; 80177867Sjfv mac->ops.rar_set = e1000_rar_set_generic; 81177867Sjfv mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 82177867Sjfv} 83177867Sjfv 84177867Sjfv/** 85177867Sjfv * e1000_null_ops_generic - No-op function, returns 0 86177867Sjfv * @hw: pointer to the HW structure 87177867Sjfv **/ 88256200Sjfvs32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw) 89177867Sjfv{ 90177867Sjfv DEBUGFUNC("e1000_null_ops_generic"); 91177867Sjfv return E1000_SUCCESS; 92177867Sjfv} 93177867Sjfv 94177867Sjfv/** 95177867Sjfv * e1000_null_mac_generic - No-op function, return void 96177867Sjfv * @hw: pointer to the HW structure 97177867Sjfv **/ 98256200Sjfvvoid e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw) 99177867Sjfv{ 100177867Sjfv DEBUGFUNC("e1000_null_mac_generic"); 101177867Sjfv return; 102177867Sjfv} 103177867Sjfv 104177867Sjfv/** 105177867Sjfv * e1000_null_link_info - No-op function, return 0 106177867Sjfv * @hw: pointer to the HW structure 107177867Sjfv **/ 108256200Sjfvs32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw, 109256200Sjfv u16 E1000_UNUSEDARG *s, u16 E1000_UNUSEDARG *d) 110177867Sjfv{ 111177867Sjfv DEBUGFUNC("e1000_null_link_info"); 112177867Sjfv return E1000_SUCCESS; 113177867Sjfv} 114177867Sjfv 115177867Sjfv/** 116177867Sjfv * e1000_null_mng_mode - No-op function, return FALSE 117177867Sjfv * @hw: pointer to the HW structure 118177867Sjfv **/ 119256200Sjfvbool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw) 120256200Sjfv{ 121177867Sjfv DEBUGFUNC("e1000_null_mng_mode"); 122177867Sjfv return FALSE; 123177867Sjfv} 124177867Sjfv 125177867Sjfv/** 126177867Sjfv * e1000_null_update_mc - No-op function, return void 127177867Sjfv * @hw: pointer to the HW structure 128177867Sjfv **/ 129256200Sjfvvoid e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw, 130256200Sjfv u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a) 131177867Sjfv{ 132177867Sjfv DEBUGFUNC("e1000_null_update_mc"); 133177867Sjfv return; 134177867Sjfv} 135177867Sjfv 136177867Sjfv/** 137177867Sjfv * e1000_null_write_vfta - No-op function, return void 138177867Sjfv * @hw: pointer to the HW structure 139177867Sjfv **/ 140256200Sjfvvoid e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw, 141256200Sjfv u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b) 142177867Sjfv{ 143177867Sjfv DEBUGFUNC("e1000_null_write_vfta"); 144177867Sjfv return; 145177867Sjfv} 146177867Sjfv 147177867Sjfv/** 148267935Sjfv * e1000_null_rar_set - No-op function, return 0 149177867Sjfv * @hw: pointer to the HW structure 150177867Sjfv **/ 151267935Sjfvint e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw, 152256200Sjfv u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a) 153177867Sjfv{ 154177867Sjfv DEBUGFUNC("e1000_null_rar_set"); 155267935Sjfv return E1000_SUCCESS; 156177867Sjfv} 157177867Sjfv 158177867Sjfv/** 159287990Ssbruno * e1000_null_set_obff_timer - No-op function, return 0 160287990Ssbruno * @hw: pointer to the HW structure 161287990Ssbruno **/ 162287990Ssbrunos32 e1000_null_set_obff_timer(struct e1000_hw E1000_UNUSEDARG *hw, 163287990Ssbruno u32 E1000_UNUSEDARG a) 164287990Ssbruno{ 165287990Ssbruno DEBUGFUNC("e1000_null_set_obff_timer"); 166287990Ssbruno return E1000_SUCCESS; 167287990Ssbruno} 168287990Ssbruno 169287990Ssbruno/** 170169240Sjfv * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 171169589Sjfv * @hw: pointer to the HW structure 172169240Sjfv * 173169240Sjfv * Determines and stores the system bus information for a particular 174169240Sjfv * network interface. The following bus information is determined and stored: 175169240Sjfv * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 176169240Sjfv **/ 177173788Sjfvs32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 178169240Sjfv{ 179185353Sjfv struct e1000_mac_info *mac = &hw->mac; 180169240Sjfv struct e1000_bus_info *bus = &hw->bus; 181169240Sjfv u32 status = E1000_READ_REG(hw, E1000_STATUS); 182169240Sjfv s32 ret_val = E1000_SUCCESS; 183169240Sjfv 184169240Sjfv DEBUGFUNC("e1000_get_bus_info_pci_generic"); 185169240Sjfv 186169240Sjfv /* PCI or PCI-X? */ 187169240Sjfv bus->type = (status & E1000_STATUS_PCIX_MODE) 188169240Sjfv ? e1000_bus_type_pcix 189169240Sjfv : e1000_bus_type_pci; 190169240Sjfv 191169240Sjfv /* Bus speed */ 192169240Sjfv if (bus->type == e1000_bus_type_pci) { 193169240Sjfv bus->speed = (status & E1000_STATUS_PCI66) 194228386Sjfv ? e1000_bus_speed_66 195228386Sjfv : e1000_bus_speed_33; 196169240Sjfv } else { 197169240Sjfv switch (status & E1000_STATUS_PCIX_SPEED) { 198169240Sjfv case E1000_STATUS_PCIX_SPEED_66: 199169240Sjfv bus->speed = e1000_bus_speed_66; 200169240Sjfv break; 201169240Sjfv case E1000_STATUS_PCIX_SPEED_100: 202169240Sjfv bus->speed = e1000_bus_speed_100; 203169240Sjfv break; 204169240Sjfv case E1000_STATUS_PCIX_SPEED_133: 205169240Sjfv bus->speed = e1000_bus_speed_133; 206169240Sjfv break; 207169240Sjfv default: 208169240Sjfv bus->speed = e1000_bus_speed_reserved; 209169240Sjfv break; 210169240Sjfv } 211169240Sjfv } 212169240Sjfv 213169240Sjfv /* Bus width */ 214169240Sjfv bus->width = (status & E1000_STATUS_BUS64) 215228386Sjfv ? e1000_bus_width_64 216228386Sjfv : e1000_bus_width_32; 217169240Sjfv 218169240Sjfv /* Which PCI(-X) function? */ 219185353Sjfv mac->ops.set_lan_id(hw); 220169240Sjfv 221169240Sjfv return ret_val; 222169240Sjfv} 223169240Sjfv 224169240Sjfv/** 225169240Sjfv * e1000_get_bus_info_pcie_generic - Get PCIe bus information 226169589Sjfv * @hw: pointer to the HW structure 227169240Sjfv * 228169240Sjfv * Determines and stores the system bus information for a particular 229169240Sjfv * network interface. The following bus information is determined and stored: 230169240Sjfv * bus speed, bus width, type (PCIe), and PCIe function. 231169240Sjfv **/ 232173788Sjfvs32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 233169240Sjfv{ 234185353Sjfv struct e1000_mac_info *mac = &hw->mac; 235169240Sjfv struct e1000_bus_info *bus = &hw->bus; 236169240Sjfv s32 ret_val; 237185353Sjfv u16 pcie_link_status; 238169240Sjfv 239169240Sjfv DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 240169240Sjfv 241169240Sjfv bus->type = e1000_bus_type_pci_express; 242169240Sjfv 243228386Sjfv ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS, 244228386Sjfv &pcie_link_status); 245205869Sjfv if (ret_val) { 246169240Sjfv bus->width = e1000_bus_width_unknown; 247205869Sjfv bus->speed = e1000_bus_speed_unknown; 248205869Sjfv } else { 249205869Sjfv switch (pcie_link_status & PCIE_LINK_SPEED_MASK) { 250205869Sjfv case PCIE_LINK_SPEED_2500: 251205869Sjfv bus->speed = e1000_bus_speed_2500; 252205869Sjfv break; 253205869Sjfv case PCIE_LINK_SPEED_5000: 254205869Sjfv bus->speed = e1000_bus_speed_5000; 255205869Sjfv break; 256205869Sjfv default: 257205869Sjfv bus->speed = e1000_bus_speed_unknown; 258205869Sjfv break; 259205869Sjfv } 260218530Sjfv 261181027Sjfv bus->width = (enum e1000_bus_width)((pcie_link_status & 262228386Sjfv PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT); 263205869Sjfv } 264169240Sjfv 265185353Sjfv mac->ops.set_lan_id(hw); 266185353Sjfv 267185353Sjfv return E1000_SUCCESS; 268185353Sjfv} 269185353Sjfv 270185353Sjfv/** 271185353Sjfv * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 272185353Sjfv * 273185353Sjfv * @hw: pointer to the HW structure 274185353Sjfv * 275185353Sjfv * Determines the LAN function id by reading memory-mapped registers 276185353Sjfv * and swaps the port value if requested. 277185353Sjfv **/ 278190872Sjfvstatic void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 279185353Sjfv{ 280185353Sjfv struct e1000_bus_info *bus = &hw->bus; 281185353Sjfv u32 reg; 282185353Sjfv 283247064Sjfv /* The status register reports the correct function number 284190872Sjfv * for the device regardless of function swap state. 285190872Sjfv */ 286185353Sjfv reg = E1000_READ_REG(hw, E1000_STATUS); 287185353Sjfv bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 288185353Sjfv} 289185353Sjfv 290185353Sjfv/** 291185353Sjfv * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 292185353Sjfv * @hw: pointer to the HW structure 293185353Sjfv * 294185353Sjfv * Determines the LAN function id by reading PCI config space. 295185353Sjfv **/ 296185353Sjfvvoid e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 297185353Sjfv{ 298185353Sjfv struct e1000_bus_info *bus = &hw->bus; 299185353Sjfv u16 pci_header_type; 300185353Sjfv u32 status; 301185353Sjfv 302169240Sjfv e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 303169240Sjfv if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 304169240Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 305169240Sjfv bus->func = (status & E1000_STATUS_FUNC_MASK) 306228386Sjfv >> E1000_STATUS_FUNC_SHIFT; 307173788Sjfv } else { 308169240Sjfv bus->func = 0; 309173788Sjfv } 310185353Sjfv} 311169240Sjfv 312185353Sjfv/** 313185353Sjfv * e1000_set_lan_id_single_port - Set LAN id for a single port device 314185353Sjfv * @hw: pointer to the HW structure 315185353Sjfv * 316185353Sjfv * Sets the LAN function id to zero for a single port device. 317185353Sjfv **/ 318185353Sjfvvoid e1000_set_lan_id_single_port(struct e1000_hw *hw) 319185353Sjfv{ 320185353Sjfv struct e1000_bus_info *bus = &hw->bus; 321185353Sjfv 322185353Sjfv bus->func = 0; 323169240Sjfv} 324169240Sjfv 325169240Sjfv/** 326169240Sjfv * e1000_clear_vfta_generic - Clear VLAN filter table 327169589Sjfv * @hw: pointer to the HW structure 328169240Sjfv * 329169240Sjfv * Clears the register array which contains the VLAN filter table by 330169240Sjfv * setting all the values to 0. 331169240Sjfv **/ 332173788Sjfvvoid e1000_clear_vfta_generic(struct e1000_hw *hw) 333169240Sjfv{ 334169240Sjfv u32 offset; 335169240Sjfv 336169240Sjfv DEBUGFUNC("e1000_clear_vfta_generic"); 337169240Sjfv 338169240Sjfv for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 339169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 340169240Sjfv E1000_WRITE_FLUSH(hw); 341169240Sjfv } 342169240Sjfv} 343169240Sjfv 344169240Sjfv/** 345169240Sjfv * e1000_write_vfta_generic - Write value to VLAN filter table 346169589Sjfv * @hw: pointer to the HW structure 347169589Sjfv * @offset: register offset in VLAN filter table 348169589Sjfv * @value: register value written to VLAN filter table 349169240Sjfv * 350169240Sjfv * Writes value at the given offset in the register array which stores 351169240Sjfv * the VLAN filter table. 352169240Sjfv **/ 353173788Sjfvvoid e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 354169240Sjfv{ 355169240Sjfv DEBUGFUNC("e1000_write_vfta_generic"); 356169240Sjfv 357169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 358169240Sjfv E1000_WRITE_FLUSH(hw); 359169240Sjfv} 360169240Sjfv 361169240Sjfv/** 362169240Sjfv * e1000_init_rx_addrs_generic - Initialize receive address's 363169589Sjfv * @hw: pointer to the HW structure 364169589Sjfv * @rar_count: receive address registers 365169240Sjfv * 366228386Sjfv * Setup the receive address registers by setting the base receive address 367169240Sjfv * register to the devices MAC address and clearing all the other receive 368169240Sjfv * address registers to 0. 369169240Sjfv **/ 370173788Sjfvvoid e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 371169240Sjfv{ 372169240Sjfv u32 i; 373190872Sjfv u8 mac_addr[ETH_ADDR_LEN] = {0}; 374169240Sjfv 375169240Sjfv DEBUGFUNC("e1000_init_rx_addrs_generic"); 376169240Sjfv 377169240Sjfv /* Setup the receive address */ 378169240Sjfv DEBUGOUT("Programming MAC Address into RAR[0]\n"); 379169240Sjfv 380177867Sjfv hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 381169240Sjfv 382169240Sjfv /* Zero out the other (rar_entry_count - 1) receive addresses */ 383169240Sjfv DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 384190872Sjfv for (i = 1; i < rar_count; i++) 385190872Sjfv hw->mac.ops.rar_set(hw, mac_addr, i); 386169240Sjfv} 387169240Sjfv 388169240Sjfv/** 389173788Sjfv * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 390173788Sjfv * @hw: pointer to the HW structure 391173788Sjfv * 392173788Sjfv * Checks the nvm for an alternate MAC address. An alternate MAC address 393173788Sjfv * can be setup by pre-boot software and must be treated like a permanent 394190872Sjfv * address and must override the actual permanent MAC address. If an 395190872Sjfv * alternate MAC address is found it is programmed into RAR0, replacing 396190872Sjfv * the permanent address that was installed into RAR0 by the Si on reset. 397190872Sjfv * This function will return SUCCESS unless it encounters an error while 398190872Sjfv * reading the EEPROM. 399173788Sjfv **/ 400173788Sjfvs32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 401173788Sjfv{ 402173788Sjfv u32 i; 403247064Sjfv s32 ret_val; 404173788Sjfv u16 offset, nvm_alt_mac_addr_offset, nvm_data; 405173788Sjfv u8 alt_mac_addr[ETH_ADDR_LEN]; 406173788Sjfv 407173788Sjfv DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 408173788Sjfv 409213234Sjfv ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); 410213234Sjfv if (ret_val) 411238148Sjfv return ret_val; 412213234Sjfv 413228386Sjfv /* not supported on older hardware or 82573 */ 414228386Sjfv if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573)) 415238148Sjfv return E1000_SUCCESS; 416213234Sjfv 417247064Sjfv /* Alternate MAC address is handled by the option ROM for 82580 418228386Sjfv * and newer. SW support not required. 419228386Sjfv */ 420228386Sjfv if (hw->mac.type >= e1000_82580) 421238148Sjfv return E1000_SUCCESS; 422228386Sjfv 423177867Sjfv ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 424228386Sjfv &nvm_alt_mac_addr_offset); 425173788Sjfv if (ret_val) { 426173788Sjfv DEBUGOUT("NVM Read Error\n"); 427238148Sjfv return ret_val; 428173788Sjfv } 429173788Sjfv 430228386Sjfv if ((nvm_alt_mac_addr_offset == 0xFFFF) || 431228386Sjfv (nvm_alt_mac_addr_offset == 0x0000)) 432190872Sjfv /* There is no Alternate MAC Address */ 433238148Sjfv return E1000_SUCCESS; 434173788Sjfv 435173788Sjfv if (hw->bus.func == E1000_FUNC_1) 436190872Sjfv nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 437200243Sjfv if (hw->bus.func == E1000_FUNC_2) 438200243Sjfv nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 439200243Sjfv 440200243Sjfv if (hw->bus.func == E1000_FUNC_3) 441200243Sjfv nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 442173788Sjfv for (i = 0; i < ETH_ADDR_LEN; i += 2) { 443173788Sjfv offset = nvm_alt_mac_addr_offset + (i >> 1); 444177867Sjfv ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 445173788Sjfv if (ret_val) { 446173788Sjfv DEBUGOUT("NVM Read Error\n"); 447238148Sjfv return ret_val; 448173788Sjfv } 449173788Sjfv 450173788Sjfv alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 451173788Sjfv alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 452173788Sjfv } 453173788Sjfv 454173788Sjfv /* if multicast bit is set, the alternate address will not be used */ 455173788Sjfv if (alt_mac_addr[0] & 0x01) { 456190872Sjfv DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 457238148Sjfv return E1000_SUCCESS; 458173788Sjfv } 459173788Sjfv 460247064Sjfv /* We have a valid alternate MAC address, and we want to treat it the 461190872Sjfv * same as the normal permanent MAC address stored by the HW into the 462190872Sjfv * RAR. Do this by mapping this address into RAR0. 463190872Sjfv */ 464190872Sjfv hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 465173788Sjfv 466238148Sjfv return E1000_SUCCESS; 467173788Sjfv} 468173788Sjfv 469173788Sjfv/** 470169240Sjfv * e1000_rar_set_generic - Set receive address register 471169589Sjfv * @hw: pointer to the HW structure 472169589Sjfv * @addr: pointer to the receive address 473169589Sjfv * @index: receive address array register 474169240Sjfv * 475169240Sjfv * Sets the receive address array register at index to the address passed 476169240Sjfv * in by addr. 477169240Sjfv **/ 478267935Sjfvstatic int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 479169240Sjfv{ 480169240Sjfv u32 rar_low, rar_high; 481169240Sjfv 482169240Sjfv DEBUGFUNC("e1000_rar_set_generic"); 483169240Sjfv 484247064Sjfv /* HW expects these in little endian so we reverse the byte order 485169240Sjfv * from network order (big endian) to little endian 486169240Sjfv */ 487228386Sjfv rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 488228386Sjfv ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 489169240Sjfv 490169240Sjfv rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 491169240Sjfv 492173788Sjfv /* If MAC address zero, no need to set the AV bit */ 493185353Sjfv if (rar_low || rar_high) 494185353Sjfv rar_high |= E1000_RAH_AV; 495169240Sjfv 496247064Sjfv /* Some bridges will combine consecutive 32-bit writes into 497190872Sjfv * a single burst write, which will malfunction on some parts. 498190872Sjfv * The flushes avoid this. 499190872Sjfv */ 500176667Sjfv E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 501190872Sjfv E1000_WRITE_FLUSH(hw); 502176667Sjfv E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 503190872Sjfv E1000_WRITE_FLUSH(hw); 504267935Sjfv 505267935Sjfv return E1000_SUCCESS; 506169240Sjfv} 507169240Sjfv 508169240Sjfv/** 509169240Sjfv * e1000_hash_mc_addr_generic - Generate a multicast hash value 510169589Sjfv * @hw: pointer to the HW structure 511169589Sjfv * @mc_addr: pointer to a multicast address 512169240Sjfv * 513169240Sjfv * Generates a multicast address hash value which is used to determine 514203049Sjfv * the multicast filter table array address and new table value. 515169240Sjfv **/ 516173788Sjfvu32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 517169240Sjfv{ 518169240Sjfv u32 hash_value, hash_mask; 519169240Sjfv u8 bit_shift = 0; 520169240Sjfv 521169240Sjfv DEBUGFUNC("e1000_hash_mc_addr_generic"); 522169240Sjfv 523169240Sjfv /* Register count multiplied by bits per register */ 524169240Sjfv hash_mask = (hw->mac.mta_reg_count * 32) - 1; 525169240Sjfv 526247064Sjfv /* For a mc_filter_type of 0, bit_shift is the number of left-shifts 527173788Sjfv * where 0xFF would still fall within the hash mask. 528173788Sjfv */ 529169240Sjfv while (hash_mask >> bit_shift != 0xFF) 530169240Sjfv bit_shift++; 531169240Sjfv 532247064Sjfv /* The portion of the address that is used for the hash table 533169240Sjfv * is determined by the mc_filter_type setting. 534169240Sjfv * The algorithm is such that there is a total of 8 bits of shifting. 535169240Sjfv * The bit_shift for a mc_filter_type of 0 represents the number of 536169240Sjfv * left-shifts where the MSB of mc_addr[5] would still fall within 537169240Sjfv * the hash_mask. Case 0 does this exactly. Since there are a total 538169240Sjfv * of 8 bits of shifting, then mc_addr[4] will shift right the 539169240Sjfv * remaining number of bits. Thus 8 - bit_shift. The rest of the 540169240Sjfv * cases are a variation of this algorithm...essentially raising the 541169240Sjfv * number of bits to shift mc_addr[5] left, while still keeping the 542169240Sjfv * 8-bit shifting total. 543173788Sjfv * 544173788Sjfv * For example, given the following Destination MAC Address and an 545169240Sjfv * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 546169240Sjfv * we can see that the bit_shift for case 0 is 4. These are the hash 547169240Sjfv * values resulting from each mc_filter_type... 548169240Sjfv * [0] [1] [2] [3] [4] [5] 549169240Sjfv * 01 AA 00 12 34 56 550228386Sjfv * LSB MSB 551169240Sjfv * 552169240Sjfv * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 553169240Sjfv * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 554169240Sjfv * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 555169240Sjfv * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 556169240Sjfv */ 557169240Sjfv switch (hw->mac.mc_filter_type) { 558185353Sjfv default: 559185353Sjfv case 0: 560185353Sjfv break; 561185353Sjfv case 1: 562185353Sjfv bit_shift += 1; 563185353Sjfv break; 564185353Sjfv case 2: 565185353Sjfv bit_shift += 2; 566185353Sjfv break; 567185353Sjfv case 3: 568185353Sjfv bit_shift += 4; 569185353Sjfv break; 570169240Sjfv } 571169240Sjfv 572169240Sjfv hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 573228386Sjfv (((u16) mc_addr[5]) << bit_shift))); 574169240Sjfv 575169240Sjfv return hash_value; 576169240Sjfv} 577169240Sjfv 578169240Sjfv/** 579238148Sjfv * e1000_update_mc_addr_list_generic - Update Multicast addresses 580238148Sjfv * @hw: pointer to the HW structure 581238148Sjfv * @mc_addr_list: array of multicast addresses to program 582238148Sjfv * @mc_addr_count: number of multicast addresses to program 583238148Sjfv * 584238148Sjfv * Updates entire Multicast Table Array. 585238148Sjfv * The caller must have a packed mc_addr_list of multicast addresses. 586238148Sjfv **/ 587238148Sjfvvoid e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 588238148Sjfv u8 *mc_addr_list, u32 mc_addr_count) 589238148Sjfv{ 590238148Sjfv u32 hash_value, hash_bit, hash_reg; 591238148Sjfv int i; 592238148Sjfv 593238148Sjfv DEBUGFUNC("e1000_update_mc_addr_list_generic"); 594238148Sjfv 595238148Sjfv /* clear mta_shadow */ 596238148Sjfv memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 597238148Sjfv 598238148Sjfv /* update mta_shadow from mc_addr_list */ 599238148Sjfv for (i = 0; (u32) i < mc_addr_count; i++) { 600238148Sjfv hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 601238148Sjfv 602238148Sjfv hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 603238148Sjfv hash_bit = hash_value & 0x1F; 604238148Sjfv 605238148Sjfv hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 606238148Sjfv mc_addr_list += (ETH_ADDR_LEN); 607238148Sjfv } 608238148Sjfv 609238148Sjfv /* replace the entire MTA table */ 610238148Sjfv for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 611238148Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 612238148Sjfv E1000_WRITE_FLUSH(hw); 613238148Sjfv} 614238148Sjfv 615238148Sjfv/** 616169240Sjfv * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 617169589Sjfv * @hw: pointer to the HW structure 618169240Sjfv * 619169240Sjfv * In certain situations, a system BIOS may report that the PCIx maximum 620169240Sjfv * memory read byte count (MMRBC) value is higher than than the actual 621176667Sjfv * value. We check the PCIx command register with the current PCIx status 622176667Sjfv * register. 623169240Sjfv **/ 624173788Sjfvvoid e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 625169240Sjfv{ 626169240Sjfv u16 cmd_mmrbc; 627169240Sjfv u16 pcix_cmd; 628169240Sjfv u16 pcix_stat_hi_word; 629169240Sjfv u16 stat_mmrbc; 630169240Sjfv 631169240Sjfv DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 632169240Sjfv 633169240Sjfv /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 634169240Sjfv if (hw->bus.type != e1000_bus_type_pcix) 635169240Sjfv return; 636169240Sjfv 637169240Sjfv e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 638169240Sjfv e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 639169240Sjfv cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 640228386Sjfv PCIX_COMMAND_MMRBC_SHIFT; 641169240Sjfv stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 642228386Sjfv PCIX_STATUS_HI_MMRBC_SHIFT; 643169240Sjfv if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 644169240Sjfv stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 645169240Sjfv if (cmd_mmrbc > stat_mmrbc) { 646169240Sjfv pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 647169240Sjfv pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 648169240Sjfv e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 649169240Sjfv } 650169240Sjfv} 651169240Sjfv 652169240Sjfv/** 653169240Sjfv * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 654169589Sjfv * @hw: pointer to the HW structure 655169240Sjfv * 656169240Sjfv * Clears the base hardware counters by reading the counter registers. 657169240Sjfv **/ 658173788Sjfvvoid e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 659169240Sjfv{ 660169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 661169240Sjfv 662185353Sjfv E1000_READ_REG(hw, E1000_CRCERRS); 663185353Sjfv E1000_READ_REG(hw, E1000_SYMERRS); 664185353Sjfv E1000_READ_REG(hw, E1000_MPC); 665185353Sjfv E1000_READ_REG(hw, E1000_SCC); 666185353Sjfv E1000_READ_REG(hw, E1000_ECOL); 667185353Sjfv E1000_READ_REG(hw, E1000_MCC); 668185353Sjfv E1000_READ_REG(hw, E1000_LATECOL); 669185353Sjfv E1000_READ_REG(hw, E1000_COLC); 670185353Sjfv E1000_READ_REG(hw, E1000_DC); 671185353Sjfv E1000_READ_REG(hw, E1000_SEC); 672185353Sjfv E1000_READ_REG(hw, E1000_RLEC); 673185353Sjfv E1000_READ_REG(hw, E1000_XONRXC); 674185353Sjfv E1000_READ_REG(hw, E1000_XONTXC); 675185353Sjfv E1000_READ_REG(hw, E1000_XOFFRXC); 676185353Sjfv E1000_READ_REG(hw, E1000_XOFFTXC); 677185353Sjfv E1000_READ_REG(hw, E1000_FCRUC); 678185353Sjfv E1000_READ_REG(hw, E1000_GPRC); 679185353Sjfv E1000_READ_REG(hw, E1000_BPRC); 680185353Sjfv E1000_READ_REG(hw, E1000_MPRC); 681185353Sjfv E1000_READ_REG(hw, E1000_GPTC); 682185353Sjfv E1000_READ_REG(hw, E1000_GORCL); 683185353Sjfv E1000_READ_REG(hw, E1000_GORCH); 684185353Sjfv E1000_READ_REG(hw, E1000_GOTCL); 685185353Sjfv E1000_READ_REG(hw, E1000_GOTCH); 686185353Sjfv E1000_READ_REG(hw, E1000_RNBC); 687185353Sjfv E1000_READ_REG(hw, E1000_RUC); 688185353Sjfv E1000_READ_REG(hw, E1000_RFC); 689185353Sjfv E1000_READ_REG(hw, E1000_ROC); 690185353Sjfv E1000_READ_REG(hw, E1000_RJC); 691185353Sjfv E1000_READ_REG(hw, E1000_TORL); 692185353Sjfv E1000_READ_REG(hw, E1000_TORH); 693185353Sjfv E1000_READ_REG(hw, E1000_TOTL); 694185353Sjfv E1000_READ_REG(hw, E1000_TOTH); 695185353Sjfv E1000_READ_REG(hw, E1000_TPR); 696185353Sjfv E1000_READ_REG(hw, E1000_TPT); 697185353Sjfv E1000_READ_REG(hw, E1000_MPTC); 698185353Sjfv E1000_READ_REG(hw, E1000_BPTC); 699169240Sjfv} 700169240Sjfv 701169240Sjfv/** 702169240Sjfv * e1000_check_for_copper_link_generic - Check for link (Copper) 703169589Sjfv * @hw: pointer to the HW structure 704169240Sjfv * 705169240Sjfv * Checks to see of the link status of the hardware has changed. If a 706169240Sjfv * change in link status has been detected, then we read the PHY registers 707169240Sjfv * to get the current speed/duplex if link exists. 708169240Sjfv **/ 709173788Sjfvs32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 710169240Sjfv{ 711169240Sjfv struct e1000_mac_info *mac = &hw->mac; 712169240Sjfv s32 ret_val; 713173788Sjfv bool link; 714169240Sjfv 715169240Sjfv DEBUGFUNC("e1000_check_for_copper_link"); 716169240Sjfv 717247064Sjfv /* We only want to go out to the PHY registers to see if Auto-Neg 718169240Sjfv * has completed and/or if our link status has changed. The 719169240Sjfv * get_link_status flag is set upon receiving a Link Status 720169240Sjfv * Change or Rx Sequence Error interrupt. 721169240Sjfv */ 722238148Sjfv if (!mac->get_link_status) 723238148Sjfv return E1000_SUCCESS; 724169240Sjfv 725247064Sjfv /* First we want to see if the MII Status Register reports 726169240Sjfv * link. If so, then we want to get the current speed/duplex 727169240Sjfv * of the PHY. 728169240Sjfv */ 729169240Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 730169240Sjfv if (ret_val) 731238148Sjfv return ret_val; 732169240Sjfv 733169240Sjfv if (!link) 734238148Sjfv return E1000_SUCCESS; /* No link detected */ 735169240Sjfv 736169240Sjfv mac->get_link_status = FALSE; 737169240Sjfv 738247064Sjfv /* Check if there was DownShift, must be checked 739173788Sjfv * immediately after link-up 740173788Sjfv */ 741169240Sjfv e1000_check_downshift_generic(hw); 742169240Sjfv 743247064Sjfv /* If we are forcing speed/duplex, then we simply return since 744169240Sjfv * we have already determined whether we have link or not. 745169240Sjfv */ 746238148Sjfv if (!mac->autoneg) 747238148Sjfv return -E1000_ERR_CONFIG; 748169240Sjfv 749247064Sjfv /* Auto-Neg is enabled. Auto Speed Detection takes care 750169240Sjfv * of MAC speed/duplex configuration. So we only need to 751169240Sjfv * configure Collision Distance in the MAC. 752169240Sjfv */ 753203049Sjfv mac->ops.config_collision_dist(hw); 754169240Sjfv 755247064Sjfv /* Configure Flow Control now that Auto-Neg has completed. 756169240Sjfv * First, we need to restore the desired flow control 757169240Sjfv * settings because we may have had to re-autoneg with a 758169240Sjfv * different link partner. 759169240Sjfv */ 760169240Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 761185353Sjfv if (ret_val) 762169240Sjfv DEBUGOUT("Error configuring flow control\n"); 763169240Sjfv 764169240Sjfv return ret_val; 765169240Sjfv} 766169240Sjfv 767169240Sjfv/** 768169240Sjfv * e1000_check_for_fiber_link_generic - Check for link (Fiber) 769169589Sjfv * @hw: pointer to the HW structure 770169240Sjfv * 771169240Sjfv * Checks for link up on the hardware. If link is not up and we have 772169240Sjfv * a signal, then we need to force link up. 773169240Sjfv **/ 774173788Sjfvs32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 775169240Sjfv{ 776169240Sjfv struct e1000_mac_info *mac = &hw->mac; 777169240Sjfv u32 rxcw; 778169240Sjfv u32 ctrl; 779169240Sjfv u32 status; 780238148Sjfv s32 ret_val; 781169240Sjfv 782169240Sjfv DEBUGFUNC("e1000_check_for_fiber_link_generic"); 783169240Sjfv 784169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 785169240Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 786169240Sjfv rxcw = E1000_READ_REG(hw, E1000_RXCW); 787169240Sjfv 788247064Sjfv /* If we don't have link (auto-negotiation failed or link partner 789169240Sjfv * cannot auto-negotiate), the cable is plugged in (we have signal), 790169240Sjfv * and our link partner is not trying to auto-negotiate with us (we 791169240Sjfv * are receiving idles or data), we need to force link up. We also 792169240Sjfv * need to give auto-negotiation time to complete, in case the cable 793169240Sjfv * was just plugged in. The autoneg_failed flag does this. 794169240Sjfv */ 795169240Sjfv /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 796238148Sjfv if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) && 797238148Sjfv !(rxcw & E1000_RXCW_C)) { 798238148Sjfv if (!mac->autoneg_failed) { 799238148Sjfv mac->autoneg_failed = TRUE; 800238148Sjfv return E1000_SUCCESS; 801169240Sjfv } 802218530Sjfv DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 803169240Sjfv 804169240Sjfv /* Disable auto-negotiation in the TXCW register */ 805169240Sjfv E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 806169240Sjfv 807169240Sjfv /* Force link-up and also force full-duplex. */ 808169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 809169240Sjfv ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 810169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 811169240Sjfv 812169240Sjfv /* Configure Flow Control after forcing link up. */ 813169240Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 814169240Sjfv if (ret_val) { 815169240Sjfv DEBUGOUT("Error configuring flow control\n"); 816238148Sjfv return ret_val; 817169240Sjfv } 818169240Sjfv } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 819247064Sjfv /* If we are forcing link and we are receiving /C/ ordered 820169240Sjfv * sets, re-enable auto-negotiation in the TXCW register 821169240Sjfv * and disable forced link in the Device Control register 822169240Sjfv * in an attempt to auto-negotiate with our link partner. 823169240Sjfv */ 824218530Sjfv DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 825169240Sjfv E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 826169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 827169240Sjfv 828169240Sjfv mac->serdes_has_link = TRUE; 829169240Sjfv } 830169240Sjfv 831238148Sjfv return E1000_SUCCESS; 832169240Sjfv} 833169240Sjfv 834169240Sjfv/** 835169240Sjfv * e1000_check_for_serdes_link_generic - Check for link (Serdes) 836169589Sjfv * @hw: pointer to the HW structure 837169240Sjfv * 838169240Sjfv * Checks for link up on the hardware. If link is not up and we have 839169240Sjfv * a signal, then we need to force link up. 840169240Sjfv **/ 841173788Sjfvs32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 842169240Sjfv{ 843169240Sjfv struct e1000_mac_info *mac = &hw->mac; 844169240Sjfv u32 rxcw; 845169240Sjfv u32 ctrl; 846169240Sjfv u32 status; 847238148Sjfv s32 ret_val; 848169240Sjfv 849169240Sjfv DEBUGFUNC("e1000_check_for_serdes_link_generic"); 850169240Sjfv 851169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 852169240Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 853169240Sjfv rxcw = E1000_READ_REG(hw, E1000_RXCW); 854169240Sjfv 855247064Sjfv /* If we don't have link (auto-negotiation failed or link partner 856169240Sjfv * cannot auto-negotiate), and our link partner is not trying to 857169240Sjfv * auto-negotiate with us (we are receiving idles or data), 858169240Sjfv * we need to force link up. We also need to give auto-negotiation 859169240Sjfv * time to complete. 860169240Sjfv */ 861169240Sjfv /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 862238148Sjfv if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) { 863238148Sjfv if (!mac->autoneg_failed) { 864238148Sjfv mac->autoneg_failed = TRUE; 865238148Sjfv return E1000_SUCCESS; 866169240Sjfv } 867218530Sjfv DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 868169240Sjfv 869169240Sjfv /* Disable auto-negotiation in the TXCW register */ 870169240Sjfv E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 871169240Sjfv 872169240Sjfv /* Force link-up and also force full-duplex. */ 873169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 874169240Sjfv ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 875169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 876169240Sjfv 877169240Sjfv /* Configure Flow Control after forcing link up. */ 878169240Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 879169240Sjfv if (ret_val) { 880169240Sjfv DEBUGOUT("Error configuring flow control\n"); 881238148Sjfv return ret_val; 882169240Sjfv } 883169240Sjfv } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 884247064Sjfv /* If we are forcing link and we are receiving /C/ ordered 885169240Sjfv * sets, re-enable auto-negotiation in the TXCW register 886169240Sjfv * and disable forced link in the Device Control register 887169240Sjfv * in an attempt to auto-negotiate with our link partner. 888169240Sjfv */ 889218530Sjfv DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 890169240Sjfv E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 891169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 892169240Sjfv 893169240Sjfv mac->serdes_has_link = TRUE; 894169240Sjfv } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 895247064Sjfv /* If we force link for non-auto-negotiation switch, check 896169240Sjfv * link status based on MAC synchronization for internal 897169240Sjfv * serdes media type. 898169240Sjfv */ 899169240Sjfv /* SYNCH bit and IV bit are sticky. */ 900169240Sjfv usec_delay(10); 901181027Sjfv rxcw = E1000_READ_REG(hw, E1000_RXCW); 902181027Sjfv if (rxcw & E1000_RXCW_SYNCH) { 903169240Sjfv if (!(rxcw & E1000_RXCW_IV)) { 904169240Sjfv mac->serdes_has_link = TRUE; 905181027Sjfv DEBUGOUT("SERDES: Link up - forced.\n"); 906169240Sjfv } 907169240Sjfv } else { 908169240Sjfv mac->serdes_has_link = FALSE; 909181027Sjfv DEBUGOUT("SERDES: Link down - force failed.\n"); 910169240Sjfv } 911169240Sjfv } 912169240Sjfv 913169240Sjfv if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 914169240Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 915181027Sjfv if (status & E1000_STATUS_LU) { 916181027Sjfv /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 917181027Sjfv usec_delay(10); 918181027Sjfv rxcw = E1000_READ_REG(hw, E1000_RXCW); 919181027Sjfv if (rxcw & E1000_RXCW_SYNCH) { 920181027Sjfv if (!(rxcw & E1000_RXCW_IV)) { 921181027Sjfv mac->serdes_has_link = TRUE; 922228386Sjfv DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n"); 923181027Sjfv } else { 924181027Sjfv mac->serdes_has_link = FALSE; 925228386Sjfv DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n"); 926181027Sjfv } 927181027Sjfv } else { 928181027Sjfv mac->serdes_has_link = FALSE; 929181027Sjfv DEBUGOUT("SERDES: Link down - no sync.\n"); 930181027Sjfv } 931181027Sjfv } else { 932181027Sjfv mac->serdes_has_link = FALSE; 933181027Sjfv DEBUGOUT("SERDES: Link down - autoneg failed\n"); 934181027Sjfv } 935169240Sjfv } 936169240Sjfv 937238148Sjfv return E1000_SUCCESS; 938169240Sjfv} 939169240Sjfv 940169240Sjfv/** 941238148Sjfv * e1000_set_default_fc_generic - Set flow control default values 942238148Sjfv * @hw: pointer to the HW structure 943238148Sjfv * 944238148Sjfv * Read the EEPROM for the default values for flow control and store the 945238148Sjfv * values. 946238148Sjfv **/ 947238148Sjfvs32 e1000_set_default_fc_generic(struct e1000_hw *hw) 948238148Sjfv{ 949238148Sjfv s32 ret_val; 950238148Sjfv u16 nvm_data; 951256200Sjfv u16 nvm_offset = 0; 952238148Sjfv 953238148Sjfv DEBUGFUNC("e1000_set_default_fc_generic"); 954238148Sjfv 955247064Sjfv /* Read and store word 0x0F of the EEPROM. This word contains bits 956238148Sjfv * that determine the hardware's default PAUSE (flow control) mode, 957238148Sjfv * a bit that determines whether the HW defaults to enabling or 958238148Sjfv * disabling auto-negotiation, and the direction of the 959238148Sjfv * SW defined pins. If there is no SW over-ride of the flow 960238148Sjfv * control setting, then the variable hw->fc will 961238148Sjfv * be initialized based on a value in the EEPROM. 962238148Sjfv */ 963256200Sjfv if (hw->mac.type == e1000_i350) { 964256200Sjfv nvm_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func); 965256200Sjfv ret_val = hw->nvm.ops.read(hw, 966256200Sjfv NVM_INIT_CONTROL2_REG + 967256200Sjfv nvm_offset, 968256200Sjfv 1, &nvm_data); 969256200Sjfv } else { 970256200Sjfv ret_val = hw->nvm.ops.read(hw, 971256200Sjfv NVM_INIT_CONTROL2_REG, 972256200Sjfv 1, &nvm_data); 973256200Sjfv } 974238148Sjfv 975256200Sjfv 976238148Sjfv if (ret_val) { 977238148Sjfv DEBUGOUT("NVM Read Error\n"); 978238148Sjfv return ret_val; 979238148Sjfv } 980238148Sjfv 981238148Sjfv if (!(nvm_data & NVM_WORD0F_PAUSE_MASK)) 982238148Sjfv hw->fc.requested_mode = e1000_fc_none; 983238148Sjfv else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 984238148Sjfv NVM_WORD0F_ASM_DIR) 985238148Sjfv hw->fc.requested_mode = e1000_fc_tx_pause; 986238148Sjfv else 987238148Sjfv hw->fc.requested_mode = e1000_fc_full; 988238148Sjfv 989238148Sjfv return E1000_SUCCESS; 990238148Sjfv} 991238148Sjfv 992238148Sjfv/** 993169240Sjfv * e1000_setup_link_generic - Setup flow control and link settings 994169589Sjfv * @hw: pointer to the HW structure 995169240Sjfv * 996169240Sjfv * Determines which flow control settings to use, then configures flow 997169240Sjfv * control. Calls the appropriate media-specific link configuration 998169240Sjfv * function. Assuming the adapter has a valid link partner, a valid link 999169240Sjfv * should be established. Assumes the hardware has previously been reset 1000169240Sjfv * and the transmitter and receiver are not enabled. 1001169240Sjfv **/ 1002173788Sjfvs32 e1000_setup_link_generic(struct e1000_hw *hw) 1003169240Sjfv{ 1004238148Sjfv s32 ret_val; 1005169240Sjfv 1006169240Sjfv DEBUGFUNC("e1000_setup_link_generic"); 1007169240Sjfv 1008247064Sjfv /* In the case of the phy reset being blocked, we already have a link. 1009169240Sjfv * We do not need to set it up again. 1010169240Sjfv */ 1011238148Sjfv if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 1012238148Sjfv return E1000_SUCCESS; 1013169240Sjfv 1014247064Sjfv /* If requested flow control is set to default, set flow control 1015185353Sjfv * based on the EEPROM flow control settings. 1016173788Sjfv */ 1017185353Sjfv if (hw->fc.requested_mode == e1000_fc_default) { 1018173788Sjfv ret_val = e1000_set_default_fc_generic(hw); 1019173788Sjfv if (ret_val) 1020238148Sjfv return ret_val; 1021173788Sjfv } 1022169240Sjfv 1023247064Sjfv /* Save off the requested flow control mode for use later. Depending 1024185353Sjfv * on the link partner's capabilities, we may or may not use this mode. 1025169240Sjfv */ 1026185353Sjfv hw->fc.current_mode = hw->fc.requested_mode; 1027169240Sjfv 1028185353Sjfv DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 1029190872Sjfv hw->fc.current_mode); 1030169240Sjfv 1031169240Sjfv /* Call the necessary media_type subroutine to configure the link. */ 1032177867Sjfv ret_val = hw->mac.ops.setup_physical_interface(hw); 1033169240Sjfv if (ret_val) 1034238148Sjfv return ret_val; 1035169240Sjfv 1036247064Sjfv /* Initialize the flow control address, type, and PAUSE timer 1037169240Sjfv * registers to their default values. This is done even if flow 1038169240Sjfv * control is disabled, because it does not hurt anything to 1039169240Sjfv * initialize these registers. 1040169240Sjfv */ 1041169240Sjfv DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1042169240Sjfv E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 1043169240Sjfv E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1044169240Sjfv E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 1045169240Sjfv 1046173788Sjfv E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 1047169240Sjfv 1048238148Sjfv return e1000_set_fc_watermarks_generic(hw); 1049169240Sjfv} 1050169240Sjfv 1051169240Sjfv/** 1052238148Sjfv * e1000_commit_fc_settings_generic - Configure flow control 1053169589Sjfv * @hw: pointer to the HW structure 1054169240Sjfv * 1055238148Sjfv * Write the flow control settings to the Transmit Config Word Register (TXCW) 1056238148Sjfv * base on the flow control settings in e1000_mac_info. 1057169240Sjfv **/ 1058238148Sjfvs32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1059169240Sjfv{ 1060203049Sjfv struct e1000_mac_info *mac = &hw->mac; 1061238148Sjfv u32 txcw; 1062169240Sjfv 1063238148Sjfv DEBUGFUNC("e1000_commit_fc_settings_generic"); 1064169240Sjfv 1065247064Sjfv /* Check for a software override of the flow control settings, and 1066238148Sjfv * setup the device accordingly. If auto-negotiation is enabled, then 1067238148Sjfv * software will have to set the "PAUSE" bits to the correct value in 1068238148Sjfv * the Transmit Config Word Register (TXCW) and re-start auto- 1069238148Sjfv * negotiation. However, if auto-negotiation is disabled, then 1070238148Sjfv * software will have to manually configure the two flow control enable 1071238148Sjfv * bits in the CTRL register. 1072238148Sjfv * 1073238148Sjfv * The possible values of the "fc" parameter are: 1074238148Sjfv * 0: Flow control is completely disabled 1075238148Sjfv * 1: Rx flow control is enabled (we can receive pause frames, 1076238148Sjfv * but not send pause frames). 1077238148Sjfv * 2: Tx flow control is enabled (we can send pause frames but we 1078238148Sjfv * do not support receiving pause frames). 1079238148Sjfv * 3: Both Rx and Tx flow control (symmetric) are enabled. 1080169240Sjfv */ 1081238148Sjfv switch (hw->fc.current_mode) { 1082238148Sjfv case e1000_fc_none: 1083238148Sjfv /* Flow control completely disabled by a software over-ride. */ 1084238148Sjfv txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1085238148Sjfv break; 1086238148Sjfv case e1000_fc_rx_pause: 1087247064Sjfv /* Rx Flow control is enabled and Tx Flow control is disabled 1088238148Sjfv * by a software over-ride. Since there really isn't a way to 1089238148Sjfv * advertise that we are capable of Rx Pause ONLY, we will 1090238148Sjfv * advertise that we support both symmetric and asymmetric Rx 1091238148Sjfv * PAUSE. Later, we will disable the adapter's ability to send 1092238148Sjfv * PAUSE frames. 1093238148Sjfv */ 1094238148Sjfv txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1095238148Sjfv break; 1096238148Sjfv case e1000_fc_tx_pause: 1097247064Sjfv /* Tx Flow control is enabled, and Rx Flow control is disabled, 1098238148Sjfv * by a software over-ride. 1099238148Sjfv */ 1100238148Sjfv txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1101238148Sjfv break; 1102238148Sjfv case e1000_fc_full: 1103247064Sjfv /* Flow control (both Rx and Tx) is enabled by a software 1104238148Sjfv * over-ride. 1105238148Sjfv */ 1106238148Sjfv txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1107238148Sjfv break; 1108238148Sjfv default: 1109238148Sjfv DEBUGOUT("Flow control param set incorrectly\n"); 1110238148Sjfv return -E1000_ERR_CONFIG; 1111238148Sjfv break; 1112169240Sjfv } 1113169240Sjfv 1114238148Sjfv E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1115238148Sjfv mac->txcw = txcw; 1116169240Sjfv 1117238148Sjfv return E1000_SUCCESS; 1118169240Sjfv} 1119169240Sjfv 1120169240Sjfv/** 1121169240Sjfv * e1000_poll_fiber_serdes_link_generic - Poll for link up 1122169589Sjfv * @hw: pointer to the HW structure 1123169240Sjfv * 1124169240Sjfv * Polls for link up by reading the status register, if link fails to come 1125169240Sjfv * up with auto-negotiation, then the link is forced if a signal is detected. 1126169240Sjfv **/ 1127218548Sbzs32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1128169240Sjfv{ 1129169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1130169240Sjfv u32 i, status; 1131238148Sjfv s32 ret_val; 1132169240Sjfv 1133169240Sjfv DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1134169240Sjfv 1135247064Sjfv /* If we have a signal (the cable is plugged in, or assumed TRUE for 1136169240Sjfv * serdes media) then poll for a "Link-Up" indication in the Device 1137169240Sjfv * Status Register. Time-out if a link isn't seen in 500 milliseconds 1138169240Sjfv * seconds (Auto-negotiation should complete in less than 500 1139169240Sjfv * milliseconds even if the other end is doing it in SW). 1140169240Sjfv */ 1141169240Sjfv for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1142169240Sjfv msec_delay(10); 1143169240Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 1144169240Sjfv if (status & E1000_STATUS_LU) 1145169240Sjfv break; 1146169240Sjfv } 1147169240Sjfv if (i == FIBER_LINK_UP_LIMIT) { 1148169240Sjfv DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1149238148Sjfv mac->autoneg_failed = TRUE; 1150247064Sjfv /* AutoNeg failed to achieve a link, so we'll call 1151169240Sjfv * mac->check_for_link. This routine will force the 1152169240Sjfv * link up if we detect a signal. This will allow us to 1153169240Sjfv * communicate with non-autonegotiating link partners. 1154169240Sjfv */ 1155203049Sjfv ret_val = mac->ops.check_for_link(hw); 1156169240Sjfv if (ret_val) { 1157169240Sjfv DEBUGOUT("Error while checking for link\n"); 1158238148Sjfv return ret_val; 1159169240Sjfv } 1160238148Sjfv mac->autoneg_failed = FALSE; 1161169240Sjfv } else { 1162238148Sjfv mac->autoneg_failed = FALSE; 1163169240Sjfv DEBUGOUT("Valid Link Found\n"); 1164169240Sjfv } 1165169240Sjfv 1166238148Sjfv return E1000_SUCCESS; 1167169240Sjfv} 1168169240Sjfv 1169169240Sjfv/** 1170238148Sjfv * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1171169589Sjfv * @hw: pointer to the HW structure 1172169240Sjfv * 1173238148Sjfv * Configures collision distance and flow control for fiber and serdes 1174238148Sjfv * links. Upon successful setup, poll for link. 1175169240Sjfv **/ 1176238148Sjfvs32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1177169240Sjfv{ 1178238148Sjfv u32 ctrl; 1179238148Sjfv s32 ret_val; 1180169240Sjfv 1181238148Sjfv DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1182169240Sjfv 1183238148Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1184238148Sjfv 1185238148Sjfv /* Take the link out of reset */ 1186238148Sjfv ctrl &= ~E1000_CTRL_LRST; 1187238148Sjfv 1188238148Sjfv hw->mac.ops.config_collision_dist(hw); 1189238148Sjfv 1190238148Sjfv ret_val = e1000_commit_fc_settings_generic(hw); 1191238148Sjfv if (ret_val) 1192238148Sjfv return ret_val; 1193238148Sjfv 1194247064Sjfv /* Since auto-negotiation is enabled, take the link out of reset (the 1195238148Sjfv * link will be in reset, because we previously reset the chip). This 1196238148Sjfv * will restart auto-negotiation. If auto-negotiation is successful 1197238148Sjfv * then the link-up status bit will be set and the flow control enable 1198238148Sjfv * bits (RFCE and TFCE) will be set according to their negotiated value. 1199169240Sjfv */ 1200238148Sjfv DEBUGOUT("Auto-negotiation enabled\n"); 1201238148Sjfv 1202238148Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1203238148Sjfv E1000_WRITE_FLUSH(hw); 1204238148Sjfv msec_delay(1); 1205238148Sjfv 1206247064Sjfv /* For these adapters, the SW definable pin 1 is set when the optics 1207238148Sjfv * detect a signal. If we have a signal, then poll for a "Link-Up" 1208238148Sjfv * indication. 1209238148Sjfv */ 1210238148Sjfv if (hw->phy.media_type == e1000_media_type_internal_serdes || 1211238148Sjfv (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1212238148Sjfv ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1213238148Sjfv } else { 1214238148Sjfv DEBUGOUT("No signal detected\n"); 1215169240Sjfv } 1216169240Sjfv 1217169240Sjfv return ret_val; 1218169240Sjfv} 1219169240Sjfv 1220169240Sjfv/** 1221238148Sjfv * e1000_config_collision_dist_generic - Configure collision distance 1222238148Sjfv * @hw: pointer to the HW structure 1223238148Sjfv * 1224238148Sjfv * Configures the collision distance to the default value and is used 1225238148Sjfv * during link setup. 1226238148Sjfv **/ 1227238148Sjfvstatic void e1000_config_collision_dist_generic(struct e1000_hw *hw) 1228238148Sjfv{ 1229238148Sjfv u32 tctl; 1230238148Sjfv 1231238148Sjfv DEBUGFUNC("e1000_config_collision_dist_generic"); 1232238148Sjfv 1233238148Sjfv tctl = E1000_READ_REG(hw, E1000_TCTL); 1234238148Sjfv 1235238148Sjfv tctl &= ~E1000_TCTL_COLD; 1236238148Sjfv tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1237238148Sjfv 1238238148Sjfv E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1239238148Sjfv E1000_WRITE_FLUSH(hw); 1240238148Sjfv} 1241238148Sjfv 1242238148Sjfv/** 1243169240Sjfv * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1244169589Sjfv * @hw: pointer to the HW structure 1245169240Sjfv * 1246169240Sjfv * Sets the flow control high/low threshold (watermark) registers. If 1247169240Sjfv * flow control XON frame transmission is enabled, then set XON frame 1248176667Sjfv * transmission as well. 1249169240Sjfv **/ 1250173788Sjfvs32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1251169240Sjfv{ 1252169240Sjfv u32 fcrtl = 0, fcrth = 0; 1253169240Sjfv 1254169240Sjfv DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1255169240Sjfv 1256247064Sjfv /* Set the flow control receive threshold registers. Normally, 1257169240Sjfv * these registers will be set to a default threshold that may be 1258169240Sjfv * adjusted later by the driver's runtime code. However, if the 1259169240Sjfv * ability to transmit pause frames is not enabled, then these 1260169240Sjfv * registers will be set to 0. 1261169240Sjfv */ 1262185353Sjfv if (hw->fc.current_mode & e1000_fc_tx_pause) { 1263247064Sjfv /* We need to set up the Receive Threshold high and low water 1264169240Sjfv * marks as well as (optionally) enabling the transmission of 1265169240Sjfv * XON frames. 1266169240Sjfv */ 1267173788Sjfv fcrtl = hw->fc.low_water; 1268173788Sjfv if (hw->fc.send_xon) 1269169240Sjfv fcrtl |= E1000_FCRTL_XONE; 1270169240Sjfv 1271173788Sjfv fcrth = hw->fc.high_water; 1272169240Sjfv } 1273169240Sjfv E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1274169240Sjfv E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1275169240Sjfv 1276203049Sjfv return E1000_SUCCESS; 1277169240Sjfv} 1278169240Sjfv 1279169240Sjfv/** 1280169240Sjfv * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1281169589Sjfv * @hw: pointer to the HW structure 1282169240Sjfv * 1283169240Sjfv * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1284169240Sjfv * device control register to reflect the adapter settings. TFCE and RFCE 1285169240Sjfv * need to be explicitly set by software when a copper PHY is used because 1286169240Sjfv * autonegotiation is managed by the PHY rather than the MAC. Software must 1287169240Sjfv * also configure these bits when link is forced on a fiber connection. 1288169240Sjfv **/ 1289173788Sjfvs32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1290169240Sjfv{ 1291169240Sjfv u32 ctrl; 1292169240Sjfv 1293169240Sjfv DEBUGFUNC("e1000_force_mac_fc_generic"); 1294169240Sjfv 1295169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1296169240Sjfv 1297247064Sjfv /* Because we didn't get link via the internal auto-negotiation 1298169240Sjfv * mechanism (we either forced link or we got link via PHY 1299169240Sjfv * auto-neg), we have to manually enable/disable transmit an 1300169240Sjfv * receive flow control. 1301169240Sjfv * 1302169240Sjfv * The "Case" statement below enables/disable flow control 1303185353Sjfv * according to the "hw->fc.current_mode" parameter. 1304169240Sjfv * 1305169240Sjfv * The possible values of the "fc" parameter are: 1306169240Sjfv * 0: Flow control is completely disabled 1307169240Sjfv * 1: Rx flow control is enabled (we can receive pause 1308169240Sjfv * frames but not send pause frames). 1309169240Sjfv * 2: Tx flow control is enabled (we can send pause frames 1310169240Sjfv * frames but we do not receive pause frames). 1311173788Sjfv * 3: Both Rx and Tx flow control (symmetric) is enabled. 1312169240Sjfv * other: No other values should be possible at this point. 1313169240Sjfv */ 1314185353Sjfv DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1315169240Sjfv 1316185353Sjfv switch (hw->fc.current_mode) { 1317169240Sjfv case e1000_fc_none: 1318169240Sjfv ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1319169240Sjfv break; 1320169240Sjfv case e1000_fc_rx_pause: 1321169240Sjfv ctrl &= (~E1000_CTRL_TFCE); 1322169240Sjfv ctrl |= E1000_CTRL_RFCE; 1323169240Sjfv break; 1324169240Sjfv case e1000_fc_tx_pause: 1325169240Sjfv ctrl &= (~E1000_CTRL_RFCE); 1326169240Sjfv ctrl |= E1000_CTRL_TFCE; 1327169240Sjfv break; 1328169240Sjfv case e1000_fc_full: 1329169240Sjfv ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1330169240Sjfv break; 1331169240Sjfv default: 1332169240Sjfv DEBUGOUT("Flow control param set incorrectly\n"); 1333238148Sjfv return -E1000_ERR_CONFIG; 1334169240Sjfv } 1335169240Sjfv 1336169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1337169240Sjfv 1338238148Sjfv return E1000_SUCCESS; 1339169240Sjfv} 1340169240Sjfv 1341169240Sjfv/** 1342169240Sjfv * e1000_config_fc_after_link_up_generic - Configures flow control after link 1343169589Sjfv * @hw: pointer to the HW structure 1344169240Sjfv * 1345169240Sjfv * Checks the status of auto-negotiation after link up to ensure that the 1346169240Sjfv * speed and duplex were not forced. If the link needed to be forced, then 1347169240Sjfv * flow control needs to be forced also. If auto-negotiation is enabled 1348169240Sjfv * and did not fail, then we configure flow control based on our link 1349169240Sjfv * partner. 1350169240Sjfv **/ 1351173788Sjfvs32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1352169240Sjfv{ 1353169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1354169240Sjfv s32 ret_val = E1000_SUCCESS; 1355247064Sjfv u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg; 1356169240Sjfv u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1357169240Sjfv u16 speed, duplex; 1358169240Sjfv 1359169240Sjfv DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1360169240Sjfv 1361247064Sjfv /* Check for the case where we have fiber media and auto-neg failed 1362169240Sjfv * so we had to force link. In this case, we need to force the 1363169240Sjfv * configuration of the MAC to match the "fc" parameter. 1364169240Sjfv */ 1365169240Sjfv if (mac->autoneg_failed) { 1366173788Sjfv if (hw->phy.media_type == e1000_media_type_fiber || 1367173788Sjfv hw->phy.media_type == e1000_media_type_internal_serdes) 1368169240Sjfv ret_val = e1000_force_mac_fc_generic(hw); 1369169240Sjfv } else { 1370173788Sjfv if (hw->phy.media_type == e1000_media_type_copper) 1371169240Sjfv ret_val = e1000_force_mac_fc_generic(hw); 1372169240Sjfv } 1373169240Sjfv 1374169240Sjfv if (ret_val) { 1375169240Sjfv DEBUGOUT("Error forcing flow control settings\n"); 1376238148Sjfv return ret_val; 1377169240Sjfv } 1378169240Sjfv 1379247064Sjfv /* Check for the case where we have copper media and auto-neg is 1380169240Sjfv * enabled. In this case, we need to check and see if Auto-Neg 1381169240Sjfv * has completed, and if so, how the PHY and link partner has 1382169240Sjfv * flow control configured. 1383169240Sjfv */ 1384173788Sjfv if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1385247064Sjfv /* Read the MII Status Register and check to see if AutoNeg 1386169240Sjfv * has completed. We read this twice because this reg has 1387169240Sjfv * some "sticky" (latched) bits. 1388169240Sjfv */ 1389185353Sjfv ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1390169240Sjfv if (ret_val) 1391238148Sjfv return ret_val; 1392185353Sjfv ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1393169240Sjfv if (ret_val) 1394238148Sjfv return ret_val; 1395169240Sjfv 1396169240Sjfv if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1397228386Sjfv DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); 1398238148Sjfv return ret_val; 1399169240Sjfv } 1400169240Sjfv 1401247064Sjfv /* The AutoNeg process has completed, so we now need to 1402169240Sjfv * read both the Auto Negotiation Advertisement 1403169240Sjfv * Register (Address 4) and the Auto_Negotiation Base 1404169240Sjfv * Page Ability Register (Address 5) to determine how 1405169240Sjfv * flow control was negotiated. 1406169240Sjfv */ 1407185353Sjfv ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1408228386Sjfv &mii_nway_adv_reg); 1409169240Sjfv if (ret_val) 1410238148Sjfv return ret_val; 1411185353Sjfv ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1412228386Sjfv &mii_nway_lp_ability_reg); 1413169240Sjfv if (ret_val) 1414238148Sjfv return ret_val; 1415169240Sjfv 1416247064Sjfv /* Two bits in the Auto Negotiation Advertisement Register 1417169240Sjfv * (Address 4) and two bits in the Auto Negotiation Base 1418169240Sjfv * Page Ability Register (Address 5) determine flow control 1419169240Sjfv * for both the PHY and the link partner. The following 1420169240Sjfv * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1421169240Sjfv * 1999, describes these PAUSE resolution bits and how flow 1422169240Sjfv * control is determined based upon these settings. 1423169240Sjfv * NOTE: DC = Don't Care 1424169240Sjfv * 1425169240Sjfv * LOCAL DEVICE | LINK PARTNER 1426169240Sjfv * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1427169240Sjfv *-------|---------|-------|---------|-------------------- 1428169240Sjfv * 0 | 0 | DC | DC | e1000_fc_none 1429169240Sjfv * 0 | 1 | 0 | DC | e1000_fc_none 1430169240Sjfv * 0 | 1 | 1 | 0 | e1000_fc_none 1431169240Sjfv * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1432169240Sjfv * 1 | 0 | 0 | DC | e1000_fc_none 1433169240Sjfv * 1 | DC | 1 | DC | e1000_fc_full 1434169240Sjfv * 1 | 1 | 0 | 0 | e1000_fc_none 1435169240Sjfv * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1436169240Sjfv * 1437173788Sjfv * Are both PAUSE bits set to 1? If so, this implies 1438169240Sjfv * Symmetric Flow Control is enabled at both ends. The 1439169240Sjfv * ASM_DIR bits are irrelevant per the spec. 1440169240Sjfv * 1441169240Sjfv * For Symmetric Flow Control: 1442169240Sjfv * 1443169240Sjfv * LOCAL DEVICE | LINK PARTNER 1444169240Sjfv * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1445169240Sjfv *-------|---------|-------|---------|-------------------- 1446169240Sjfv * 1 | DC | 1 | DC | E1000_fc_full 1447169240Sjfv * 1448169240Sjfv */ 1449169240Sjfv if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1450169240Sjfv (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1451247064Sjfv /* Now we need to check if the user selected Rx ONLY 1452169240Sjfv * of pause frames. In this case, we had to advertise 1453200243Sjfv * FULL flow control because we could not advertise Rx 1454169240Sjfv * ONLY. Hence, we must now check to see if we need to 1455228386Sjfv * turn OFF the TRANSMISSION of PAUSE frames. 1456169240Sjfv */ 1457185353Sjfv if (hw->fc.requested_mode == e1000_fc_full) { 1458185353Sjfv hw->fc.current_mode = e1000_fc_full; 1459228386Sjfv DEBUGOUT("Flow Control = FULL.\n"); 1460169240Sjfv } else { 1461185353Sjfv hw->fc.current_mode = e1000_fc_rx_pause; 1462228386Sjfv DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1463169240Sjfv } 1464169240Sjfv } 1465247064Sjfv /* For receiving PAUSE frames ONLY. 1466169240Sjfv * 1467169240Sjfv * LOCAL DEVICE | LINK PARTNER 1468169240Sjfv * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1469169240Sjfv *-------|---------|-------|---------|-------------------- 1470169240Sjfv * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1471169240Sjfv */ 1472169240Sjfv else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1473228386Sjfv (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1474228386Sjfv (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1475228386Sjfv (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1476185353Sjfv hw->fc.current_mode = e1000_fc_tx_pause; 1477228386Sjfv DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1478169240Sjfv } 1479247064Sjfv /* For transmitting PAUSE frames ONLY. 1480169240Sjfv * 1481169240Sjfv * LOCAL DEVICE | LINK PARTNER 1482169240Sjfv * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1483169240Sjfv *-------|---------|-------|---------|-------------------- 1484169240Sjfv * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1485169240Sjfv */ 1486169240Sjfv else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1487228386Sjfv (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1488228386Sjfv !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1489228386Sjfv (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1490185353Sjfv hw->fc.current_mode = e1000_fc_rx_pause; 1491228386Sjfv DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1492173788Sjfv } else { 1493247064Sjfv /* Per the IEEE spec, at this point flow control 1494173788Sjfv * should be disabled. 1495173788Sjfv */ 1496185353Sjfv hw->fc.current_mode = e1000_fc_none; 1497228386Sjfv DEBUGOUT("Flow Control = NONE.\n"); 1498169240Sjfv } 1499169240Sjfv 1500247064Sjfv /* Now we need to do one last check... If we auto- 1501169240Sjfv * negotiated to HALF DUPLEX, flow control should not be 1502169240Sjfv * enabled per IEEE 802.3 spec. 1503169240Sjfv */ 1504177867Sjfv ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1505169240Sjfv if (ret_val) { 1506169240Sjfv DEBUGOUT("Error getting link speed and duplex\n"); 1507238148Sjfv return ret_val; 1508169240Sjfv } 1509169240Sjfv 1510169240Sjfv if (duplex == HALF_DUPLEX) 1511185353Sjfv hw->fc.current_mode = e1000_fc_none; 1512169240Sjfv 1513247064Sjfv /* Now we call a subroutine to actually force the MAC 1514169240Sjfv * controller to use the correct flow control settings. 1515169240Sjfv */ 1516169240Sjfv ret_val = e1000_force_mac_fc_generic(hw); 1517169240Sjfv if (ret_val) { 1518169240Sjfv DEBUGOUT("Error forcing flow control settings\n"); 1519238148Sjfv return ret_val; 1520169240Sjfv } 1521169240Sjfv } 1522169240Sjfv 1523247064Sjfv /* Check for the case where we have SerDes media and auto-neg is 1524247064Sjfv * enabled. In this case, we need to check and see if Auto-Neg 1525247064Sjfv * has completed, and if so, how the PHY and link partner has 1526247064Sjfv * flow control configured. 1527247064Sjfv */ 1528247064Sjfv if ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1529247064Sjfv mac->autoneg) { 1530247064Sjfv /* Read the PCS_LSTS and check to see if AutoNeg 1531247064Sjfv * has completed. 1532247064Sjfv */ 1533247064Sjfv pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT); 1534247064Sjfv 1535247064Sjfv if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) { 1536247064Sjfv DEBUGOUT("PCS Auto Neg has not completed.\n"); 1537247064Sjfv return ret_val; 1538247064Sjfv } 1539247064Sjfv 1540247064Sjfv /* The AutoNeg process has completed, so we now need to 1541247064Sjfv * read both the Auto Negotiation Advertisement 1542247064Sjfv * Register (PCS_ANADV) and the Auto_Negotiation Base 1543247064Sjfv * Page Ability Register (PCS_LPAB) to determine how 1544247064Sjfv * flow control was negotiated. 1545247064Sjfv */ 1546247064Sjfv pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); 1547247064Sjfv pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB); 1548247064Sjfv 1549247064Sjfv /* Two bits in the Auto Negotiation Advertisement Register 1550247064Sjfv * (PCS_ANADV) and two bits in the Auto Negotiation Base 1551247064Sjfv * Page Ability Register (PCS_LPAB) determine flow control 1552247064Sjfv * for both the PHY and the link partner. The following 1553247064Sjfv * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1554247064Sjfv * 1999, describes these PAUSE resolution bits and how flow 1555247064Sjfv * control is determined based upon these settings. 1556247064Sjfv * NOTE: DC = Don't Care 1557247064Sjfv * 1558247064Sjfv * LOCAL DEVICE | LINK PARTNER 1559247064Sjfv * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1560247064Sjfv *-------|---------|-------|---------|-------------------- 1561247064Sjfv * 0 | 0 | DC | DC | e1000_fc_none 1562247064Sjfv * 0 | 1 | 0 | DC | e1000_fc_none 1563247064Sjfv * 0 | 1 | 1 | 0 | e1000_fc_none 1564247064Sjfv * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1565247064Sjfv * 1 | 0 | 0 | DC | e1000_fc_none 1566247064Sjfv * 1 | DC | 1 | DC | e1000_fc_full 1567247064Sjfv * 1 | 1 | 0 | 0 | e1000_fc_none 1568247064Sjfv * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1569247064Sjfv * 1570247064Sjfv * Are both PAUSE bits set to 1? If so, this implies 1571247064Sjfv * Symmetric Flow Control is enabled at both ends. The 1572247064Sjfv * ASM_DIR bits are irrelevant per the spec. 1573247064Sjfv * 1574247064Sjfv * For Symmetric Flow Control: 1575247064Sjfv * 1576247064Sjfv * LOCAL DEVICE | LINK PARTNER 1577247064Sjfv * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1578247064Sjfv *-------|---------|-------|---------|-------------------- 1579247064Sjfv * 1 | DC | 1 | DC | e1000_fc_full 1580247064Sjfv * 1581247064Sjfv */ 1582247064Sjfv if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1583247064Sjfv (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) { 1584247064Sjfv /* Now we need to check if the user selected Rx ONLY 1585247064Sjfv * of pause frames. In this case, we had to advertise 1586247064Sjfv * FULL flow control because we could not advertise Rx 1587247064Sjfv * ONLY. Hence, we must now check to see if we need to 1588247064Sjfv * turn OFF the TRANSMISSION of PAUSE frames. 1589247064Sjfv */ 1590247064Sjfv if (hw->fc.requested_mode == e1000_fc_full) { 1591247064Sjfv hw->fc.current_mode = e1000_fc_full; 1592247064Sjfv DEBUGOUT("Flow Control = FULL.\n"); 1593247064Sjfv } else { 1594247064Sjfv hw->fc.current_mode = e1000_fc_rx_pause; 1595247064Sjfv DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1596247064Sjfv } 1597247064Sjfv } 1598247064Sjfv /* For receiving PAUSE frames ONLY. 1599247064Sjfv * 1600247064Sjfv * LOCAL DEVICE | LINK PARTNER 1601247064Sjfv * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1602247064Sjfv *-------|---------|-------|---------|-------------------- 1603247064Sjfv * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1604247064Sjfv */ 1605247064Sjfv else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) && 1606247064Sjfv (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1607247064Sjfv (pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1608247064Sjfv (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1609247064Sjfv hw->fc.current_mode = e1000_fc_tx_pause; 1610247064Sjfv DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1611247064Sjfv } 1612247064Sjfv /* For transmitting PAUSE frames ONLY. 1613247064Sjfv * 1614247064Sjfv * LOCAL DEVICE | LINK PARTNER 1615247064Sjfv * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1616247064Sjfv *-------|---------|-------|---------|-------------------- 1617247064Sjfv * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1618247064Sjfv */ 1619247064Sjfv else if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1620247064Sjfv (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1621247064Sjfv !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1622247064Sjfv (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1623247064Sjfv hw->fc.current_mode = e1000_fc_rx_pause; 1624247064Sjfv DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1625247064Sjfv } else { 1626247064Sjfv /* Per the IEEE spec, at this point flow control 1627247064Sjfv * should be disabled. 1628247064Sjfv */ 1629247064Sjfv hw->fc.current_mode = e1000_fc_none; 1630247064Sjfv DEBUGOUT("Flow Control = NONE.\n"); 1631247064Sjfv } 1632247064Sjfv 1633247064Sjfv /* Now we call a subroutine to actually force the MAC 1634247064Sjfv * controller to use the correct flow control settings. 1635247064Sjfv */ 1636247064Sjfv pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1637247064Sjfv pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1638247064Sjfv E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg); 1639247064Sjfv 1640247064Sjfv ret_val = e1000_force_mac_fc_generic(hw); 1641247064Sjfv if (ret_val) { 1642247064Sjfv DEBUGOUT("Error forcing flow control settings\n"); 1643247064Sjfv return ret_val; 1644247064Sjfv } 1645247064Sjfv } 1646247064Sjfv 1647238148Sjfv return E1000_SUCCESS; 1648169240Sjfv} 1649169240Sjfv 1650169240Sjfv/** 1651176667Sjfv * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1652169589Sjfv * @hw: pointer to the HW structure 1653169589Sjfv * @speed: stores the current speed 1654169589Sjfv * @duplex: stores the current duplex 1655169240Sjfv * 1656169240Sjfv * Read the status register for the current speed/duplex and store the current 1657169240Sjfv * speed and duplex for copper connections. 1658169240Sjfv **/ 1659173788Sjfvs32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1660228386Sjfv u16 *duplex) 1661169240Sjfv{ 1662169240Sjfv u32 status; 1663169240Sjfv 1664169240Sjfv DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1665169240Sjfv 1666169240Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 1667169240Sjfv if (status & E1000_STATUS_SPEED_1000) { 1668169240Sjfv *speed = SPEED_1000; 1669169240Sjfv DEBUGOUT("1000 Mbs, "); 1670169240Sjfv } else if (status & E1000_STATUS_SPEED_100) { 1671169240Sjfv *speed = SPEED_100; 1672169240Sjfv DEBUGOUT("100 Mbs, "); 1673169240Sjfv } else { 1674169240Sjfv *speed = SPEED_10; 1675169240Sjfv DEBUGOUT("10 Mbs, "); 1676169240Sjfv } 1677169240Sjfv 1678169240Sjfv if (status & E1000_STATUS_FD) { 1679169240Sjfv *duplex = FULL_DUPLEX; 1680169240Sjfv DEBUGOUT("Full Duplex\n"); 1681169240Sjfv } else { 1682169240Sjfv *duplex = HALF_DUPLEX; 1683169240Sjfv DEBUGOUT("Half Duplex\n"); 1684169240Sjfv } 1685169240Sjfv 1686169240Sjfv return E1000_SUCCESS; 1687169240Sjfv} 1688169240Sjfv 1689169240Sjfv/** 1690176667Sjfv * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1691169589Sjfv * @hw: pointer to the HW structure 1692169589Sjfv * @speed: stores the current speed 1693169589Sjfv * @duplex: stores the current duplex 1694169240Sjfv * 1695169240Sjfv * Sets the speed and duplex to gigabit full duplex (the only possible option) 1696169240Sjfv * for fiber/serdes links. 1697169240Sjfv **/ 1698256200Sjfvs32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw, 1699228386Sjfv u16 *speed, u16 *duplex) 1700169240Sjfv{ 1701169240Sjfv DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1702169240Sjfv 1703169240Sjfv *speed = SPEED_1000; 1704169240Sjfv *duplex = FULL_DUPLEX; 1705169240Sjfv 1706169240Sjfv return E1000_SUCCESS; 1707169240Sjfv} 1708169240Sjfv 1709169240Sjfv/** 1710169240Sjfv * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1711169589Sjfv * @hw: pointer to the HW structure 1712169240Sjfv * 1713169589Sjfv * Acquire the HW semaphore to access the PHY or NVM 1714169240Sjfv **/ 1715173788Sjfvs32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1716169240Sjfv{ 1717169240Sjfv u32 swsm; 1718169240Sjfv s32 timeout = hw->nvm.word_size + 1; 1719169240Sjfv s32 i = 0; 1720169240Sjfv 1721169240Sjfv DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1722169240Sjfv 1723169589Sjfv /* Get the SW semaphore */ 1724169589Sjfv while (i < timeout) { 1725169589Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 1726169589Sjfv if (!(swsm & E1000_SWSM_SMBI)) 1727169589Sjfv break; 1728169589Sjfv 1729169589Sjfv usec_delay(50); 1730169589Sjfv i++; 1731169589Sjfv } 1732169589Sjfv 1733169589Sjfv if (i == timeout) { 1734169589Sjfv DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1735238148Sjfv return -E1000_ERR_NVM; 1736169589Sjfv } 1737169589Sjfv 1738169240Sjfv /* Get the FW semaphore. */ 1739169240Sjfv for (i = 0; i < timeout; i++) { 1740169240Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 1741169240Sjfv E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1742169240Sjfv 1743169240Sjfv /* Semaphore acquired if bit latched */ 1744169240Sjfv if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1745169240Sjfv break; 1746169240Sjfv 1747169240Sjfv usec_delay(50); 1748169240Sjfv } 1749169240Sjfv 1750169240Sjfv if (i == timeout) { 1751169240Sjfv /* Release semaphores */ 1752169240Sjfv e1000_put_hw_semaphore_generic(hw); 1753169240Sjfv DEBUGOUT("Driver can't access the NVM\n"); 1754238148Sjfv return -E1000_ERR_NVM; 1755169240Sjfv } 1756169240Sjfv 1757238148Sjfv return E1000_SUCCESS; 1758169240Sjfv} 1759169240Sjfv 1760169240Sjfv/** 1761169240Sjfv * e1000_put_hw_semaphore_generic - Release hardware semaphore 1762169589Sjfv * @hw: pointer to the HW structure 1763169240Sjfv * 1764169589Sjfv * Release hardware semaphore used to access the PHY or NVM 1765169240Sjfv **/ 1766173788Sjfvvoid e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1767169240Sjfv{ 1768169240Sjfv u32 swsm; 1769169240Sjfv 1770169240Sjfv DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1771169240Sjfv 1772169240Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 1773169240Sjfv 1774169589Sjfv swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1775169240Sjfv 1776169240Sjfv E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1777169240Sjfv} 1778169240Sjfv 1779169240Sjfv/** 1780169240Sjfv * e1000_get_auto_rd_done_generic - Check for auto read completion 1781169589Sjfv * @hw: pointer to the HW structure 1782169240Sjfv * 1783169240Sjfv * Check EEPROM for Auto Read done bit. 1784169240Sjfv **/ 1785173788Sjfvs32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1786169240Sjfv{ 1787169240Sjfv s32 i = 0; 1788169240Sjfv 1789169240Sjfv DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1790169240Sjfv 1791169240Sjfv while (i < AUTO_READ_DONE_TIMEOUT) { 1792169240Sjfv if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1793169240Sjfv break; 1794169240Sjfv msec_delay(1); 1795169240Sjfv i++; 1796169240Sjfv } 1797169240Sjfv 1798169240Sjfv if (i == AUTO_READ_DONE_TIMEOUT) { 1799169240Sjfv DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1800238148Sjfv return -E1000_ERR_RESET; 1801169240Sjfv } 1802169240Sjfv 1803238148Sjfv return E1000_SUCCESS; 1804169240Sjfv} 1805169240Sjfv 1806169240Sjfv/** 1807169240Sjfv * e1000_valid_led_default_generic - Verify a valid default LED config 1808169589Sjfv * @hw: pointer to the HW structure 1809169589Sjfv * @data: pointer to the NVM (EEPROM) 1810169240Sjfv * 1811169240Sjfv * Read the EEPROM for the current default LED configuration. If the 1812169240Sjfv * LED configuration is not valid, set to a valid LED configuration. 1813169240Sjfv **/ 1814173788Sjfvs32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1815169240Sjfv{ 1816169240Sjfv s32 ret_val; 1817169240Sjfv 1818169240Sjfv DEBUGFUNC("e1000_valid_led_default_generic"); 1819169240Sjfv 1820177867Sjfv ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1821169240Sjfv if (ret_val) { 1822169240Sjfv DEBUGOUT("NVM Read Error\n"); 1823238148Sjfv return ret_val; 1824169240Sjfv } 1825169240Sjfv 1826169240Sjfv if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1827169240Sjfv *data = ID_LED_DEFAULT; 1828169240Sjfv 1829238148Sjfv return E1000_SUCCESS; 1830169240Sjfv} 1831169240Sjfv 1832169240Sjfv/** 1833169240Sjfv * e1000_id_led_init_generic - 1834169589Sjfv * @hw: pointer to the HW structure 1835169240Sjfv * 1836169240Sjfv **/ 1837185353Sjfvs32 e1000_id_led_init_generic(struct e1000_hw *hw) 1838169240Sjfv{ 1839169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1840169240Sjfv s32 ret_val; 1841169240Sjfv const u32 ledctl_mask = 0x000000FF; 1842169240Sjfv const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1843169240Sjfv const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1844169240Sjfv u16 data, i, temp; 1845169240Sjfv const u16 led_mask = 0x0F; 1846169240Sjfv 1847169240Sjfv DEBUGFUNC("e1000_id_led_init_generic"); 1848169240Sjfv 1849177867Sjfv ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1850169240Sjfv if (ret_val) 1851238148Sjfv return ret_val; 1852169240Sjfv 1853169240Sjfv mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1854169240Sjfv mac->ledctl_mode1 = mac->ledctl_default; 1855169240Sjfv mac->ledctl_mode2 = mac->ledctl_default; 1856169240Sjfv 1857169240Sjfv for (i = 0; i < 4; i++) { 1858169240Sjfv temp = (data >> (i << 2)) & led_mask; 1859169240Sjfv switch (temp) { 1860169240Sjfv case ID_LED_ON1_DEF2: 1861169240Sjfv case ID_LED_ON1_ON2: 1862169240Sjfv case ID_LED_ON1_OFF2: 1863169240Sjfv mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1864169240Sjfv mac->ledctl_mode1 |= ledctl_on << (i << 3); 1865169240Sjfv break; 1866169240Sjfv case ID_LED_OFF1_DEF2: 1867169240Sjfv case ID_LED_OFF1_ON2: 1868169240Sjfv case ID_LED_OFF1_OFF2: 1869169240Sjfv mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1870169240Sjfv mac->ledctl_mode1 |= ledctl_off << (i << 3); 1871169240Sjfv break; 1872169240Sjfv default: 1873169240Sjfv /* Do nothing */ 1874169240Sjfv break; 1875169240Sjfv } 1876169240Sjfv switch (temp) { 1877169240Sjfv case ID_LED_DEF1_ON2: 1878169240Sjfv case ID_LED_ON1_ON2: 1879169240Sjfv case ID_LED_OFF1_ON2: 1880169240Sjfv mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1881169240Sjfv mac->ledctl_mode2 |= ledctl_on << (i << 3); 1882169240Sjfv break; 1883169240Sjfv case ID_LED_DEF1_OFF2: 1884169240Sjfv case ID_LED_ON1_OFF2: 1885169240Sjfv case ID_LED_OFF1_OFF2: 1886169240Sjfv mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1887169240Sjfv mac->ledctl_mode2 |= ledctl_off << (i << 3); 1888169240Sjfv break; 1889169240Sjfv default: 1890169240Sjfv /* Do nothing */ 1891169240Sjfv break; 1892169240Sjfv } 1893169240Sjfv } 1894169240Sjfv 1895238148Sjfv return E1000_SUCCESS; 1896169240Sjfv} 1897169240Sjfv 1898169240Sjfv/** 1899169240Sjfv * e1000_setup_led_generic - Configures SW controllable LED 1900169589Sjfv * @hw: pointer to the HW structure 1901169240Sjfv * 1902169240Sjfv * This prepares the SW controllable LED for use and saves the current state 1903169240Sjfv * of the LED so it can be later restored. 1904169240Sjfv **/ 1905173788Sjfvs32 e1000_setup_led_generic(struct e1000_hw *hw) 1906169240Sjfv{ 1907169240Sjfv u32 ledctl; 1908169240Sjfv 1909169240Sjfv DEBUGFUNC("e1000_setup_led_generic"); 1910169240Sjfv 1911238148Sjfv if (hw->mac.ops.setup_led != e1000_setup_led_generic) 1912238148Sjfv return -E1000_ERR_CONFIG; 1913169240Sjfv 1914173788Sjfv if (hw->phy.media_type == e1000_media_type_fiber) { 1915169240Sjfv ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1916169240Sjfv hw->mac.ledctl_default = ledctl; 1917169240Sjfv /* Turn off LED0 */ 1918228386Sjfv ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | 1919228386Sjfv E1000_LEDCTL_LED0_MODE_MASK); 1920169240Sjfv ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1921228386Sjfv E1000_LEDCTL_LED0_MODE_SHIFT); 1922169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1923173788Sjfv } else if (hw->phy.media_type == e1000_media_type_copper) { 1924169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1925169240Sjfv } 1926169240Sjfv 1927238148Sjfv return E1000_SUCCESS; 1928169240Sjfv} 1929169240Sjfv 1930169240Sjfv/** 1931169240Sjfv * e1000_cleanup_led_generic - Set LED config to default operation 1932169589Sjfv * @hw: pointer to the HW structure 1933169240Sjfv * 1934169240Sjfv * Remove the current LED configuration and set the LED configuration 1935169240Sjfv * to the default value, saved from the EEPROM. 1936169240Sjfv **/ 1937173788Sjfvs32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1938169240Sjfv{ 1939169240Sjfv DEBUGFUNC("e1000_cleanup_led_generic"); 1940169240Sjfv 1941169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1942203049Sjfv return E1000_SUCCESS; 1943169240Sjfv} 1944169240Sjfv 1945169240Sjfv/** 1946169240Sjfv * e1000_blink_led_generic - Blink LED 1947169589Sjfv * @hw: pointer to the HW structure 1948169240Sjfv * 1949176667Sjfv * Blink the LEDs which are set to be on. 1950169240Sjfv **/ 1951173788Sjfvs32 e1000_blink_led_generic(struct e1000_hw *hw) 1952169240Sjfv{ 1953169240Sjfv u32 ledctl_blink = 0; 1954169240Sjfv u32 i; 1955169240Sjfv 1956169240Sjfv DEBUGFUNC("e1000_blink_led_generic"); 1957169240Sjfv 1958173788Sjfv if (hw->phy.media_type == e1000_media_type_fiber) { 1959169240Sjfv /* always blink LED0 for PCI-E fiber */ 1960169240Sjfv ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1961169240Sjfv (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1962169240Sjfv } else { 1963247064Sjfv /* Set the blink bit for each LED that's "on" (0x0E) 1964247064Sjfv * (or "off" if inverted) in ledctl_mode2. The blink 1965247064Sjfv * logic in hardware only works when mode is set to "on" 1966247064Sjfv * so it must be changed accordingly when the mode is 1967247064Sjfv * "off" and inverted. 1968173788Sjfv */ 1969169240Sjfv ledctl_blink = hw->mac.ledctl_mode2; 1970247064Sjfv for (i = 0; i < 32; i += 8) { 1971247064Sjfv u32 mode = (hw->mac.ledctl_mode2 >> i) & 1972247064Sjfv E1000_LEDCTL_LED0_MODE_MASK; 1973247064Sjfv u32 led_default = hw->mac.ledctl_default >> i; 1974247064Sjfv 1975247064Sjfv if ((!(led_default & E1000_LEDCTL_LED0_IVRT) && 1976247064Sjfv (mode == E1000_LEDCTL_MODE_LED_ON)) || 1977247064Sjfv ((led_default & E1000_LEDCTL_LED0_IVRT) && 1978247064Sjfv (mode == E1000_LEDCTL_MODE_LED_OFF))) { 1979247064Sjfv ledctl_blink &= 1980247064Sjfv ~(E1000_LEDCTL_LED0_MODE_MASK << i); 1981247064Sjfv ledctl_blink |= (E1000_LEDCTL_LED0_BLINK | 1982247064Sjfv E1000_LEDCTL_MODE_LED_ON) << i; 1983247064Sjfv } 1984247064Sjfv } 1985169240Sjfv } 1986169240Sjfv 1987169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1988169240Sjfv 1989169240Sjfv return E1000_SUCCESS; 1990169240Sjfv} 1991169240Sjfv 1992169240Sjfv/** 1993169240Sjfv * e1000_led_on_generic - Turn LED on 1994169589Sjfv * @hw: pointer to the HW structure 1995169240Sjfv * 1996169240Sjfv * Turn LED on. 1997169240Sjfv **/ 1998173788Sjfvs32 e1000_led_on_generic(struct e1000_hw *hw) 1999169240Sjfv{ 2000169240Sjfv u32 ctrl; 2001169240Sjfv 2002169240Sjfv DEBUGFUNC("e1000_led_on_generic"); 2003169240Sjfv 2004173788Sjfv switch (hw->phy.media_type) { 2005169240Sjfv case e1000_media_type_fiber: 2006169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 2007169240Sjfv ctrl &= ~E1000_CTRL_SWDPIN0; 2008169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 2009169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2010169240Sjfv break; 2011169240Sjfv case e1000_media_type_copper: 2012169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 2013169240Sjfv break; 2014169240Sjfv default: 2015169240Sjfv break; 2016169240Sjfv } 2017169240Sjfv 2018169240Sjfv return E1000_SUCCESS; 2019169240Sjfv} 2020169240Sjfv 2021169240Sjfv/** 2022169240Sjfv * e1000_led_off_generic - Turn LED off 2023169589Sjfv * @hw: pointer to the HW structure 2024169240Sjfv * 2025169240Sjfv * Turn LED off. 2026169240Sjfv **/ 2027173788Sjfvs32 e1000_led_off_generic(struct e1000_hw *hw) 2028169240Sjfv{ 2029169240Sjfv u32 ctrl; 2030169240Sjfv 2031169240Sjfv DEBUGFUNC("e1000_led_off_generic"); 2032169240Sjfv 2033173788Sjfv switch (hw->phy.media_type) { 2034169240Sjfv case e1000_media_type_fiber: 2035169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 2036169240Sjfv ctrl |= E1000_CTRL_SWDPIN0; 2037169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 2038169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2039169240Sjfv break; 2040169240Sjfv case e1000_media_type_copper: 2041169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 2042169240Sjfv break; 2043169240Sjfv default: 2044169240Sjfv break; 2045169240Sjfv } 2046169240Sjfv 2047169240Sjfv return E1000_SUCCESS; 2048169240Sjfv} 2049169240Sjfv 2050169240Sjfv/** 2051169240Sjfv * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 2052169589Sjfv * @hw: pointer to the HW structure 2053169589Sjfv * @no_snoop: bitmap of snoop events 2054169240Sjfv * 2055169240Sjfv * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 2056169240Sjfv **/ 2057173788Sjfvvoid e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 2058169240Sjfv{ 2059169240Sjfv u32 gcr; 2060169240Sjfv 2061169240Sjfv DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 2062169240Sjfv 2063169240Sjfv if (hw->bus.type != e1000_bus_type_pci_express) 2064238148Sjfv return; 2065169240Sjfv 2066169240Sjfv if (no_snoop) { 2067169240Sjfv gcr = E1000_READ_REG(hw, E1000_GCR); 2068169240Sjfv gcr &= ~(PCIE_NO_SNOOP_ALL); 2069169240Sjfv gcr |= no_snoop; 2070169240Sjfv E1000_WRITE_REG(hw, E1000_GCR, gcr); 2071169240Sjfv } 2072169240Sjfv} 2073169240Sjfv 2074169240Sjfv/** 2075169240Sjfv * e1000_disable_pcie_master_generic - Disables PCI-express master access 2076169589Sjfv * @hw: pointer to the HW structure 2077169240Sjfv * 2078200243Sjfv * Returns E1000_SUCCESS if successful, else returns -10 2079176667Sjfv * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 2080169240Sjfv * the master requests to be disabled. 2081169240Sjfv * 2082169240Sjfv * Disables PCI-Express master access and verifies there are no pending 2083169240Sjfv * requests. 2084169240Sjfv **/ 2085173788Sjfvs32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 2086169240Sjfv{ 2087169240Sjfv u32 ctrl; 2088169240Sjfv s32 timeout = MASTER_DISABLE_TIMEOUT; 2089169240Sjfv 2090169240Sjfv DEBUGFUNC("e1000_disable_pcie_master_generic"); 2091169240Sjfv 2092169240Sjfv if (hw->bus.type != e1000_bus_type_pci_express) 2093238148Sjfv return E1000_SUCCESS; 2094169240Sjfv 2095169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 2096169240Sjfv ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2097169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2098169240Sjfv 2099169240Sjfv while (timeout) { 2100169240Sjfv if (!(E1000_READ_REG(hw, E1000_STATUS) & 2101267935Sjfv E1000_STATUS_GIO_MASTER_ENABLE) || 2102267935Sjfv E1000_REMOVED(hw->hw_addr)) 2103169240Sjfv break; 2104169240Sjfv usec_delay(100); 2105169240Sjfv timeout--; 2106169240Sjfv } 2107169240Sjfv 2108169240Sjfv if (!timeout) { 2109169240Sjfv DEBUGOUT("Master requests are pending.\n"); 2110238148Sjfv return -E1000_ERR_MASTER_REQUESTS_PENDING; 2111169240Sjfv } 2112169240Sjfv 2113238148Sjfv return E1000_SUCCESS; 2114169240Sjfv} 2115169240Sjfv 2116169240Sjfv/** 2117169240Sjfv * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2118169589Sjfv * @hw: pointer to the HW structure 2119169240Sjfv * 2120169240Sjfv * Reset the Adaptive Interframe Spacing throttle to default values. 2121169240Sjfv **/ 2122173788Sjfvvoid e1000_reset_adaptive_generic(struct e1000_hw *hw) 2123169240Sjfv{ 2124169240Sjfv struct e1000_mac_info *mac = &hw->mac; 2125169240Sjfv 2126169240Sjfv DEBUGFUNC("e1000_reset_adaptive_generic"); 2127169240Sjfv 2128169240Sjfv if (!mac->adaptive_ifs) { 2129169240Sjfv DEBUGOUT("Not in Adaptive IFS mode!\n"); 2130238148Sjfv return; 2131169240Sjfv } 2132169240Sjfv 2133185353Sjfv mac->current_ifs_val = 0; 2134185353Sjfv mac->ifs_min_val = IFS_MIN; 2135185353Sjfv mac->ifs_max_val = IFS_MAX; 2136185353Sjfv mac->ifs_step_size = IFS_STEP; 2137185353Sjfv mac->ifs_ratio = IFS_RATIO; 2138169240Sjfv 2139169240Sjfv mac->in_ifs_mode = FALSE; 2140169240Sjfv E1000_WRITE_REG(hw, E1000_AIT, 0); 2141169240Sjfv} 2142169240Sjfv 2143169240Sjfv/** 2144169240Sjfv * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2145169589Sjfv * @hw: pointer to the HW structure 2146169240Sjfv * 2147169240Sjfv * Update the Adaptive Interframe Spacing Throttle value based on the 2148169240Sjfv * time between transmitted packets and time between collisions. 2149169240Sjfv **/ 2150173788Sjfvvoid e1000_update_adaptive_generic(struct e1000_hw *hw) 2151169240Sjfv{ 2152169240Sjfv struct e1000_mac_info *mac = &hw->mac; 2153169240Sjfv 2154169240Sjfv DEBUGFUNC("e1000_update_adaptive_generic"); 2155169240Sjfv 2156169240Sjfv if (!mac->adaptive_ifs) { 2157169240Sjfv DEBUGOUT("Not in Adaptive IFS mode!\n"); 2158238148Sjfv return; 2159169240Sjfv } 2160169240Sjfv 2161169240Sjfv if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2162169240Sjfv if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2163169240Sjfv mac->in_ifs_mode = TRUE; 2164169240Sjfv if (mac->current_ifs_val < mac->ifs_max_val) { 2165169240Sjfv if (!mac->current_ifs_val) 2166169240Sjfv mac->current_ifs_val = mac->ifs_min_val; 2167169240Sjfv else 2168169240Sjfv mac->current_ifs_val += 2169169240Sjfv mac->ifs_step_size; 2170228386Sjfv E1000_WRITE_REG(hw, E1000_AIT, 2171228386Sjfv mac->current_ifs_val); 2172169240Sjfv } 2173169240Sjfv } 2174169240Sjfv } else { 2175169240Sjfv if (mac->in_ifs_mode && 2176169240Sjfv (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2177169240Sjfv mac->current_ifs_val = 0; 2178169240Sjfv mac->in_ifs_mode = FALSE; 2179169240Sjfv E1000_WRITE_REG(hw, E1000_AIT, 0); 2180169240Sjfv } 2181169240Sjfv } 2182169240Sjfv} 2183169240Sjfv 2184169240Sjfv/** 2185169240Sjfv * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2186169589Sjfv * @hw: pointer to the HW structure 2187169240Sjfv * 2188176667Sjfv * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2189169240Sjfv * set, which is forced to MDI mode only. 2190169240Sjfv **/ 2191200243Sjfvstatic s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2192169240Sjfv{ 2193169240Sjfv DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2194169240Sjfv 2195169240Sjfv if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2196169240Sjfv DEBUGOUT("Invalid MDI setting detected\n"); 2197169240Sjfv hw->phy.mdix = 1; 2198238148Sjfv return -E1000_ERR_CONFIG; 2199169240Sjfv } 2200169240Sjfv 2201238148Sjfv return E1000_SUCCESS; 2202169240Sjfv} 2203169240Sjfv 2204169240Sjfv/** 2205247064Sjfv * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings 2206247064Sjfv * @hw: pointer to the HW structure 2207247064Sjfv * 2208247064Sjfv * Validate the MDI/MDIx setting, allowing for auto-crossover during forced 2209247064Sjfv * operation. 2210247064Sjfv **/ 2211256200Sjfvs32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw) 2212247064Sjfv{ 2213247064Sjfv DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic"); 2214247064Sjfv 2215247064Sjfv return E1000_SUCCESS; 2216247064Sjfv} 2217247064Sjfv 2218247064Sjfv/** 2219169240Sjfv * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2220169589Sjfv * @hw: pointer to the HW structure 2221169589Sjfv * @reg: 32bit register offset such as E1000_SCTL 2222169589Sjfv * @offset: register offset to write to 2223169589Sjfv * @data: data to write at register offset 2224169240Sjfv * 2225169240Sjfv * Writes an address/data control type register. There are several of these 2226169240Sjfv * and they all have the format address << 8 | data and bit 31 is polled for 2227169240Sjfv * completion. 2228169240Sjfv **/ 2229173788Sjfvs32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2230228386Sjfv u32 offset, u8 data) 2231169240Sjfv{ 2232169240Sjfv u32 i, regvalue = 0; 2233169240Sjfv 2234169240Sjfv DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2235169240Sjfv 2236169240Sjfv /* Set up the address and data */ 2237169240Sjfv regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2238169240Sjfv E1000_WRITE_REG(hw, reg, regvalue); 2239169240Sjfv 2240169240Sjfv /* Poll the ready bit to see if the MDI read completed */ 2241169240Sjfv for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2242169240Sjfv usec_delay(5); 2243169240Sjfv regvalue = E1000_READ_REG(hw, reg); 2244169240Sjfv if (regvalue & E1000_GEN_CTL_READY) 2245169240Sjfv break; 2246169240Sjfv } 2247169240Sjfv if (!(regvalue & E1000_GEN_CTL_READY)) { 2248169240Sjfv DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2249238148Sjfv return -E1000_ERR_PHY; 2250169240Sjfv } 2251169240Sjfv 2252238148Sjfv return E1000_SUCCESS; 2253169240Sjfv} 2254