e1000_82571.c revision 169248
1/******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/dev/em/e1000_82571.c 169248 2007-05-04 13:30:44Z rwatson $"); 36 37 38/* e1000_82571 39 * e1000_82572 40 * e1000_82573 41 */ 42 43#include "e1000_82571.h" 44 45void e1000_init_function_pointers_82571(struct e1000_hw *hw); 46 47STATIC s32 e1000_init_phy_params_82571(struct e1000_hw *hw); 48STATIC s32 e1000_init_nvm_params_82571(struct e1000_hw *hw); 49STATIC s32 e1000_init_mac_params_82571(struct e1000_hw *hw); 50STATIC s32 e1000_acquire_nvm_82571(struct e1000_hw *hw); 51STATIC void e1000_release_nvm_82571(struct e1000_hw *hw); 52STATIC s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, 53 u16 words, u16 *data); 54STATIC s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw); 55STATIC s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw); 56STATIC s32 e1000_get_cfg_done_82571(struct e1000_hw *hw); 57STATIC s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, 58 boolean_t active); 59STATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw); 60STATIC s32 e1000_init_hw_82571(struct e1000_hw *hw); 61STATIC void e1000_clear_vfta_82571(struct e1000_hw *hw); 62STATIC void e1000_mc_addr_list_update_82571(struct e1000_hw *hw, 63 u8 *mc_addr_list, u32 mc_addr_count, 64 u32 rar_used_count, u32 rar_count); 65STATIC s32 e1000_setup_link_82571(struct e1000_hw *hw); 66STATIC s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); 67STATIC s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); 68STATIC s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data); 69STATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); 70static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); 71static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); 72static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); 73static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 74 u16 words, u16 *data); 75 76struct e1000_dev_spec_82571 { 77 boolean_t laa_is_present; 78}; 79 80/** 81 * e1000_init_phy_params_82571 - Init PHY func ptrs. 82 * @hw - pointer to the HW structure 83 * 84 * This is a function pointer entry point called by the api module. 85 **/ 86STATIC s32 87e1000_init_phy_params_82571(struct e1000_hw *hw) 88{ 89 struct e1000_phy_info *phy = &hw->phy; 90 struct e1000_functions *func = &hw->func; 91 s32 ret_val = E1000_SUCCESS; 92 93 DEBUGFUNC("e1000_init_phy_params_82571"); 94 95 if (hw->media_type != e1000_media_type_copper) { 96 phy->type = e1000_phy_none; 97 goto out; 98 } 99 100 phy->addr = 1; 101 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 102 phy->reset_delay_us = 100; 103 104 func->acquire_phy = e1000_get_hw_semaphore_generic; 105 func->check_polarity = e1000_check_polarity_igp; 106 func->check_reset_block = e1000_check_reset_block_generic; 107 func->release_phy = e1000_put_hw_semaphore_generic; 108 func->reset_phy = e1000_phy_hw_reset_generic; 109 func->set_d0_lplu_state = e1000_set_d0_lplu_state_82571; 110 func->set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 111 112 switch (hw->mac.type) { 113 case e1000_82571: 114 case e1000_82572: 115 phy->type = e1000_phy_igp_2; 116 func->get_cfg_done = e1000_get_cfg_done_82571; 117 func->get_phy_info = e1000_get_phy_info_igp; 118 func->force_speed_duplex = e1000_phy_force_speed_duplex_igp; 119 func->get_cable_length = e1000_get_cable_length_igp_2; 120 func->read_phy_reg = e1000_read_phy_reg_igp; 121 func->write_phy_reg = e1000_write_phy_reg_igp; 122 break; 123 case e1000_82573: 124 phy->type = e1000_phy_m88; 125 func->get_cfg_done = e1000_get_cfg_done_generic; 126 func->get_phy_info = e1000_get_phy_info_m88; 127 func->commit_phy = e1000_phy_sw_reset_generic; 128 func->force_speed_duplex = e1000_phy_force_speed_duplex_m88; 129 func->get_cable_length = e1000_get_cable_length_m88; 130 func->read_phy_reg = e1000_read_phy_reg_m88; 131 func->write_phy_reg = e1000_write_phy_reg_m88; 132 break; 133 default: 134 ret_val = -E1000_ERR_PHY; 135 goto out; 136 break; 137 } 138 139 /* This can only be done after all function pointers are setup. */ 140 ret_val = e1000_get_phy_id_82571(hw); 141 142 /* Verify phy id */ 143 switch (hw->mac.type) { 144 case e1000_82571: 145 case e1000_82572: 146 if (phy->id != IGP01E1000_I_PHY_ID) { 147 ret_val = -E1000_ERR_PHY; 148 goto out; 149 } 150 break; 151 case e1000_82573: 152 if (phy->id != M88E1111_I_PHY_ID) { 153 ret_val = -E1000_ERR_PHY; 154 goto out; 155 } 156 break; 157 default: 158 ret_val = -E1000_ERR_PHY; 159 goto out; 160 break; 161 } 162 163out: 164 return ret_val; 165} 166 167/** 168 * e1000_init_nvm_params_82571 - Init NVM func ptrs. 169 * @hw - pointer to the HW structure 170 * 171 * This is a function pointer entry point called by the api module. 172 **/ 173STATIC s32 174e1000_init_nvm_params_82571(struct e1000_hw *hw) 175{ 176 struct e1000_nvm_info *nvm = &hw->nvm; 177 struct e1000_functions *func = &hw->func; 178 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 179 u16 size; 180 181 DEBUGFUNC("e1000_init_nvm_params_82571"); 182 183 nvm->opcode_bits = 8; 184 nvm->delay_usec = 1; 185 switch (nvm->override) { 186 case e1000_nvm_override_spi_large: 187 nvm->page_size = 32; 188 nvm->address_bits = 16; 189 break; 190 case e1000_nvm_override_spi_small: 191 nvm->page_size = 8; 192 nvm->address_bits = 8; 193 break; 194 default: 195 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 196 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 197 break; 198 } 199 200 switch (hw->mac.type) { 201 case e1000_82573: 202 if (((eecd >> 15) & 0x3) == 0x3) { 203 nvm->type = e1000_nvm_flash_hw; 204 nvm->word_size = 2048; 205 /* Autonomous Flash update bit must be cleared due 206 * to Flash update issue. 207 */ 208 eecd &= ~E1000_EECD_AUPDEN; 209 E1000_WRITE_REG(hw, E1000_EECD, eecd); 210 break; 211 } 212 /* Fall Through */ 213 default: 214 nvm->type = e1000_nvm_eeprom_spi; 215 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 216 E1000_EECD_SIZE_EX_SHIFT); 217 /* Added to a constant, "size" becomes the left-shift value 218 * for setting word_size. 219 */ 220 size += NVM_WORD_SIZE_BASE_SHIFT; 221 nvm->word_size = 1 << size; 222 break; 223 } 224 225 /* Function Pointers */ 226 func->acquire_nvm = e1000_acquire_nvm_82571; 227 func->read_nvm = (hw->mac.type == e1000_82573) 228 ? e1000_read_nvm_eerd 229 : e1000_read_nvm_spi; 230 func->release_nvm = e1000_release_nvm_82571; 231 func->update_nvm = e1000_update_nvm_checksum_82571; 232 func->validate_nvm = e1000_validate_nvm_checksum_82571; 233 func->valid_led_default = e1000_valid_led_default_82571; 234 func->write_nvm = e1000_write_nvm_82571; 235 236 return E1000_SUCCESS; 237} 238 239/** 240 * e1000_init_mac_params_82571 - Init MAC func ptrs. 241 * @hw - pointer to the HW structure 242 * 243 * This is a function pointer entry point called by the api module. 244 **/ 245STATIC s32 246e1000_init_mac_params_82571(struct e1000_hw *hw) 247{ 248 struct e1000_mac_info *mac = &hw->mac; 249 struct e1000_functions *func = &hw->func; 250 s32 ret_val = E1000_SUCCESS; 251 252 DEBUGFUNC("e1000_init_mac_params_82571"); 253 254 /* Set media type */ 255 switch (hw->device_id) { 256 case E1000_DEV_ID_82571EB_FIBER: 257 case E1000_DEV_ID_82572EI_FIBER: 258 case E1000_DEV_ID_82571EB_QUAD_FIBER: 259 hw->media_type = e1000_media_type_fiber; 260 break; 261 case E1000_DEV_ID_82571EB_SERDES: 262 case E1000_DEV_ID_82572EI_SERDES: 263 hw->media_type = e1000_media_type_internal_serdes; 264 break; 265 default: 266 hw->media_type = e1000_media_type_copper; 267 break; 268 } 269 270 /* Set mta register count */ 271 mac->mta_reg_count = 128; 272 /* Set rar entry count */ 273 mac->rar_entry_count = E1000_RAR_ENTRIES; 274 /* Set if part includes ASF firmware */ 275 mac->asf_firmware_present = TRUE; 276 /* Set if manageability features are enabled. */ 277 mac->arc_subsystem_valid = 278 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 279 ? TRUE : FALSE; 280 281 /* Function pointers */ 282 283 /* bus type/speed/width */ 284 func->get_bus_info = e1000_get_bus_info_pcie_generic; 285 /* reset */ 286 func->reset_hw = e1000_reset_hw_82571; 287 /* hw initialization */ 288 func->init_hw = e1000_init_hw_82571; 289 /* link setup */ 290 func->setup_link = e1000_setup_link_82571; 291 /* physical interface link setup */ 292 func->setup_physical_interface = 293 (hw->media_type == e1000_media_type_copper) 294 ? e1000_setup_copper_link_82571 295 : e1000_setup_fiber_serdes_link_82571; 296 /* check for link */ 297 switch (hw->media_type) { 298 case e1000_media_type_copper: 299 func->check_for_link = e1000_check_for_copper_link_generic; 300 break; 301 case e1000_media_type_fiber: 302 func->check_for_link = e1000_check_for_fiber_link_generic; 303 break; 304 case e1000_media_type_internal_serdes: 305 func->check_for_link = e1000_check_for_serdes_link_generic; 306 break; 307 default: 308 ret_val = -E1000_ERR_CONFIG; 309 goto out; 310 break; 311 } 312 /* check management mode */ 313 func->check_mng_mode = e1000_check_mng_mode_generic; 314 /* multicast address update */ 315 func->mc_addr_list_update = e1000_mc_addr_list_update_82571; 316 /* writing VFTA */ 317 func->write_vfta = e1000_write_vfta_generic; 318 /* clearing VFTA */ 319 func->clear_vfta = e1000_clear_vfta_82571; 320 /* setting MTA */ 321 func->mta_set = e1000_mta_set_generic; 322 /* blink LED */ 323 func->blink_led = e1000_blink_led_generic; 324 /* setup LED */ 325 func->setup_led = e1000_setup_led_generic; 326 /* cleanup LED */ 327 func->cleanup_led = e1000_cleanup_led_generic; 328 /* turn on/off LED */ 329 func->led_on = e1000_led_on_generic; 330 func->led_off = e1000_led_off_generic; 331 /* remove device */ 332 func->remove_device = e1000_remove_device_generic; 333 /* clear hardware counters */ 334 func->clear_hw_cntrs = e1000_clear_hw_cntrs_82571; 335 /* link info */ 336 func->get_link_up_info = 337 (hw->media_type == e1000_media_type_copper) 338 ? e1000_get_speed_and_duplex_copper_generic 339 : e1000_get_speed_and_duplex_fiber_serdes_generic; 340 341 hw->dev_spec_size = sizeof(struct e1000_dev_spec_82571); 342 343 /* Device-specific structure allocation */ 344 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 345 346out: 347 return ret_val; 348} 349 350/** 351 * e1000_init_function_pointers_82571 - Init func ptrs. 352 * @hw - pointer to the HW structure 353 * 354 * The only function explicitly called by the api module to initialize 355 * all function pointers and parameters. 356 **/ 357void 358e1000_init_function_pointers_82571(struct e1000_hw *hw) 359{ 360 DEBUGFUNC("e1000_init_function_pointers_82571"); 361 362 hw->func.init_mac_params = e1000_init_mac_params_82571; 363 hw->func.init_nvm_params = e1000_init_nvm_params_82571; 364 hw->func.init_phy_params = e1000_init_phy_params_82571; 365} 366 367/** 368 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision 369 * @hw - pointer to the HW structure 370 * 371 * Reads the PHY registers and stores the PHY ID and possibly the PHY 372 * revision in the hardware structure. 373 **/ 374static s32 375e1000_get_phy_id_82571(struct e1000_hw *hw) 376{ 377 struct e1000_phy_info *phy = &hw->phy; 378 s32 ret_val = E1000_SUCCESS; 379 380 DEBUGFUNC("e1000_get_phy_id_82571"); 381 382 switch (hw->mac.type) { 383 case e1000_82571: 384 case e1000_82572: 385 /* The 82571 firmware may still be configuring the PHY. 386 * In this case, we cannot access the PHY until the 387 * configuration is done. So we explicitly set the 388 * PHY ID. */ 389 phy->id = IGP01E1000_I_PHY_ID; 390 break; 391 case e1000_82573: 392 ret_val = e1000_get_phy_id(hw); 393 break; 394 default: 395 ret_val = -E1000_ERR_PHY; 396 break; 397 } 398 399 return ret_val; 400} 401 402/** 403 * e1000_acquire_nvm_82571 - Request for access to the EEPROM 404 * @hw - pointer to the HW structure 405 * 406 * To gain access to the EEPROM, first we must obtain a hardware semaphore. 407 * Then for non-82573 hardware, set the EEPROM access request bit and wait 408 * for EEPROM access grant bit. If the access grant bit is not set, release 409 * hardware semaphore. 410 **/ 411STATIC s32 412e1000_acquire_nvm_82571(struct e1000_hw *hw) 413{ 414 s32 ret_val; 415 416 DEBUGFUNC("e1000_acquire_nvm_82571"); 417 418 ret_val = e1000_get_hw_semaphore_generic(hw); 419 if (ret_val) 420 goto out; 421 422 if (hw->mac.type != e1000_82573) 423 ret_val = e1000_acquire_nvm_generic(hw); 424 425 if (ret_val) 426 e1000_put_hw_semaphore_generic(hw); 427 428out: 429 return ret_val; 430} 431 432/** 433 * e1000_release_nvm_82571 - Release exclusive access to EEPROM 434 * @hw - pointer to the HW structure 435 * 436 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 437 **/ 438STATIC void 439e1000_release_nvm_82571(struct e1000_hw *hw) 440{ 441 DEBUGFUNC("e1000_release_nvm_82571"); 442 443 e1000_release_nvm_generic(hw); 444 e1000_put_hw_semaphore_generic(hw); 445} 446 447/** 448 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface 449 * @hw - pointer to the HW structure 450 * @offset - offset within the EEPROM to be written to 451 * @words - number of words to write 452 * @data - 16 bit word(s) to be written to the EEPROM 453 * 454 * For non-82573 silicon, write data to EEPROM at offset using SPI interface. 455 * 456 * If e1000_update_nvm_checksum is not called after this function, the 457 * EEPROM will most likley contain an invalid checksum. 458 **/ 459STATIC s32 460e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 461{ 462 s32 ret_val = E1000_SUCCESS; 463 464 DEBUGFUNC("e1000_write_nvm_82571"); 465 466 switch (hw->mac.type) { 467 case e1000_82573: 468 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); 469 break; 470 case e1000_82571: 471 case e1000_82572: 472 ret_val = e1000_write_nvm_spi(hw, offset, words, data); 473 break; 474 default: 475 ret_val = -E1000_ERR_NVM; 476 break; 477 } 478 479 return ret_val; 480} 481 482/** 483 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum 484 * @hw - pointer to the HW structure 485 * 486 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 487 * up to the checksum. Then calculates the EEPROM checksum and writes the 488 * value to the EEPROM. 489 **/ 490STATIC s32 491e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 492{ 493 u32 eecd; 494 s32 ret_val; 495 u16 i; 496 497 DEBUGFUNC("e1000_update_nvm_checksum_82571"); 498 499 ret_val = e1000_update_nvm_checksum_generic(hw); 500 if (ret_val) 501 goto out; 502 503 /* If our nvm is an EEPROM, then we're done 504 * otherwise, commit the checksum to the flash NVM. */ 505 if (hw->nvm.type != e1000_nvm_flash_hw) 506 goto out; 507 508 /* Check for pending operations. */ 509 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 510 msec_delay(1); 511 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 512 break; 513 } 514 515 if (i == E1000_FLASH_UPDATES) { 516 ret_val = -E1000_ERR_NVM; 517 goto out; 518 } 519 520 /* Reset the firmware if using STM opcode. */ 521 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) { 522 /* The enabling of and the actual reset must be done 523 * in two write cycles. 524 */ 525 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE); 526 E1000_WRITE_FLUSH(hw); 527 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET); 528 } 529 530 /* Commit the write to flash */ 531 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD; 532 E1000_WRITE_REG(hw, E1000_EECD, eecd); 533 534 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 535 msec_delay(1); 536 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 537 break; 538 } 539 540 if (i == E1000_FLASH_UPDATES) { 541 ret_val = -E1000_ERR_NVM; 542 goto out; 543 } 544 545out: 546 return ret_val; 547} 548 549/** 550 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum 551 * @hw - pointer to the HW structure 552 * 553 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 554 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 555 **/ 556STATIC s32 557e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) 558{ 559 DEBUGFUNC("e1000_validate_nvm_checksum_82571"); 560 561 if (hw->nvm.type == e1000_nvm_flash_hw) 562 e1000_fix_nvm_checksum_82571(hw); 563 564 return e1000_validate_nvm_checksum_generic(hw); 565} 566 567/** 568 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon 569 * @hw - pointer to the HW structure 570 * @offset - offset within the EEPROM to be written to 571 * @words - number of words to write 572 * @data - 16 bit word(s) to be written to the EEPROM 573 * 574 * After checking for invalid values, poll the EEPROM to ensure the previous 575 * command has completed before trying to write the next word. After write 576 * poll for completion. 577 * 578 * If e1000_update_nvm_checksum is not called after this function, the 579 * EEPROM will most likley contain an invalid checksum. 580 **/ 581static s32 582e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, u16 words, 583 u16 *data) 584{ 585 struct e1000_nvm_info *nvm = &hw->nvm; 586 u32 i, eewr = 0; 587 s32 ret_val = 0; 588 589 DEBUGFUNC("e1000_write_nvm_eewr_82571"); 590 591 /* A check for invalid values: offset too large, too many words, 592 * and not enough words. */ 593 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 594 (words == 0)) { 595 DEBUGOUT("nvm parameter(s) out of bounds\n"); 596 ret_val = -E1000_ERR_NVM; 597 goto out; 598 } 599 600 for (i = 0; i < words; i++) { 601 eewr = (data[i] << E1000_NVM_RW_REG_DATA) | 602 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | 603 E1000_NVM_RW_REG_START; 604 605 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 606 if (ret_val) 607 break; 608 609 E1000_WRITE_REG(hw, E1000_EEWR, eewr); 610 611 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 612 if (ret_val) 613 break; 614 } 615 616out: 617 return ret_val; 618} 619 620/** 621 * e1000_get_cfg_done_82571 - Poll for configuration done 622 * @hw - pointer to the HW structure 623 * 624 * Reads the management control register for the config done bit to be set. 625 **/ 626STATIC s32 627e1000_get_cfg_done_82571(struct e1000_hw *hw) 628{ 629 s32 timeout = PHY_CFG_TIMEOUT; 630 s32 ret_val = E1000_SUCCESS; 631 632 DEBUGFUNC("e1000_get_cfg_done_82571"); 633 634 while (timeout) { 635 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0) 636 break; 637 msec_delay(1); 638 timeout--; 639 } 640 if (!timeout) { 641 DEBUGOUT("MNG configuration cycle has not completed.\n"); 642 ret_val = -E1000_ERR_RESET; 643 goto out; 644 } 645 646out: 647 return ret_val; 648} 649 650/** 651 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state 652 * @hw - pointer to the HW structure 653 * @active - TRUE to enable LPLU, FALSE to disable 654 * 655 * Sets the LPLU D0 state according to the active flag. When activating LPLU 656 * this function also disables smart speed and vice versa. LPLU will not be 657 * activated unless the device autonegotiation advertisement meets standards 658 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function 659 * pointer entry point only called by PHY setup routines. 660 **/ 661STATIC s32 662e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, boolean_t active) 663{ 664 struct e1000_phy_info *phy = &hw->phy; 665 s32 ret_val; 666 u16 data; 667 668 DEBUGFUNC("e1000_set_d0_lplu_state_82571"); 669 670 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 671 if (ret_val) 672 goto out; 673 674 if (active) { 675 data |= IGP02E1000_PM_D0_LPLU; 676 ret_val = e1000_write_phy_reg(hw, 677 IGP02E1000_PHY_POWER_MGMT, 678 data); 679 if (ret_val) 680 goto out; 681 682 /* When LPLU is enabled, we should disable SmartSpeed */ 683 ret_val = e1000_read_phy_reg(hw, 684 IGP01E1000_PHY_PORT_CONFIG, 685 &data); 686 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 687 ret_val = e1000_write_phy_reg(hw, 688 IGP01E1000_PHY_PORT_CONFIG, 689 data); 690 if (ret_val) 691 goto out; 692 } else { 693 data &= ~IGP02E1000_PM_D0_LPLU; 694 ret_val = e1000_write_phy_reg(hw, 695 IGP02E1000_PHY_POWER_MGMT, 696 data); 697 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 698 * during Dx states where the power conservation is most 699 * important. During driver activity we should enable 700 * SmartSpeed, so performance is maintained. */ 701 if (phy->smart_speed == e1000_smart_speed_on) { 702 ret_val = e1000_read_phy_reg(hw, 703 IGP01E1000_PHY_PORT_CONFIG, 704 &data); 705 if (ret_val) 706 goto out; 707 708 data |= IGP01E1000_PSCFR_SMART_SPEED; 709 ret_val = e1000_write_phy_reg(hw, 710 IGP01E1000_PHY_PORT_CONFIG, 711 data); 712 if (ret_val) 713 goto out; 714 } else if (phy->smart_speed == e1000_smart_speed_off) { 715 ret_val = e1000_read_phy_reg(hw, 716 IGP01E1000_PHY_PORT_CONFIG, 717 &data); 718 if (ret_val) 719 goto out; 720 721 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 722 ret_val = e1000_write_phy_reg(hw, 723 IGP01E1000_PHY_PORT_CONFIG, 724 data); 725 if (ret_val) 726 goto out; 727 } 728 } 729 730out: 731 return ret_val; 732} 733 734/** 735 * e1000_reset_hw_82571 - Reset hardware 736 * @hw - pointer to the HW structure 737 * 738 * This resets the hardware into a known state. This is a 739 * function pointer entry point called by the api module. 740 **/ 741STATIC s32 742e1000_reset_hw_82571(struct e1000_hw *hw) 743{ 744 u32 ctrl, extcnf_ctrl, ctrl_ext, icr; 745 s32 ret_val; 746 u16 i = 0; 747 748 DEBUGFUNC("e1000_reset_hw_82571"); 749 750 /* Prevent the PCI-E bus from sticking if there is no TLP connection 751 * on the last TLP read/write transaction when MAC is reset. 752 */ 753 ret_val = e1000_disable_pcie_master_generic(hw); 754 if (ret_val) { 755 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 756 } 757 758 DEBUGOUT("Masking off all interrupts\n"); 759 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 760 761 E1000_WRITE_REG(hw, E1000_RCTL, 0); 762 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 763 E1000_WRITE_FLUSH(hw); 764 765 msec_delay(10); 766 767 /* Must acquire the MDIO ownership before MAC reset. 768 * Ownership defaults to firmware after a reset. */ 769 if (hw->mac.type == e1000_82573) { 770 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 771 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 772 773 do { 774 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 775 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 776 777 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 778 break; 779 780 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 781 782 msec_delay(2); 783 i++; 784 } while (i < MDIO_OWNERSHIP_TIMEOUT); 785 } 786 787 ctrl = E1000_READ_REG(hw, E1000_CTRL); 788 789 DEBUGOUT("Issuing a global reset to MAC\n"); 790 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 791 792 if (hw->nvm.type == e1000_nvm_flash_hw) { 793 usec_delay(10); 794 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 795 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 796 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 797 E1000_WRITE_FLUSH(hw); 798 } 799 800 ret_val = e1000_get_auto_rd_done_generic(hw); 801 if (ret_val) 802 /* We don't want to continue accessing MAC registers. */ 803 goto out; 804 805 /* Phy configuration from NVM just starts after EECD_AUTO_RD is set. 806 * Need to wait for Phy configuration completion before accessing 807 * NVM and Phy. 808 */ 809 if (hw->mac.type == e1000_82573) 810 msec_delay(25); 811 812 /* Clear any pending interrupt events. */ 813 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 814 icr = E1000_READ_REG(hw, E1000_ICR); 815 816out: 817 return ret_val; 818} 819 820/** 821 * e1000_init_hw_82571 - Initialize hardware 822 * @hw - pointer to the HW structure 823 * 824 * This inits the hardware readying it for operation. 825 **/ 826STATIC s32 827e1000_init_hw_82571(struct e1000_hw *hw) 828{ 829 struct e1000_mac_info *mac = &hw->mac; 830 u32 reg_data; 831 s32 ret_val; 832 u16 i, rar_count = mac->rar_entry_count; 833 834 DEBUGFUNC("e1000_init_hw_82571"); 835 836 e1000_initialize_hw_bits_82571(hw); 837 838 /* Initialize identification LED */ 839 ret_val = e1000_id_led_init_generic(hw); 840 if (ret_val) { 841 DEBUGOUT("Error initializing identification LED\n"); 842 goto out; 843 } 844 845 /* Disabling VLAN filtering */ 846 DEBUGOUT("Initializing the IEEE VLAN\n"); 847 e1000_clear_vfta(hw); 848 849 /* Setup the receive address. */ 850 /* If, however, a locally administered address was assigned to the 851 * 82571, we must reserve a RAR for it to work around an issue where 852 * resetting one port will reload the MAC on the other port. 853 */ 854 if (e1000_get_laa_state_82571(hw) == TRUE) 855 rar_count--; 856 e1000_init_rx_addrs_generic(hw, rar_count); 857 858 /* Zero out the Multicast HASH table */ 859 DEBUGOUT("Zeroing the MTA\n"); 860 for (i = 0; i < mac->mta_reg_count; i++) 861 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 862 863 /* Setup link and flow control */ 864 ret_val = e1000_setup_link(hw); 865 866 /* Set the transmit descriptor write-back policy */ 867 reg_data = E1000_READ_REG(hw, E1000_TXDCTL); 868 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 869 E1000_TXDCTL_FULL_TX_DESC_WB | 870 E1000_TXDCTL_COUNT_DESC; 871 E1000_WRITE_REG(hw, E1000_TXDCTL, reg_data); 872 873 /* ...for both queues. */ 874 if (mac->type != e1000_82573) { 875 reg_data = E1000_READ_REG(hw, E1000_TXDCTL1); 876 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 877 E1000_TXDCTL_FULL_TX_DESC_WB | 878 E1000_TXDCTL_COUNT_DESC; 879 E1000_WRITE_REG(hw, E1000_TXDCTL1, reg_data); 880 } else { 881 e1000_enable_tx_pkt_filtering(hw); 882 reg_data = E1000_READ_REG(hw, E1000_GCR); 883 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 884 E1000_WRITE_REG(hw, E1000_GCR, reg_data); 885 } 886 887 /* Clear all of the statistics registers (clear on read). It is 888 * important that we do this after we have tried to establish link 889 * because the symbol error count will increment wildly if there 890 * is no link. 891 */ 892 e1000_clear_hw_cntrs_82571(hw); 893 894out: 895 return ret_val; 896} 897 898/** 899 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits 900 * @hw - pointer to the HW structure 901 * 902 * Initializes required hardware-dependent bits needed for normal operation. 903 **/ 904static void 905e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 906{ 907 u32 reg; 908 909 DEBUGFUNC("e1000_initialize_hw_bits_82571"); 910 911 if (hw->mac.disable_hw_init_bits) 912 goto out; 913 914 /* Transmit Descriptor Control 0 */ 915 reg = E1000_READ_REG(hw, E1000_TXDCTL); 916 reg |= (1 << 22); 917 E1000_WRITE_REG(hw, E1000_TXDCTL, reg); 918 919 /* Transmit Descriptor Control 1 */ 920 reg = E1000_READ_REG(hw, E1000_TXDCTL1); 921 reg |= (1 << 22); 922 E1000_WRITE_REG(hw, E1000_TXDCTL1, reg); 923 924 /* Transmit Arbitration Control 0 */ 925 reg = E1000_READ_REG(hw, E1000_TARC0); 926 reg &= ~(0xF << 27); /* 30:27 */ 927 switch (hw->mac.type) { 928 case e1000_82571: 929 case e1000_82572: 930 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); 931 break; 932 default: 933 break; 934 } 935 E1000_WRITE_REG(hw, E1000_TARC0, reg); 936 937 /* Transmit Arbitration Control 1 */ 938 reg = E1000_READ_REG(hw, E1000_TARC1); 939 switch (hw->mac.type) { 940 case e1000_82571: 941 case e1000_82572: 942 reg &= ~((1 << 29) | (1 << 30)); 943 reg |= (1 << 24) | (1 << 25) | (1 << 26); 944 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 945 reg &= ~(1 << 28); 946 else 947 reg |= (1 << 28); 948 E1000_WRITE_REG(hw, E1000_TARC1, reg); 949 break; 950 default: 951 break; 952 } 953 954 /* Device Control */ 955 if (hw->mac.type == e1000_82573) { 956 reg = E1000_READ_REG(hw, E1000_CTRL); 957 reg &= ~(1 << 29); 958 E1000_WRITE_REG(hw, E1000_CTRL, reg); 959 } 960 961 /* Extended Device Control */ 962 if (hw->mac.type == e1000_82573) { 963 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 964 reg &= ~(1 << 23); 965 reg |= (1 << 22); 966 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 967 } 968 969out: 970 return; 971} 972 973/** 974 * e1000_clear_vfta_82571 - Clear VLAN filter table 975 * @hw - pointer to the HW structure 976 * 977 * Clears the register array which contains the VLAN filter table by 978 * setting all the values to 0. 979 **/ 980STATIC void 981e1000_clear_vfta_82571(struct e1000_hw *hw) 982{ 983 u32 offset; 984 u32 vfta_value = 0; 985 u32 vfta_offset = 0; 986 u32 vfta_bit_in_reg = 0; 987 988 DEBUGFUNC("e1000_clear_vfta_82571"); 989 990 if (hw->mac.type == e1000_82573) { 991 if (hw->mng_cookie.vlan_id != 0) { 992 /* The VFTA is a 4096b bit-field, each identifying 993 * a single VLAN ID. The following operations 994 * determine which 32b entry (i.e. offset) into the 995 * array we want to set the VLAN ID (i.e. bit) of 996 * the manageability unit. 997 */ 998 vfta_offset = (hw->mng_cookie.vlan_id >> 999 E1000_VFTA_ENTRY_SHIFT) & 1000 E1000_VFTA_ENTRY_MASK; 1001 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 1002 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 1003 } 1004 } 1005 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 1006 /* If the offset we want to clear is the same offset of the 1007 * manageability VLAN ID, then clear all bits except that of 1008 * the manageability unit. 1009 */ 1010 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 1011 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); 1012 E1000_WRITE_FLUSH(hw); 1013 } 1014} 1015 1016/** 1017 * e1000_mc_addr_list_update_82571 - Update Multicast addresses 1018 * @hw - pointer to the HW structure 1019 * @mc_addr_list - array of multicast addresses to program 1020 * @mc_addr_count - number of multicast addresses to program 1021 * @rar_used_count - the first RAR register free to program 1022 * @rar_count - total number of supported Receive Address Registers 1023 * 1024 * Updates the Receive Address Registers and Multicast Table Array. 1025 * The caller must have a packed mc_addr_list of multicast addresses. 1026 * The parameter rar_count will usually be hw->mac.rar_entry_count 1027 * unless there are workarounds that change this. 1028 **/ 1029STATIC void 1030e1000_mc_addr_list_update_82571(struct e1000_hw *hw, 1031 u8 *mc_addr_list, u32 mc_addr_count, 1032 u32 rar_used_count, u32 rar_count) 1033{ 1034 DEBUGFUNC("e1000_mc_addr_list_update_82571"); 1035 1036 if (e1000_get_laa_state_82571(hw)) 1037 rar_count--; 1038 1039 e1000_mc_addr_list_update_generic(hw, mc_addr_list, mc_addr_count, 1040 rar_used_count, rar_count); 1041} 1042 1043/** 1044 * e1000_setup_link_82571 - Setup flow control and link settings 1045 * @hw - pointer to the HW structure 1046 * 1047 * Determines which flow control settings to use, then configures flow 1048 * control. Calls the appropriate media-specific link configuration 1049 * function. Assuming the adapter has a valid link partner, a valid link 1050 * should be established. Assumes the hardware has previously been reset 1051 * and the transmitter and receiver are not enabled. 1052 **/ 1053STATIC s32 1054e1000_setup_link_82571(struct e1000_hw *hw) 1055{ 1056 DEBUGFUNC("e1000_setup_link_82571"); 1057 1058 /* 82573 does not have a word in the NVM to determine 1059 * the default flow control setting, so we explicitly 1060 * set it to full. 1061 */ 1062 if (hw->mac.type == e1000_82573) 1063 hw->mac.fc = e1000_fc_full; 1064 1065 return e1000_setup_link_generic(hw); 1066} 1067 1068/** 1069 * e1000_setup_copper_link_82571 - Configure copper link settings 1070 * @hw - pointer to the HW structure 1071 * 1072 * Configures the link for auto-neg or forced speed and duplex. Then we check 1073 * for link, once link is established calls to configure collision distance 1074 * and flow control are called. 1075 **/ 1076STATIC s32 1077e1000_setup_copper_link_82571(struct e1000_hw *hw) 1078{ 1079 u32 ctrl, led_ctrl; 1080 s32 ret_val; 1081 1082 DEBUGFUNC("e1000_setup_copper_link_82571"); 1083 1084 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1085 ctrl |= E1000_CTRL_SLU; 1086 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1087 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1088 1089 switch (hw->phy.type) { 1090 case e1000_phy_m88: 1091 ret_val = e1000_copper_link_setup_m88(hw); 1092 break; 1093 case e1000_phy_igp_2: 1094 ret_val = e1000_copper_link_setup_igp(hw); 1095 /* Setup activity LED */ 1096 led_ctrl = E1000_READ_REG(hw, E1000_LEDCTL); 1097 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1098 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1099 E1000_WRITE_REG(hw, E1000_LEDCTL, led_ctrl); 1100 break; 1101 default: 1102 ret_val = -E1000_ERR_PHY; 1103 break; 1104 } 1105 1106 if (ret_val) 1107 goto out; 1108 1109 ret_val = e1000_setup_copper_link_generic(hw); 1110 1111out: 1112 return ret_val; 1113} 1114 1115/** 1116 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes 1117 * @hw - pointer to the HW structure 1118 * 1119 * Configures collision distance and flow control for fiber and serdes links. 1120 * Upon successful setup, poll for link. 1121 **/ 1122STATIC s32 1123e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) 1124{ 1125 DEBUGFUNC("e1000_setup_fiber_serdes_link_82571"); 1126 1127 switch (hw->mac.type) { 1128 case e1000_82571: 1129 case e1000_82572: 1130 /* If SerDes loopback mode is entered, there is no form 1131 * of reset to take the adapter out of that mode. So we 1132 * have to explicitly take the adapter out of loopback 1133 * mode. This prevents drivers from twidling their thumbs 1134 * if another tool failed to take it out of loopback mode. 1135 */ 1136 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1137 break; 1138 default: 1139 break; 1140 } 1141 1142 return e1000_setup_fiber_serdes_link_generic(hw); 1143} 1144 1145/** 1146 * e1000_valid_led_default_82571 - Verify a valid default LED config 1147 * @hw - pointer to the HW structure 1148 * @data - pointer to the NVM (EEPROM) 1149 * 1150 * Read the EEPROM for the current default LED configuration. If the 1151 * LED configuration is not valid, set to a valid LED configuration. 1152 **/ 1153STATIC s32 1154e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) 1155{ 1156 s32 ret_val; 1157 1158 DEBUGFUNC("e1000_valid_led_default_82571"); 1159 1160 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 1161 if (ret_val) { 1162 DEBUGOUT("NVM Read Error\n"); 1163 goto out; 1164 } 1165 1166 if (hw->mac.type == e1000_82573 && 1167 *data == ID_LED_RESERVED_F746) 1168 *data = ID_LED_DEFAULT_82573; 1169 else if (*data == ID_LED_RESERVED_0000 || 1170 *data == ID_LED_RESERVED_FFFF) 1171 *data = ID_LED_DEFAULT; 1172 1173out: 1174 return ret_val; 1175} 1176 1177/** 1178 * e1000_get_laa_state_82571 - Get locally administered address state 1179 * @hw - pointer to the HW structure 1180 * 1181 * Retrieve and return the current locally administed address state. 1182 **/ 1183boolean_t 1184e1000_get_laa_state_82571(struct e1000_hw *hw) 1185{ 1186 struct e1000_dev_spec_82571 *dev_spec; 1187 boolean_t state = FALSE; 1188 1189 DEBUGFUNC("e1000_get_laa_state_82571"); 1190 1191 if (hw->mac.type != e1000_82571) 1192 goto out; 1193 1194 dev_spec = (struct e1000_dev_spec_82571 *)hw->dev_spec; 1195 1196 state = dev_spec->laa_is_present; 1197 1198out: 1199 return state; 1200} 1201 1202/** 1203 * e1000_set_laa_state_82571 - Set locally administered address state 1204 * @hw - pointer to the HW structure 1205 * @state - enable/disable locally administered address 1206 * 1207 * Enable/Disable the current locally administed address state. 1208 **/ 1209void 1210e1000_set_laa_state_82571(struct e1000_hw *hw, boolean_t state) 1211{ 1212 struct e1000_dev_spec_82571 *dev_spec; 1213 1214 DEBUGFUNC("e1000_set_laa_state_82571"); 1215 1216 if (hw->mac.type != e1000_82571) 1217 goto out; 1218 1219 dev_spec = (struct e1000_dev_spec_82571 *)hw->dev_spec; 1220 1221 dev_spec->laa_is_present = state; 1222 1223 /* If workaround is activated... */ 1224 if (state == TRUE) { 1225 /* Hold a copy of the LAA in RAR[14] This is done so that 1226 * between the time RAR[0] gets clobbered and the time it 1227 * gets fixed, the actual LAA is in one of the RARs and no 1228 * incoming packets directed to this port are dropped. 1229 * Eventually the LAA will be in RAR[0] and RAR[14]. 1230 */ 1231 e1000_rar_set_generic(hw, hw->mac.addr, 1232 hw->mac.rar_entry_count - 1); 1233 } 1234 1235out: 1236 return; 1237} 1238 1239/** 1240 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum 1241 * @hw - pointer to the HW structure 1242 * 1243 * Verifies that the EEPROM has completed the update. After updating the 1244 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If 1245 * the checksum fix is not implemented, we need to set the bit and update 1246 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, 1247 * we need to return bad checksum. 1248 **/ 1249static s32 1250e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 1251{ 1252 struct e1000_nvm_info *nvm = &hw->nvm; 1253 s32 ret_val = E1000_SUCCESS; 1254 u16 data; 1255 1256 DEBUGFUNC("e1000_fix_nvm_checksum_82571"); 1257 1258 if (nvm->type != e1000_nvm_flash_hw) 1259 goto out; 1260 1261 /* Check bit 4 of word 10h. If it is 0, firmware is done updating 1262 * 10h-12h. Checksum may need to be fixed. 1263 */ 1264 ret_val = e1000_read_nvm(hw, 0x10, 1, &data); 1265 if (ret_val) 1266 goto out; 1267 1268 if (!(data & 0x10)) { 1269 /* Read 0x23 and check bit 15. This bit is a 1 1270 * when the checksum has already been fixed. If 1271 * the checksum is still wrong and this bit is a 1272 * 1, we need to return bad checksum. Otherwise, 1273 * we need to set this bit to a 1 and update the 1274 * checksum. 1275 */ 1276 ret_val = e1000_read_nvm(hw, 0x23, 1, &data); 1277 if (ret_val) 1278 goto out; 1279 1280 if (!(data & 0x8000)) { 1281 data |= 0x8000; 1282 ret_val = e1000_write_nvm(hw, 0x23, 1, &data); 1283 if (ret_val) 1284 goto out; 1285 ret_val = e1000_update_nvm_checksum(hw); 1286 } 1287 } 1288 1289out: 1290 return ret_val; 1291} 1292 1293/** 1294 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters 1295 * @hw - pointer to the HW structure 1296 * 1297 * Clears the hardware counters by reading the counter registers. 1298 **/ 1299STATIC void 1300e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) 1301{ 1302 volatile u32 temp; 1303 1304 DEBUGFUNC("e1000_clear_hw_cntrs_82571"); 1305 1306 e1000_clear_hw_cntrs_base_generic(hw); 1307 1308 temp = E1000_READ_REG(hw, E1000_PRC64); 1309 temp = E1000_READ_REG(hw, E1000_PRC127); 1310 temp = E1000_READ_REG(hw, E1000_PRC255); 1311 temp = E1000_READ_REG(hw, E1000_PRC511); 1312 temp = E1000_READ_REG(hw, E1000_PRC1023); 1313 temp = E1000_READ_REG(hw, E1000_PRC1522); 1314 temp = E1000_READ_REG(hw, E1000_PTC64); 1315 temp = E1000_READ_REG(hw, E1000_PTC127); 1316 temp = E1000_READ_REG(hw, E1000_PTC255); 1317 temp = E1000_READ_REG(hw, E1000_PTC511); 1318 temp = E1000_READ_REG(hw, E1000_PTC1023); 1319 temp = E1000_READ_REG(hw, E1000_PTC1522); 1320 1321 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1322 temp = E1000_READ_REG(hw, E1000_RXERRC); 1323 temp = E1000_READ_REG(hw, E1000_TNCRS); 1324 temp = E1000_READ_REG(hw, E1000_CEXTERR); 1325 temp = E1000_READ_REG(hw, E1000_TSCTC); 1326 temp = E1000_READ_REG(hw, E1000_TSCTFC); 1327 1328 temp = E1000_READ_REG(hw, E1000_MGTPRC); 1329 temp = E1000_READ_REG(hw, E1000_MGTPDC); 1330 temp = E1000_READ_REG(hw, E1000_MGTPTC); 1331 1332 temp = E1000_READ_REG(hw, E1000_IAC); 1333 temp = E1000_READ_REG(hw, E1000_ICRXOC); 1334 1335 temp = E1000_READ_REG(hw, E1000_ICRXPTC); 1336 temp = E1000_READ_REG(hw, E1000_ICRXATC); 1337 temp = E1000_READ_REG(hw, E1000_ICTXPTC); 1338 temp = E1000_READ_REG(hw, E1000_ICTXATC); 1339 temp = E1000_READ_REG(hw, E1000_ICTXQEC); 1340 temp = E1000_READ_REG(hw, E1000_ICTXQMTC); 1341 temp = E1000_READ_REG(hw, E1000_ICRXDMTC); 1342} 1343