e1000_82571.c revision 169240
1/******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33$FreeBSD: head/sys/dev/em/e1000_82571.c 169240 2007-05-04 00:00:12Z jfv $ 34 35 36/* e1000_82571 37 * e1000_82572 38 * e1000_82573 39 */ 40 41#include "e1000_82571.h" 42 43void e1000_init_function_pointers_82571(struct e1000_hw *hw); 44 45STATIC s32 e1000_init_phy_params_82571(struct e1000_hw *hw); 46STATIC s32 e1000_init_nvm_params_82571(struct e1000_hw *hw); 47STATIC s32 e1000_init_mac_params_82571(struct e1000_hw *hw); 48STATIC s32 e1000_acquire_nvm_82571(struct e1000_hw *hw); 49STATIC void e1000_release_nvm_82571(struct e1000_hw *hw); 50STATIC s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, 51 u16 words, u16 *data); 52STATIC s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw); 53STATIC s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw); 54STATIC s32 e1000_get_cfg_done_82571(struct e1000_hw *hw); 55STATIC s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, 56 boolean_t active); 57STATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw); 58STATIC s32 e1000_init_hw_82571(struct e1000_hw *hw); 59STATIC void e1000_clear_vfta_82571(struct e1000_hw *hw); 60STATIC void e1000_mc_addr_list_update_82571(struct e1000_hw *hw, 61 u8 *mc_addr_list, u32 mc_addr_count, 62 u32 rar_used_count, u32 rar_count); 63STATIC s32 e1000_setup_link_82571(struct e1000_hw *hw); 64STATIC s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); 65STATIC s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); 66STATIC s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data); 67STATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); 68static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); 69static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); 70static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); 71static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 72 u16 words, u16 *data); 73 74struct e1000_dev_spec_82571 { 75 boolean_t laa_is_present; 76}; 77 78/** 79 * e1000_init_phy_params_82571 - Init PHY func ptrs. 80 * @hw - pointer to the HW structure 81 * 82 * This is a function pointer entry point called by the api module. 83 **/ 84STATIC s32 85e1000_init_phy_params_82571(struct e1000_hw *hw) 86{ 87 struct e1000_phy_info *phy = &hw->phy; 88 struct e1000_functions *func = &hw->func; 89 s32 ret_val = E1000_SUCCESS; 90 91 DEBUGFUNC("e1000_init_phy_params_82571"); 92 93 if (hw->media_type != e1000_media_type_copper) { 94 phy->type = e1000_phy_none; 95 goto out; 96 } 97 98 phy->addr = 1; 99 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 100 phy->reset_delay_us = 100; 101 102 func->acquire_phy = e1000_get_hw_semaphore_generic; 103 func->check_polarity = e1000_check_polarity_igp; 104 func->check_reset_block = e1000_check_reset_block_generic; 105 func->release_phy = e1000_put_hw_semaphore_generic; 106 func->reset_phy = e1000_phy_hw_reset_generic; 107 func->set_d0_lplu_state = e1000_set_d0_lplu_state_82571; 108 func->set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 109 110 switch (hw->mac.type) { 111 case e1000_82571: 112 case e1000_82572: 113 phy->type = e1000_phy_igp_2; 114 func->get_cfg_done = e1000_get_cfg_done_82571; 115 func->get_phy_info = e1000_get_phy_info_igp; 116 func->force_speed_duplex = e1000_phy_force_speed_duplex_igp; 117 func->get_cable_length = e1000_get_cable_length_igp_2; 118 func->read_phy_reg = e1000_read_phy_reg_igp; 119 func->write_phy_reg = e1000_write_phy_reg_igp; 120 break; 121 case e1000_82573: 122 phy->type = e1000_phy_m88; 123 func->get_cfg_done = e1000_get_cfg_done_generic; 124 func->get_phy_info = e1000_get_phy_info_m88; 125 func->commit_phy = e1000_phy_sw_reset_generic; 126 func->force_speed_duplex = e1000_phy_force_speed_duplex_m88; 127 func->get_cable_length = e1000_get_cable_length_m88; 128 func->read_phy_reg = e1000_read_phy_reg_m88; 129 func->write_phy_reg = e1000_write_phy_reg_m88; 130 break; 131 default: 132 ret_val = -E1000_ERR_PHY; 133 goto out; 134 break; 135 } 136 137 /* This can only be done after all function pointers are setup. */ 138 ret_val = e1000_get_phy_id_82571(hw); 139 140 /* Verify phy id */ 141 switch (hw->mac.type) { 142 case e1000_82571: 143 case e1000_82572: 144 if (phy->id != IGP01E1000_I_PHY_ID) { 145 ret_val = -E1000_ERR_PHY; 146 goto out; 147 } 148 break; 149 case e1000_82573: 150 if (phy->id != M88E1111_I_PHY_ID) { 151 ret_val = -E1000_ERR_PHY; 152 goto out; 153 } 154 break; 155 default: 156 ret_val = -E1000_ERR_PHY; 157 goto out; 158 break; 159 } 160 161out: 162 return ret_val; 163} 164 165/** 166 * e1000_init_nvm_params_82571 - Init NVM func ptrs. 167 * @hw - pointer to the HW structure 168 * 169 * This is a function pointer entry point called by the api module. 170 **/ 171STATIC s32 172e1000_init_nvm_params_82571(struct e1000_hw *hw) 173{ 174 struct e1000_nvm_info *nvm = &hw->nvm; 175 struct e1000_functions *func = &hw->func; 176 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 177 u16 size; 178 179 DEBUGFUNC("e1000_init_nvm_params_82571"); 180 181 nvm->opcode_bits = 8; 182 nvm->delay_usec = 1; 183 switch (nvm->override) { 184 case e1000_nvm_override_spi_large: 185 nvm->page_size = 32; 186 nvm->address_bits = 16; 187 break; 188 case e1000_nvm_override_spi_small: 189 nvm->page_size = 8; 190 nvm->address_bits = 8; 191 break; 192 default: 193 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 194 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 195 break; 196 } 197 198 switch (hw->mac.type) { 199 case e1000_82573: 200 if (((eecd >> 15) & 0x3) == 0x3) { 201 nvm->type = e1000_nvm_flash_hw; 202 nvm->word_size = 2048; 203 /* Autonomous Flash update bit must be cleared due 204 * to Flash update issue. 205 */ 206 eecd &= ~E1000_EECD_AUPDEN; 207 E1000_WRITE_REG(hw, E1000_EECD, eecd); 208 break; 209 } 210 /* Fall Through */ 211 default: 212 nvm->type = e1000_nvm_eeprom_spi; 213 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 214 E1000_EECD_SIZE_EX_SHIFT); 215 /* Added to a constant, "size" becomes the left-shift value 216 * for setting word_size. 217 */ 218 size += NVM_WORD_SIZE_BASE_SHIFT; 219 nvm->word_size = 1 << size; 220 break; 221 } 222 223 /* Function Pointers */ 224 func->acquire_nvm = e1000_acquire_nvm_82571; 225 func->read_nvm = (hw->mac.type == e1000_82573) 226 ? e1000_read_nvm_eerd 227 : e1000_read_nvm_spi; 228 func->release_nvm = e1000_release_nvm_82571; 229 func->update_nvm = e1000_update_nvm_checksum_82571; 230 func->validate_nvm = e1000_validate_nvm_checksum_82571; 231 func->valid_led_default = e1000_valid_led_default_82571; 232 func->write_nvm = e1000_write_nvm_82571; 233 234 return E1000_SUCCESS; 235} 236 237/** 238 * e1000_init_mac_params_82571 - Init MAC func ptrs. 239 * @hw - pointer to the HW structure 240 * 241 * This is a function pointer entry point called by the api module. 242 **/ 243STATIC s32 244e1000_init_mac_params_82571(struct e1000_hw *hw) 245{ 246 struct e1000_mac_info *mac = &hw->mac; 247 struct e1000_functions *func = &hw->func; 248 s32 ret_val = E1000_SUCCESS; 249 250 DEBUGFUNC("e1000_init_mac_params_82571"); 251 252 /* Set media type */ 253 switch (hw->device_id) { 254 case E1000_DEV_ID_82571EB_FIBER: 255 case E1000_DEV_ID_82572EI_FIBER: 256 case E1000_DEV_ID_82571EB_QUAD_FIBER: 257 hw->media_type = e1000_media_type_fiber; 258 break; 259 case E1000_DEV_ID_82571EB_SERDES: 260 case E1000_DEV_ID_82572EI_SERDES: 261 hw->media_type = e1000_media_type_internal_serdes; 262 break; 263 default: 264 hw->media_type = e1000_media_type_copper; 265 break; 266 } 267 268 /* Set mta register count */ 269 mac->mta_reg_count = 128; 270 /* Set rar entry count */ 271 mac->rar_entry_count = E1000_RAR_ENTRIES; 272 /* Set if part includes ASF firmware */ 273 mac->asf_firmware_present = TRUE; 274 /* Set if manageability features are enabled. */ 275 mac->arc_subsystem_valid = 276 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 277 ? TRUE : FALSE; 278 279 /* Function pointers */ 280 281 /* bus type/speed/width */ 282 func->get_bus_info = e1000_get_bus_info_pcie_generic; 283 /* reset */ 284 func->reset_hw = e1000_reset_hw_82571; 285 /* hw initialization */ 286 func->init_hw = e1000_init_hw_82571; 287 /* link setup */ 288 func->setup_link = e1000_setup_link_82571; 289 /* physical interface link setup */ 290 func->setup_physical_interface = 291 (hw->media_type == e1000_media_type_copper) 292 ? e1000_setup_copper_link_82571 293 : e1000_setup_fiber_serdes_link_82571; 294 /* check for link */ 295 switch (hw->media_type) { 296 case e1000_media_type_copper: 297 func->check_for_link = e1000_check_for_copper_link_generic; 298 break; 299 case e1000_media_type_fiber: 300 func->check_for_link = e1000_check_for_fiber_link_generic; 301 break; 302 case e1000_media_type_internal_serdes: 303 func->check_for_link = e1000_check_for_serdes_link_generic; 304 break; 305 default: 306 ret_val = -E1000_ERR_CONFIG; 307 goto out; 308 break; 309 } 310 /* check management mode */ 311 func->check_mng_mode = e1000_check_mng_mode_generic; 312 /* multicast address update */ 313 func->mc_addr_list_update = e1000_mc_addr_list_update_82571; 314 /* writing VFTA */ 315 func->write_vfta = e1000_write_vfta_generic; 316 /* clearing VFTA */ 317 func->clear_vfta = e1000_clear_vfta_82571; 318 /* setting MTA */ 319 func->mta_set = e1000_mta_set_generic; 320 /* blink LED */ 321 func->blink_led = e1000_blink_led_generic; 322 /* setup LED */ 323 func->setup_led = e1000_setup_led_generic; 324 /* cleanup LED */ 325 func->cleanup_led = e1000_cleanup_led_generic; 326 /* turn on/off LED */ 327 func->led_on = e1000_led_on_generic; 328 func->led_off = e1000_led_off_generic; 329 /* remove device */ 330 func->remove_device = e1000_remove_device_generic; 331 /* clear hardware counters */ 332 func->clear_hw_cntrs = e1000_clear_hw_cntrs_82571; 333 /* link info */ 334 func->get_link_up_info = 335 (hw->media_type == e1000_media_type_copper) 336 ? e1000_get_speed_and_duplex_copper_generic 337 : e1000_get_speed_and_duplex_fiber_serdes_generic; 338 339 hw->dev_spec_size = sizeof(struct e1000_dev_spec_82571); 340 341 /* Device-specific structure allocation */ 342 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 343 344out: 345 return ret_val; 346} 347 348/** 349 * e1000_init_function_pointers_82571 - Init func ptrs. 350 * @hw - pointer to the HW structure 351 * 352 * The only function explicitly called by the api module to initialize 353 * all function pointers and parameters. 354 **/ 355void 356e1000_init_function_pointers_82571(struct e1000_hw *hw) 357{ 358 DEBUGFUNC("e1000_init_function_pointers_82571"); 359 360 hw->func.init_mac_params = e1000_init_mac_params_82571; 361 hw->func.init_nvm_params = e1000_init_nvm_params_82571; 362 hw->func.init_phy_params = e1000_init_phy_params_82571; 363} 364 365/** 366 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision 367 * @hw - pointer to the HW structure 368 * 369 * Reads the PHY registers and stores the PHY ID and possibly the PHY 370 * revision in the hardware structure. 371 **/ 372static s32 373e1000_get_phy_id_82571(struct e1000_hw *hw) 374{ 375 struct e1000_phy_info *phy = &hw->phy; 376 s32 ret_val = E1000_SUCCESS; 377 378 DEBUGFUNC("e1000_get_phy_id_82571"); 379 380 switch (hw->mac.type) { 381 case e1000_82571: 382 case e1000_82572: 383 /* The 82571 firmware may still be configuring the PHY. 384 * In this case, we cannot access the PHY until the 385 * configuration is done. So we explicitly set the 386 * PHY ID. */ 387 phy->id = IGP01E1000_I_PHY_ID; 388 break; 389 case e1000_82573: 390 ret_val = e1000_get_phy_id(hw); 391 break; 392 default: 393 ret_val = -E1000_ERR_PHY; 394 break; 395 } 396 397 return ret_val; 398} 399 400/** 401 * e1000_acquire_nvm_82571 - Request for access to the EEPROM 402 * @hw - pointer to the HW structure 403 * 404 * To gain access to the EEPROM, first we must obtain a hardware semaphore. 405 * Then for non-82573 hardware, set the EEPROM access request bit and wait 406 * for EEPROM access grant bit. If the access grant bit is not set, release 407 * hardware semaphore. 408 **/ 409STATIC s32 410e1000_acquire_nvm_82571(struct e1000_hw *hw) 411{ 412 s32 ret_val; 413 414 DEBUGFUNC("e1000_acquire_nvm_82571"); 415 416 ret_val = e1000_get_hw_semaphore_generic(hw); 417 if (ret_val) 418 goto out; 419 420 if (hw->mac.type != e1000_82573) 421 ret_val = e1000_acquire_nvm_generic(hw); 422 423 if (ret_val) 424 e1000_put_hw_semaphore_generic(hw); 425 426out: 427 return ret_val; 428} 429 430/** 431 * e1000_release_nvm_82571 - Release exclusive access to EEPROM 432 * @hw - pointer to the HW structure 433 * 434 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 435 **/ 436STATIC void 437e1000_release_nvm_82571(struct e1000_hw *hw) 438{ 439 DEBUGFUNC("e1000_release_nvm_82571"); 440 441 e1000_release_nvm_generic(hw); 442 e1000_put_hw_semaphore_generic(hw); 443} 444 445/** 446 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface 447 * @hw - pointer to the HW structure 448 * @offset - offset within the EEPROM to be written to 449 * @words - number of words to write 450 * @data - 16 bit word(s) to be written to the EEPROM 451 * 452 * For non-82573 silicon, write data to EEPROM at offset using SPI interface. 453 * 454 * If e1000_update_nvm_checksum is not called after this function, the 455 * EEPROM will most likley contain an invalid checksum. 456 **/ 457STATIC s32 458e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 459{ 460 s32 ret_val = E1000_SUCCESS; 461 462 DEBUGFUNC("e1000_write_nvm_82571"); 463 464 switch (hw->mac.type) { 465 case e1000_82573: 466 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); 467 break; 468 case e1000_82571: 469 case e1000_82572: 470 ret_val = e1000_write_nvm_spi(hw, offset, words, data); 471 break; 472 default: 473 ret_val = -E1000_ERR_NVM; 474 break; 475 } 476 477 return ret_val; 478} 479 480/** 481 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum 482 * @hw - pointer to the HW structure 483 * 484 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 485 * up to the checksum. Then calculates the EEPROM checksum and writes the 486 * value to the EEPROM. 487 **/ 488STATIC s32 489e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 490{ 491 u32 eecd; 492 s32 ret_val; 493 u16 i; 494 495 DEBUGFUNC("e1000_update_nvm_checksum_82571"); 496 497 ret_val = e1000_update_nvm_checksum_generic(hw); 498 if (ret_val) 499 goto out; 500 501 /* If our nvm is an EEPROM, then we're done 502 * otherwise, commit the checksum to the flash NVM. */ 503 if (hw->nvm.type != e1000_nvm_flash_hw) 504 goto out; 505 506 /* Check for pending operations. */ 507 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 508 msec_delay(1); 509 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 510 break; 511 } 512 513 if (i == E1000_FLASH_UPDATES) { 514 ret_val = -E1000_ERR_NVM; 515 goto out; 516 } 517 518 /* Reset the firmware if using STM opcode. */ 519 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) { 520 /* The enabling of and the actual reset must be done 521 * in two write cycles. 522 */ 523 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE); 524 E1000_WRITE_FLUSH(hw); 525 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET); 526 } 527 528 /* Commit the write to flash */ 529 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD; 530 E1000_WRITE_REG(hw, E1000_EECD, eecd); 531 532 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 533 msec_delay(1); 534 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 535 break; 536 } 537 538 if (i == E1000_FLASH_UPDATES) { 539 ret_val = -E1000_ERR_NVM; 540 goto out; 541 } 542 543out: 544 return ret_val; 545} 546 547/** 548 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum 549 * @hw - pointer to the HW structure 550 * 551 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 552 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 553 **/ 554STATIC s32 555e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) 556{ 557 DEBUGFUNC("e1000_validate_nvm_checksum_82571"); 558 559 if (hw->nvm.type == e1000_nvm_flash_hw) 560 e1000_fix_nvm_checksum_82571(hw); 561 562 return e1000_validate_nvm_checksum_generic(hw); 563} 564 565/** 566 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon 567 * @hw - pointer to the HW structure 568 * @offset - offset within the EEPROM to be written to 569 * @words - number of words to write 570 * @data - 16 bit word(s) to be written to the EEPROM 571 * 572 * After checking for invalid values, poll the EEPROM to ensure the previous 573 * command has completed before trying to write the next word. After write 574 * poll for completion. 575 * 576 * If e1000_update_nvm_checksum is not called after this function, the 577 * EEPROM will most likley contain an invalid checksum. 578 **/ 579static s32 580e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, u16 words, 581 u16 *data) 582{ 583 struct e1000_nvm_info *nvm = &hw->nvm; 584 u32 i, eewr = 0; 585 s32 ret_val = 0; 586 587 DEBUGFUNC("e1000_write_nvm_eewr_82571"); 588 589 /* A check for invalid values: offset too large, too many words, 590 * and not enough words. */ 591 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 592 (words == 0)) { 593 DEBUGOUT("nvm parameter(s) out of bounds\n"); 594 ret_val = -E1000_ERR_NVM; 595 goto out; 596 } 597 598 for (i = 0; i < words; i++) { 599 eewr = (data[i] << E1000_NVM_RW_REG_DATA) | 600 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | 601 E1000_NVM_RW_REG_START; 602 603 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 604 if (ret_val) 605 break; 606 607 E1000_WRITE_REG(hw, E1000_EEWR, eewr); 608 609 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 610 if (ret_val) 611 break; 612 } 613 614out: 615 return ret_val; 616} 617 618/** 619 * e1000_get_cfg_done_82571 - Poll for configuration done 620 * @hw - pointer to the HW structure 621 * 622 * Reads the management control register for the config done bit to be set. 623 **/ 624STATIC s32 625e1000_get_cfg_done_82571(struct e1000_hw *hw) 626{ 627 s32 timeout = PHY_CFG_TIMEOUT; 628 s32 ret_val = E1000_SUCCESS; 629 630 DEBUGFUNC("e1000_get_cfg_done_82571"); 631 632 while (timeout) { 633 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0) 634 break; 635 msec_delay(1); 636 timeout--; 637 } 638 if (!timeout) { 639 DEBUGOUT("MNG configuration cycle has not completed.\n"); 640 ret_val = -E1000_ERR_RESET; 641 goto out; 642 } 643 644out: 645 return ret_val; 646} 647 648/** 649 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state 650 * @hw - pointer to the HW structure 651 * @active - TRUE to enable LPLU, FALSE to disable 652 * 653 * Sets the LPLU D0 state according to the active flag. When activating LPLU 654 * this function also disables smart speed and vice versa. LPLU will not be 655 * activated unless the device autonegotiation advertisement meets standards 656 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function 657 * pointer entry point only called by PHY setup routines. 658 **/ 659STATIC s32 660e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, boolean_t active) 661{ 662 struct e1000_phy_info *phy = &hw->phy; 663 s32 ret_val; 664 u16 data; 665 666 DEBUGFUNC("e1000_set_d0_lplu_state_82571"); 667 668 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 669 if (ret_val) 670 goto out; 671 672 if (active) { 673 data |= IGP02E1000_PM_D0_LPLU; 674 ret_val = e1000_write_phy_reg(hw, 675 IGP02E1000_PHY_POWER_MGMT, 676 data); 677 if (ret_val) 678 goto out; 679 680 /* When LPLU is enabled, we should disable SmartSpeed */ 681 ret_val = e1000_read_phy_reg(hw, 682 IGP01E1000_PHY_PORT_CONFIG, 683 &data); 684 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 685 ret_val = e1000_write_phy_reg(hw, 686 IGP01E1000_PHY_PORT_CONFIG, 687 data); 688 if (ret_val) 689 goto out; 690 } else { 691 data &= ~IGP02E1000_PM_D0_LPLU; 692 ret_val = e1000_write_phy_reg(hw, 693 IGP02E1000_PHY_POWER_MGMT, 694 data); 695 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 696 * during Dx states where the power conservation is most 697 * important. During driver activity we should enable 698 * SmartSpeed, so performance is maintained. */ 699 if (phy->smart_speed == e1000_smart_speed_on) { 700 ret_val = e1000_read_phy_reg(hw, 701 IGP01E1000_PHY_PORT_CONFIG, 702 &data); 703 if (ret_val) 704 goto out; 705 706 data |= IGP01E1000_PSCFR_SMART_SPEED; 707 ret_val = e1000_write_phy_reg(hw, 708 IGP01E1000_PHY_PORT_CONFIG, 709 data); 710 if (ret_val) 711 goto out; 712 } else if (phy->smart_speed == e1000_smart_speed_off) { 713 ret_val = e1000_read_phy_reg(hw, 714 IGP01E1000_PHY_PORT_CONFIG, 715 &data); 716 if (ret_val) 717 goto out; 718 719 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 720 ret_val = e1000_write_phy_reg(hw, 721 IGP01E1000_PHY_PORT_CONFIG, 722 data); 723 if (ret_val) 724 goto out; 725 } 726 } 727 728out: 729 return ret_val; 730} 731 732/** 733 * e1000_reset_hw_82571 - Reset hardware 734 * @hw - pointer to the HW structure 735 * 736 * This resets the hardware into a known state. This is a 737 * function pointer entry point called by the api module. 738 **/ 739STATIC s32 740e1000_reset_hw_82571(struct e1000_hw *hw) 741{ 742 u32 ctrl, extcnf_ctrl, ctrl_ext, icr; 743 s32 ret_val; 744 u16 i = 0; 745 746 DEBUGFUNC("e1000_reset_hw_82571"); 747 748 /* Prevent the PCI-E bus from sticking if there is no TLP connection 749 * on the last TLP read/write transaction when MAC is reset. 750 */ 751 ret_val = e1000_disable_pcie_master_generic(hw); 752 if (ret_val) { 753 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 754 } 755 756 DEBUGOUT("Masking off all interrupts\n"); 757 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 758 759 E1000_WRITE_REG(hw, E1000_RCTL, 0); 760 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 761 E1000_WRITE_FLUSH(hw); 762 763 msec_delay(10); 764 765 /* Must acquire the MDIO ownership before MAC reset. 766 * Ownership defaults to firmware after a reset. */ 767 if (hw->mac.type == e1000_82573) { 768 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 769 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 770 771 do { 772 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 773 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 774 775 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 776 break; 777 778 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 779 780 msec_delay(2); 781 i++; 782 } while (i < MDIO_OWNERSHIP_TIMEOUT); 783 } 784 785 ctrl = E1000_READ_REG(hw, E1000_CTRL); 786 787 DEBUGOUT("Issuing a global reset to MAC\n"); 788 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 789 790 if (hw->nvm.type == e1000_nvm_flash_hw) { 791 usec_delay(10); 792 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 793 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 794 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 795 E1000_WRITE_FLUSH(hw); 796 } 797 798 ret_val = e1000_get_auto_rd_done_generic(hw); 799 if (ret_val) 800 /* We don't want to continue accessing MAC registers. */ 801 goto out; 802 803 /* Phy configuration from NVM just starts after EECD_AUTO_RD is set. 804 * Need to wait for Phy configuration completion before accessing 805 * NVM and Phy. 806 */ 807 if (hw->mac.type == e1000_82573) 808 msec_delay(25); 809 810 /* Clear any pending interrupt events. */ 811 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 812 icr = E1000_READ_REG(hw, E1000_ICR); 813 814out: 815 return ret_val; 816} 817 818/** 819 * e1000_init_hw_82571 - Initialize hardware 820 * @hw - pointer to the HW structure 821 * 822 * This inits the hardware readying it for operation. 823 **/ 824STATIC s32 825e1000_init_hw_82571(struct e1000_hw *hw) 826{ 827 struct e1000_mac_info *mac = &hw->mac; 828 u32 reg_data; 829 s32 ret_val; 830 u16 i, rar_count = mac->rar_entry_count; 831 832 DEBUGFUNC("e1000_init_hw_82571"); 833 834 e1000_initialize_hw_bits_82571(hw); 835 836 /* Initialize identification LED */ 837 ret_val = e1000_id_led_init_generic(hw); 838 if (ret_val) { 839 DEBUGOUT("Error initializing identification LED\n"); 840 goto out; 841 } 842 843 /* Disabling VLAN filtering */ 844 DEBUGOUT("Initializing the IEEE VLAN\n"); 845 e1000_clear_vfta(hw); 846 847 /* Setup the receive address. */ 848 /* If, however, a locally administered address was assigned to the 849 * 82571, we must reserve a RAR for it to work around an issue where 850 * resetting one port will reload the MAC on the other port. 851 */ 852 if (e1000_get_laa_state_82571(hw) == TRUE) 853 rar_count--; 854 e1000_init_rx_addrs_generic(hw, rar_count); 855 856 /* Zero out the Multicast HASH table */ 857 DEBUGOUT("Zeroing the MTA\n"); 858 for (i = 0; i < mac->mta_reg_count; i++) 859 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 860 861 /* Setup link and flow control */ 862 ret_val = e1000_setup_link(hw); 863 864 /* Set the transmit descriptor write-back policy */ 865 reg_data = E1000_READ_REG(hw, E1000_TXDCTL); 866 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 867 E1000_TXDCTL_FULL_TX_DESC_WB | 868 E1000_TXDCTL_COUNT_DESC; 869 E1000_WRITE_REG(hw, E1000_TXDCTL, reg_data); 870 871 /* ...for both queues. */ 872 if (mac->type != e1000_82573) { 873 reg_data = E1000_READ_REG(hw, E1000_TXDCTL1); 874 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 875 E1000_TXDCTL_FULL_TX_DESC_WB | 876 E1000_TXDCTL_COUNT_DESC; 877 E1000_WRITE_REG(hw, E1000_TXDCTL1, reg_data); 878 } else { 879 e1000_enable_tx_pkt_filtering(hw); 880 reg_data = E1000_READ_REG(hw, E1000_GCR); 881 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 882 E1000_WRITE_REG(hw, E1000_GCR, reg_data); 883 } 884 885 /* Clear all of the statistics registers (clear on read). It is 886 * important that we do this after we have tried to establish link 887 * because the symbol error count will increment wildly if there 888 * is no link. 889 */ 890 e1000_clear_hw_cntrs_82571(hw); 891 892out: 893 return ret_val; 894} 895 896/** 897 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits 898 * @hw - pointer to the HW structure 899 * 900 * Initializes required hardware-dependent bits needed for normal operation. 901 **/ 902static void 903e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 904{ 905 u32 reg; 906 907 DEBUGFUNC("e1000_initialize_hw_bits_82571"); 908 909 if (hw->mac.disable_hw_init_bits) 910 goto out; 911 912 /* Transmit Descriptor Control 0 */ 913 reg = E1000_READ_REG(hw, E1000_TXDCTL); 914 reg |= (1 << 22); 915 E1000_WRITE_REG(hw, E1000_TXDCTL, reg); 916 917 /* Transmit Descriptor Control 1 */ 918 reg = E1000_READ_REG(hw, E1000_TXDCTL1); 919 reg |= (1 << 22); 920 E1000_WRITE_REG(hw, E1000_TXDCTL1, reg); 921 922 /* Transmit Arbitration Control 0 */ 923 reg = E1000_READ_REG(hw, E1000_TARC0); 924 reg &= ~(0xF << 27); /* 30:27 */ 925 switch (hw->mac.type) { 926 case e1000_82571: 927 case e1000_82572: 928 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); 929 break; 930 default: 931 break; 932 } 933 E1000_WRITE_REG(hw, E1000_TARC0, reg); 934 935 /* Transmit Arbitration Control 1 */ 936 reg = E1000_READ_REG(hw, E1000_TARC1); 937 switch (hw->mac.type) { 938 case e1000_82571: 939 case e1000_82572: 940 reg &= ~((1 << 29) | (1 << 30)); 941 reg |= (1 << 24) | (1 << 25) | (1 << 26); 942 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 943 reg &= ~(1 << 28); 944 else 945 reg |= (1 << 28); 946 E1000_WRITE_REG(hw, E1000_TARC1, reg); 947 break; 948 default: 949 break; 950 } 951 952 /* Device Control */ 953 if (hw->mac.type == e1000_82573) { 954 reg = E1000_READ_REG(hw, E1000_CTRL); 955 reg &= ~(1 << 29); 956 E1000_WRITE_REG(hw, E1000_CTRL, reg); 957 } 958 959 /* Extended Device Control */ 960 if (hw->mac.type == e1000_82573) { 961 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 962 reg &= ~(1 << 23); 963 reg |= (1 << 22); 964 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 965 } 966 967out: 968 return; 969} 970 971/** 972 * e1000_clear_vfta_82571 - Clear VLAN filter table 973 * @hw - pointer to the HW structure 974 * 975 * Clears the register array which contains the VLAN filter table by 976 * setting all the values to 0. 977 **/ 978STATIC void 979e1000_clear_vfta_82571(struct e1000_hw *hw) 980{ 981 u32 offset; 982 u32 vfta_value = 0; 983 u32 vfta_offset = 0; 984 u32 vfta_bit_in_reg = 0; 985 986 DEBUGFUNC("e1000_clear_vfta_82571"); 987 988 if (hw->mac.type == e1000_82573) { 989 if (hw->mng_cookie.vlan_id != 0) { 990 /* The VFTA is a 4096b bit-field, each identifying 991 * a single VLAN ID. The following operations 992 * determine which 32b entry (i.e. offset) into the 993 * array we want to set the VLAN ID (i.e. bit) of 994 * the manageability unit. 995 */ 996 vfta_offset = (hw->mng_cookie.vlan_id >> 997 E1000_VFTA_ENTRY_SHIFT) & 998 E1000_VFTA_ENTRY_MASK; 999 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 1000 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 1001 } 1002 } 1003 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 1004 /* If the offset we want to clear is the same offset of the 1005 * manageability VLAN ID, then clear all bits except that of 1006 * the manageability unit. 1007 */ 1008 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 1009 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); 1010 E1000_WRITE_FLUSH(hw); 1011 } 1012} 1013 1014/** 1015 * e1000_mc_addr_list_update_82571 - Update Multicast addresses 1016 * @hw - pointer to the HW structure 1017 * @mc_addr_list - array of multicast addresses to program 1018 * @mc_addr_count - number of multicast addresses to program 1019 * @rar_used_count - the first RAR register free to program 1020 * @rar_count - total number of supported Receive Address Registers 1021 * 1022 * Updates the Receive Address Registers and Multicast Table Array. 1023 * The caller must have a packed mc_addr_list of multicast addresses. 1024 * The parameter rar_count will usually be hw->mac.rar_entry_count 1025 * unless there are workarounds that change this. 1026 **/ 1027STATIC void 1028e1000_mc_addr_list_update_82571(struct e1000_hw *hw, 1029 u8 *mc_addr_list, u32 mc_addr_count, 1030 u32 rar_used_count, u32 rar_count) 1031{ 1032 DEBUGFUNC("e1000_mc_addr_list_update_82571"); 1033 1034 if (e1000_get_laa_state_82571(hw)) 1035 rar_count--; 1036 1037 e1000_mc_addr_list_update_generic(hw, mc_addr_list, mc_addr_count, 1038 rar_used_count, rar_count); 1039} 1040 1041/** 1042 * e1000_setup_link_82571 - Setup flow control and link settings 1043 * @hw - pointer to the HW structure 1044 * 1045 * Determines which flow control settings to use, then configures flow 1046 * control. Calls the appropriate media-specific link configuration 1047 * function. Assuming the adapter has a valid link partner, a valid link 1048 * should be established. Assumes the hardware has previously been reset 1049 * and the transmitter and receiver are not enabled. 1050 **/ 1051STATIC s32 1052e1000_setup_link_82571(struct e1000_hw *hw) 1053{ 1054 DEBUGFUNC("e1000_setup_link_82571"); 1055 1056 /* 82573 does not have a word in the NVM to determine 1057 * the default flow control setting, so we explicitly 1058 * set it to full. 1059 */ 1060 if (hw->mac.type == e1000_82573) 1061 hw->mac.fc = e1000_fc_full; 1062 1063 return e1000_setup_link_generic(hw); 1064} 1065 1066/** 1067 * e1000_setup_copper_link_82571 - Configure copper link settings 1068 * @hw - pointer to the HW structure 1069 * 1070 * Configures the link for auto-neg or forced speed and duplex. Then we check 1071 * for link, once link is established calls to configure collision distance 1072 * and flow control are called. 1073 **/ 1074STATIC s32 1075e1000_setup_copper_link_82571(struct e1000_hw *hw) 1076{ 1077 u32 ctrl, led_ctrl; 1078 s32 ret_val; 1079 1080 DEBUGFUNC("e1000_setup_copper_link_82571"); 1081 1082 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1083 ctrl |= E1000_CTRL_SLU; 1084 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1085 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1086 1087 switch (hw->phy.type) { 1088 case e1000_phy_m88: 1089 ret_val = e1000_copper_link_setup_m88(hw); 1090 break; 1091 case e1000_phy_igp_2: 1092 ret_val = e1000_copper_link_setup_igp(hw); 1093 /* Setup activity LED */ 1094 led_ctrl = E1000_READ_REG(hw, E1000_LEDCTL); 1095 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1096 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1097 E1000_WRITE_REG(hw, E1000_LEDCTL, led_ctrl); 1098 break; 1099 default: 1100 ret_val = -E1000_ERR_PHY; 1101 break; 1102 } 1103 1104 if (ret_val) 1105 goto out; 1106 1107 ret_val = e1000_setup_copper_link_generic(hw); 1108 1109out: 1110 return ret_val; 1111} 1112 1113/** 1114 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes 1115 * @hw - pointer to the HW structure 1116 * 1117 * Configures collision distance and flow control for fiber and serdes links. 1118 * Upon successful setup, poll for link. 1119 **/ 1120STATIC s32 1121e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) 1122{ 1123 DEBUGFUNC("e1000_setup_fiber_serdes_link_82571"); 1124 1125 switch (hw->mac.type) { 1126 case e1000_82571: 1127 case e1000_82572: 1128 /* If SerDes loopback mode is entered, there is no form 1129 * of reset to take the adapter out of that mode. So we 1130 * have to explicitly take the adapter out of loopback 1131 * mode. This prevents drivers from twidling their thumbs 1132 * if another tool failed to take it out of loopback mode. 1133 */ 1134 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1135 break; 1136 default: 1137 break; 1138 } 1139 1140 return e1000_setup_fiber_serdes_link_generic(hw); 1141} 1142 1143/** 1144 * e1000_valid_led_default_82571 - Verify a valid default LED config 1145 * @hw - pointer to the HW structure 1146 * @data - pointer to the NVM (EEPROM) 1147 * 1148 * Read the EEPROM for the current default LED configuration. If the 1149 * LED configuration is not valid, set to a valid LED configuration. 1150 **/ 1151STATIC s32 1152e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) 1153{ 1154 s32 ret_val; 1155 1156 DEBUGFUNC("e1000_valid_led_default_82571"); 1157 1158 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 1159 if (ret_val) { 1160 DEBUGOUT("NVM Read Error\n"); 1161 goto out; 1162 } 1163 1164 if (hw->mac.type == e1000_82573 && 1165 *data == ID_LED_RESERVED_F746) 1166 *data = ID_LED_DEFAULT_82573; 1167 else if (*data == ID_LED_RESERVED_0000 || 1168 *data == ID_LED_RESERVED_FFFF) 1169 *data = ID_LED_DEFAULT; 1170 1171out: 1172 return ret_val; 1173} 1174 1175/** 1176 * e1000_get_laa_state_82571 - Get locally administered address state 1177 * @hw - pointer to the HW structure 1178 * 1179 * Retrieve and return the current locally administed address state. 1180 **/ 1181boolean_t 1182e1000_get_laa_state_82571(struct e1000_hw *hw) 1183{ 1184 struct e1000_dev_spec_82571 *dev_spec; 1185 boolean_t state = FALSE; 1186 1187 DEBUGFUNC("e1000_get_laa_state_82571"); 1188 1189 if (hw->mac.type != e1000_82571) 1190 goto out; 1191 1192 dev_spec = (struct e1000_dev_spec_82571 *)hw->dev_spec; 1193 1194 state = dev_spec->laa_is_present; 1195 1196out: 1197 return state; 1198} 1199 1200/** 1201 * e1000_set_laa_state_82571 - Set locally administered address state 1202 * @hw - pointer to the HW structure 1203 * @state - enable/disable locally administered address 1204 * 1205 * Enable/Disable the current locally administed address state. 1206 **/ 1207void 1208e1000_set_laa_state_82571(struct e1000_hw *hw, boolean_t state) 1209{ 1210 struct e1000_dev_spec_82571 *dev_spec; 1211 1212 DEBUGFUNC("e1000_set_laa_state_82571"); 1213 1214 if (hw->mac.type != e1000_82571) 1215 goto out; 1216 1217 dev_spec = (struct e1000_dev_spec_82571 *)hw->dev_spec; 1218 1219 dev_spec->laa_is_present = state; 1220 1221 /* If workaround is activated... */ 1222 if (state == TRUE) { 1223 /* Hold a copy of the LAA in RAR[14] This is done so that 1224 * between the time RAR[0] gets clobbered and the time it 1225 * gets fixed, the actual LAA is in one of the RARs and no 1226 * incoming packets directed to this port are dropped. 1227 * Eventually the LAA will be in RAR[0] and RAR[14]. 1228 */ 1229 e1000_rar_set_generic(hw, hw->mac.addr, 1230 hw->mac.rar_entry_count - 1); 1231 } 1232 1233out: 1234 return; 1235} 1236 1237/** 1238 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum 1239 * @hw - pointer to the HW structure 1240 * 1241 * Verifies that the EEPROM has completed the update. After updating the 1242 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If 1243 * the checksum fix is not implemented, we need to set the bit and update 1244 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, 1245 * we need to return bad checksum. 1246 **/ 1247static s32 1248e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 1249{ 1250 struct e1000_nvm_info *nvm = &hw->nvm; 1251 s32 ret_val = E1000_SUCCESS; 1252 u16 data; 1253 1254 DEBUGFUNC("e1000_fix_nvm_checksum_82571"); 1255 1256 if (nvm->type != e1000_nvm_flash_hw) 1257 goto out; 1258 1259 /* Check bit 4 of word 10h. If it is 0, firmware is done updating 1260 * 10h-12h. Checksum may need to be fixed. 1261 */ 1262 ret_val = e1000_read_nvm(hw, 0x10, 1, &data); 1263 if (ret_val) 1264 goto out; 1265 1266 if (!(data & 0x10)) { 1267 /* Read 0x23 and check bit 15. This bit is a 1 1268 * when the checksum has already been fixed. If 1269 * the checksum is still wrong and this bit is a 1270 * 1, we need to return bad checksum. Otherwise, 1271 * we need to set this bit to a 1 and update the 1272 * checksum. 1273 */ 1274 ret_val = e1000_read_nvm(hw, 0x23, 1, &data); 1275 if (ret_val) 1276 goto out; 1277 1278 if (!(data & 0x8000)) { 1279 data |= 0x8000; 1280 ret_val = e1000_write_nvm(hw, 0x23, 1, &data); 1281 if (ret_val) 1282 goto out; 1283 ret_val = e1000_update_nvm_checksum(hw); 1284 } 1285 } 1286 1287out: 1288 return ret_val; 1289} 1290 1291/** 1292 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters 1293 * @hw - pointer to the HW structure 1294 * 1295 * Clears the hardware counters by reading the counter registers. 1296 **/ 1297STATIC void 1298e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) 1299{ 1300 volatile u32 temp; 1301 1302 DEBUGFUNC("e1000_clear_hw_cntrs_82571"); 1303 1304 e1000_clear_hw_cntrs_base_generic(hw); 1305 1306 temp = E1000_READ_REG(hw, E1000_PRC64); 1307 temp = E1000_READ_REG(hw, E1000_PRC127); 1308 temp = E1000_READ_REG(hw, E1000_PRC255); 1309 temp = E1000_READ_REG(hw, E1000_PRC511); 1310 temp = E1000_READ_REG(hw, E1000_PRC1023); 1311 temp = E1000_READ_REG(hw, E1000_PRC1522); 1312 temp = E1000_READ_REG(hw, E1000_PTC64); 1313 temp = E1000_READ_REG(hw, E1000_PTC127); 1314 temp = E1000_READ_REG(hw, E1000_PTC255); 1315 temp = E1000_READ_REG(hw, E1000_PTC511); 1316 temp = E1000_READ_REG(hw, E1000_PTC1023); 1317 temp = E1000_READ_REG(hw, E1000_PTC1522); 1318 1319 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1320 temp = E1000_READ_REG(hw, E1000_RXERRC); 1321 temp = E1000_READ_REG(hw, E1000_TNCRS); 1322 temp = E1000_READ_REG(hw, E1000_CEXTERR); 1323 temp = E1000_READ_REG(hw, E1000_TSCTC); 1324 temp = E1000_READ_REG(hw, E1000_TSCTFC); 1325 1326 temp = E1000_READ_REG(hw, E1000_MGTPRC); 1327 temp = E1000_READ_REG(hw, E1000_MGTPDC); 1328 temp = E1000_READ_REG(hw, E1000_MGTPTC); 1329 1330 temp = E1000_READ_REG(hw, E1000_IAC); 1331 temp = E1000_READ_REG(hw, E1000_ICRXOC); 1332 1333 temp = E1000_READ_REG(hw, E1000_ICRXPTC); 1334 temp = E1000_READ_REG(hw, E1000_ICRXATC); 1335 temp = E1000_READ_REG(hw, E1000_ICTXPTC); 1336 temp = E1000_READ_REG(hw, E1000_ICTXATC); 1337 temp = E1000_READ_REG(hw, E1000_ICTXQEC); 1338 temp = E1000_READ_REG(hw, E1000_ICTXQMTC); 1339 temp = E1000_READ_REG(hw, E1000_ICRXDMTC); 1340} 1341