e1000_82571.c revision 247064
1177867Sjfv/****************************************************************************** 2169240Sjfv 3247064Sjfv Copyright (c) 2001-2013, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD: head/sys/dev/e1000/e1000_82571.c 247064 2013-02-21 00:25:45Z jfv $*/ 34169240Sjfv 35247064Sjfv/* 82571EB Gigabit Ethernet Controller 36185353Sjfv * 82571EB Gigabit Ethernet Controller (Copper) 37185353Sjfv * 82571EB Gigabit Ethernet Controller (Fiber) 38185353Sjfv * 82571EB Dual Port Gigabit Mezzanine Adapter 39185353Sjfv * 82571EB Quad Port Gigabit Mezzanine Adapter 40185353Sjfv * 82571PT Gigabit PT Quad Port Server ExpressModule 41185353Sjfv * 82572EI Gigabit Ethernet Controller (Copper) 42185353Sjfv * 82572EI Gigabit Ethernet Controller (Fiber) 43185353Sjfv * 82572EI Gigabit Ethernet Controller 44185353Sjfv * 82573V Gigabit Ethernet Controller (Copper) 45185353Sjfv * 82573E Gigabit Ethernet Controller (Copper) 46185353Sjfv * 82573L Gigabit Ethernet Controller 47185353Sjfv * 82574L Gigabit Network Connection 48194865Sjfv * 82583V Gigabit Network Connection 49169240Sjfv */ 50169240Sjfv 51169589Sjfv#include "e1000_api.h" 52169240Sjfv 53177867Sjfvstatic s32 e1000_acquire_nvm_82571(struct e1000_hw *hw); 54177867Sjfvstatic void e1000_release_nvm_82571(struct e1000_hw *hw); 55177867Sjfvstatic s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, 56228386Sjfv u16 words, u16 *data); 57177867Sjfvstatic s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw); 58177867Sjfvstatic s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw); 59177867Sjfvstatic s32 e1000_get_cfg_done_82571(struct e1000_hw *hw); 60177867Sjfvstatic s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, 61228386Sjfv bool active); 62177867Sjfvstatic s32 e1000_reset_hw_82571(struct e1000_hw *hw); 63177867Sjfvstatic s32 e1000_init_hw_82571(struct e1000_hw *hw); 64177867Sjfvstatic void e1000_clear_vfta_82571(struct e1000_hw *hw); 65181027Sjfvstatic bool e1000_check_mng_mode_82574(struct e1000_hw *hw); 66181027Sjfvstatic s32 e1000_led_on_82574(struct e1000_hw *hw); 67177867Sjfvstatic s32 e1000_setup_link_82571(struct e1000_hw *hw); 68177867Sjfvstatic s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); 69190872Sjfvstatic s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); 70177867Sjfvstatic s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); 71177867Sjfvstatic s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data); 72177867Sjfvstatic void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); 73169589Sjfvstatic s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw); 74169240Sjfvstatic s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); 75169240Sjfvstatic s32 e1000_get_phy_id_82571(struct e1000_hw *hw); 76169589Sjfvstatic void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); 77213234Sjfvstatic void e1000_put_hw_semaphore_82573(struct e1000_hw *hw); 78213234Sjfvstatic s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw); 79213234Sjfvstatic void e1000_put_hw_semaphore_82574(struct e1000_hw *hw); 80218588Sjfvstatic s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, 81228386Sjfv bool active); 82218588Sjfvstatic s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, 83228386Sjfv bool active); 84169240Sjfvstatic void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); 85169240Sjfvstatic s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 86228386Sjfv u16 words, u16 *data); 87177867Sjfvstatic s32 e1000_read_mac_addr_82571(struct e1000_hw *hw); 88177867Sjfvstatic void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); 89169240Sjfv 90169240Sjfv/** 91169240Sjfv * e1000_init_phy_params_82571 - Init PHY func ptrs. 92169589Sjfv * @hw: pointer to the HW structure 93169240Sjfv **/ 94177867Sjfvstatic s32 e1000_init_phy_params_82571(struct e1000_hw *hw) 95169240Sjfv{ 96169240Sjfv struct e1000_phy_info *phy = &hw->phy; 97247064Sjfv s32 ret_val; 98169240Sjfv 99169240Sjfv DEBUGFUNC("e1000_init_phy_params_82571"); 100169240Sjfv 101173788Sjfv if (hw->phy.media_type != e1000_media_type_copper) { 102185353Sjfv phy->type = e1000_phy_none; 103247064Sjfv return E1000_SUCCESS; 104169240Sjfv } 105169240Sjfv 106228386Sjfv phy->addr = 1; 107228386Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 108228386Sjfv phy->reset_delay_us = 100; 109169240Sjfv 110228386Sjfv phy->ops.check_reset_block = e1000_check_reset_block_generic; 111228386Sjfv phy->ops.reset = e1000_phy_hw_reset_generic; 112228386Sjfv phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571; 113228386Sjfv phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 114228386Sjfv phy->ops.power_up = e1000_power_up_phy_copper; 115228386Sjfv phy->ops.power_down = e1000_power_down_phy_copper_82571; 116169240Sjfv 117169240Sjfv switch (hw->mac.type) { 118169240Sjfv case e1000_82571: 119169240Sjfv case e1000_82572: 120228386Sjfv phy->type = e1000_phy_igp_2; 121228386Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_82571; 122228386Sjfv phy->ops.get_info = e1000_get_phy_info_igp; 123228386Sjfv phy->ops.check_polarity = e1000_check_polarity_igp; 124177867Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 125228386Sjfv phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 126228386Sjfv phy->ops.read_reg = e1000_read_phy_reg_igp; 127228386Sjfv phy->ops.write_reg = e1000_write_phy_reg_igp; 128228386Sjfv phy->ops.acquire = e1000_get_hw_semaphore_82571; 129228386Sjfv phy->ops.release = e1000_put_hw_semaphore_82571; 130169240Sjfv break; 131169240Sjfv case e1000_82573: 132228386Sjfv phy->type = e1000_phy_m88; 133228386Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 134228386Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 135228386Sjfv phy->ops.check_polarity = e1000_check_polarity_m88; 136228386Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 137177867Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 138228386Sjfv phy->ops.get_cable_length = e1000_get_cable_length_m88; 139228386Sjfv phy->ops.read_reg = e1000_read_phy_reg_m88; 140228386Sjfv phy->ops.write_reg = e1000_write_phy_reg_m88; 141228386Sjfv phy->ops.acquire = e1000_get_hw_semaphore_82571; 142228386Sjfv phy->ops.release = e1000_put_hw_semaphore_82571; 143169240Sjfv break; 144200243Sjfv case e1000_82574: 145194865Sjfv case e1000_82583: 146218588Sjfv E1000_MUTEX_INIT(&hw->dev_spec._82571.swflag_mutex); 147213234Sjfv 148228386Sjfv phy->type = e1000_phy_bm; 149228386Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 150228386Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 151228386Sjfv phy->ops.check_polarity = e1000_check_polarity_m88; 152228386Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 153178523Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 154228386Sjfv phy->ops.get_cable_length = e1000_get_cable_length_m88; 155228386Sjfv phy->ops.read_reg = e1000_read_phy_reg_bm2; 156228386Sjfv phy->ops.write_reg = e1000_write_phy_reg_bm2; 157228386Sjfv phy->ops.acquire = e1000_get_hw_semaphore_82574; 158228386Sjfv phy->ops.release = e1000_put_hw_semaphore_82574; 159228386Sjfv phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574; 160228386Sjfv phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574; 161218588Sjfv break; 162218588Sjfv default: 163247064Sjfv return -E1000_ERR_PHY; 164218588Sjfv break; 165218588Sjfv } 166178523Sjfv 167218588Sjfv /* This can only be done after all function pointers are setup. */ 168218588Sjfv ret_val = e1000_get_phy_id_82571(hw); 169218588Sjfv if (ret_val) { 170218588Sjfv DEBUGOUT("Error getting PHY ID\n"); 171247064Sjfv return ret_val; 172218588Sjfv } 173218588Sjfv 174218588Sjfv /* Verify phy id */ 175218588Sjfv switch (hw->mac.type) { 176218588Sjfv case e1000_82571: 177218588Sjfv case e1000_82572: 178218588Sjfv if (phy->id != IGP01E1000_I_PHY_ID) 179178523Sjfv ret_val = -E1000_ERR_PHY; 180178523Sjfv break; 181218588Sjfv case e1000_82573: 182218588Sjfv if (phy->id != M88E1111_I_PHY_ID) 183218588Sjfv ret_val = -E1000_ERR_PHY; 184218588Sjfv break; 185218588Sjfv case e1000_82574: 186218588Sjfv case e1000_82583: 187218588Sjfv if (phy->id != BME1000_E_PHY_ID_R2) 188218588Sjfv ret_val = -E1000_ERR_PHY; 189218588Sjfv break; 190169240Sjfv default: 191169240Sjfv ret_val = -E1000_ERR_PHY; 192169240Sjfv break; 193169240Sjfv } 194169240Sjfv 195218588Sjfv if (ret_val) 196218588Sjfv DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 197218588Sjfv 198169240Sjfv return ret_val; 199169240Sjfv} 200169240Sjfv 201169240Sjfv/** 202169240Sjfv * e1000_init_nvm_params_82571 - Init NVM func ptrs. 203169589Sjfv * @hw: pointer to the HW structure 204169240Sjfv **/ 205177867Sjfvstatic s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) 206169240Sjfv{ 207169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 208169240Sjfv u32 eecd = E1000_READ_REG(hw, E1000_EECD); 209169240Sjfv u16 size; 210169240Sjfv 211169240Sjfv DEBUGFUNC("e1000_init_nvm_params_82571"); 212169240Sjfv 213185353Sjfv nvm->opcode_bits = 8; 214185353Sjfv nvm->delay_usec = 1; 215169240Sjfv switch (nvm->override) { 216169240Sjfv case e1000_nvm_override_spi_large: 217185353Sjfv nvm->page_size = 32; 218169240Sjfv nvm->address_bits = 16; 219169240Sjfv break; 220169240Sjfv case e1000_nvm_override_spi_small: 221185353Sjfv nvm->page_size = 8; 222169240Sjfv nvm->address_bits = 8; 223169240Sjfv break; 224169240Sjfv default: 225185353Sjfv nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 226169240Sjfv nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 227169240Sjfv break; 228169240Sjfv } 229169240Sjfv 230169240Sjfv switch (hw->mac.type) { 231169240Sjfv case e1000_82573: 232178523Sjfv case e1000_82574: 233194865Sjfv case e1000_82583: 234169240Sjfv if (((eecd >> 15) & 0x3) == 0x3) { 235169240Sjfv nvm->type = e1000_nvm_flash_hw; 236169240Sjfv nvm->word_size = 2048; 237247064Sjfv /* Autonomous Flash update bit must be cleared due 238169240Sjfv * to Flash update issue. 239169240Sjfv */ 240169240Sjfv eecd &= ~E1000_EECD_AUPDEN; 241169240Sjfv E1000_WRITE_REG(hw, E1000_EECD, eecd); 242169240Sjfv break; 243169240Sjfv } 244169240Sjfv /* Fall Through */ 245169240Sjfv default: 246185353Sjfv nvm->type = e1000_nvm_eeprom_spi; 247169240Sjfv size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 248228386Sjfv E1000_EECD_SIZE_EX_SHIFT); 249247064Sjfv /* Added to a constant, "size" becomes the left-shift value 250169240Sjfv * for setting word_size. 251169240Sjfv */ 252169240Sjfv size += NVM_WORD_SIZE_BASE_SHIFT; 253173788Sjfv 254173788Sjfv /* EEPROM access above 16k is unsupported */ 255173788Sjfv if (size > 14) 256173788Sjfv size = 14; 257228386Sjfv nvm->word_size = 1 << size; 258169240Sjfv break; 259169240Sjfv } 260169240Sjfv 261169240Sjfv /* Function Pointers */ 262213234Sjfv switch (hw->mac.type) { 263213234Sjfv case e1000_82574: 264213234Sjfv case e1000_82583: 265213234Sjfv nvm->ops.acquire = e1000_get_hw_semaphore_82574; 266213234Sjfv nvm->ops.release = e1000_put_hw_semaphore_82574; 267213234Sjfv break; 268213234Sjfv default: 269213234Sjfv nvm->ops.acquire = e1000_acquire_nvm_82571; 270213234Sjfv nvm->ops.release = e1000_release_nvm_82571; 271213234Sjfv break; 272213234Sjfv } 273228386Sjfv nvm->ops.read = e1000_read_nvm_eerd; 274228386Sjfv nvm->ops.update = e1000_update_nvm_checksum_82571; 275228386Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_82571; 276177867Sjfv nvm->ops.valid_led_default = e1000_valid_led_default_82571; 277228386Sjfv nvm->ops.write = e1000_write_nvm_82571; 278169240Sjfv 279169240Sjfv return E1000_SUCCESS; 280169240Sjfv} 281169240Sjfv 282169240Sjfv/** 283169240Sjfv * e1000_init_mac_params_82571 - Init MAC func ptrs. 284169589Sjfv * @hw: pointer to the HW structure 285169240Sjfv **/ 286177867Sjfvstatic s32 e1000_init_mac_params_82571(struct e1000_hw *hw) 287169240Sjfv{ 288169240Sjfv struct e1000_mac_info *mac = &hw->mac; 289194865Sjfv u32 swsm = 0; 290194865Sjfv u32 swsm2 = 0; 291194865Sjfv bool force_clear_smbi = FALSE; 292169240Sjfv 293169240Sjfv DEBUGFUNC("e1000_init_mac_params_82571"); 294169240Sjfv 295200243Sjfv /* Set media type and media-dependent function pointers */ 296169240Sjfv switch (hw->device_id) { 297169240Sjfv case E1000_DEV_ID_82571EB_FIBER: 298169240Sjfv case E1000_DEV_ID_82572EI_FIBER: 299169240Sjfv case E1000_DEV_ID_82571EB_QUAD_FIBER: 300173788Sjfv hw->phy.media_type = e1000_media_type_fiber; 301200243Sjfv mac->ops.setup_physical_interface = 302200243Sjfv e1000_setup_fiber_serdes_link_82571; 303200243Sjfv mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 304200243Sjfv mac->ops.get_link_up_info = 305200243Sjfv e1000_get_speed_and_duplex_fiber_serdes_generic; 306169240Sjfv break; 307169240Sjfv case E1000_DEV_ID_82571EB_SERDES: 308169589Sjfv case E1000_DEV_ID_82571EB_SERDES_DUAL: 309169589Sjfv case E1000_DEV_ID_82571EB_SERDES_QUAD: 310169240Sjfv case E1000_DEV_ID_82572EI_SERDES: 311173788Sjfv hw->phy.media_type = e1000_media_type_internal_serdes; 312200243Sjfv mac->ops.setup_physical_interface = 313200243Sjfv e1000_setup_fiber_serdes_link_82571; 314200243Sjfv mac->ops.check_for_link = e1000_check_for_serdes_link_82571; 315200243Sjfv mac->ops.get_link_up_info = 316200243Sjfv e1000_get_speed_and_duplex_fiber_serdes_generic; 317169240Sjfv break; 318169240Sjfv default: 319173788Sjfv hw->phy.media_type = e1000_media_type_copper; 320200243Sjfv mac->ops.setup_physical_interface = 321200243Sjfv e1000_setup_copper_link_82571; 322200243Sjfv mac->ops.check_for_link = e1000_check_for_copper_link_generic; 323200243Sjfv mac->ops.get_link_up_info = 324200243Sjfv e1000_get_speed_and_duplex_copper_generic; 325169240Sjfv break; 326169240Sjfv } 327169240Sjfv 328169240Sjfv /* Set mta register count */ 329169240Sjfv mac->mta_reg_count = 128; 330169240Sjfv /* Set rar entry count */ 331169240Sjfv mac->rar_entry_count = E1000_RAR_ENTRIES; 332169240Sjfv /* Set if part includes ASF firmware */ 333169240Sjfv mac->asf_firmware_present = TRUE; 334200243Sjfv /* Adaptive IFS supported */ 335200243Sjfv mac->adaptive_ifs = TRUE; 336169240Sjfv 337169240Sjfv /* Function pointers */ 338169240Sjfv 339169240Sjfv /* bus type/speed/width */ 340177867Sjfv mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 341169240Sjfv /* reset */ 342177867Sjfv mac->ops.reset_hw = e1000_reset_hw_82571; 343169240Sjfv /* hw initialization */ 344177867Sjfv mac->ops.init_hw = e1000_init_hw_82571; 345169240Sjfv /* link setup */ 346177867Sjfv mac->ops.setup_link = e1000_setup_link_82571; 347169240Sjfv /* multicast address update */ 348190872Sjfv mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 349169240Sjfv /* writing VFTA */ 350177867Sjfv mac->ops.write_vfta = e1000_write_vfta_generic; 351169240Sjfv /* clearing VFTA */ 352177867Sjfv mac->ops.clear_vfta = e1000_clear_vfta_82571; 353173788Sjfv /* read mac address */ 354177867Sjfv mac->ops.read_mac_addr = e1000_read_mac_addr_82571; 355190872Sjfv /* ID LED init */ 356190872Sjfv mac->ops.id_led_init = e1000_id_led_init_generic; 357169240Sjfv /* setup LED */ 358177867Sjfv mac->ops.setup_led = e1000_setup_led_generic; 359169240Sjfv /* cleanup LED */ 360177867Sjfv mac->ops.cleanup_led = e1000_cleanup_led_generic; 361200243Sjfv /* turn off LED */ 362200243Sjfv mac->ops.led_off = e1000_led_off_generic; 363200243Sjfv /* clear hardware counters */ 364200243Sjfv mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571; 365200243Sjfv 366200243Sjfv /* MAC-specific function pointers */ 367181027Sjfv switch (hw->mac.type) { 368200243Sjfv case e1000_82573: 369200243Sjfv mac->ops.set_lan_id = e1000_set_lan_id_single_port; 370200243Sjfv mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 371200243Sjfv mac->ops.led_on = e1000_led_on_generic; 372228386Sjfv mac->ops.blink_led = e1000_blink_led_generic; 373205869Sjfv 374205869Sjfv /* FWSM register */ 375205869Sjfv mac->has_fwsm = TRUE; 376247064Sjfv /* ARC supported; valid only if manageability features are 377205869Sjfv * enabled. 378205869Sjfv */ 379247064Sjfv mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) & 380247064Sjfv E1000_FWSM_MODE_MASK); 381200243Sjfv break; 382181027Sjfv case e1000_82574: 383194865Sjfv case e1000_82583: 384200243Sjfv mac->ops.set_lan_id = e1000_set_lan_id_single_port; 385200243Sjfv mac->ops.check_mng_mode = e1000_check_mng_mode_82574; 386181027Sjfv mac->ops.led_on = e1000_led_on_82574; 387181027Sjfv break; 388181027Sjfv default: 389200243Sjfv mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 390181027Sjfv mac->ops.led_on = e1000_led_on_generic; 391228386Sjfv mac->ops.blink_led = e1000_blink_led_generic; 392205869Sjfv 393205869Sjfv /* FWSM register */ 394205869Sjfv mac->has_fwsm = TRUE; 395181027Sjfv break; 396181027Sjfv } 397169240Sjfv 398247064Sjfv /* Ensure that the inter-port SWSM.SMBI lock bit is clear before 399194865Sjfv * first NVM or PHY acess. This should be done for single-port 400194865Sjfv * devices, and for one port only on dual-port devices so that 401194865Sjfv * for those devices we can still use the SMBI lock to synchronize 402194865Sjfv * inter-port accesses to the PHY & NVM. 403194865Sjfv */ 404194865Sjfv switch (hw->mac.type) { 405194865Sjfv case e1000_82571: 406194865Sjfv case e1000_82572: 407194865Sjfv swsm2 = E1000_READ_REG(hw, E1000_SWSM2); 408194865Sjfv 409194865Sjfv if (!(swsm2 & E1000_SWSM2_LOCK)) { 410194865Sjfv /* Only do this for the first interface on this card */ 411228386Sjfv E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 | 412228386Sjfv E1000_SWSM2_LOCK); 413194865Sjfv force_clear_smbi = TRUE; 414247064Sjfv } else { 415194865Sjfv force_clear_smbi = FALSE; 416247064Sjfv } 417194865Sjfv break; 418194865Sjfv default: 419194865Sjfv force_clear_smbi = TRUE; 420194865Sjfv break; 421194865Sjfv } 422194865Sjfv 423194865Sjfv if (force_clear_smbi) { 424194865Sjfv /* Make sure SWSM.SMBI is clear */ 425194865Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 426194865Sjfv if (swsm & E1000_SWSM_SMBI) { 427194865Sjfv /* This bit should not be set on a first interface, and 428194865Sjfv * indicates that the bootagent or EFI code has 429194865Sjfv * improperly left this bit enabled 430194865Sjfv */ 431194865Sjfv DEBUGOUT("Please update your 82571 Bootagent\n"); 432194865Sjfv } 433194865Sjfv E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI); 434194865Sjfv } 435194865Sjfv 436247064Sjfv /* Initialze device specific counter of SMBI acquisition timeouts. */ 437194865Sjfv hw->dev_spec._82571.smb_counter = 0; 438194865Sjfv 439200243Sjfv return E1000_SUCCESS; 440169240Sjfv} 441169240Sjfv 442169240Sjfv/** 443169240Sjfv * e1000_init_function_pointers_82571 - Init func ptrs. 444169589Sjfv * @hw: pointer to the HW structure 445169240Sjfv * 446185353Sjfv * Called to initialize all function pointers and parameters. 447169240Sjfv **/ 448173788Sjfvvoid e1000_init_function_pointers_82571(struct e1000_hw *hw) 449169240Sjfv{ 450169240Sjfv DEBUGFUNC("e1000_init_function_pointers_82571"); 451169240Sjfv 452177867Sjfv hw->mac.ops.init_params = e1000_init_mac_params_82571; 453177867Sjfv hw->nvm.ops.init_params = e1000_init_nvm_params_82571; 454177867Sjfv hw->phy.ops.init_params = e1000_init_phy_params_82571; 455169240Sjfv} 456169240Sjfv 457169240Sjfv/** 458169240Sjfv * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision 459169589Sjfv * @hw: pointer to the HW structure 460169240Sjfv * 461169240Sjfv * Reads the PHY registers and stores the PHY ID and possibly the PHY 462169240Sjfv * revision in the hardware structure. 463169240Sjfv **/ 464173788Sjfvstatic s32 e1000_get_phy_id_82571(struct e1000_hw *hw) 465169240Sjfv{ 466169240Sjfv struct e1000_phy_info *phy = &hw->phy; 467247064Sjfv s32 ret_val; 468178523Sjfv u16 phy_id = 0; 469169240Sjfv 470169240Sjfv DEBUGFUNC("e1000_get_phy_id_82571"); 471169240Sjfv 472169240Sjfv switch (hw->mac.type) { 473169240Sjfv case e1000_82571: 474169240Sjfv case e1000_82572: 475247064Sjfv /* The 82571 firmware may still be configuring the PHY. 476169240Sjfv * In this case, we cannot access the PHY until the 477169240Sjfv * configuration is done. So we explicitly set the 478173788Sjfv * PHY ID. 479173788Sjfv */ 480169240Sjfv phy->id = IGP01E1000_I_PHY_ID; 481169240Sjfv break; 482169240Sjfv case e1000_82573: 483247064Sjfv return e1000_get_phy_id(hw); 484169240Sjfv break; 485178523Sjfv case e1000_82574: 486194865Sjfv case e1000_82583: 487178523Sjfv ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 488178523Sjfv if (ret_val) 489247064Sjfv return ret_val; 490178523Sjfv 491178523Sjfv phy->id = (u32)(phy_id << 16); 492178523Sjfv usec_delay(20); 493178523Sjfv ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 494178523Sjfv if (ret_val) 495247064Sjfv return ret_val; 496178523Sjfv 497178523Sjfv phy->id |= (u32)(phy_id); 498178523Sjfv phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 499178523Sjfv break; 500169240Sjfv default: 501247064Sjfv return -E1000_ERR_PHY; 502169240Sjfv break; 503169240Sjfv } 504247064Sjfv 505247064Sjfv return E1000_SUCCESS; 506169240Sjfv} 507169240Sjfv 508169240Sjfv/** 509169589Sjfv * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore 510169589Sjfv * @hw: pointer to the HW structure 511169589Sjfv * 512169589Sjfv * Acquire the HW semaphore to access the PHY or NVM 513169589Sjfv **/ 514200243Sjfvstatic s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 515169589Sjfv{ 516169589Sjfv u32 swsm; 517194865Sjfv s32 sw_timeout = hw->nvm.word_size + 1; 518194865Sjfv s32 fw_timeout = hw->nvm.word_size + 1; 519169589Sjfv s32 i = 0; 520169589Sjfv 521169589Sjfv DEBUGFUNC("e1000_get_hw_semaphore_82571"); 522169589Sjfv 523247064Sjfv /* If we have timedout 3 times on trying to acquire 524194865Sjfv * the inter-port SMBI semaphore, there is old code 525194865Sjfv * operating on the other port, and it is not 526194865Sjfv * releasing SMBI. Modify the number of times that 527194865Sjfv * we try for the semaphore to interwork with this 528194865Sjfv * older code. 529194865Sjfv */ 530194865Sjfv if (hw->dev_spec._82571.smb_counter > 2) 531194865Sjfv sw_timeout = 1; 532194865Sjfv 533194865Sjfv /* Get the SW semaphore */ 534194865Sjfv while (i < sw_timeout) { 535194865Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 536194865Sjfv if (!(swsm & E1000_SWSM_SMBI)) 537194865Sjfv break; 538194865Sjfv 539194865Sjfv usec_delay(50); 540194865Sjfv i++; 541194865Sjfv } 542194865Sjfv 543194865Sjfv if (i == sw_timeout) { 544194865Sjfv DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 545194865Sjfv hw->dev_spec._82571.smb_counter++; 546194865Sjfv } 547169589Sjfv /* Get the FW semaphore. */ 548194865Sjfv for (i = 0; i < fw_timeout; i++) { 549169589Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 550169589Sjfv E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 551169589Sjfv 552169589Sjfv /* Semaphore acquired if bit latched */ 553169589Sjfv if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 554169589Sjfv break; 555169589Sjfv 556169589Sjfv usec_delay(50); 557169589Sjfv } 558169589Sjfv 559194865Sjfv if (i == fw_timeout) { 560169589Sjfv /* Release semaphores */ 561194865Sjfv e1000_put_hw_semaphore_82571(hw); 562169589Sjfv DEBUGOUT("Driver can't access the NVM\n"); 563247064Sjfv return -E1000_ERR_NVM; 564169589Sjfv } 565169589Sjfv 566247064Sjfv return E1000_SUCCESS; 567169589Sjfv} 568169589Sjfv 569169589Sjfv/** 570169589Sjfv * e1000_put_hw_semaphore_82571 - Release hardware semaphore 571169589Sjfv * @hw: pointer to the HW structure 572169589Sjfv * 573169589Sjfv * Release hardware semaphore used to access the PHY or NVM 574169589Sjfv **/ 575200243Sjfvstatic void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) 576169589Sjfv{ 577169589Sjfv u32 swsm; 578169589Sjfv 579194865Sjfv DEBUGFUNC("e1000_put_hw_semaphore_generic"); 580169589Sjfv 581169589Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 582169589Sjfv 583194865Sjfv swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 584169589Sjfv 585169589Sjfv E1000_WRITE_REG(hw, E1000_SWSM, swsm); 586169589Sjfv} 587169589Sjfv 588169589Sjfv/** 589213234Sjfv * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore 590213234Sjfv * @hw: pointer to the HW structure 591213234Sjfv * 592213234Sjfv * Acquire the HW semaphore during reset. 593213234Sjfv * 594213234Sjfv **/ 595213234Sjfvstatic s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) 596213234Sjfv{ 597213234Sjfv u32 extcnf_ctrl; 598213234Sjfv s32 i = 0; 599213234Sjfv 600213234Sjfv DEBUGFUNC("e1000_get_hw_semaphore_82573"); 601213234Sjfv 602213234Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 603213234Sjfv do { 604247064Sjfv extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 605213234Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 606213234Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 607213234Sjfv 608213234Sjfv if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 609213234Sjfv break; 610213234Sjfv 611213234Sjfv msec_delay(2); 612213234Sjfv i++; 613213234Sjfv } while (i < MDIO_OWNERSHIP_TIMEOUT); 614213234Sjfv 615213234Sjfv if (i == MDIO_OWNERSHIP_TIMEOUT) { 616213234Sjfv /* Release semaphores */ 617213234Sjfv e1000_put_hw_semaphore_82573(hw); 618213234Sjfv DEBUGOUT("Driver can't access the PHY\n"); 619247064Sjfv return -E1000_ERR_PHY; 620213234Sjfv } 621213234Sjfv 622247064Sjfv return E1000_SUCCESS; 623213234Sjfv} 624213234Sjfv 625213234Sjfv/** 626213234Sjfv * e1000_put_hw_semaphore_82573 - Release hardware semaphore 627213234Sjfv * @hw: pointer to the HW structure 628213234Sjfv * 629213234Sjfv * Release hardware semaphore used during reset. 630213234Sjfv * 631213234Sjfv **/ 632213234Sjfvstatic void e1000_put_hw_semaphore_82573(struct e1000_hw *hw) 633213234Sjfv{ 634213234Sjfv u32 extcnf_ctrl; 635213234Sjfv 636213234Sjfv DEBUGFUNC("e1000_put_hw_semaphore_82573"); 637213234Sjfv 638213234Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 639213234Sjfv extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 640213234Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 641213234Sjfv} 642213234Sjfv 643213234Sjfv/** 644213234Sjfv * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore 645213234Sjfv * @hw: pointer to the HW structure 646213234Sjfv * 647213234Sjfv * Acquire the HW semaphore to access the PHY or NVM. 648213234Sjfv * 649213234Sjfv **/ 650213234Sjfvstatic s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw) 651213234Sjfv{ 652214646Sjfv s32 ret_val; 653214646Sjfv 654213234Sjfv DEBUGFUNC("e1000_get_hw_semaphore_82574"); 655213234Sjfv 656213234Sjfv E1000_MUTEX_LOCK(&hw->dev_spec._82571.swflag_mutex); 657214646Sjfv ret_val = e1000_get_hw_semaphore_82573(hw); 658214646Sjfv if (ret_val) 659214646Sjfv E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex); 660214646Sjfv return ret_val; 661213234Sjfv} 662213234Sjfv 663213234Sjfv/** 664213234Sjfv * e1000_put_hw_semaphore_82574 - Release hardware semaphore 665213234Sjfv * @hw: pointer to the HW structure 666213234Sjfv * 667213234Sjfv * Release hardware semaphore used to access the PHY or NVM 668213234Sjfv * 669213234Sjfv **/ 670213234Sjfvstatic void e1000_put_hw_semaphore_82574(struct e1000_hw *hw) 671213234Sjfv{ 672213234Sjfv DEBUGFUNC("e1000_put_hw_semaphore_82574"); 673213234Sjfv 674213234Sjfv e1000_put_hw_semaphore_82573(hw); 675213234Sjfv E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex); 676213234Sjfv} 677213234Sjfv 678213234Sjfv/** 679218588Sjfv * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state 680218588Sjfv * @hw: pointer to the HW structure 681218588Sjfv * @active: TRUE to enable LPLU, FALSE to disable 682218588Sjfv * 683218588Sjfv * Sets the LPLU D0 state according to the active flag. 684218588Sjfv * LPLU will not be activated unless the 685218588Sjfv * device autonegotiation advertisement meets standards of 686218588Sjfv * either 10 or 10/100 or 10/100/1000 at all duplexes. 687218588Sjfv * This is a function pointer entry point only called by 688218588Sjfv * PHY setup routines. 689218588Sjfv **/ 690218588Sjfvstatic s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active) 691218588Sjfv{ 692247064Sjfv u32 data = E1000_READ_REG(hw, E1000_POEMB); 693218588Sjfv 694218588Sjfv DEBUGFUNC("e1000_set_d0_lplu_state_82574"); 695218588Sjfv 696218588Sjfv if (active) 697218588Sjfv data |= E1000_PHY_CTRL_D0A_LPLU; 698218588Sjfv else 699218588Sjfv data &= ~E1000_PHY_CTRL_D0A_LPLU; 700218588Sjfv 701218588Sjfv E1000_WRITE_REG(hw, E1000_POEMB, data); 702218588Sjfv return E1000_SUCCESS; 703218588Sjfv} 704218588Sjfv 705218588Sjfv/** 706218588Sjfv * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3 707218588Sjfv * @hw: pointer to the HW structure 708218588Sjfv * @active: boolean used to enable/disable lplu 709218588Sjfv * 710218588Sjfv * The low power link up (lplu) state is set to the power management level D3 711218588Sjfv * when active is TRUE, else clear lplu for D3. LPLU 712218588Sjfv * is used during Dx states where the power conservation is most important. 713218588Sjfv * During driver activity, SmartSpeed should be enabled so performance is 714218588Sjfv * maintained. 715218588Sjfv **/ 716218588Sjfvstatic s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active) 717218588Sjfv{ 718247064Sjfv u32 data = E1000_READ_REG(hw, E1000_POEMB); 719218588Sjfv 720218588Sjfv DEBUGFUNC("e1000_set_d3_lplu_state_82574"); 721218588Sjfv 722218588Sjfv if (!active) { 723218588Sjfv data &= ~E1000_PHY_CTRL_NOND0A_LPLU; 724218588Sjfv } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 725228386Sjfv (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) || 726228386Sjfv (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) { 727218588Sjfv data |= E1000_PHY_CTRL_NOND0A_LPLU; 728218588Sjfv } 729218588Sjfv 730218588Sjfv E1000_WRITE_REG(hw, E1000_POEMB, data); 731218588Sjfv return E1000_SUCCESS; 732218588Sjfv} 733218588Sjfv 734218588Sjfv/** 735169240Sjfv * e1000_acquire_nvm_82571 - Request for access to the EEPROM 736169589Sjfv * @hw: pointer to the HW structure 737169240Sjfv * 738169240Sjfv * To gain access to the EEPROM, first we must obtain a hardware semaphore. 739169240Sjfv * Then for non-82573 hardware, set the EEPROM access request bit and wait 740169240Sjfv * for EEPROM access grant bit. If the access grant bit is not set, release 741169240Sjfv * hardware semaphore. 742169240Sjfv **/ 743177867Sjfvstatic s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) 744169240Sjfv{ 745169240Sjfv s32 ret_val; 746169240Sjfv 747169240Sjfv DEBUGFUNC("e1000_acquire_nvm_82571"); 748169240Sjfv 749169589Sjfv ret_val = e1000_get_hw_semaphore_82571(hw); 750169240Sjfv if (ret_val) 751247064Sjfv return ret_val; 752169240Sjfv 753190872Sjfv switch (hw->mac.type) { 754200243Sjfv case e1000_82573: 755190872Sjfv break; 756190872Sjfv default: 757169240Sjfv ret_val = e1000_acquire_nvm_generic(hw); 758190872Sjfv break; 759190872Sjfv } 760169240Sjfv 761169240Sjfv if (ret_val) 762169589Sjfv e1000_put_hw_semaphore_82571(hw); 763169240Sjfv 764169240Sjfv return ret_val; 765169240Sjfv} 766169240Sjfv 767169240Sjfv/** 768169240Sjfv * e1000_release_nvm_82571 - Release exclusive access to EEPROM 769169589Sjfv * @hw: pointer to the HW structure 770169240Sjfv * 771169240Sjfv * Stop any current commands to the EEPROM and clear the EEPROM request bit. 772169240Sjfv **/ 773177867Sjfvstatic void e1000_release_nvm_82571(struct e1000_hw *hw) 774169240Sjfv{ 775169240Sjfv DEBUGFUNC("e1000_release_nvm_82571"); 776169240Sjfv 777169240Sjfv e1000_release_nvm_generic(hw); 778169589Sjfv e1000_put_hw_semaphore_82571(hw); 779169240Sjfv} 780169240Sjfv 781169240Sjfv/** 782169240Sjfv * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface 783169589Sjfv * @hw: pointer to the HW structure 784169589Sjfv * @offset: offset within the EEPROM to be written to 785169589Sjfv * @words: number of words to write 786169589Sjfv * @data: 16 bit word(s) to be written to the EEPROM 787169240Sjfv * 788169240Sjfv * For non-82573 silicon, write data to EEPROM at offset using SPI interface. 789169240Sjfv * 790169240Sjfv * If e1000_update_nvm_checksum is not called after this function, the 791176667Sjfv * EEPROM will most likely contain an invalid checksum. 792169240Sjfv **/ 793177867Sjfvstatic s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, 794228386Sjfv u16 *data) 795169240Sjfv{ 796247064Sjfv s32 ret_val; 797169240Sjfv 798169240Sjfv DEBUGFUNC("e1000_write_nvm_82571"); 799169240Sjfv 800169240Sjfv switch (hw->mac.type) { 801169240Sjfv case e1000_82573: 802178523Sjfv case e1000_82574: 803194865Sjfv case e1000_82583: 804169240Sjfv ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); 805169240Sjfv break; 806169240Sjfv case e1000_82571: 807169240Sjfv case e1000_82572: 808169240Sjfv ret_val = e1000_write_nvm_spi(hw, offset, words, data); 809169240Sjfv break; 810169240Sjfv default: 811169240Sjfv ret_val = -E1000_ERR_NVM; 812169240Sjfv break; 813169240Sjfv } 814169240Sjfv 815169240Sjfv return ret_val; 816169240Sjfv} 817169240Sjfv 818169240Sjfv/** 819169240Sjfv * e1000_update_nvm_checksum_82571 - Update EEPROM checksum 820169589Sjfv * @hw: pointer to the HW structure 821169240Sjfv * 822169240Sjfv * Updates the EEPROM checksum by reading/adding each word of the EEPROM 823169240Sjfv * up to the checksum. Then calculates the EEPROM checksum and writes the 824169240Sjfv * value to the EEPROM. 825169240Sjfv **/ 826177867Sjfvstatic s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 827169240Sjfv{ 828169240Sjfv u32 eecd; 829169240Sjfv s32 ret_val; 830169240Sjfv u16 i; 831169240Sjfv 832169240Sjfv DEBUGFUNC("e1000_update_nvm_checksum_82571"); 833169240Sjfv 834169240Sjfv ret_val = e1000_update_nvm_checksum_generic(hw); 835169240Sjfv if (ret_val) 836247064Sjfv return ret_val; 837169240Sjfv 838247064Sjfv /* If our nvm is an EEPROM, then we're done 839173788Sjfv * otherwise, commit the checksum to the flash NVM. 840173788Sjfv */ 841169240Sjfv if (hw->nvm.type != e1000_nvm_flash_hw) 842247064Sjfv return E1000_SUCCESS; 843169240Sjfv 844169240Sjfv /* Check for pending operations. */ 845169240Sjfv for (i = 0; i < E1000_FLASH_UPDATES; i++) { 846169240Sjfv msec_delay(1); 847247064Sjfv if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD)) 848169240Sjfv break; 849169240Sjfv } 850169240Sjfv 851247064Sjfv if (i == E1000_FLASH_UPDATES) 852247064Sjfv return -E1000_ERR_NVM; 853169240Sjfv 854169240Sjfv /* Reset the firmware if using STM opcode. */ 855169240Sjfv if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) { 856247064Sjfv /* The enabling of and the actual reset must be done 857169240Sjfv * in two write cycles. 858169240Sjfv */ 859169240Sjfv E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE); 860169240Sjfv E1000_WRITE_FLUSH(hw); 861169240Sjfv E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET); 862169240Sjfv } 863169240Sjfv 864169240Sjfv /* Commit the write to flash */ 865169240Sjfv eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD; 866169240Sjfv E1000_WRITE_REG(hw, E1000_EECD, eecd); 867169240Sjfv 868169240Sjfv for (i = 0; i < E1000_FLASH_UPDATES; i++) { 869169240Sjfv msec_delay(1); 870247064Sjfv if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD)) 871169240Sjfv break; 872169240Sjfv } 873169240Sjfv 874247064Sjfv if (i == E1000_FLASH_UPDATES) 875247064Sjfv return -E1000_ERR_NVM; 876169240Sjfv 877247064Sjfv return E1000_SUCCESS; 878169240Sjfv} 879169240Sjfv 880169240Sjfv/** 881169240Sjfv * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum 882169589Sjfv * @hw: pointer to the HW structure 883169240Sjfv * 884169240Sjfv * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 885169240Sjfv * and then verifies that the sum of the EEPROM is equal to 0xBABA. 886169240Sjfv **/ 887177867Sjfvstatic s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) 888169240Sjfv{ 889169240Sjfv DEBUGFUNC("e1000_validate_nvm_checksum_82571"); 890169240Sjfv 891169240Sjfv if (hw->nvm.type == e1000_nvm_flash_hw) 892169240Sjfv e1000_fix_nvm_checksum_82571(hw); 893169240Sjfv 894169240Sjfv return e1000_validate_nvm_checksum_generic(hw); 895169240Sjfv} 896169240Sjfv 897169240Sjfv/** 898169240Sjfv * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon 899169589Sjfv * @hw: pointer to the HW structure 900169589Sjfv * @offset: offset within the EEPROM to be written to 901169589Sjfv * @words: number of words to write 902169589Sjfv * @data: 16 bit word(s) to be written to the EEPROM 903169240Sjfv * 904169240Sjfv * After checking for invalid values, poll the EEPROM to ensure the previous 905169240Sjfv * command has completed before trying to write the next word. After write 906169240Sjfv * poll for completion. 907169240Sjfv * 908169240Sjfv * If e1000_update_nvm_checksum is not called after this function, the 909176667Sjfv * EEPROM will most likely contain an invalid checksum. 910169240Sjfv **/ 911173788Sjfvstatic s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 912228386Sjfv u16 words, u16 *data) 913169240Sjfv{ 914169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 915169240Sjfv u32 i, eewr = 0; 916247064Sjfv s32 ret_val = E1000_SUCCESS; 917169240Sjfv 918169240Sjfv DEBUGFUNC("e1000_write_nvm_eewr_82571"); 919169240Sjfv 920247064Sjfv /* A check for invalid values: offset too large, too many words, 921173788Sjfv * and not enough words. 922173788Sjfv */ 923169240Sjfv if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 924169240Sjfv (words == 0)) { 925169240Sjfv DEBUGOUT("nvm parameter(s) out of bounds\n"); 926247064Sjfv return -E1000_ERR_NVM; 927169240Sjfv } 928169240Sjfv 929169240Sjfv for (i = 0; i < words; i++) { 930169240Sjfv eewr = (data[i] << E1000_NVM_RW_REG_DATA) | 931169240Sjfv ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | 932169240Sjfv E1000_NVM_RW_REG_START; 933169240Sjfv 934169240Sjfv ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 935169240Sjfv if (ret_val) 936169240Sjfv break; 937169240Sjfv 938169240Sjfv E1000_WRITE_REG(hw, E1000_EEWR, eewr); 939169240Sjfv 940169240Sjfv ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 941169240Sjfv if (ret_val) 942169240Sjfv break; 943169240Sjfv } 944169240Sjfv 945169240Sjfv return ret_val; 946169240Sjfv} 947169240Sjfv 948169240Sjfv/** 949169240Sjfv * e1000_get_cfg_done_82571 - Poll for configuration done 950169589Sjfv * @hw: pointer to the HW structure 951169240Sjfv * 952169240Sjfv * Reads the management control register for the config done bit to be set. 953169240Sjfv **/ 954177867Sjfvstatic s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) 955169240Sjfv{ 956169240Sjfv s32 timeout = PHY_CFG_TIMEOUT; 957169240Sjfv 958169240Sjfv DEBUGFUNC("e1000_get_cfg_done_82571"); 959169240Sjfv 960169240Sjfv while (timeout) { 961200243Sjfv if (E1000_READ_REG(hw, E1000_EEMNGCTL) & 962200243Sjfv E1000_NVM_CFG_DONE_PORT_0) 963169240Sjfv break; 964169240Sjfv msec_delay(1); 965169240Sjfv timeout--; 966169240Sjfv } 967169240Sjfv if (!timeout) { 968169240Sjfv DEBUGOUT("MNG configuration cycle has not completed.\n"); 969247064Sjfv return -E1000_ERR_RESET; 970169240Sjfv } 971169240Sjfv 972247064Sjfv return E1000_SUCCESS; 973169240Sjfv} 974169240Sjfv 975169240Sjfv/** 976169240Sjfv * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state 977169589Sjfv * @hw: pointer to the HW structure 978169589Sjfv * @active: TRUE to enable LPLU, FALSE to disable 979169240Sjfv * 980169240Sjfv * Sets the LPLU D0 state according to the active flag. When activating LPLU 981169240Sjfv * this function also disables smart speed and vice versa. LPLU will not be 982169240Sjfv * activated unless the device autonegotiation advertisement meets standards 983169240Sjfv * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function 984169240Sjfv * pointer entry point only called by PHY setup routines. 985169240Sjfv **/ 986177867Sjfvstatic s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) 987169240Sjfv{ 988169240Sjfv struct e1000_phy_info *phy = &hw->phy; 989247064Sjfv s32 ret_val; 990169240Sjfv u16 data; 991169240Sjfv 992169240Sjfv DEBUGFUNC("e1000_set_d0_lplu_state_82571"); 993169240Sjfv 994177867Sjfv if (!(phy->ops.read_reg)) 995247064Sjfv return E1000_SUCCESS; 996177867Sjfv 997177867Sjfv ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 998169240Sjfv if (ret_val) 999247064Sjfv return ret_val; 1000169240Sjfv 1001169240Sjfv if (active) { 1002169240Sjfv data |= IGP02E1000_PM_D0_LPLU; 1003177867Sjfv ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1004228386Sjfv data); 1005169240Sjfv if (ret_val) 1006247064Sjfv return ret_val; 1007169240Sjfv 1008169240Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 1009177867Sjfv ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1010228386Sjfv &data); 1011247064Sjfv if (ret_val) 1012247064Sjfv return ret_val; 1013169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1014177867Sjfv ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1015228386Sjfv data); 1016169240Sjfv if (ret_val) 1017247064Sjfv return ret_val; 1018169240Sjfv } else { 1019169240Sjfv data &= ~IGP02E1000_PM_D0_LPLU; 1020177867Sjfv ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1021228386Sjfv data); 1022247064Sjfv /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1023169240Sjfv * during Dx states where the power conservation is most 1024169240Sjfv * important. During driver activity we should enable 1025173788Sjfv * SmartSpeed, so performance is maintained. 1026173788Sjfv */ 1027169240Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 1028177867Sjfv ret_val = phy->ops.read_reg(hw, 1029228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 1030228386Sjfv &data); 1031169240Sjfv if (ret_val) 1032247064Sjfv return ret_val; 1033169240Sjfv 1034169240Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 1035177867Sjfv ret_val = phy->ops.write_reg(hw, 1036228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 1037228386Sjfv data); 1038169240Sjfv if (ret_val) 1039247064Sjfv return ret_val; 1040169240Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 1041177867Sjfv ret_val = phy->ops.read_reg(hw, 1042228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 1043228386Sjfv &data); 1044169240Sjfv if (ret_val) 1045247064Sjfv return ret_val; 1046169240Sjfv 1047169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1048177867Sjfv ret_val = phy->ops.write_reg(hw, 1049228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 1050228386Sjfv data); 1051169240Sjfv if (ret_val) 1052247064Sjfv return ret_val; 1053169240Sjfv } 1054169240Sjfv } 1055169240Sjfv 1056247064Sjfv return E1000_SUCCESS; 1057169240Sjfv} 1058169240Sjfv 1059169240Sjfv/** 1060169240Sjfv * e1000_reset_hw_82571 - Reset hardware 1061169589Sjfv * @hw: pointer to the HW structure 1062169240Sjfv * 1063185353Sjfv * This resets the hardware into a known state. 1064169240Sjfv **/ 1065177867Sjfvstatic s32 e1000_reset_hw_82571(struct e1000_hw *hw) 1066169240Sjfv{ 1067247064Sjfv u32 ctrl, ctrl_ext, eecd, tctl; 1068169240Sjfv s32 ret_val; 1069169240Sjfv 1070169240Sjfv DEBUGFUNC("e1000_reset_hw_82571"); 1071169240Sjfv 1072247064Sjfv /* Prevent the PCI-E bus from sticking if there is no TLP connection 1073169240Sjfv * on the last TLP read/write transaction when MAC is reset. 1074169240Sjfv */ 1075169240Sjfv ret_val = e1000_disable_pcie_master_generic(hw); 1076185353Sjfv if (ret_val) 1077169240Sjfv DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1078169240Sjfv 1079169240Sjfv DEBUGOUT("Masking off all interrupts\n"); 1080169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1081169240Sjfv 1082169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 1083247064Sjfv tctl = E1000_READ_REG(hw, E1000_TCTL); 1084247064Sjfv tctl &= ~E1000_TCTL_EN; 1085247064Sjfv E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1086169240Sjfv E1000_WRITE_FLUSH(hw); 1087169240Sjfv 1088169240Sjfv msec_delay(10); 1089169240Sjfv 1090247064Sjfv /* Must acquire the MDIO ownership before MAC reset. 1091173788Sjfv * Ownership defaults to firmware after a reset. 1092173788Sjfv */ 1093190872Sjfv switch (hw->mac.type) { 1094200243Sjfv case e1000_82573: 1095213234Sjfv ret_val = e1000_get_hw_semaphore_82573(hw); 1096213234Sjfv break; 1097190872Sjfv case e1000_82574: 1098194865Sjfv case e1000_82583: 1099213234Sjfv ret_val = e1000_get_hw_semaphore_82574(hw); 1100190872Sjfv break; 1101190872Sjfv default: 1102190872Sjfv break; 1103169240Sjfv } 1104213234Sjfv if (ret_val) 1105213234Sjfv DEBUGOUT("Cannot acquire MDIO ownership\n"); 1106169240Sjfv 1107169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1108169240Sjfv 1109169240Sjfv DEBUGOUT("Issuing a global reset to MAC\n"); 1110169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1111169240Sjfv 1112213234Sjfv /* Must release MDIO ownership and mutex after MAC reset. */ 1113213234Sjfv switch (hw->mac.type) { 1114213234Sjfv case e1000_82574: 1115213234Sjfv case e1000_82583: 1116213234Sjfv e1000_put_hw_semaphore_82574(hw); 1117213234Sjfv break; 1118213234Sjfv default: 1119213234Sjfv break; 1120213234Sjfv } 1121213234Sjfv 1122169240Sjfv if (hw->nvm.type == e1000_nvm_flash_hw) { 1123169240Sjfv usec_delay(10); 1124169240Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1125169240Sjfv ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1126169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1127169240Sjfv E1000_WRITE_FLUSH(hw); 1128169240Sjfv } 1129169240Sjfv 1130169240Sjfv ret_val = e1000_get_auto_rd_done_generic(hw); 1131169240Sjfv if (ret_val) 1132169240Sjfv /* We don't want to continue accessing MAC registers. */ 1133247064Sjfv return ret_val; 1134169240Sjfv 1135247064Sjfv /* Phy configuration from NVM just starts after EECD_AUTO_RD is set. 1136169240Sjfv * Need to wait for Phy configuration completion before accessing 1137169240Sjfv * NVM and Phy. 1138169240Sjfv */ 1139190872Sjfv 1140190872Sjfv switch (hw->mac.type) { 1141247064Sjfv case e1000_82571: 1142247064Sjfv case e1000_82572: 1143247064Sjfv /* REQ and GNT bits need to be cleared when using AUTO_RD 1144247064Sjfv * to access the EEPROM. 1145247064Sjfv */ 1146247064Sjfv eecd = E1000_READ_REG(hw, E1000_EECD); 1147247064Sjfv eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT); 1148247064Sjfv E1000_WRITE_REG(hw, E1000_EECD, eecd); 1149247064Sjfv break; 1150200243Sjfv case e1000_82573: 1151190872Sjfv case e1000_82574: 1152194865Sjfv case e1000_82583: 1153169240Sjfv msec_delay(25); 1154190872Sjfv break; 1155190872Sjfv default: 1156190872Sjfv break; 1157190872Sjfv } 1158169240Sjfv 1159169240Sjfv /* Clear any pending interrupt events. */ 1160169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1161218588Sjfv E1000_READ_REG(hw, E1000_ICR); 1162169240Sjfv 1163213234Sjfv if (hw->mac.type == e1000_82571) { 1164213234Sjfv /* Install any alternate MAC address into RAR0 */ 1165213234Sjfv ret_val = e1000_check_alt_mac_addr_generic(hw); 1166213234Sjfv if (ret_val) 1167247064Sjfv return ret_val; 1168173788Sjfv 1169213234Sjfv e1000_set_laa_state_82571(hw, TRUE); 1170213234Sjfv } 1171190872Sjfv 1172190872Sjfv /* Reinitialize the 82571 serdes link state machine */ 1173190872Sjfv if (hw->phy.media_type == e1000_media_type_internal_serdes) 1174190872Sjfv hw->mac.serdes_link_state = e1000_serdes_link_down; 1175190872Sjfv 1176247064Sjfv return E1000_SUCCESS; 1177169240Sjfv} 1178169240Sjfv 1179169240Sjfv/** 1180169240Sjfv * e1000_init_hw_82571 - Initialize hardware 1181169589Sjfv * @hw: pointer to the HW structure 1182169240Sjfv * 1183169240Sjfv * This inits the hardware readying it for operation. 1184169240Sjfv **/ 1185177867Sjfvstatic s32 e1000_init_hw_82571(struct e1000_hw *hw) 1186169240Sjfv{ 1187169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1188169240Sjfv u32 reg_data; 1189169240Sjfv s32 ret_val; 1190169240Sjfv u16 i, rar_count = mac->rar_entry_count; 1191169240Sjfv 1192169240Sjfv DEBUGFUNC("e1000_init_hw_82571"); 1193169240Sjfv 1194169240Sjfv e1000_initialize_hw_bits_82571(hw); 1195169240Sjfv 1196169240Sjfv /* Initialize identification LED */ 1197190872Sjfv ret_val = mac->ops.id_led_init(hw); 1198247064Sjfv /* An error is not fatal and we should not stop init due to this */ 1199200243Sjfv if (ret_val) 1200169240Sjfv DEBUGOUT("Error initializing identification LED\n"); 1201169240Sjfv 1202169240Sjfv /* Disabling VLAN filtering */ 1203169240Sjfv DEBUGOUT("Initializing the IEEE VLAN\n"); 1204177867Sjfv mac->ops.clear_vfta(hw); 1205169240Sjfv 1206247064Sjfv /* Setup the receive address. 1207173788Sjfv * If, however, a locally administered address was assigned to the 1208169240Sjfv * 82571, we must reserve a RAR for it to work around an issue where 1209169240Sjfv * resetting one port will reload the MAC on the other port. 1210169240Sjfv */ 1211173788Sjfv if (e1000_get_laa_state_82571(hw)) 1212169240Sjfv rar_count--; 1213169240Sjfv e1000_init_rx_addrs_generic(hw, rar_count); 1214169240Sjfv 1215169240Sjfv /* Zero out the Multicast HASH table */ 1216169240Sjfv DEBUGOUT("Zeroing the MTA\n"); 1217169240Sjfv for (i = 0; i < mac->mta_reg_count; i++) 1218169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1219169240Sjfv 1220169240Sjfv /* Setup link and flow control */ 1221177867Sjfv ret_val = mac->ops.setup_link(hw); 1222169240Sjfv 1223169240Sjfv /* Set the transmit descriptor write-back policy */ 1224173788Sjfv reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1225169240Sjfv reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 1226228386Sjfv E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 1227173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 1228169240Sjfv 1229169240Sjfv /* ...for both queues. */ 1230190872Sjfv switch (mac->type) { 1231200243Sjfv case e1000_82573: 1232205869Sjfv e1000_enable_tx_pkt_filtering_generic(hw); 1233205869Sjfv /* fall through */ 1234190872Sjfv case e1000_82574: 1235194865Sjfv case e1000_82583: 1236169240Sjfv reg_data = E1000_READ_REG(hw, E1000_GCR); 1237169240Sjfv reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1238169240Sjfv E1000_WRITE_REG(hw, E1000_GCR, reg_data); 1239190872Sjfv break; 1240190872Sjfv default: 1241190872Sjfv reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1242190872Sjfv reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 1243228386Sjfv E1000_TXDCTL_FULL_TX_DESC_WB | 1244228386Sjfv E1000_TXDCTL_COUNT_DESC; 1245190872Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 1246190872Sjfv break; 1247169240Sjfv } 1248169240Sjfv 1249247064Sjfv /* Clear all of the statistics registers (clear on read). It is 1250169240Sjfv * important that we do this after we have tried to establish link 1251169240Sjfv * because the symbol error count will increment wildly if there 1252169240Sjfv * is no link. 1253169240Sjfv */ 1254169240Sjfv e1000_clear_hw_cntrs_82571(hw); 1255169240Sjfv 1256169240Sjfv return ret_val; 1257169240Sjfv} 1258169240Sjfv 1259169240Sjfv/** 1260169240Sjfv * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits 1261169589Sjfv * @hw: pointer to the HW structure 1262169240Sjfv * 1263169240Sjfv * Initializes required hardware-dependent bits needed for normal operation. 1264169240Sjfv **/ 1265173788Sjfvstatic void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 1266169240Sjfv{ 1267169240Sjfv u32 reg; 1268169240Sjfv 1269169240Sjfv DEBUGFUNC("e1000_initialize_hw_bits_82571"); 1270169240Sjfv 1271169240Sjfv /* Transmit Descriptor Control 0 */ 1272173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1273169240Sjfv reg |= (1 << 22); 1274173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 1275169240Sjfv 1276169240Sjfv /* Transmit Descriptor Control 1 */ 1277173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1278169240Sjfv reg |= (1 << 22); 1279173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 1280169240Sjfv 1281169240Sjfv /* Transmit Arbitration Control 0 */ 1282173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(0)); 1283169240Sjfv reg &= ~(0xF << 27); /* 30:27 */ 1284169240Sjfv switch (hw->mac.type) { 1285169240Sjfv case e1000_82571: 1286169240Sjfv case e1000_82572: 1287169240Sjfv reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); 1288169240Sjfv break; 1289228386Sjfv case e1000_82574: 1290228386Sjfv case e1000_82583: 1291228386Sjfv reg |= (1 << 26); 1292228386Sjfv break; 1293169240Sjfv default: 1294169240Sjfv break; 1295169240Sjfv } 1296173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(0), reg); 1297169240Sjfv 1298169240Sjfv /* Transmit Arbitration Control 1 */ 1299173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(1)); 1300169240Sjfv switch (hw->mac.type) { 1301169240Sjfv case e1000_82571: 1302169240Sjfv case e1000_82572: 1303169240Sjfv reg &= ~((1 << 29) | (1 << 30)); 1304169589Sjfv reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); 1305169240Sjfv if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1306169240Sjfv reg &= ~(1 << 28); 1307169240Sjfv else 1308169240Sjfv reg |= (1 << 28); 1309173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(1), reg); 1310169240Sjfv break; 1311169240Sjfv default: 1312169240Sjfv break; 1313169240Sjfv } 1314169240Sjfv 1315169240Sjfv /* Device Control */ 1316190872Sjfv switch (hw->mac.type) { 1317200243Sjfv case e1000_82573: 1318190872Sjfv case e1000_82574: 1319194865Sjfv case e1000_82583: 1320169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL); 1321169240Sjfv reg &= ~(1 << 29); 1322169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, reg); 1323190872Sjfv break; 1324190872Sjfv default: 1325190872Sjfv break; 1326169240Sjfv } 1327169240Sjfv 1328169240Sjfv /* Extended Device Control */ 1329190872Sjfv switch (hw->mac.type) { 1330200243Sjfv case e1000_82573: 1331190872Sjfv case e1000_82574: 1332194865Sjfv case e1000_82583: 1333169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1334169240Sjfv reg &= ~(1 << 23); 1335169240Sjfv reg |= (1 << 22); 1336169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1337190872Sjfv break; 1338190872Sjfv default: 1339190872Sjfv break; 1340169240Sjfv } 1341169240Sjfv 1342190872Sjfv if (hw->mac.type == e1000_82571) { 1343190872Sjfv reg = E1000_READ_REG(hw, E1000_PBA_ECC); 1344190872Sjfv reg |= E1000_PBA_ECC_CORR_EN; 1345190872Sjfv E1000_WRITE_REG(hw, E1000_PBA_ECC, reg); 1346190872Sjfv } 1347190872Sjfv 1348247064Sjfv /* Workaround for hardware errata. 1349190872Sjfv * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 1350190872Sjfv */ 1351190872Sjfv if ((hw->mac.type == e1000_82571) || 1352190872Sjfv (hw->mac.type == e1000_82572)) { 1353190872Sjfv reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1354190872Sjfv reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; 1355190872Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1356190872Sjfv } 1357190872Sjfv 1358247064Sjfv /* Disable IPv6 extension header parsing because some malformed 1359247064Sjfv * IPv6 headers can hang the Rx. 1360247064Sjfv */ 1361247064Sjfv if (hw->mac.type <= e1000_82573) { 1362247064Sjfv reg = E1000_READ_REG(hw, E1000_RFCTL); 1363247064Sjfv reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 1364247064Sjfv E1000_WRITE_REG(hw, E1000_RFCTL, reg); 1365247064Sjfv } 1366247064Sjfv 1367190872Sjfv /* PCI-Ex Control Registers */ 1368190872Sjfv switch (hw->mac.type) { 1369190872Sjfv case e1000_82574: 1370194865Sjfv case e1000_82583: 1371181027Sjfv reg = E1000_READ_REG(hw, E1000_GCR); 1372181027Sjfv reg |= (1 << 22); 1373185353Sjfv E1000_WRITE_REG(hw, E1000_GCR, reg); 1374200243Sjfv 1375247064Sjfv /* Workaround for hardware errata. 1376190872Sjfv * apply workaround for hardware errata documented in errata 1377190872Sjfv * docs Fixes issue where some error prone or unreliable PCIe 1378190872Sjfv * completions are occurring, particularly with ASPM enabled. 1379218588Sjfv * Without fix, issue can cause Tx timeouts. 1380190872Sjfv */ 1381190872Sjfv reg = E1000_READ_REG(hw, E1000_GCR2); 1382190872Sjfv reg |= 1; 1383190872Sjfv E1000_WRITE_REG(hw, E1000_GCR2, reg); 1384190872Sjfv break; 1385190872Sjfv default: 1386190872Sjfv break; 1387181027Sjfv } 1388181027Sjfv 1389169240Sjfv return; 1390169240Sjfv} 1391169240Sjfv 1392169240Sjfv/** 1393169240Sjfv * e1000_clear_vfta_82571 - Clear VLAN filter table 1394169589Sjfv * @hw: pointer to the HW structure 1395169240Sjfv * 1396169240Sjfv * Clears the register array which contains the VLAN filter table by 1397169240Sjfv * setting all the values to 0. 1398169240Sjfv **/ 1399177867Sjfvstatic void e1000_clear_vfta_82571(struct e1000_hw *hw) 1400169240Sjfv{ 1401169240Sjfv u32 offset; 1402169240Sjfv u32 vfta_value = 0; 1403169240Sjfv u32 vfta_offset = 0; 1404169240Sjfv u32 vfta_bit_in_reg = 0; 1405169240Sjfv 1406169240Sjfv DEBUGFUNC("e1000_clear_vfta_82571"); 1407169240Sjfv 1408190872Sjfv switch (hw->mac.type) { 1409200243Sjfv case e1000_82573: 1410190872Sjfv case e1000_82574: 1411194865Sjfv case e1000_82583: 1412169240Sjfv if (hw->mng_cookie.vlan_id != 0) { 1413247064Sjfv /* The VFTA is a 4096b bit-field, each identifying 1414200243Sjfv * a single VLAN ID. The following operations 1415200243Sjfv * determine which 32b entry (i.e. offset) into the 1416200243Sjfv * array we want to set the VLAN ID (i.e. bit) of 1417200243Sjfv * the manageability unit. 1418200243Sjfv */ 1419169240Sjfv vfta_offset = (hw->mng_cookie.vlan_id >> 1420247064Sjfv E1000_VFTA_ENTRY_SHIFT) & 1421247064Sjfv E1000_VFTA_ENTRY_MASK; 1422247064Sjfv vfta_bit_in_reg = 1423247064Sjfv 1 << (hw->mng_cookie.vlan_id & 1424247064Sjfv E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 1425169240Sjfv } 1426190872Sjfv break; 1427190872Sjfv default: 1428190872Sjfv break; 1429169240Sjfv } 1430200243Sjfv for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 1431247064Sjfv /* If the offset we want to clear is the same offset of the 1432200243Sjfv * manageability VLAN ID, then clear all bits except that of 1433200243Sjfv * the manageability unit. 1434200243Sjfv */ 1435200243Sjfv vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 1436200243Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); 1437200243Sjfv E1000_WRITE_FLUSH(hw); 1438200243Sjfv } 1439169240Sjfv} 1440169240Sjfv 1441169240Sjfv/** 1442181027Sjfv * e1000_check_mng_mode_82574 - Check manageability is enabled 1443181027Sjfv * @hw: pointer to the HW structure 1444181027Sjfv * 1445181027Sjfv * Reads the NVM Initialization Control Word 2 and returns TRUE 1446181027Sjfv * (>0) if any manageability is enabled, else FALSE (0). 1447181027Sjfv **/ 1448181027Sjfvstatic bool e1000_check_mng_mode_82574(struct e1000_hw *hw) 1449181027Sjfv{ 1450181027Sjfv u16 data; 1451181027Sjfv 1452181027Sjfv DEBUGFUNC("e1000_check_mng_mode_82574"); 1453181027Sjfv 1454181027Sjfv hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1455185353Sjfv return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; 1456181027Sjfv} 1457181027Sjfv 1458181027Sjfv/** 1459181027Sjfv * e1000_led_on_82574 - Turn LED on 1460181027Sjfv * @hw: pointer to the HW structure 1461185353Sjfv * 1462181027Sjfv * Turn LED on. 1463181027Sjfv **/ 1464181027Sjfvstatic s32 e1000_led_on_82574(struct e1000_hw *hw) 1465181027Sjfv{ 1466181027Sjfv u32 ctrl; 1467181027Sjfv u32 i; 1468181027Sjfv 1469181027Sjfv DEBUGFUNC("e1000_led_on_82574"); 1470181027Sjfv 1471181027Sjfv ctrl = hw->mac.ledctl_mode2; 1472181027Sjfv if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) { 1473247064Sjfv /* If no link, then turn LED on by setting the invert bit 1474181027Sjfv * for each LED that's "on" (0x0E) in ledctl_mode2. 1475181027Sjfv */ 1476181027Sjfv for (i = 0; i < 4; i++) 1477181027Sjfv if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1478181027Sjfv E1000_LEDCTL_MODE_LED_ON) 1479181027Sjfv ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); 1480181027Sjfv } 1481181027Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl); 1482181027Sjfv 1483181027Sjfv return E1000_SUCCESS; 1484181027Sjfv} 1485181027Sjfv 1486213234Sjfv/** 1487213234Sjfv * e1000_check_phy_82574 - check 82574 phy hung state 1488213234Sjfv * @hw: pointer to the HW structure 1489213234Sjfv * 1490213234Sjfv * Returns whether phy is hung or not 1491213234Sjfv **/ 1492213234Sjfvbool e1000_check_phy_82574(struct e1000_hw *hw) 1493213234Sjfv{ 1494213234Sjfv u16 status_1kbt = 0; 1495213234Sjfv u16 receive_errors = 0; 1496247064Sjfv s32 ret_val; 1497169240Sjfv 1498213234Sjfv DEBUGFUNC("e1000_check_phy_82574"); 1499213234Sjfv 1500247064Sjfv /* Read PHY Receive Error counter first, if its is max - all F's then 1501213234Sjfv * read the Base1000T status register If both are max then PHY is hung. 1502213234Sjfv */ 1503213234Sjfv ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER, 1504228386Sjfv &receive_errors); 1505213234Sjfv if (ret_val) 1506247064Sjfv return FALSE; 1507218588Sjfv if (receive_errors == E1000_RECEIVE_ERROR_MAX) { 1508213234Sjfv ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS, 1509228386Sjfv &status_1kbt); 1510213234Sjfv if (ret_val) 1511247064Sjfv return FALSE; 1512213234Sjfv if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) == 1513213234Sjfv E1000_IDLE_ERROR_COUNT_MASK) 1514247064Sjfv return TRUE; 1515213234Sjfv } 1516247064Sjfv 1517247064Sjfv return FALSE; 1518213234Sjfv} 1519213234Sjfv 1520213234Sjfv 1521169240Sjfv/** 1522169240Sjfv * e1000_setup_link_82571 - Setup flow control and link settings 1523169589Sjfv * @hw: pointer to the HW structure 1524169240Sjfv * 1525169240Sjfv * Determines which flow control settings to use, then configures flow 1526169240Sjfv * control. Calls the appropriate media-specific link configuration 1527169240Sjfv * function. Assuming the adapter has a valid link partner, a valid link 1528169240Sjfv * should be established. Assumes the hardware has previously been reset 1529169240Sjfv * and the transmitter and receiver are not enabled. 1530169240Sjfv **/ 1531177867Sjfvstatic s32 e1000_setup_link_82571(struct e1000_hw *hw) 1532169240Sjfv{ 1533169240Sjfv DEBUGFUNC("e1000_setup_link_82571"); 1534169240Sjfv 1535247064Sjfv /* 82573 does not have a word in the NVM to determine 1536169240Sjfv * the default flow control setting, so we explicitly 1537169240Sjfv * set it to full. 1538169240Sjfv */ 1539190872Sjfv switch (hw->mac.type) { 1540200243Sjfv case e1000_82573: 1541190872Sjfv case e1000_82574: 1542194865Sjfv case e1000_82583: 1543190872Sjfv if (hw->fc.requested_mode == e1000_fc_default) 1544190872Sjfv hw->fc.requested_mode = e1000_fc_full; 1545190872Sjfv break; 1546190872Sjfv default: 1547190872Sjfv break; 1548190872Sjfv } 1549218588Sjfv 1550169240Sjfv return e1000_setup_link_generic(hw); 1551169240Sjfv} 1552169240Sjfv 1553169240Sjfv/** 1554169240Sjfv * e1000_setup_copper_link_82571 - Configure copper link settings 1555169589Sjfv * @hw: pointer to the HW structure 1556169240Sjfv * 1557169240Sjfv * Configures the link for auto-neg or forced speed and duplex. Then we check 1558169240Sjfv * for link, once link is established calls to configure collision distance 1559169240Sjfv * and flow control are called. 1560169240Sjfv **/ 1561177867Sjfvstatic s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) 1562169240Sjfv{ 1563194865Sjfv u32 ctrl; 1564205869Sjfv s32 ret_val; 1565169240Sjfv 1566169240Sjfv DEBUGFUNC("e1000_setup_copper_link_82571"); 1567169240Sjfv 1568169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1569169240Sjfv ctrl |= E1000_CTRL_SLU; 1570169240Sjfv ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1571169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1572169240Sjfv 1573169240Sjfv switch (hw->phy.type) { 1574169240Sjfv case e1000_phy_m88: 1575176667Sjfv case e1000_phy_bm: 1576169240Sjfv ret_val = e1000_copper_link_setup_m88(hw); 1577169240Sjfv break; 1578169240Sjfv case e1000_phy_igp_2: 1579169240Sjfv ret_val = e1000_copper_link_setup_igp(hw); 1580169240Sjfv break; 1581169240Sjfv default: 1582247064Sjfv return -E1000_ERR_PHY; 1583169240Sjfv break; 1584169240Sjfv } 1585169240Sjfv 1586169240Sjfv if (ret_val) 1587247064Sjfv return ret_val; 1588169240Sjfv 1589247064Sjfv return e1000_setup_copper_link_generic(hw); 1590169240Sjfv} 1591169240Sjfv 1592169240Sjfv/** 1593169240Sjfv * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes 1594169589Sjfv * @hw: pointer to the HW structure 1595169240Sjfv * 1596169240Sjfv * Configures collision distance and flow control for fiber and serdes links. 1597169240Sjfv * Upon successful setup, poll for link. 1598169240Sjfv **/ 1599177867Sjfvstatic s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) 1600169240Sjfv{ 1601169240Sjfv DEBUGFUNC("e1000_setup_fiber_serdes_link_82571"); 1602169240Sjfv 1603169240Sjfv switch (hw->mac.type) { 1604169240Sjfv case e1000_82571: 1605169240Sjfv case e1000_82572: 1606247064Sjfv /* If SerDes loopback mode is entered, there is no form 1607169240Sjfv * of reset to take the adapter out of that mode. So we 1608169240Sjfv * have to explicitly take the adapter out of loopback 1609176667Sjfv * mode. This prevents drivers from twiddling their thumbs 1610169240Sjfv * if another tool failed to take it out of loopback mode. 1611169240Sjfv */ 1612228386Sjfv E1000_WRITE_REG(hw, E1000_SCTL, 1613228386Sjfv E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1614169240Sjfv break; 1615169240Sjfv default: 1616169240Sjfv break; 1617169240Sjfv } 1618169240Sjfv 1619169240Sjfv return e1000_setup_fiber_serdes_link_generic(hw); 1620169240Sjfv} 1621169240Sjfv 1622169240Sjfv/** 1623190872Sjfv * e1000_check_for_serdes_link_82571 - Check for link (Serdes) 1624190872Sjfv * @hw: pointer to the HW structure 1625190872Sjfv * 1626194865Sjfv * Reports the link state as up or down. 1627194865Sjfv * 1628194865Sjfv * If autonegotiation is supported by the link partner, the link state is 1629200243Sjfv * determined by the result of autonegotiation. This is the most likely case. 1630194865Sjfv * If autonegotiation is not supported by the link partner, and the link 1631194865Sjfv * has a valid signal, force the link up. 1632194865Sjfv * 1633194865Sjfv * The link state is represented internally here by 4 states: 1634194865Sjfv * 1635194865Sjfv * 1) down 1636194865Sjfv * 2) autoneg_progress 1637228386Sjfv * 3) autoneg_complete (the link successfully autonegotiated) 1638194865Sjfv * 4) forced_up (the link has been forced up, it did not autonegotiate) 1639194865Sjfv * 1640190872Sjfv **/ 1641200243Sjfvstatic s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) 1642190872Sjfv{ 1643190872Sjfv struct e1000_mac_info *mac = &hw->mac; 1644190872Sjfv u32 rxcw; 1645190872Sjfv u32 ctrl; 1646190872Sjfv u32 status; 1647213234Sjfv u32 txcw; 1648213234Sjfv u32 i; 1649190872Sjfv s32 ret_val = E1000_SUCCESS; 1650190872Sjfv 1651190872Sjfv DEBUGFUNC("e1000_check_for_serdes_link_82571"); 1652190872Sjfv 1653190872Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1654190872Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 1655247064Sjfv E1000_READ_REG(hw, E1000_RXCW); 1656247064Sjfv /* SYNCH bit and IV bit are sticky */ 1657247064Sjfv usec_delay(10); 1658190872Sjfv rxcw = E1000_READ_REG(hw, E1000_RXCW); 1659190872Sjfv 1660190872Sjfv if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { 1661190872Sjfv /* Receiver is synchronized with no invalid bits. */ 1662190872Sjfv switch (mac->serdes_link_state) { 1663190872Sjfv case e1000_serdes_link_autoneg_complete: 1664190872Sjfv if (!(status & E1000_STATUS_LU)) { 1665247064Sjfv /* We have lost link, retry autoneg before 1666190872Sjfv * reporting link failure 1667190872Sjfv */ 1668190872Sjfv mac->serdes_link_state = 1669190872Sjfv e1000_serdes_link_autoneg_progress; 1670194865Sjfv mac->serdes_has_link = FALSE; 1671190872Sjfv DEBUGOUT("AN_UP -> AN_PROG\n"); 1672213234Sjfv } else { 1673213234Sjfv mac->serdes_has_link = TRUE; 1674190872Sjfv } 1675213234Sjfv break; 1676190872Sjfv 1677190872Sjfv case e1000_serdes_link_forced_up: 1678247064Sjfv /* If we are receiving /C/ ordered sets, re-enable 1679190872Sjfv * auto-negotiation in the TXCW register and disable 1680190872Sjfv * forced link in the Device Control register in an 1681190872Sjfv * attempt to auto-negotiate with our link partner. 1682190872Sjfv */ 1683247064Sjfv if (rxcw & E1000_RXCW_C) { 1684190872Sjfv /* Enable autoneg, and unforce link up */ 1685190872Sjfv E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1686190872Sjfv E1000_WRITE_REG(hw, E1000_CTRL, 1687190872Sjfv (ctrl & ~E1000_CTRL_SLU)); 1688190872Sjfv mac->serdes_link_state = 1689190872Sjfv e1000_serdes_link_autoneg_progress; 1690194865Sjfv mac->serdes_has_link = FALSE; 1691190872Sjfv DEBUGOUT("FORCED_UP -> AN_PROG\n"); 1692213234Sjfv } else { 1693213234Sjfv mac->serdes_has_link = TRUE; 1694190872Sjfv } 1695190872Sjfv break; 1696190872Sjfv 1697190872Sjfv case e1000_serdes_link_autoneg_progress: 1698194865Sjfv if (rxcw & E1000_RXCW_C) { 1699247064Sjfv /* We received /C/ ordered sets, meaning the 1700194865Sjfv * link partner has autonegotiated, and we can 1701200243Sjfv * trust the Link Up (LU) status bit. 1702194865Sjfv */ 1703194865Sjfv if (status & E1000_STATUS_LU) { 1704194865Sjfv mac->serdes_link_state = 1705194865Sjfv e1000_serdes_link_autoneg_complete; 1706194865Sjfv DEBUGOUT("AN_PROG -> AN_UP\n"); 1707194865Sjfv mac->serdes_has_link = TRUE; 1708194865Sjfv } else { 1709200243Sjfv /* Autoneg completed, but failed. */ 1710194865Sjfv mac->serdes_link_state = 1711194865Sjfv e1000_serdes_link_down; 1712194865Sjfv DEBUGOUT("AN_PROG -> DOWN\n"); 1713194865Sjfv } 1714190872Sjfv } else { 1715247064Sjfv /* The link partner did not autoneg. 1716194865Sjfv * Force link up and full duplex, and change 1717194865Sjfv * state to forced. 1718190872Sjfv */ 1719190872Sjfv E1000_WRITE_REG(hw, E1000_TXCW, 1720194865Sjfv (mac->txcw & ~E1000_TXCW_ANE)); 1721190872Sjfv ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1722190872Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1723190872Sjfv 1724190872Sjfv /* Configure Flow Control after link up. */ 1725190872Sjfv ret_val = 1726190872Sjfv e1000_config_fc_after_link_up_generic(hw); 1727190872Sjfv if (ret_val) { 1728190872Sjfv DEBUGOUT("Error config flow control\n"); 1729190872Sjfv break; 1730190872Sjfv } 1731190872Sjfv mac->serdes_link_state = 1732228386Sjfv e1000_serdes_link_forced_up; 1733194865Sjfv mac->serdes_has_link = TRUE; 1734190872Sjfv DEBUGOUT("AN_PROG -> FORCED_UP\n"); 1735190872Sjfv } 1736190872Sjfv break; 1737190872Sjfv 1738190872Sjfv case e1000_serdes_link_down: 1739190872Sjfv default: 1740247064Sjfv /* The link was down but the receiver has now gained 1741190872Sjfv * valid sync, so lets see if we can bring the link 1742200243Sjfv * up. 1743200243Sjfv */ 1744190872Sjfv E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1745228386Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & 1746228386Sjfv ~E1000_CTRL_SLU)); 1747190872Sjfv mac->serdes_link_state = 1748228386Sjfv e1000_serdes_link_autoneg_progress; 1749213234Sjfv mac->serdes_has_link = FALSE; 1750190872Sjfv DEBUGOUT("DOWN -> AN_PROG\n"); 1751190872Sjfv break; 1752190872Sjfv } 1753190872Sjfv } else { 1754190872Sjfv if (!(rxcw & E1000_RXCW_SYNCH)) { 1755190872Sjfv mac->serdes_has_link = FALSE; 1756190872Sjfv mac->serdes_link_state = e1000_serdes_link_down; 1757190872Sjfv DEBUGOUT("ANYSTATE -> DOWN\n"); 1758190872Sjfv } else { 1759247064Sjfv /* Check several times, if SYNCH bit and CONFIG 1760247064Sjfv * bit both are consistently 1 then simply ignore 1761247064Sjfv * the IV bit and restart Autoneg 1762190872Sjfv */ 1763213234Sjfv for (i = 0; i < AN_RETRY_COUNT; i++) { 1764213234Sjfv usec_delay(10); 1765213234Sjfv rxcw = E1000_READ_REG(hw, E1000_RXCW); 1766247064Sjfv if ((rxcw & E1000_RXCW_SYNCH) && 1767247064Sjfv (rxcw & E1000_RXCW_C)) 1768247064Sjfv continue; 1769247064Sjfv 1770247064Sjfv if (rxcw & E1000_RXCW_IV) { 1771213234Sjfv mac->serdes_has_link = FALSE; 1772213234Sjfv mac->serdes_link_state = 1773228386Sjfv e1000_serdes_link_down; 1774213234Sjfv DEBUGOUT("ANYSTATE -> DOWN\n"); 1775213234Sjfv break; 1776213234Sjfv } 1777213234Sjfv } 1778213234Sjfv 1779213234Sjfv if (i == AN_RETRY_COUNT) { 1780213234Sjfv txcw = E1000_READ_REG(hw, E1000_TXCW); 1781213234Sjfv txcw |= E1000_TXCW_ANE; 1782213234Sjfv E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1783213234Sjfv mac->serdes_link_state = 1784228386Sjfv e1000_serdes_link_autoneg_progress; 1785190872Sjfv mac->serdes_has_link = FALSE; 1786213234Sjfv DEBUGOUT("ANYSTATE -> AN_PROG\n"); 1787190872Sjfv } 1788190872Sjfv } 1789190872Sjfv } 1790190872Sjfv 1791190872Sjfv return ret_val; 1792190872Sjfv} 1793190872Sjfv 1794190872Sjfv/** 1795169240Sjfv * e1000_valid_led_default_82571 - Verify a valid default LED config 1796169589Sjfv * @hw: pointer to the HW structure 1797169589Sjfv * @data: pointer to the NVM (EEPROM) 1798169240Sjfv * 1799169240Sjfv * Read the EEPROM for the current default LED configuration. If the 1800169240Sjfv * LED configuration is not valid, set to a valid LED configuration. 1801169240Sjfv **/ 1802177867Sjfvstatic s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) 1803169240Sjfv{ 1804169240Sjfv s32 ret_val; 1805169240Sjfv 1806169240Sjfv DEBUGFUNC("e1000_valid_led_default_82571"); 1807169240Sjfv 1808177867Sjfv ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1809169240Sjfv if (ret_val) { 1810169240Sjfv DEBUGOUT("NVM Read Error\n"); 1811247064Sjfv return ret_val; 1812169240Sjfv } 1813169240Sjfv 1814190872Sjfv switch (hw->mac.type) { 1815200243Sjfv case e1000_82573: 1816190872Sjfv case e1000_82574: 1817194865Sjfv case e1000_82583: 1818200243Sjfv if (*data == ID_LED_RESERVED_F746) 1819190872Sjfv *data = ID_LED_DEFAULT_82573; 1820190872Sjfv break; 1821190872Sjfv default: 1822190872Sjfv if (*data == ID_LED_RESERVED_0000 || 1823200243Sjfv *data == ID_LED_RESERVED_FFFF) 1824190872Sjfv *data = ID_LED_DEFAULT; 1825190872Sjfv break; 1826190872Sjfv } 1827190872Sjfv 1828247064Sjfv return E1000_SUCCESS; 1829169240Sjfv} 1830169240Sjfv 1831169240Sjfv/** 1832169240Sjfv * e1000_get_laa_state_82571 - Get locally administered address state 1833169589Sjfv * @hw: pointer to the HW structure 1834169240Sjfv * 1835176667Sjfv * Retrieve and return the current locally administered address state. 1836169240Sjfv **/ 1837173788Sjfvbool e1000_get_laa_state_82571(struct e1000_hw *hw) 1838169240Sjfv{ 1839169240Sjfv DEBUGFUNC("e1000_get_laa_state_82571"); 1840169240Sjfv 1841169240Sjfv if (hw->mac.type != e1000_82571) 1842185353Sjfv return FALSE; 1843169240Sjfv 1844185353Sjfv return hw->dev_spec._82571.laa_is_present; 1845169240Sjfv} 1846169240Sjfv 1847169240Sjfv/** 1848169240Sjfv * e1000_set_laa_state_82571 - Set locally administered address state 1849169589Sjfv * @hw: pointer to the HW structure 1850169589Sjfv * @state: enable/disable locally administered address 1851169240Sjfv * 1852176667Sjfv * Enable/Disable the current locally administered address state. 1853169240Sjfv **/ 1854173788Sjfvvoid e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) 1855169240Sjfv{ 1856169240Sjfv DEBUGFUNC("e1000_set_laa_state_82571"); 1857169240Sjfv 1858169240Sjfv if (hw->mac.type != e1000_82571) 1859185353Sjfv return; 1860169240Sjfv 1861185353Sjfv hw->dev_spec._82571.laa_is_present = state; 1862169240Sjfv 1863169240Sjfv /* If workaround is activated... */ 1864185353Sjfv if (state) 1865247064Sjfv /* Hold a copy of the LAA in RAR[14] This is done so that 1866169240Sjfv * between the time RAR[0] gets clobbered and the time it 1867169240Sjfv * gets fixed, the actual LAA is in one of the RARs and no 1868169240Sjfv * incoming packets directed to this port are dropped. 1869169240Sjfv * Eventually the LAA will be in RAR[0] and RAR[14]. 1870169240Sjfv */ 1871238148Sjfv hw->mac.ops.rar_set(hw, hw->mac.addr, 1872247064Sjfv hw->mac.rar_entry_count - 1); 1873169240Sjfv return; 1874169240Sjfv} 1875169240Sjfv 1876169240Sjfv/** 1877169240Sjfv * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum 1878169589Sjfv * @hw: pointer to the HW structure 1879169240Sjfv * 1880169240Sjfv * Verifies that the EEPROM has completed the update. After updating the 1881169240Sjfv * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If 1882169240Sjfv * the checksum fix is not implemented, we need to set the bit and update 1883169240Sjfv * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, 1884169240Sjfv * we need to return bad checksum. 1885169240Sjfv **/ 1886173788Sjfvstatic s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 1887169240Sjfv{ 1888169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 1889247064Sjfv s32 ret_val; 1890169240Sjfv u16 data; 1891169240Sjfv 1892169240Sjfv DEBUGFUNC("e1000_fix_nvm_checksum_82571"); 1893169240Sjfv 1894169240Sjfv if (nvm->type != e1000_nvm_flash_hw) 1895247064Sjfv return E1000_SUCCESS; 1896169240Sjfv 1897247064Sjfv /* Check bit 4 of word 10h. If it is 0, firmware is done updating 1898169240Sjfv * 10h-12h. Checksum may need to be fixed. 1899169240Sjfv */ 1900177867Sjfv ret_val = nvm->ops.read(hw, 0x10, 1, &data); 1901169240Sjfv if (ret_val) 1902247064Sjfv return ret_val; 1903169240Sjfv 1904169240Sjfv if (!(data & 0x10)) { 1905247064Sjfv /* Read 0x23 and check bit 15. This bit is a 1 1906169240Sjfv * when the checksum has already been fixed. If 1907169240Sjfv * the checksum is still wrong and this bit is a 1908169240Sjfv * 1, we need to return bad checksum. Otherwise, 1909169240Sjfv * we need to set this bit to a 1 and update the 1910169240Sjfv * checksum. 1911169240Sjfv */ 1912177867Sjfv ret_val = nvm->ops.read(hw, 0x23, 1, &data); 1913169240Sjfv if (ret_val) 1914247064Sjfv return ret_val; 1915169240Sjfv 1916169240Sjfv if (!(data & 0x8000)) { 1917169240Sjfv data |= 0x8000; 1918177867Sjfv ret_val = nvm->ops.write(hw, 0x23, 1, &data); 1919169240Sjfv if (ret_val) 1920247064Sjfv return ret_val; 1921177867Sjfv ret_val = nvm->ops.update(hw); 1922247064Sjfv if (ret_val) 1923247064Sjfv return ret_val; 1924169240Sjfv } 1925169240Sjfv } 1926169240Sjfv 1927247064Sjfv return E1000_SUCCESS; 1928169240Sjfv} 1929169240Sjfv 1930190872Sjfv 1931169240Sjfv/** 1932173788Sjfv * e1000_read_mac_addr_82571 - Read device MAC address 1933173788Sjfv * @hw: pointer to the HW structure 1934173788Sjfv **/ 1935177867Sjfvstatic s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) 1936173788Sjfv{ 1937173788Sjfv DEBUGFUNC("e1000_read_mac_addr_82571"); 1938173788Sjfv 1939213234Sjfv if (hw->mac.type == e1000_82571) { 1940247064Sjfv s32 ret_val; 1941247064Sjfv 1942247064Sjfv /* If there's an alternate MAC address place it in RAR0 1943213234Sjfv * so that it will override the Si installed default perm 1944213234Sjfv * address. 1945213234Sjfv */ 1946213234Sjfv ret_val = e1000_check_alt_mac_addr_generic(hw); 1947213234Sjfv if (ret_val) 1948247064Sjfv return ret_val; 1949213234Sjfv } 1950190872Sjfv 1951247064Sjfv return e1000_read_mac_addr_generic(hw); 1952173788Sjfv} 1953173788Sjfv 1954173788Sjfv/** 1955173788Sjfv * e1000_power_down_phy_copper_82571 - Remove link during PHY power down 1956173788Sjfv * @hw: pointer to the HW structure 1957173788Sjfv * 1958173788Sjfv * In the case of a PHY power down to save power, or to turn off link during a 1959173788Sjfv * driver unload, or wake on lan is not enabled, remove the link. 1960173788Sjfv **/ 1961177867Sjfvstatic void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) 1962173788Sjfv{ 1963177867Sjfv struct e1000_phy_info *phy = &hw->phy; 1964177867Sjfv struct e1000_mac_info *mac = &hw->mac; 1965177867Sjfv 1966247064Sjfv if (!phy->ops.check_reset_block) 1967177867Sjfv return; 1968177867Sjfv 1969173788Sjfv /* If the management interface is not enabled, then power down */ 1970177867Sjfv if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 1971173788Sjfv e1000_power_down_phy_copper(hw); 1972173788Sjfv 1973173788Sjfv return; 1974173788Sjfv} 1975173788Sjfv 1976173788Sjfv/** 1977169240Sjfv * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters 1978169589Sjfv * @hw: pointer to the HW structure 1979169240Sjfv * 1980169240Sjfv * Clears the hardware counters by reading the counter registers. 1981169240Sjfv **/ 1982177867Sjfvstatic void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) 1983169240Sjfv{ 1984169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_82571"); 1985169240Sjfv 1986169240Sjfv e1000_clear_hw_cntrs_base_generic(hw); 1987169240Sjfv 1988185353Sjfv E1000_READ_REG(hw, E1000_PRC64); 1989185353Sjfv E1000_READ_REG(hw, E1000_PRC127); 1990185353Sjfv E1000_READ_REG(hw, E1000_PRC255); 1991185353Sjfv E1000_READ_REG(hw, E1000_PRC511); 1992185353Sjfv E1000_READ_REG(hw, E1000_PRC1023); 1993185353Sjfv E1000_READ_REG(hw, E1000_PRC1522); 1994185353Sjfv E1000_READ_REG(hw, E1000_PTC64); 1995185353Sjfv E1000_READ_REG(hw, E1000_PTC127); 1996185353Sjfv E1000_READ_REG(hw, E1000_PTC255); 1997185353Sjfv E1000_READ_REG(hw, E1000_PTC511); 1998185353Sjfv E1000_READ_REG(hw, E1000_PTC1023); 1999185353Sjfv E1000_READ_REG(hw, E1000_PTC1522); 2000169240Sjfv 2001185353Sjfv E1000_READ_REG(hw, E1000_ALGNERRC); 2002185353Sjfv E1000_READ_REG(hw, E1000_RXERRC); 2003185353Sjfv E1000_READ_REG(hw, E1000_TNCRS); 2004185353Sjfv E1000_READ_REG(hw, E1000_CEXTERR); 2005185353Sjfv E1000_READ_REG(hw, E1000_TSCTC); 2006185353Sjfv E1000_READ_REG(hw, E1000_TSCTFC); 2007169240Sjfv 2008185353Sjfv E1000_READ_REG(hw, E1000_MGTPRC); 2009185353Sjfv E1000_READ_REG(hw, E1000_MGTPDC); 2010185353Sjfv E1000_READ_REG(hw, E1000_MGTPTC); 2011169240Sjfv 2012185353Sjfv E1000_READ_REG(hw, E1000_IAC); 2013185353Sjfv E1000_READ_REG(hw, E1000_ICRXOC); 2014185353Sjfv 2015185353Sjfv E1000_READ_REG(hw, E1000_ICRXPTC); 2016185353Sjfv E1000_READ_REG(hw, E1000_ICRXATC); 2017185353Sjfv E1000_READ_REG(hw, E1000_ICTXPTC); 2018185353Sjfv E1000_READ_REG(hw, E1000_ICTXATC); 2019185353Sjfv E1000_READ_REG(hw, E1000_ICTXQEC); 2020185353Sjfv E1000_READ_REG(hw, E1000_ICTXQMTC); 2021185353Sjfv E1000_READ_REG(hw, E1000_ICRXDMTC); 2022169240Sjfv} 2023