e1000_82571.c revision 194865
1177867Sjfv/****************************************************************************** 2169240Sjfv 3190872Sjfv Copyright (c) 2001-2009, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD: head/sys/dev/e1000/e1000_82571.c 194865 2009-06-24 17:41:29Z jfv $*/ 34169240Sjfv 35185353Sjfv/* 36185353Sjfv * 82571EB Gigabit Ethernet Controller 37185353Sjfv * 82571EB Gigabit Ethernet Controller (Copper) 38185353Sjfv * 82571EB Gigabit Ethernet Controller (Fiber) 39185353Sjfv * 82571EB Dual Port Gigabit Mezzanine Adapter 40185353Sjfv * 82571EB Quad Port Gigabit Mezzanine Adapter 41185353Sjfv * 82571PT Gigabit PT Quad Port Server ExpressModule 42185353Sjfv * 82572EI Gigabit Ethernet Controller (Copper) 43185353Sjfv * 82572EI Gigabit Ethernet Controller (Fiber) 44185353Sjfv * 82572EI Gigabit Ethernet Controller 45185353Sjfv * 82573V Gigabit Ethernet Controller (Copper) 46185353Sjfv * 82573E Gigabit Ethernet Controller (Copper) 47185353Sjfv * 82573L Gigabit Ethernet Controller 48185353Sjfv * 82574L Gigabit Network Connection 49190872Sjfv * 82574L Gigabit Network Connection 50194865Sjfv * 82583V Gigabit Network Connection 51169240Sjfv */ 52169240Sjfv 53169589Sjfv#include "e1000_api.h" 54169240Sjfv 55177867Sjfvstatic s32 e1000_init_phy_params_82571(struct e1000_hw *hw); 56177867Sjfvstatic s32 e1000_init_nvm_params_82571(struct e1000_hw *hw); 57177867Sjfvstatic s32 e1000_init_mac_params_82571(struct e1000_hw *hw); 58177867Sjfvstatic s32 e1000_acquire_nvm_82571(struct e1000_hw *hw); 59177867Sjfvstatic void e1000_release_nvm_82571(struct e1000_hw *hw); 60177867Sjfvstatic s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, 61169240Sjfv u16 words, u16 *data); 62177867Sjfvstatic s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw); 63177867Sjfvstatic s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw); 64177867Sjfvstatic s32 e1000_get_cfg_done_82571(struct e1000_hw *hw); 65177867Sjfvstatic s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, 66173788Sjfv bool active); 67177867Sjfvstatic s32 e1000_reset_hw_82571(struct e1000_hw *hw); 68177867Sjfvstatic s32 e1000_init_hw_82571(struct e1000_hw *hw); 69177867Sjfvstatic void e1000_clear_vfta_82571(struct e1000_hw *hw); 70181027Sjfvstatic bool e1000_check_mng_mode_82574(struct e1000_hw *hw); 71181027Sjfvstatic s32 e1000_led_on_82574(struct e1000_hw *hw); 72177867Sjfvstatic s32 e1000_setup_link_82571(struct e1000_hw *hw); 73177867Sjfvstatic s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); 74190872Sjfvstatic s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); 75177867Sjfvstatic s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); 76177867Sjfvstatic s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data); 77177867Sjfvstatic void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); 78169589Sjfvstatic s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw); 79169240Sjfvstatic s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); 80169240Sjfvstatic s32 e1000_get_phy_id_82571(struct e1000_hw *hw); 81169589Sjfvstatic void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); 82169240Sjfvstatic void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); 83169240Sjfvstatic s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 84169240Sjfv u16 words, u16 *data); 85177867Sjfvstatic s32 e1000_read_mac_addr_82571(struct e1000_hw *hw); 86177867Sjfvstatic void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); 87169240Sjfv 88169240Sjfv/** 89169240Sjfv * e1000_init_phy_params_82571 - Init PHY func ptrs. 90169589Sjfv * @hw: pointer to the HW structure 91169240Sjfv **/ 92177867Sjfvstatic s32 e1000_init_phy_params_82571(struct e1000_hw *hw) 93169240Sjfv{ 94169240Sjfv struct e1000_phy_info *phy = &hw->phy; 95169240Sjfv s32 ret_val = E1000_SUCCESS; 96169240Sjfv 97169240Sjfv DEBUGFUNC("e1000_init_phy_params_82571"); 98169240Sjfv 99173788Sjfv if (hw->phy.media_type != e1000_media_type_copper) { 100185353Sjfv phy->type = e1000_phy_none; 101169240Sjfv goto out; 102169240Sjfv } 103169240Sjfv 104169240Sjfv phy->addr = 1; 105169240Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 106169240Sjfv phy->reset_delay_us = 100; 107169240Sjfv 108177867Sjfv phy->ops.acquire = e1000_get_hw_semaphore_82571; 109177867Sjfv phy->ops.check_polarity = e1000_check_polarity_igp; 110177867Sjfv phy->ops.check_reset_block = e1000_check_reset_block_generic; 111177867Sjfv phy->ops.release = e1000_put_hw_semaphore_82571; 112177867Sjfv phy->ops.reset = e1000_phy_hw_reset_generic; 113177867Sjfv phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571; 114177867Sjfv phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 115177867Sjfv phy->ops.power_up = e1000_power_up_phy_copper; 116177867Sjfv phy->ops.power_down = e1000_power_down_phy_copper_82571; 117169240Sjfv 118169240Sjfv switch (hw->mac.type) { 119169240Sjfv case e1000_82571: 120169240Sjfv case e1000_82572: 121177867Sjfv phy->type = e1000_phy_igp_2; 122177867Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_82571; 123177867Sjfv phy->ops.get_info = e1000_get_phy_info_igp; 124177867Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 125177867Sjfv phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 126177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_igp; 127177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_igp; 128173788Sjfv 129173788Sjfv /* This uses above function pointers */ 130173788Sjfv ret_val = e1000_get_phy_id_82571(hw); 131173788Sjfv 132173788Sjfv /* Verify PHY ID */ 133173788Sjfv if (phy->id != IGP01E1000_I_PHY_ID) { 134173788Sjfv ret_val = -E1000_ERR_PHY; 135173788Sjfv goto out; 136173788Sjfv } 137169240Sjfv break; 138169240Sjfv case e1000_82573: 139177867Sjfv phy->type = e1000_phy_m88; 140177867Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 141177867Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 142177867Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 143177867Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 144177867Sjfv phy->ops.get_cable_length = e1000_get_cable_length_m88; 145177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_m88; 146177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_m88; 147169240Sjfv 148173788Sjfv /* This uses above function pointers */ 149173788Sjfv ret_val = e1000_get_phy_id_82571(hw); 150169240Sjfv 151173788Sjfv /* Verify PHY ID */ 152169240Sjfv if (phy->id != M88E1111_I_PHY_ID) { 153169240Sjfv ret_val = -E1000_ERR_PHY; 154173788Sjfv DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 155169240Sjfv goto out; 156169240Sjfv } 157169240Sjfv break; 158194865Sjfv case e1000_82583: 159178523Sjfv case e1000_82574: 160178523Sjfv phy->type = e1000_phy_bm; 161178523Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 162178523Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 163178523Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 164178523Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 165178523Sjfv phy->ops.get_cable_length = e1000_get_cable_length_m88; 166178523Sjfv phy->ops.read_reg = e1000_read_phy_reg_bm2; 167178523Sjfv phy->ops.write_reg = e1000_write_phy_reg_bm2; 168178523Sjfv 169178523Sjfv /* This uses above function pointers */ 170178523Sjfv ret_val = e1000_get_phy_id_82571(hw); 171178523Sjfv /* Verify PHY ID */ 172185353Sjfv if (phy->id != BME1000_E_PHY_ID_R2) { 173178523Sjfv ret_val = -E1000_ERR_PHY; 174178523Sjfv DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 175178523Sjfv goto out; 176178523Sjfv } 177178523Sjfv break; 178169240Sjfv default: 179169240Sjfv ret_val = -E1000_ERR_PHY; 180169240Sjfv goto out; 181169240Sjfv break; 182169240Sjfv } 183169240Sjfv 184169240Sjfvout: 185169240Sjfv return ret_val; 186169240Sjfv} 187169240Sjfv 188169240Sjfv/** 189169240Sjfv * e1000_init_nvm_params_82571 - Init NVM func ptrs. 190169589Sjfv * @hw: pointer to the HW structure 191169240Sjfv **/ 192177867Sjfvstatic s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) 193169240Sjfv{ 194169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 195169240Sjfv u32 eecd = E1000_READ_REG(hw, E1000_EECD); 196169240Sjfv u16 size; 197169240Sjfv 198169240Sjfv DEBUGFUNC("e1000_init_nvm_params_82571"); 199169240Sjfv 200185353Sjfv nvm->opcode_bits = 8; 201185353Sjfv nvm->delay_usec = 1; 202169240Sjfv switch (nvm->override) { 203169240Sjfv case e1000_nvm_override_spi_large: 204185353Sjfv nvm->page_size = 32; 205169240Sjfv nvm->address_bits = 16; 206169240Sjfv break; 207169240Sjfv case e1000_nvm_override_spi_small: 208185353Sjfv nvm->page_size = 8; 209169240Sjfv nvm->address_bits = 8; 210169240Sjfv break; 211169240Sjfv default: 212185353Sjfv nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 213169240Sjfv nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 214169240Sjfv break; 215169240Sjfv } 216169240Sjfv 217169240Sjfv switch (hw->mac.type) { 218169240Sjfv case e1000_82573: 219178523Sjfv case e1000_82574: 220194865Sjfv case e1000_82583: 221169240Sjfv if (((eecd >> 15) & 0x3) == 0x3) { 222169240Sjfv nvm->type = e1000_nvm_flash_hw; 223169240Sjfv nvm->word_size = 2048; 224173788Sjfv /* 225173788Sjfv * Autonomous Flash update bit must be cleared due 226169240Sjfv * to Flash update issue. 227169240Sjfv */ 228169240Sjfv eecd &= ~E1000_EECD_AUPDEN; 229169240Sjfv E1000_WRITE_REG(hw, E1000_EECD, eecd); 230169240Sjfv break; 231169240Sjfv } 232169240Sjfv /* Fall Through */ 233169240Sjfv default: 234185353Sjfv nvm->type = e1000_nvm_eeprom_spi; 235169240Sjfv size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 236169240Sjfv E1000_EECD_SIZE_EX_SHIFT); 237173788Sjfv /* 238173788Sjfv * Added to a constant, "size" becomes the left-shift value 239169240Sjfv * for setting word_size. 240169240Sjfv */ 241169240Sjfv size += NVM_WORD_SIZE_BASE_SHIFT; 242173788Sjfv 243173788Sjfv /* EEPROM access above 16k is unsupported */ 244173788Sjfv if (size > 14) 245173788Sjfv size = 14; 246169240Sjfv nvm->word_size = 1 << size; 247169240Sjfv break; 248169240Sjfv } 249169240Sjfv 250169240Sjfv /* Function Pointers */ 251177867Sjfv nvm->ops.acquire = e1000_acquire_nvm_82571; 252177867Sjfv nvm->ops.read = e1000_read_nvm_eerd; 253177867Sjfv nvm->ops.release = e1000_release_nvm_82571; 254177867Sjfv nvm->ops.update = e1000_update_nvm_checksum_82571; 255177867Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_82571; 256177867Sjfv nvm->ops.valid_led_default = e1000_valid_led_default_82571; 257177867Sjfv nvm->ops.write = e1000_write_nvm_82571; 258169240Sjfv 259169240Sjfv return E1000_SUCCESS; 260169240Sjfv} 261169240Sjfv 262169240Sjfv/** 263169240Sjfv * e1000_init_mac_params_82571 - Init MAC func ptrs. 264169589Sjfv * @hw: pointer to the HW structure 265169240Sjfv **/ 266177867Sjfvstatic s32 e1000_init_mac_params_82571(struct e1000_hw *hw) 267169240Sjfv{ 268169240Sjfv struct e1000_mac_info *mac = &hw->mac; 269169240Sjfv s32 ret_val = E1000_SUCCESS; 270194865Sjfv u32 swsm = 0; 271194865Sjfv u32 swsm2 = 0; 272194865Sjfv bool force_clear_smbi = FALSE; 273169240Sjfv 274169240Sjfv DEBUGFUNC("e1000_init_mac_params_82571"); 275169240Sjfv 276169240Sjfv /* Set media type */ 277169240Sjfv switch (hw->device_id) { 278169240Sjfv case E1000_DEV_ID_82571EB_FIBER: 279169240Sjfv case E1000_DEV_ID_82572EI_FIBER: 280169240Sjfv case E1000_DEV_ID_82571EB_QUAD_FIBER: 281173788Sjfv hw->phy.media_type = e1000_media_type_fiber; 282169240Sjfv break; 283169240Sjfv case E1000_DEV_ID_82571EB_SERDES: 284169589Sjfv case E1000_DEV_ID_82571EB_SERDES_DUAL: 285169589Sjfv case E1000_DEV_ID_82571EB_SERDES_QUAD: 286169240Sjfv case E1000_DEV_ID_82572EI_SERDES: 287173788Sjfv hw->phy.media_type = e1000_media_type_internal_serdes; 288169240Sjfv break; 289169240Sjfv default: 290173788Sjfv hw->phy.media_type = e1000_media_type_copper; 291169240Sjfv break; 292169240Sjfv } 293169240Sjfv 294169240Sjfv /* Set mta register count */ 295169240Sjfv mac->mta_reg_count = 128; 296169240Sjfv /* Set rar entry count */ 297169240Sjfv mac->rar_entry_count = E1000_RAR_ENTRIES; 298169240Sjfv /* Set if part includes ASF firmware */ 299169240Sjfv mac->asf_firmware_present = TRUE; 300169240Sjfv /* Set if manageability features are enabled. */ 301169240Sjfv mac->arc_subsystem_valid = 302169240Sjfv (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 303169240Sjfv ? TRUE : FALSE; 304169240Sjfv 305169240Sjfv /* Function pointers */ 306169240Sjfv 307169240Sjfv /* bus type/speed/width */ 308177867Sjfv mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 309185353Sjfv /* function id */ 310185353Sjfv switch (hw->mac.type) { 311185353Sjfv case e1000_82573: 312185353Sjfv case e1000_82574: 313194865Sjfv case e1000_82583: 314185353Sjfv mac->ops.set_lan_id = e1000_set_lan_id_single_port; 315185353Sjfv break; 316185353Sjfv default: 317185353Sjfv break; 318185353Sjfv } 319169240Sjfv /* reset */ 320177867Sjfv mac->ops.reset_hw = e1000_reset_hw_82571; 321169240Sjfv /* hw initialization */ 322177867Sjfv mac->ops.init_hw = e1000_init_hw_82571; 323169240Sjfv /* link setup */ 324177867Sjfv mac->ops.setup_link = e1000_setup_link_82571; 325169240Sjfv /* physical interface link setup */ 326177867Sjfv mac->ops.setup_physical_interface = 327173788Sjfv (hw->phy.media_type == e1000_media_type_copper) 328169240Sjfv ? e1000_setup_copper_link_82571 329169240Sjfv : e1000_setup_fiber_serdes_link_82571; 330169240Sjfv /* check for link */ 331173788Sjfv switch (hw->phy.media_type) { 332169240Sjfv case e1000_media_type_copper: 333177867Sjfv mac->ops.check_for_link = e1000_check_for_copper_link_generic; 334169240Sjfv break; 335169240Sjfv case e1000_media_type_fiber: 336177867Sjfv mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 337169240Sjfv break; 338169240Sjfv case e1000_media_type_internal_serdes: 339190872Sjfv mac->ops.check_for_link = e1000_check_for_serdes_link_82571; 340169240Sjfv break; 341169240Sjfv default: 342169240Sjfv ret_val = -E1000_ERR_CONFIG; 343169240Sjfv goto out; 344169240Sjfv break; 345169240Sjfv } 346169240Sjfv /* check management mode */ 347181027Sjfv switch (hw->mac.type) { 348181027Sjfv case e1000_82574: 349194865Sjfv case e1000_82583: 350181027Sjfv mac->ops.check_mng_mode = e1000_check_mng_mode_82574; 351181027Sjfv break; 352181027Sjfv default: 353181027Sjfv mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 354181027Sjfv break; 355181027Sjfv } 356169240Sjfv /* multicast address update */ 357190872Sjfv mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 358169240Sjfv /* writing VFTA */ 359177867Sjfv mac->ops.write_vfta = e1000_write_vfta_generic; 360169240Sjfv /* clearing VFTA */ 361177867Sjfv mac->ops.clear_vfta = e1000_clear_vfta_82571; 362169240Sjfv /* setting MTA */ 363177867Sjfv mac->ops.mta_set = e1000_mta_set_generic; 364173788Sjfv /* read mac address */ 365177867Sjfv mac->ops.read_mac_addr = e1000_read_mac_addr_82571; 366190872Sjfv /* ID LED init */ 367190872Sjfv mac->ops.id_led_init = e1000_id_led_init_generic; 368169240Sjfv /* blink LED */ 369177867Sjfv mac->ops.blink_led = e1000_blink_led_generic; 370169240Sjfv /* setup LED */ 371177867Sjfv mac->ops.setup_led = e1000_setup_led_generic; 372169240Sjfv /* cleanup LED */ 373177867Sjfv mac->ops.cleanup_led = e1000_cleanup_led_generic; 374169240Sjfv /* turn on/off LED */ 375181027Sjfv switch (hw->mac.type) { 376181027Sjfv case e1000_82574: 377194865Sjfv case e1000_82583: 378181027Sjfv mac->ops.led_on = e1000_led_on_82574; 379181027Sjfv break; 380181027Sjfv default: 381181027Sjfv mac->ops.led_on = e1000_led_on_generic; 382181027Sjfv break; 383181027Sjfv } 384177867Sjfv mac->ops.led_off = e1000_led_off_generic; 385169240Sjfv /* clear hardware counters */ 386177867Sjfv mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571; 387169240Sjfv /* link info */ 388177867Sjfv mac->ops.get_link_up_info = 389173788Sjfv (hw->phy.media_type == e1000_media_type_copper) 390169240Sjfv ? e1000_get_speed_and_duplex_copper_generic 391169240Sjfv : e1000_get_speed_and_duplex_fiber_serdes_generic; 392169240Sjfv 393194865Sjfv /* 394194865Sjfv * Ensure that the inter-port SWSM.SMBI lock bit is clear before 395194865Sjfv * first NVM or PHY acess. This should be done for single-port 396194865Sjfv * devices, and for one port only on dual-port devices so that 397194865Sjfv * for those devices we can still use the SMBI lock to synchronize 398194865Sjfv * inter-port accesses to the PHY & NVM. 399194865Sjfv */ 400194865Sjfv switch (hw->mac.type) { 401194865Sjfv case e1000_82571: 402194865Sjfv case e1000_82572: 403194865Sjfv swsm2 = E1000_READ_REG(hw, E1000_SWSM2); 404194865Sjfv 405194865Sjfv if (!(swsm2 & E1000_SWSM2_LOCK)) { 406194865Sjfv /* Only do this for the first interface on this card */ 407194865Sjfv E1000_WRITE_REG(hw, E1000_SWSM2, 408194865Sjfv swsm2 | E1000_SWSM2_LOCK); 409194865Sjfv force_clear_smbi = TRUE; 410194865Sjfv } else 411194865Sjfv force_clear_smbi = FALSE; 412194865Sjfv break; 413194865Sjfv default: 414194865Sjfv force_clear_smbi = TRUE; 415194865Sjfv break; 416194865Sjfv } 417194865Sjfv 418194865Sjfv if (force_clear_smbi) { 419194865Sjfv /* Make sure SWSM.SMBI is clear */ 420194865Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 421194865Sjfv if (swsm & E1000_SWSM_SMBI) { 422194865Sjfv /* This bit should not be set on a first interface, and 423194865Sjfv * indicates that the bootagent or EFI code has 424194865Sjfv * improperly left this bit enabled 425194865Sjfv */ 426194865Sjfv DEBUGOUT("Please update your 82571 Bootagent\n"); 427194865Sjfv } 428194865Sjfv E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI); 429194865Sjfv } 430194865Sjfv 431194865Sjfv /* 432194865Sjfv * Initialze device specific counter of SMBI acquisition 433194865Sjfv * timeouts. 434194865Sjfv */ 435194865Sjfv hw->dev_spec._82571.smb_counter = 0; 436194865Sjfv 437169240Sjfvout: 438169240Sjfv return ret_val; 439169240Sjfv} 440169240Sjfv 441169240Sjfv/** 442169240Sjfv * e1000_init_function_pointers_82571 - Init func ptrs. 443169589Sjfv * @hw: pointer to the HW structure 444169240Sjfv * 445185353Sjfv * Called to initialize all function pointers and parameters. 446169240Sjfv **/ 447173788Sjfvvoid e1000_init_function_pointers_82571(struct e1000_hw *hw) 448169240Sjfv{ 449169240Sjfv DEBUGFUNC("e1000_init_function_pointers_82571"); 450169240Sjfv 451177867Sjfv hw->mac.ops.init_params = e1000_init_mac_params_82571; 452177867Sjfv hw->nvm.ops.init_params = e1000_init_nvm_params_82571; 453177867Sjfv hw->phy.ops.init_params = e1000_init_phy_params_82571; 454169240Sjfv} 455169240Sjfv 456169240Sjfv/** 457169240Sjfv * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision 458169589Sjfv * @hw: pointer to the HW structure 459169240Sjfv * 460169240Sjfv * Reads the PHY registers and stores the PHY ID and possibly the PHY 461169240Sjfv * revision in the hardware structure. 462169240Sjfv **/ 463173788Sjfvstatic s32 e1000_get_phy_id_82571(struct e1000_hw *hw) 464169240Sjfv{ 465169240Sjfv struct e1000_phy_info *phy = &hw->phy; 466169240Sjfv s32 ret_val = E1000_SUCCESS; 467178523Sjfv u16 phy_id = 0; 468169240Sjfv 469169240Sjfv DEBUGFUNC("e1000_get_phy_id_82571"); 470169240Sjfv 471169240Sjfv switch (hw->mac.type) { 472169240Sjfv case e1000_82571: 473169240Sjfv case e1000_82572: 474173788Sjfv /* 475173788Sjfv * The 82571 firmware may still be configuring the PHY. 476169240Sjfv * In this case, we cannot access the PHY until the 477169240Sjfv * configuration is done. So we explicitly set the 478173788Sjfv * PHY ID. 479173788Sjfv */ 480169240Sjfv phy->id = IGP01E1000_I_PHY_ID; 481169240Sjfv break; 482169240Sjfv case e1000_82573: 483169240Sjfv ret_val = e1000_get_phy_id(hw); 484169240Sjfv break; 485178523Sjfv case e1000_82574: 486194865Sjfv case e1000_82583: 487178523Sjfv ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 488178523Sjfv if (ret_val) 489178523Sjfv goto out; 490178523Sjfv 491178523Sjfv phy->id = (u32)(phy_id << 16); 492178523Sjfv usec_delay(20); 493178523Sjfv ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 494178523Sjfv if (ret_val) 495178523Sjfv goto out; 496178523Sjfv 497178523Sjfv phy->id |= (u32)(phy_id); 498178523Sjfv phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 499178523Sjfv break; 500169240Sjfv default: 501169240Sjfv ret_val = -E1000_ERR_PHY; 502169240Sjfv break; 503169240Sjfv } 504169240Sjfv 505178523Sjfvout: 506169240Sjfv return ret_val; 507169240Sjfv} 508169240Sjfv 509169240Sjfv/** 510169589Sjfv * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore 511169589Sjfv * @hw: pointer to the HW structure 512169589Sjfv * 513169589Sjfv * Acquire the HW semaphore to access the PHY or NVM 514169589Sjfv **/ 515194865Sjfvs32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 516169589Sjfv{ 517169589Sjfv u32 swsm; 518169589Sjfv s32 ret_val = E1000_SUCCESS; 519194865Sjfv s32 sw_timeout = hw->nvm.word_size + 1; 520194865Sjfv s32 fw_timeout = hw->nvm.word_size + 1; 521169589Sjfv s32 i = 0; 522169589Sjfv 523169589Sjfv DEBUGFUNC("e1000_get_hw_semaphore_82571"); 524169589Sjfv 525194865Sjfv /* 526194865Sjfv * If we have timedout 3 times on trying to acquire 527194865Sjfv * the inter-port SMBI semaphore, there is old code 528194865Sjfv * operating on the other port, and it is not 529194865Sjfv * releasing SMBI. Modify the number of times that 530194865Sjfv * we try for the semaphore to interwork with this 531194865Sjfv * older code. 532194865Sjfv */ 533194865Sjfv if (hw->dev_spec._82571.smb_counter > 2) 534194865Sjfv sw_timeout = 1; 535194865Sjfv 536194865Sjfv /* Get the SW semaphore */ 537194865Sjfv while (i < sw_timeout) { 538194865Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 539194865Sjfv if (!(swsm & E1000_SWSM_SMBI)) 540194865Sjfv break; 541194865Sjfv 542194865Sjfv usec_delay(50); 543194865Sjfv i++; 544194865Sjfv } 545194865Sjfv 546194865Sjfv if (i == sw_timeout) { 547194865Sjfv DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 548194865Sjfv hw->dev_spec._82571.smb_counter++; 549194865Sjfv } 550169589Sjfv /* Get the FW semaphore. */ 551194865Sjfv for (i = 0; i < fw_timeout; i++) { 552169589Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 553169589Sjfv E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 554169589Sjfv 555169589Sjfv /* Semaphore acquired if bit latched */ 556169589Sjfv if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 557169589Sjfv break; 558169589Sjfv 559169589Sjfv usec_delay(50); 560169589Sjfv } 561169589Sjfv 562194865Sjfv if (i == fw_timeout) { 563169589Sjfv /* Release semaphores */ 564194865Sjfv e1000_put_hw_semaphore_82571(hw); 565169589Sjfv DEBUGOUT("Driver can't access the NVM\n"); 566169589Sjfv ret_val = -E1000_ERR_NVM; 567169589Sjfv goto out; 568169589Sjfv } 569169589Sjfv 570169589Sjfvout: 571169589Sjfv return ret_val; 572169589Sjfv} 573169589Sjfv 574169589Sjfv/** 575169589Sjfv * e1000_put_hw_semaphore_82571 - Release hardware semaphore 576169589Sjfv * @hw: pointer to the HW structure 577169589Sjfv * 578169589Sjfv * Release hardware semaphore used to access the PHY or NVM 579169589Sjfv **/ 580194865Sjfvvoid e1000_put_hw_semaphore_82571(struct e1000_hw *hw) 581169589Sjfv{ 582169589Sjfv u32 swsm; 583169589Sjfv 584194865Sjfv DEBUGFUNC("e1000_put_hw_semaphore_generic"); 585169589Sjfv 586169589Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 587169589Sjfv 588194865Sjfv swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 589169589Sjfv 590169589Sjfv E1000_WRITE_REG(hw, E1000_SWSM, swsm); 591169589Sjfv} 592169589Sjfv 593169589Sjfv/** 594169240Sjfv * e1000_acquire_nvm_82571 - Request for access to the EEPROM 595169589Sjfv * @hw: pointer to the HW structure 596169240Sjfv * 597169240Sjfv * To gain access to the EEPROM, first we must obtain a hardware semaphore. 598169240Sjfv * Then for non-82573 hardware, set the EEPROM access request bit and wait 599169240Sjfv * for EEPROM access grant bit. If the access grant bit is not set, release 600169240Sjfv * hardware semaphore. 601169240Sjfv **/ 602177867Sjfvstatic s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) 603169240Sjfv{ 604169240Sjfv s32 ret_val; 605169240Sjfv 606169240Sjfv DEBUGFUNC("e1000_acquire_nvm_82571"); 607169240Sjfv 608169589Sjfv ret_val = e1000_get_hw_semaphore_82571(hw); 609169240Sjfv if (ret_val) 610169240Sjfv goto out; 611169240Sjfv 612190872Sjfv switch (hw->mac.type) { 613190872Sjfv case e1000_82574: 614194865Sjfv case e1000_82583: 615190872Sjfv case e1000_82573: 616190872Sjfv break; 617190872Sjfv default: 618169240Sjfv ret_val = e1000_acquire_nvm_generic(hw); 619190872Sjfv break; 620190872Sjfv } 621169240Sjfv 622169240Sjfv if (ret_val) 623169589Sjfv e1000_put_hw_semaphore_82571(hw); 624169240Sjfv 625169240Sjfvout: 626169240Sjfv return ret_val; 627169240Sjfv} 628169240Sjfv 629169240Sjfv/** 630169240Sjfv * e1000_release_nvm_82571 - Release exclusive access to EEPROM 631169589Sjfv * @hw: pointer to the HW structure 632169240Sjfv * 633169240Sjfv * Stop any current commands to the EEPROM and clear the EEPROM request bit. 634169240Sjfv **/ 635177867Sjfvstatic void e1000_release_nvm_82571(struct e1000_hw *hw) 636169240Sjfv{ 637169240Sjfv DEBUGFUNC("e1000_release_nvm_82571"); 638169240Sjfv 639169240Sjfv e1000_release_nvm_generic(hw); 640169589Sjfv e1000_put_hw_semaphore_82571(hw); 641169240Sjfv} 642169240Sjfv 643169240Sjfv/** 644169240Sjfv * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface 645169589Sjfv * @hw: pointer to the HW structure 646169589Sjfv * @offset: offset within the EEPROM to be written to 647169589Sjfv * @words: number of words to write 648169589Sjfv * @data: 16 bit word(s) to be written to the EEPROM 649169240Sjfv * 650169240Sjfv * For non-82573 silicon, write data to EEPROM at offset using SPI interface. 651169240Sjfv * 652169240Sjfv * If e1000_update_nvm_checksum is not called after this function, the 653176667Sjfv * EEPROM will most likely contain an invalid checksum. 654169240Sjfv **/ 655177867Sjfvstatic s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, 656173788Sjfv u16 *data) 657169240Sjfv{ 658169240Sjfv s32 ret_val = E1000_SUCCESS; 659169240Sjfv 660169240Sjfv DEBUGFUNC("e1000_write_nvm_82571"); 661169240Sjfv 662169240Sjfv switch (hw->mac.type) { 663169240Sjfv case e1000_82573: 664178523Sjfv case e1000_82574: 665194865Sjfv case e1000_82583: 666169240Sjfv ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); 667169240Sjfv break; 668169240Sjfv case e1000_82571: 669169240Sjfv case e1000_82572: 670169240Sjfv ret_val = e1000_write_nvm_spi(hw, offset, words, data); 671169240Sjfv break; 672169240Sjfv default: 673169240Sjfv ret_val = -E1000_ERR_NVM; 674169240Sjfv break; 675169240Sjfv } 676169240Sjfv 677169240Sjfv return ret_val; 678169240Sjfv} 679169240Sjfv 680169240Sjfv/** 681169240Sjfv * e1000_update_nvm_checksum_82571 - Update EEPROM checksum 682169589Sjfv * @hw: pointer to the HW structure 683169240Sjfv * 684169240Sjfv * Updates the EEPROM checksum by reading/adding each word of the EEPROM 685169240Sjfv * up to the checksum. Then calculates the EEPROM checksum and writes the 686169240Sjfv * value to the EEPROM. 687169240Sjfv **/ 688177867Sjfvstatic s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 689169240Sjfv{ 690169240Sjfv u32 eecd; 691169240Sjfv s32 ret_val; 692169240Sjfv u16 i; 693169240Sjfv 694169240Sjfv DEBUGFUNC("e1000_update_nvm_checksum_82571"); 695169240Sjfv 696169240Sjfv ret_val = e1000_update_nvm_checksum_generic(hw); 697169240Sjfv if (ret_val) 698169240Sjfv goto out; 699169240Sjfv 700173788Sjfv /* 701173788Sjfv * If our nvm is an EEPROM, then we're done 702173788Sjfv * otherwise, commit the checksum to the flash NVM. 703173788Sjfv */ 704169240Sjfv if (hw->nvm.type != e1000_nvm_flash_hw) 705169240Sjfv goto out; 706169240Sjfv 707169240Sjfv /* Check for pending operations. */ 708169240Sjfv for (i = 0; i < E1000_FLASH_UPDATES; i++) { 709169240Sjfv msec_delay(1); 710169240Sjfv if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 711169240Sjfv break; 712169240Sjfv } 713169240Sjfv 714169240Sjfv if (i == E1000_FLASH_UPDATES) { 715169240Sjfv ret_val = -E1000_ERR_NVM; 716169240Sjfv goto out; 717169240Sjfv } 718169240Sjfv 719169240Sjfv /* Reset the firmware if using STM opcode. */ 720169240Sjfv if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) { 721173788Sjfv /* 722173788Sjfv * The enabling of and the actual reset must be done 723169240Sjfv * in two write cycles. 724169240Sjfv */ 725169240Sjfv E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE); 726169240Sjfv E1000_WRITE_FLUSH(hw); 727169240Sjfv E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET); 728169240Sjfv } 729169240Sjfv 730169240Sjfv /* Commit the write to flash */ 731169240Sjfv eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD; 732169240Sjfv E1000_WRITE_REG(hw, E1000_EECD, eecd); 733169240Sjfv 734169240Sjfv for (i = 0; i < E1000_FLASH_UPDATES; i++) { 735169240Sjfv msec_delay(1); 736169240Sjfv if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 737169240Sjfv break; 738169240Sjfv } 739169240Sjfv 740169240Sjfv if (i == E1000_FLASH_UPDATES) { 741169240Sjfv ret_val = -E1000_ERR_NVM; 742169240Sjfv goto out; 743169240Sjfv } 744169240Sjfv 745169240Sjfvout: 746169240Sjfv return ret_val; 747169240Sjfv} 748169240Sjfv 749169240Sjfv/** 750169240Sjfv * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum 751169589Sjfv * @hw: pointer to the HW structure 752169240Sjfv * 753169240Sjfv * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 754169240Sjfv * and then verifies that the sum of the EEPROM is equal to 0xBABA. 755169240Sjfv **/ 756177867Sjfvstatic s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) 757169240Sjfv{ 758169240Sjfv DEBUGFUNC("e1000_validate_nvm_checksum_82571"); 759169240Sjfv 760169240Sjfv if (hw->nvm.type == e1000_nvm_flash_hw) 761169240Sjfv e1000_fix_nvm_checksum_82571(hw); 762169240Sjfv 763169240Sjfv return e1000_validate_nvm_checksum_generic(hw); 764169240Sjfv} 765169240Sjfv 766169240Sjfv/** 767169240Sjfv * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon 768169589Sjfv * @hw: pointer to the HW structure 769169589Sjfv * @offset: offset within the EEPROM to be written to 770169589Sjfv * @words: number of words to write 771169589Sjfv * @data: 16 bit word(s) to be written to the EEPROM 772169240Sjfv * 773169240Sjfv * After checking for invalid values, poll the EEPROM to ensure the previous 774169240Sjfv * command has completed before trying to write the next word. After write 775169240Sjfv * poll for completion. 776169240Sjfv * 777169240Sjfv * If e1000_update_nvm_checksum is not called after this function, the 778176667Sjfv * EEPROM will most likely contain an invalid checksum. 779169240Sjfv **/ 780173788Sjfvstatic s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 781173788Sjfv u16 words, u16 *data) 782169240Sjfv{ 783169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 784169240Sjfv u32 i, eewr = 0; 785169240Sjfv s32 ret_val = 0; 786169240Sjfv 787169240Sjfv DEBUGFUNC("e1000_write_nvm_eewr_82571"); 788169240Sjfv 789173788Sjfv /* 790173788Sjfv * A check for invalid values: offset too large, too many words, 791173788Sjfv * and not enough words. 792173788Sjfv */ 793169240Sjfv if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 794169240Sjfv (words == 0)) { 795169240Sjfv DEBUGOUT("nvm parameter(s) out of bounds\n"); 796169240Sjfv ret_val = -E1000_ERR_NVM; 797169240Sjfv goto out; 798169240Sjfv } 799169240Sjfv 800169240Sjfv for (i = 0; i < words; i++) { 801169240Sjfv eewr = (data[i] << E1000_NVM_RW_REG_DATA) | 802169240Sjfv ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | 803169240Sjfv E1000_NVM_RW_REG_START; 804169240Sjfv 805169240Sjfv ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 806169240Sjfv if (ret_val) 807169240Sjfv break; 808169240Sjfv 809169240Sjfv E1000_WRITE_REG(hw, E1000_EEWR, eewr); 810169240Sjfv 811169240Sjfv ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 812169240Sjfv if (ret_val) 813169240Sjfv break; 814169240Sjfv } 815169240Sjfv 816169240Sjfvout: 817169240Sjfv return ret_val; 818169240Sjfv} 819169240Sjfv 820169240Sjfv/** 821169240Sjfv * e1000_get_cfg_done_82571 - Poll for configuration done 822169589Sjfv * @hw: pointer to the HW structure 823169240Sjfv * 824169240Sjfv * Reads the management control register for the config done bit to be set. 825169240Sjfv **/ 826177867Sjfvstatic s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) 827169240Sjfv{ 828169240Sjfv s32 timeout = PHY_CFG_TIMEOUT; 829169240Sjfv s32 ret_val = E1000_SUCCESS; 830169240Sjfv 831169240Sjfv DEBUGFUNC("e1000_get_cfg_done_82571"); 832169240Sjfv 833169240Sjfv while (timeout) { 834169240Sjfv if (E1000_READ_REG(hw, E1000_EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0) 835169240Sjfv break; 836169240Sjfv msec_delay(1); 837169240Sjfv timeout--; 838169240Sjfv } 839169240Sjfv if (!timeout) { 840169240Sjfv DEBUGOUT("MNG configuration cycle has not completed.\n"); 841169240Sjfv ret_val = -E1000_ERR_RESET; 842169240Sjfv goto out; 843169240Sjfv } 844169240Sjfv 845169240Sjfvout: 846169240Sjfv return ret_val; 847169240Sjfv} 848169240Sjfv 849169240Sjfv/** 850169240Sjfv * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state 851169589Sjfv * @hw: pointer to the HW structure 852169589Sjfv * @active: TRUE to enable LPLU, FALSE to disable 853169240Sjfv * 854169240Sjfv * Sets the LPLU D0 state according to the active flag. When activating LPLU 855169240Sjfv * this function also disables smart speed and vice versa. LPLU will not be 856169240Sjfv * activated unless the device autonegotiation advertisement meets standards 857169240Sjfv * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function 858169240Sjfv * pointer entry point only called by PHY setup routines. 859169240Sjfv **/ 860177867Sjfvstatic s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) 861169240Sjfv{ 862169240Sjfv struct e1000_phy_info *phy = &hw->phy; 863177867Sjfv s32 ret_val = E1000_SUCCESS; 864169240Sjfv u16 data; 865169240Sjfv 866169240Sjfv DEBUGFUNC("e1000_set_d0_lplu_state_82571"); 867169240Sjfv 868177867Sjfv if (!(phy->ops.read_reg)) 869177867Sjfv goto out; 870177867Sjfv 871177867Sjfv ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 872169240Sjfv if (ret_val) 873169240Sjfv goto out; 874169240Sjfv 875169240Sjfv if (active) { 876169240Sjfv data |= IGP02E1000_PM_D0_LPLU; 877177867Sjfv ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 878177867Sjfv data); 879169240Sjfv if (ret_val) 880169240Sjfv goto out; 881169240Sjfv 882169240Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 883177867Sjfv ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 884177867Sjfv &data); 885169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 886177867Sjfv ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 887177867Sjfv data); 888169240Sjfv if (ret_val) 889169240Sjfv goto out; 890169240Sjfv } else { 891169240Sjfv data &= ~IGP02E1000_PM_D0_LPLU; 892177867Sjfv ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 893177867Sjfv data); 894173788Sjfv /* 895173788Sjfv * LPLU and SmartSpeed are mutually exclusive. LPLU is used 896169240Sjfv * during Dx states where the power conservation is most 897169240Sjfv * important. During driver activity we should enable 898173788Sjfv * SmartSpeed, so performance is maintained. 899173788Sjfv */ 900169240Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 901177867Sjfv ret_val = phy->ops.read_reg(hw, 902177867Sjfv IGP01E1000_PHY_PORT_CONFIG, 903177867Sjfv &data); 904169240Sjfv if (ret_val) 905169240Sjfv goto out; 906169240Sjfv 907169240Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 908177867Sjfv ret_val = phy->ops.write_reg(hw, 909169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 910169240Sjfv data); 911169240Sjfv if (ret_val) 912169240Sjfv goto out; 913169240Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 914177867Sjfv ret_val = phy->ops.read_reg(hw, 915177867Sjfv IGP01E1000_PHY_PORT_CONFIG, 916177867Sjfv &data); 917169240Sjfv if (ret_val) 918169240Sjfv goto out; 919169240Sjfv 920169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 921177867Sjfv ret_val = phy->ops.write_reg(hw, 922169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 923169240Sjfv data); 924169240Sjfv if (ret_val) 925169240Sjfv goto out; 926169240Sjfv } 927169240Sjfv } 928169240Sjfv 929169240Sjfvout: 930169240Sjfv return ret_val; 931169240Sjfv} 932169240Sjfv 933169240Sjfv/** 934169240Sjfv * e1000_reset_hw_82571 - Reset hardware 935169589Sjfv * @hw: pointer to the HW structure 936169240Sjfv * 937185353Sjfv * This resets the hardware into a known state. 938169240Sjfv **/ 939177867Sjfvstatic s32 e1000_reset_hw_82571(struct e1000_hw *hw) 940169240Sjfv{ 941169240Sjfv u32 ctrl, extcnf_ctrl, ctrl_ext, icr; 942169240Sjfv s32 ret_val; 943169240Sjfv u16 i = 0; 944169240Sjfv 945169240Sjfv DEBUGFUNC("e1000_reset_hw_82571"); 946169240Sjfv 947173788Sjfv /* 948173788Sjfv * Prevent the PCI-E bus from sticking if there is no TLP connection 949169240Sjfv * on the last TLP read/write transaction when MAC is reset. 950169240Sjfv */ 951169240Sjfv ret_val = e1000_disable_pcie_master_generic(hw); 952185353Sjfv if (ret_val) 953169240Sjfv DEBUGOUT("PCI-E Master disable polling has failed.\n"); 954169240Sjfv 955169240Sjfv DEBUGOUT("Masking off all interrupts\n"); 956169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 957169240Sjfv 958169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 959169240Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 960169240Sjfv E1000_WRITE_FLUSH(hw); 961169240Sjfv 962169240Sjfv msec_delay(10); 963169240Sjfv 964173788Sjfv /* 965173788Sjfv * Must acquire the MDIO ownership before MAC reset. 966173788Sjfv * Ownership defaults to firmware after a reset. 967173788Sjfv */ 968190872Sjfv switch (hw->mac.type) { 969190872Sjfv case e1000_82574: 970194865Sjfv case e1000_82583: 971190872Sjfv case e1000_82573: 972169240Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 973169240Sjfv extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 974169240Sjfv 975169240Sjfv do { 976169240Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 977169240Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 978169240Sjfv 979169240Sjfv if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 980169240Sjfv break; 981169240Sjfv 982169240Sjfv extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 983169240Sjfv 984169240Sjfv msec_delay(2); 985169240Sjfv i++; 986169240Sjfv } while (i < MDIO_OWNERSHIP_TIMEOUT); 987190872Sjfv break; 988190872Sjfv default: 989190872Sjfv break; 990169240Sjfv } 991169240Sjfv 992169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 993169240Sjfv 994169240Sjfv DEBUGOUT("Issuing a global reset to MAC\n"); 995169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 996169240Sjfv 997169240Sjfv if (hw->nvm.type == e1000_nvm_flash_hw) { 998169240Sjfv usec_delay(10); 999169240Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1000169240Sjfv ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1001169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1002169240Sjfv E1000_WRITE_FLUSH(hw); 1003169240Sjfv } 1004169240Sjfv 1005169240Sjfv ret_val = e1000_get_auto_rd_done_generic(hw); 1006169240Sjfv if (ret_val) 1007169240Sjfv /* We don't want to continue accessing MAC registers. */ 1008169240Sjfv goto out; 1009169240Sjfv 1010173788Sjfv /* 1011173788Sjfv * Phy configuration from NVM just starts after EECD_AUTO_RD is set. 1012169240Sjfv * Need to wait for Phy configuration completion before accessing 1013169240Sjfv * NVM and Phy. 1014169240Sjfv */ 1015190872Sjfv 1016190872Sjfv switch (hw->mac.type) { 1017190872Sjfv case e1000_82574: 1018194865Sjfv case e1000_82583: 1019190872Sjfv case e1000_82573: 1020169240Sjfv msec_delay(25); 1021190872Sjfv break; 1022190872Sjfv default: 1023190872Sjfv break; 1024190872Sjfv } 1025169240Sjfv 1026169240Sjfv /* Clear any pending interrupt events. */ 1027169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1028169240Sjfv icr = E1000_READ_REG(hw, E1000_ICR); 1029169240Sjfv 1030190872Sjfv /* Install any alternate MAC address into RAR0 */ 1031190872Sjfv ret_val = e1000_check_alt_mac_addr_generic(hw); 1032190872Sjfv if (ret_val) 1033190872Sjfv goto out; 1034173788Sjfv 1035190872Sjfv e1000_set_laa_state_82571(hw, TRUE); 1036190872Sjfv 1037190872Sjfv /* Reinitialize the 82571 serdes link state machine */ 1038190872Sjfv if (hw->phy.media_type == e1000_media_type_internal_serdes) 1039190872Sjfv hw->mac.serdes_link_state = e1000_serdes_link_down; 1040190872Sjfv 1041169240Sjfvout: 1042169240Sjfv return ret_val; 1043169240Sjfv} 1044169240Sjfv 1045169240Sjfv/** 1046169240Sjfv * e1000_init_hw_82571 - Initialize hardware 1047169589Sjfv * @hw: pointer to the HW structure 1048169240Sjfv * 1049169240Sjfv * This inits the hardware readying it for operation. 1050169240Sjfv **/ 1051177867Sjfvstatic s32 e1000_init_hw_82571(struct e1000_hw *hw) 1052169240Sjfv{ 1053169240Sjfv struct e1000_mac_info *mac = &hw->mac; 1054169240Sjfv u32 reg_data; 1055169240Sjfv s32 ret_val; 1056169240Sjfv u16 i, rar_count = mac->rar_entry_count; 1057169240Sjfv 1058169240Sjfv DEBUGFUNC("e1000_init_hw_82571"); 1059169240Sjfv 1060169240Sjfv e1000_initialize_hw_bits_82571(hw); 1061169240Sjfv 1062169240Sjfv /* Initialize identification LED */ 1063190872Sjfv ret_val = mac->ops.id_led_init(hw); 1064169240Sjfv if (ret_val) { 1065169240Sjfv DEBUGOUT("Error initializing identification LED\n"); 1066173788Sjfv /* This is not fatal and we should not stop init due to this */ 1067169240Sjfv } 1068169240Sjfv 1069169240Sjfv /* Disabling VLAN filtering */ 1070169240Sjfv DEBUGOUT("Initializing the IEEE VLAN\n"); 1071177867Sjfv mac->ops.clear_vfta(hw); 1072169240Sjfv 1073169240Sjfv /* Setup the receive address. */ 1074173788Sjfv /* 1075173788Sjfv * If, however, a locally administered address was assigned to the 1076169240Sjfv * 82571, we must reserve a RAR for it to work around an issue where 1077169240Sjfv * resetting one port will reload the MAC on the other port. 1078169240Sjfv */ 1079173788Sjfv if (e1000_get_laa_state_82571(hw)) 1080169240Sjfv rar_count--; 1081169240Sjfv e1000_init_rx_addrs_generic(hw, rar_count); 1082169240Sjfv 1083169240Sjfv /* Zero out the Multicast HASH table */ 1084169240Sjfv DEBUGOUT("Zeroing the MTA\n"); 1085169240Sjfv for (i = 0; i < mac->mta_reg_count; i++) 1086169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1087169240Sjfv 1088169240Sjfv /* Setup link and flow control */ 1089177867Sjfv ret_val = mac->ops.setup_link(hw); 1090169240Sjfv 1091169240Sjfv /* Set the transmit descriptor write-back policy */ 1092173788Sjfv reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1093169240Sjfv reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 1094169240Sjfv E1000_TXDCTL_FULL_TX_DESC_WB | 1095169240Sjfv E1000_TXDCTL_COUNT_DESC; 1096173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 1097169240Sjfv 1098169240Sjfv /* ...for both queues. */ 1099190872Sjfv switch (mac->type) { 1100190872Sjfv case e1000_82574: 1101194865Sjfv case e1000_82583: 1102190872Sjfv case e1000_82573: 1103181027Sjfv e1000_enable_tx_pkt_filtering_generic(hw); 1104169240Sjfv reg_data = E1000_READ_REG(hw, E1000_GCR); 1105169240Sjfv reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1106169240Sjfv E1000_WRITE_REG(hw, E1000_GCR, reg_data); 1107190872Sjfv break; 1108190872Sjfv default: 1109190872Sjfv reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1110190872Sjfv reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 1111190872Sjfv E1000_TXDCTL_FULL_TX_DESC_WB | 1112190872Sjfv E1000_TXDCTL_COUNT_DESC; 1113190872Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 1114190872Sjfv break; 1115169240Sjfv } 1116169240Sjfv 1117173788Sjfv /* 1118173788Sjfv * Clear all of the statistics registers (clear on read). It is 1119169240Sjfv * important that we do this after we have tried to establish link 1120169240Sjfv * because the symbol error count will increment wildly if there 1121169240Sjfv * is no link. 1122169240Sjfv */ 1123169240Sjfv e1000_clear_hw_cntrs_82571(hw); 1124169240Sjfv 1125169240Sjfv return ret_val; 1126169240Sjfv} 1127169240Sjfv 1128169240Sjfv/** 1129169240Sjfv * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits 1130169589Sjfv * @hw: pointer to the HW structure 1131169240Sjfv * 1132169240Sjfv * Initializes required hardware-dependent bits needed for normal operation. 1133169240Sjfv **/ 1134173788Sjfvstatic void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 1135169240Sjfv{ 1136169240Sjfv u32 reg; 1137169240Sjfv 1138169240Sjfv DEBUGFUNC("e1000_initialize_hw_bits_82571"); 1139169240Sjfv 1140169240Sjfv /* Transmit Descriptor Control 0 */ 1141173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1142169240Sjfv reg |= (1 << 22); 1143173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 1144169240Sjfv 1145169240Sjfv /* Transmit Descriptor Control 1 */ 1146173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1147169240Sjfv reg |= (1 << 22); 1148173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 1149169240Sjfv 1150169240Sjfv /* Transmit Arbitration Control 0 */ 1151173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(0)); 1152169240Sjfv reg &= ~(0xF << 27); /* 30:27 */ 1153169240Sjfv switch (hw->mac.type) { 1154169240Sjfv case e1000_82571: 1155169240Sjfv case e1000_82572: 1156169240Sjfv reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); 1157169240Sjfv break; 1158169240Sjfv default: 1159169240Sjfv break; 1160169240Sjfv } 1161173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(0), reg); 1162169240Sjfv 1163169240Sjfv /* Transmit Arbitration Control 1 */ 1164173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(1)); 1165169240Sjfv switch (hw->mac.type) { 1166169240Sjfv case e1000_82571: 1167169240Sjfv case e1000_82572: 1168169240Sjfv reg &= ~((1 << 29) | (1 << 30)); 1169169589Sjfv reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); 1170169240Sjfv if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1171169240Sjfv reg &= ~(1 << 28); 1172169240Sjfv else 1173169240Sjfv reg |= (1 << 28); 1174173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(1), reg); 1175169240Sjfv break; 1176169240Sjfv default: 1177169240Sjfv break; 1178169240Sjfv } 1179169240Sjfv 1180169240Sjfv /* Device Control */ 1181190872Sjfv 1182190872Sjfv switch (hw->mac.type) { 1183190872Sjfv case e1000_82574: 1184194865Sjfv case e1000_82583: 1185190872Sjfv case e1000_82573: 1186169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL); 1187169240Sjfv reg &= ~(1 << 29); 1188169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, reg); 1189190872Sjfv break; 1190190872Sjfv default: 1191190872Sjfv break; 1192169240Sjfv } 1193169240Sjfv 1194169240Sjfv /* Extended Device Control */ 1195190872Sjfv switch (hw->mac.type) { 1196190872Sjfv case e1000_82574: 1197194865Sjfv case e1000_82583: 1198190872Sjfv case e1000_82573: 1199169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1200169240Sjfv reg &= ~(1 << 23); 1201169240Sjfv reg |= (1 << 22); 1202169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1203190872Sjfv break; 1204190872Sjfv default: 1205190872Sjfv break; 1206169240Sjfv } 1207169240Sjfv 1208190872Sjfv 1209190872Sjfv if (hw->mac.type == e1000_82571) { 1210190872Sjfv reg = E1000_READ_REG(hw, E1000_PBA_ECC); 1211190872Sjfv reg |= E1000_PBA_ECC_CORR_EN; 1212190872Sjfv E1000_WRITE_REG(hw, E1000_PBA_ECC, reg); 1213190872Sjfv } 1214190872Sjfv 1215190872Sjfv /* 1216190872Sjfv * Workaround for hardware errata. 1217190872Sjfv * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 1218190872Sjfv */ 1219190872Sjfv 1220190872Sjfv if ((hw->mac.type == e1000_82571) || 1221190872Sjfv (hw->mac.type == e1000_82572)) { 1222190872Sjfv reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1223190872Sjfv reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; 1224190872Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1225190872Sjfv } 1226190872Sjfv 1227190872Sjfv /* PCI-Ex Control Registers */ 1228190872Sjfv 1229190872Sjfv switch (hw->mac.type) { 1230190872Sjfv case e1000_82574: 1231194865Sjfv case e1000_82583: 1232181027Sjfv reg = E1000_READ_REG(hw, E1000_GCR); 1233181027Sjfv reg |= (1 << 22); 1234185353Sjfv E1000_WRITE_REG(hw, E1000_GCR, reg); 1235190872Sjfv /* 1236190872Sjfv * Workaround for hardware errata. 1237190872Sjfv * apply workaround for hardware errata documented in errata 1238190872Sjfv * docs Fixes issue where some error prone or unreliable PCIe 1239190872Sjfv * completions are occurring, particularly with ASPM enabled. 1240190872Sjfv * Without fix, issue can cause tx timeouts. 1241190872Sjfv */ 1242190872Sjfv reg = E1000_READ_REG(hw, E1000_GCR2); 1243190872Sjfv reg |= 1; 1244190872Sjfv E1000_WRITE_REG(hw, E1000_GCR2, reg); 1245190872Sjfv break; 1246190872Sjfv default: 1247190872Sjfv break; 1248181027Sjfv } 1249181027Sjfv 1250169240Sjfv return; 1251169240Sjfv} 1252169240Sjfv 1253169240Sjfv/** 1254169240Sjfv * e1000_clear_vfta_82571 - Clear VLAN filter table 1255169589Sjfv * @hw: pointer to the HW structure 1256169240Sjfv * 1257169240Sjfv * Clears the register array which contains the VLAN filter table by 1258169240Sjfv * setting all the values to 0. 1259169240Sjfv **/ 1260177867Sjfvstatic void e1000_clear_vfta_82571(struct e1000_hw *hw) 1261169240Sjfv{ 1262169240Sjfv u32 offset; 1263169240Sjfv u32 vfta_value = 0; 1264169240Sjfv u32 vfta_offset = 0; 1265169240Sjfv u32 vfta_bit_in_reg = 0; 1266169240Sjfv 1267169240Sjfv DEBUGFUNC("e1000_clear_vfta_82571"); 1268169240Sjfv 1269190872Sjfv switch (hw->mac.type) { 1270190872Sjfv case e1000_82574: 1271194865Sjfv case e1000_82583: 1272190872Sjfv case e1000_82573: 1273169240Sjfv if (hw->mng_cookie.vlan_id != 0) { 1274173788Sjfv /* 1275190872Sjfv *The VFTA is a 4096b bit-field, each identifying 1276190872Sjfv *a single VLAN ID. The following operations 1277190872Sjfv *determine which 32b entry (i.e. offset) into the 1278190872Sjfv *array we want to set the VLAN ID (i.e. bit) of 1279190872Sjfv *the manageability unit. 1280190872Sjfv */ 1281169240Sjfv vfta_offset = (hw->mng_cookie.vlan_id >> 1282190872Sjfv E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; 1283169240Sjfv vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 1284190872Sjfv E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 1285169240Sjfv } 1286190872Sjfv 1287190872Sjfv for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 1288190872Sjfv /* 1289190872Sjfv *If the offset we want to clear is the same offset of 1290190872Sjfv *the manageability VLAN ID, then clear all bits except 1291190872Sjfv *that of the manageability unit 1292190872Sjfv */ 1293190872Sjfv vfta_value = (offset == vfta_offset) ? 1294190872Sjfv vfta_bit_in_reg : 0; 1295190872Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 1296190872Sjfv vfta_value); 1297190872Sjfv E1000_WRITE_FLUSH(hw); 1298190872Sjfv } 1299190872Sjfv break; 1300190872Sjfv default: 1301190872Sjfv break; 1302169240Sjfv } 1303169240Sjfv} 1304169240Sjfv 1305169240Sjfv/** 1306181027Sjfv * e1000_check_mng_mode_82574 - Check manageability is enabled 1307181027Sjfv * @hw: pointer to the HW structure 1308181027Sjfv * 1309181027Sjfv * Reads the NVM Initialization Control Word 2 and returns TRUE 1310181027Sjfv * (>0) if any manageability is enabled, else FALSE (0). 1311181027Sjfv **/ 1312181027Sjfvstatic bool e1000_check_mng_mode_82574(struct e1000_hw *hw) 1313181027Sjfv{ 1314181027Sjfv u16 data; 1315181027Sjfv 1316181027Sjfv DEBUGFUNC("e1000_check_mng_mode_82574"); 1317181027Sjfv 1318181027Sjfv hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1319185353Sjfv return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; 1320181027Sjfv} 1321181027Sjfv 1322181027Sjfv/** 1323181027Sjfv * e1000_led_on_82574 - Turn LED on 1324181027Sjfv * @hw: pointer to the HW structure 1325185353Sjfv * 1326181027Sjfv * Turn LED on. 1327181027Sjfv **/ 1328181027Sjfvstatic s32 e1000_led_on_82574(struct e1000_hw *hw) 1329181027Sjfv{ 1330181027Sjfv u32 ctrl; 1331181027Sjfv u32 i; 1332181027Sjfv 1333181027Sjfv DEBUGFUNC("e1000_led_on_82574"); 1334181027Sjfv 1335181027Sjfv ctrl = hw->mac.ledctl_mode2; 1336181027Sjfv if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) { 1337185353Sjfv /* 1338185353Sjfv * If no link, then turn LED on by setting the invert bit 1339181027Sjfv * for each LED that's "on" (0x0E) in ledctl_mode2. 1340181027Sjfv */ 1341181027Sjfv for (i = 0; i < 4; i++) 1342181027Sjfv if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1343181027Sjfv E1000_LEDCTL_MODE_LED_ON) 1344181027Sjfv ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); 1345181027Sjfv } 1346181027Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl); 1347181027Sjfv 1348181027Sjfv return E1000_SUCCESS; 1349181027Sjfv} 1350181027Sjfv 1351169240Sjfv 1352169240Sjfv/** 1353169240Sjfv * e1000_setup_link_82571 - Setup flow control and link settings 1354169589Sjfv * @hw: pointer to the HW structure 1355169240Sjfv * 1356169240Sjfv * Determines which flow control settings to use, then configures flow 1357169240Sjfv * control. Calls the appropriate media-specific link configuration 1358169240Sjfv * function. Assuming the adapter has a valid link partner, a valid link 1359169240Sjfv * should be established. Assumes the hardware has previously been reset 1360169240Sjfv * and the transmitter and receiver are not enabled. 1361169240Sjfv **/ 1362177867Sjfvstatic s32 e1000_setup_link_82571(struct e1000_hw *hw) 1363169240Sjfv{ 1364169240Sjfv DEBUGFUNC("e1000_setup_link_82571"); 1365169240Sjfv 1366173788Sjfv /* 1367173788Sjfv * 82573 does not have a word in the NVM to determine 1368169240Sjfv * the default flow control setting, so we explicitly 1369169240Sjfv * set it to full. 1370169240Sjfv */ 1371190872Sjfv switch (hw->mac.type) { 1372190872Sjfv case e1000_82574: 1373194865Sjfv case e1000_82583: 1374190872Sjfv case e1000_82573: 1375190872Sjfv if (hw->fc.requested_mode == e1000_fc_default) 1376190872Sjfv hw->fc.requested_mode = e1000_fc_full; 1377190872Sjfv break; 1378190872Sjfv default: 1379190872Sjfv break; 1380190872Sjfv } 1381169240Sjfv return e1000_setup_link_generic(hw); 1382169240Sjfv} 1383169240Sjfv 1384169240Sjfv/** 1385169240Sjfv * e1000_setup_copper_link_82571 - Configure copper link settings 1386169589Sjfv * @hw: pointer to the HW structure 1387169240Sjfv * 1388169240Sjfv * Configures the link for auto-neg or forced speed and duplex. Then we check 1389169240Sjfv * for link, once link is established calls to configure collision distance 1390169240Sjfv * and flow control are called. 1391169240Sjfv **/ 1392177867Sjfvstatic s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) 1393169240Sjfv{ 1394194865Sjfv u32 ctrl; 1395169240Sjfv s32 ret_val; 1396169240Sjfv 1397169240Sjfv DEBUGFUNC("e1000_setup_copper_link_82571"); 1398169240Sjfv 1399169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1400169240Sjfv ctrl |= E1000_CTRL_SLU; 1401169240Sjfv ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1402169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1403169240Sjfv 1404169240Sjfv switch (hw->phy.type) { 1405169240Sjfv case e1000_phy_m88: 1406176667Sjfv case e1000_phy_bm: 1407169240Sjfv ret_val = e1000_copper_link_setup_m88(hw); 1408169240Sjfv break; 1409169240Sjfv case e1000_phy_igp_2: 1410169240Sjfv ret_val = e1000_copper_link_setup_igp(hw); 1411169240Sjfv break; 1412169240Sjfv default: 1413169240Sjfv ret_val = -E1000_ERR_PHY; 1414169240Sjfv break; 1415169240Sjfv } 1416169240Sjfv 1417169240Sjfv if (ret_val) 1418169240Sjfv goto out; 1419169240Sjfv 1420169240Sjfv ret_val = e1000_setup_copper_link_generic(hw); 1421169240Sjfv 1422169240Sjfvout: 1423169240Sjfv return ret_val; 1424169240Sjfv} 1425169240Sjfv 1426169240Sjfv/** 1427169240Sjfv * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes 1428169589Sjfv * @hw: pointer to the HW structure 1429169240Sjfv * 1430169240Sjfv * Configures collision distance and flow control for fiber and serdes links. 1431169240Sjfv * Upon successful setup, poll for link. 1432169240Sjfv **/ 1433177867Sjfvstatic s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) 1434169240Sjfv{ 1435169240Sjfv DEBUGFUNC("e1000_setup_fiber_serdes_link_82571"); 1436169240Sjfv 1437169240Sjfv switch (hw->mac.type) { 1438169240Sjfv case e1000_82571: 1439169240Sjfv case e1000_82572: 1440173788Sjfv /* 1441173788Sjfv * If SerDes loopback mode is entered, there is no form 1442169240Sjfv * of reset to take the adapter out of that mode. So we 1443169240Sjfv * have to explicitly take the adapter out of loopback 1444176667Sjfv * mode. This prevents drivers from twiddling their thumbs 1445169240Sjfv * if another tool failed to take it out of loopback mode. 1446169240Sjfv */ 1447169240Sjfv E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1448169240Sjfv break; 1449169240Sjfv default: 1450169240Sjfv break; 1451169240Sjfv } 1452169240Sjfv 1453169240Sjfv return e1000_setup_fiber_serdes_link_generic(hw); 1454169240Sjfv} 1455169240Sjfv 1456169240Sjfv/** 1457190872Sjfv * e1000_check_for_serdes_link_82571 - Check for link (Serdes) 1458190872Sjfv * @hw: pointer to the HW structure 1459190872Sjfv * 1460194865Sjfv * Reports the link state as up or down. 1461194865Sjfv * 1462194865Sjfv * If autonegotiation is supported by the link partner, the link state is 1463194865Sjfv * determined by the result of autongotiation. This is the most likely case. 1464194865Sjfv * If autonegotiation is not supported by the link partner, and the link 1465194865Sjfv * has a valid signal, force the link up. 1466194865Sjfv * 1467194865Sjfv * The link state is represented internally here by 4 states: 1468194865Sjfv * 1469194865Sjfv * 1) down 1470194865Sjfv * 2) autoneg_progress 1471194865Sjfv * 3) autoneg_complete (the link sucessfully autonegotiated) 1472194865Sjfv * 4) forced_up (the link has been forced up, it did not autonegotiate) 1473194865Sjfv * 1474190872Sjfv **/ 1475190872Sjfvs32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) 1476190872Sjfv{ 1477190872Sjfv struct e1000_mac_info *mac = &hw->mac; 1478190872Sjfv u32 rxcw; 1479190872Sjfv u32 ctrl; 1480190872Sjfv u32 status; 1481190872Sjfv s32 ret_val = E1000_SUCCESS; 1482190872Sjfv 1483190872Sjfv DEBUGFUNC("e1000_check_for_serdes_link_82571"); 1484190872Sjfv 1485190872Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1486190872Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 1487190872Sjfv rxcw = E1000_READ_REG(hw, E1000_RXCW); 1488190872Sjfv 1489190872Sjfv if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { 1490190872Sjfv 1491190872Sjfv /* Receiver is synchronized with no invalid bits. */ 1492190872Sjfv switch (mac->serdes_link_state) { 1493190872Sjfv case e1000_serdes_link_autoneg_complete: 1494190872Sjfv if (!(status & E1000_STATUS_LU)) { 1495190872Sjfv /* 1496190872Sjfv * We have lost link, retry autoneg before 1497190872Sjfv * reporting link failure 1498190872Sjfv */ 1499190872Sjfv mac->serdes_link_state = 1500190872Sjfv e1000_serdes_link_autoneg_progress; 1501194865Sjfv mac->serdes_has_link = FALSE; 1502190872Sjfv DEBUGOUT("AN_UP -> AN_PROG\n"); 1503190872Sjfv } 1504190872Sjfv break; 1505190872Sjfv 1506190872Sjfv case e1000_serdes_link_forced_up: 1507190872Sjfv /* 1508190872Sjfv * If we are receiving /C/ ordered sets, re-enable 1509190872Sjfv * auto-negotiation in the TXCW register and disable 1510190872Sjfv * forced link in the Device Control register in an 1511190872Sjfv * attempt to auto-negotiate with our link partner. 1512190872Sjfv */ 1513190872Sjfv if (rxcw & E1000_RXCW_C) { 1514190872Sjfv /* Enable autoneg, and unforce link up */ 1515190872Sjfv E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1516190872Sjfv E1000_WRITE_REG(hw, E1000_CTRL, 1517190872Sjfv (ctrl & ~E1000_CTRL_SLU)); 1518190872Sjfv mac->serdes_link_state = 1519190872Sjfv e1000_serdes_link_autoneg_progress; 1520194865Sjfv mac->serdes_has_link = FALSE; 1521190872Sjfv DEBUGOUT("FORCED_UP -> AN_PROG\n"); 1522190872Sjfv } 1523190872Sjfv break; 1524190872Sjfv 1525190872Sjfv case e1000_serdes_link_autoneg_progress: 1526194865Sjfv if (rxcw & E1000_RXCW_C) { 1527194865Sjfv /* We received /C/ ordered sets, meaning the 1528194865Sjfv * link partner has autonegotiated, and we can 1529194865Sjfv * trust the Link Up (LU) status bit 1530194865Sjfv */ 1531194865Sjfv if (status & E1000_STATUS_LU) { 1532194865Sjfv mac->serdes_link_state = 1533194865Sjfv e1000_serdes_link_autoneg_complete; 1534194865Sjfv DEBUGOUT("AN_PROG -> AN_UP\n"); 1535194865Sjfv mac->serdes_has_link = TRUE; 1536194865Sjfv } else { 1537194865Sjfv /* Autoneg completed, but failed */ 1538194865Sjfv mac->serdes_link_state = 1539194865Sjfv e1000_serdes_link_down; 1540194865Sjfv DEBUGOUT("AN_PROG -> DOWN\n"); 1541194865Sjfv } 1542190872Sjfv } else { 1543194865Sjfv /* The link partner did not autoneg. 1544194865Sjfv * Force link up and full duplex, and change 1545194865Sjfv * state to forced. 1546190872Sjfv */ 1547190872Sjfv E1000_WRITE_REG(hw, E1000_TXCW, 1548194865Sjfv (mac->txcw & ~E1000_TXCW_ANE)); 1549190872Sjfv ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1550190872Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1551190872Sjfv 1552190872Sjfv /* Configure Flow Control after link up. */ 1553190872Sjfv ret_val = 1554190872Sjfv e1000_config_fc_after_link_up_generic(hw); 1555190872Sjfv if (ret_val) { 1556190872Sjfv DEBUGOUT("Error config flow control\n"); 1557190872Sjfv break; 1558190872Sjfv } 1559190872Sjfv mac->serdes_link_state = 1560194865Sjfv e1000_serdes_link_forced_up; 1561194865Sjfv mac->serdes_has_link = TRUE; 1562190872Sjfv DEBUGOUT("AN_PROG -> FORCED_UP\n"); 1563190872Sjfv } 1564190872Sjfv break; 1565190872Sjfv 1566190872Sjfv case e1000_serdes_link_down: 1567190872Sjfv default: 1568190872Sjfv /* The link was down but the receiver has now gained 1569190872Sjfv * valid sync, so lets see if we can bring the link 1570190872Sjfv * up. */ 1571190872Sjfv E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1572190872Sjfv E1000_WRITE_REG(hw, E1000_CTRL, 1573190872Sjfv (ctrl & ~E1000_CTRL_SLU)); 1574190872Sjfv mac->serdes_link_state = 1575190872Sjfv e1000_serdes_link_autoneg_progress; 1576190872Sjfv DEBUGOUT("DOWN -> AN_PROG\n"); 1577190872Sjfv break; 1578190872Sjfv } 1579190872Sjfv } else { 1580190872Sjfv if (!(rxcw & E1000_RXCW_SYNCH)) { 1581190872Sjfv mac->serdes_has_link = FALSE; 1582190872Sjfv mac->serdes_link_state = e1000_serdes_link_down; 1583190872Sjfv DEBUGOUT("ANYSTATE -> DOWN\n"); 1584190872Sjfv } else { 1585190872Sjfv /* 1586190872Sjfv * We have sync, and can tolerate one 1587190872Sjfv * invalid (IV) codeword before declaring 1588190872Sjfv * link down, so reread to look again 1589190872Sjfv */ 1590190872Sjfv usec_delay(10); 1591190872Sjfv rxcw = E1000_READ_REG(hw, E1000_RXCW); 1592190872Sjfv if (rxcw & E1000_RXCW_IV) { 1593190872Sjfv mac->serdes_link_state = e1000_serdes_link_down; 1594190872Sjfv mac->serdes_has_link = FALSE; 1595190872Sjfv DEBUGOUT("ANYSTATE -> DOWN\n"); 1596190872Sjfv } 1597190872Sjfv } 1598190872Sjfv } 1599190872Sjfv 1600190872Sjfv return ret_val; 1601190872Sjfv} 1602190872Sjfv 1603190872Sjfv/** 1604169240Sjfv * e1000_valid_led_default_82571 - Verify a valid default LED config 1605169589Sjfv * @hw: pointer to the HW structure 1606169589Sjfv * @data: pointer to the NVM (EEPROM) 1607169240Sjfv * 1608169240Sjfv * Read the EEPROM for the current default LED configuration. If the 1609169240Sjfv * LED configuration is not valid, set to a valid LED configuration. 1610169240Sjfv **/ 1611177867Sjfvstatic s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) 1612169240Sjfv{ 1613169240Sjfv s32 ret_val; 1614169240Sjfv 1615169240Sjfv DEBUGFUNC("e1000_valid_led_default_82571"); 1616169240Sjfv 1617177867Sjfv ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1618169240Sjfv if (ret_val) { 1619169240Sjfv DEBUGOUT("NVM Read Error\n"); 1620169240Sjfv goto out; 1621169240Sjfv } 1622169240Sjfv 1623190872Sjfv switch (hw->mac.type) { 1624190872Sjfv case e1000_82574: 1625194865Sjfv case e1000_82583: 1626190872Sjfv case e1000_82573: 1627190872Sjfv if(*data == ID_LED_RESERVED_F746) 1628190872Sjfv *data = ID_LED_DEFAULT_82573; 1629190872Sjfv break; 1630190872Sjfv default: 1631190872Sjfv if (*data == ID_LED_RESERVED_0000 || 1632190872Sjfv *data == ID_LED_RESERVED_FFFF) 1633190872Sjfv *data = ID_LED_DEFAULT; 1634190872Sjfv break; 1635190872Sjfv } 1636190872Sjfv 1637169240Sjfvout: 1638169240Sjfv return ret_val; 1639169240Sjfv} 1640169240Sjfv 1641169240Sjfv/** 1642169240Sjfv * e1000_get_laa_state_82571 - Get locally administered address state 1643169589Sjfv * @hw: pointer to the HW structure 1644169240Sjfv * 1645176667Sjfv * Retrieve and return the current locally administered address state. 1646169240Sjfv **/ 1647173788Sjfvbool e1000_get_laa_state_82571(struct e1000_hw *hw) 1648169240Sjfv{ 1649169240Sjfv DEBUGFUNC("e1000_get_laa_state_82571"); 1650169240Sjfv 1651169240Sjfv if (hw->mac.type != e1000_82571) 1652185353Sjfv return FALSE; 1653169240Sjfv 1654185353Sjfv return hw->dev_spec._82571.laa_is_present; 1655169240Sjfv} 1656169240Sjfv 1657169240Sjfv/** 1658169240Sjfv * e1000_set_laa_state_82571 - Set locally administered address state 1659169589Sjfv * @hw: pointer to the HW structure 1660169589Sjfv * @state: enable/disable locally administered address 1661169240Sjfv * 1662176667Sjfv * Enable/Disable the current locally administered address state. 1663169240Sjfv **/ 1664173788Sjfvvoid e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) 1665169240Sjfv{ 1666169240Sjfv DEBUGFUNC("e1000_set_laa_state_82571"); 1667169240Sjfv 1668169240Sjfv if (hw->mac.type != e1000_82571) 1669185353Sjfv return; 1670169240Sjfv 1671185353Sjfv hw->dev_spec._82571.laa_is_present = state; 1672169240Sjfv 1673169240Sjfv /* If workaround is activated... */ 1674185353Sjfv if (state) 1675173788Sjfv /* 1676173788Sjfv * Hold a copy of the LAA in RAR[14] This is done so that 1677169240Sjfv * between the time RAR[0] gets clobbered and the time it 1678169240Sjfv * gets fixed, the actual LAA is in one of the RARs and no 1679169240Sjfv * incoming packets directed to this port are dropped. 1680169240Sjfv * Eventually the LAA will be in RAR[0] and RAR[14]. 1681169240Sjfv */ 1682169240Sjfv e1000_rar_set_generic(hw, hw->mac.addr, 1683169240Sjfv hw->mac.rar_entry_count - 1); 1684169240Sjfv return; 1685169240Sjfv} 1686169240Sjfv 1687169240Sjfv/** 1688169240Sjfv * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum 1689169589Sjfv * @hw: pointer to the HW structure 1690169240Sjfv * 1691169240Sjfv * Verifies that the EEPROM has completed the update. After updating the 1692169240Sjfv * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If 1693169240Sjfv * the checksum fix is not implemented, we need to set the bit and update 1694169240Sjfv * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, 1695169240Sjfv * we need to return bad checksum. 1696169240Sjfv **/ 1697173788Sjfvstatic s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 1698169240Sjfv{ 1699169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 1700169240Sjfv s32 ret_val = E1000_SUCCESS; 1701169240Sjfv u16 data; 1702169240Sjfv 1703169240Sjfv DEBUGFUNC("e1000_fix_nvm_checksum_82571"); 1704169240Sjfv 1705169240Sjfv if (nvm->type != e1000_nvm_flash_hw) 1706169240Sjfv goto out; 1707169240Sjfv 1708173788Sjfv /* 1709173788Sjfv * Check bit 4 of word 10h. If it is 0, firmware is done updating 1710169240Sjfv * 10h-12h. Checksum may need to be fixed. 1711169240Sjfv */ 1712177867Sjfv ret_val = nvm->ops.read(hw, 0x10, 1, &data); 1713169240Sjfv if (ret_val) 1714169240Sjfv goto out; 1715169240Sjfv 1716169240Sjfv if (!(data & 0x10)) { 1717173788Sjfv /* 1718173788Sjfv * Read 0x23 and check bit 15. This bit is a 1 1719169240Sjfv * when the checksum has already been fixed. If 1720169240Sjfv * the checksum is still wrong and this bit is a 1721169240Sjfv * 1, we need to return bad checksum. Otherwise, 1722169240Sjfv * we need to set this bit to a 1 and update the 1723169240Sjfv * checksum. 1724169240Sjfv */ 1725177867Sjfv ret_val = nvm->ops.read(hw, 0x23, 1, &data); 1726169240Sjfv if (ret_val) 1727169240Sjfv goto out; 1728169240Sjfv 1729169240Sjfv if (!(data & 0x8000)) { 1730169240Sjfv data |= 0x8000; 1731177867Sjfv ret_val = nvm->ops.write(hw, 0x23, 1, &data); 1732169240Sjfv if (ret_val) 1733169240Sjfv goto out; 1734177867Sjfv ret_val = nvm->ops.update(hw); 1735169240Sjfv } 1736169240Sjfv } 1737169240Sjfv 1738169240Sjfvout: 1739169240Sjfv return ret_val; 1740169240Sjfv} 1741169240Sjfv 1742190872Sjfv 1743169240Sjfv/** 1744173788Sjfv * e1000_read_mac_addr_82571 - Read device MAC address 1745173788Sjfv * @hw: pointer to the HW structure 1746173788Sjfv **/ 1747177867Sjfvstatic s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) 1748173788Sjfv{ 1749173788Sjfv s32 ret_val = E1000_SUCCESS; 1750173788Sjfv 1751173788Sjfv DEBUGFUNC("e1000_read_mac_addr_82571"); 1752173788Sjfv 1753190872Sjfv /* 1754190872Sjfv * If there's an alternate MAC address place it in RAR0 1755190872Sjfv * so that it will override the Si installed default perm 1756190872Sjfv * address. 1757190872Sjfv */ 1758190872Sjfv ret_val = e1000_check_alt_mac_addr_generic(hw); 1759190872Sjfv if (ret_val) 1760190872Sjfv goto out; 1761190872Sjfv 1762190872Sjfv ret_val = e1000_read_mac_addr_generic(hw); 1763190872Sjfv 1764190872Sjfvout: 1765173788Sjfv return ret_val; 1766173788Sjfv} 1767173788Sjfv 1768173788Sjfv/** 1769173788Sjfv * e1000_power_down_phy_copper_82571 - Remove link during PHY power down 1770173788Sjfv * @hw: pointer to the HW structure 1771173788Sjfv * 1772173788Sjfv * In the case of a PHY power down to save power, or to turn off link during a 1773173788Sjfv * driver unload, or wake on lan is not enabled, remove the link. 1774173788Sjfv **/ 1775177867Sjfvstatic void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) 1776173788Sjfv{ 1777177867Sjfv struct e1000_phy_info *phy = &hw->phy; 1778177867Sjfv struct e1000_mac_info *mac = &hw->mac; 1779177867Sjfv 1780177867Sjfv if (!(phy->ops.check_reset_block)) 1781177867Sjfv return; 1782177867Sjfv 1783173788Sjfv /* If the management interface is not enabled, then power down */ 1784177867Sjfv if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 1785173788Sjfv e1000_power_down_phy_copper(hw); 1786173788Sjfv 1787173788Sjfv return; 1788173788Sjfv} 1789173788Sjfv 1790173788Sjfv/** 1791169240Sjfv * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters 1792169589Sjfv * @hw: pointer to the HW structure 1793169240Sjfv * 1794169240Sjfv * Clears the hardware counters by reading the counter registers. 1795169240Sjfv **/ 1796177867Sjfvstatic void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) 1797169240Sjfv{ 1798169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_82571"); 1799169240Sjfv 1800169240Sjfv e1000_clear_hw_cntrs_base_generic(hw); 1801169240Sjfv 1802185353Sjfv E1000_READ_REG(hw, E1000_PRC64); 1803185353Sjfv E1000_READ_REG(hw, E1000_PRC127); 1804185353Sjfv E1000_READ_REG(hw, E1000_PRC255); 1805185353Sjfv E1000_READ_REG(hw, E1000_PRC511); 1806185353Sjfv E1000_READ_REG(hw, E1000_PRC1023); 1807185353Sjfv E1000_READ_REG(hw, E1000_PRC1522); 1808185353Sjfv E1000_READ_REG(hw, E1000_PTC64); 1809185353Sjfv E1000_READ_REG(hw, E1000_PTC127); 1810185353Sjfv E1000_READ_REG(hw, E1000_PTC255); 1811185353Sjfv E1000_READ_REG(hw, E1000_PTC511); 1812185353Sjfv E1000_READ_REG(hw, E1000_PTC1023); 1813185353Sjfv E1000_READ_REG(hw, E1000_PTC1522); 1814169240Sjfv 1815185353Sjfv E1000_READ_REG(hw, E1000_ALGNERRC); 1816185353Sjfv E1000_READ_REG(hw, E1000_RXERRC); 1817185353Sjfv E1000_READ_REG(hw, E1000_TNCRS); 1818185353Sjfv E1000_READ_REG(hw, E1000_CEXTERR); 1819185353Sjfv E1000_READ_REG(hw, E1000_TSCTC); 1820185353Sjfv E1000_READ_REG(hw, E1000_TSCTFC); 1821169240Sjfv 1822185353Sjfv E1000_READ_REG(hw, E1000_MGTPRC); 1823185353Sjfv E1000_READ_REG(hw, E1000_MGTPDC); 1824185353Sjfv E1000_READ_REG(hw, E1000_MGTPTC); 1825169240Sjfv 1826185353Sjfv E1000_READ_REG(hw, E1000_IAC); 1827185353Sjfv E1000_READ_REG(hw, E1000_ICRXOC); 1828185353Sjfv 1829185353Sjfv E1000_READ_REG(hw, E1000_ICRXPTC); 1830185353Sjfv E1000_READ_REG(hw, E1000_ICRXATC); 1831185353Sjfv E1000_READ_REG(hw, E1000_ICTXPTC); 1832185353Sjfv E1000_READ_REG(hw, E1000_ICTXATC); 1833185353Sjfv E1000_READ_REG(hw, E1000_ICTXQEC); 1834185353Sjfv E1000_READ_REG(hw, E1000_ICTXQMTC); 1835185353Sjfv E1000_READ_REG(hw, E1000_ICRXDMTC); 1836169240Sjfv} 1837