e1000_82571.c revision 181027
1177867Sjfv/****************************************************************************** 2169240Sjfv 3176667Sjfv Copyright (c) 2001-2008, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD: head/sys/dev/e1000/e1000_82571.c 181027 2008-07-30 21:56:53Z jfv $*/ 34169240Sjfv 35169240Sjfv/* e1000_82571 36169240Sjfv * e1000_82572 37169240Sjfv * e1000_82573 38173788Sjfv * e1000_82574 39169240Sjfv */ 40169240Sjfv 41169589Sjfv#include "e1000_api.h" 42169240Sjfv 43177867Sjfvstatic s32 e1000_init_phy_params_82571(struct e1000_hw *hw); 44177867Sjfvstatic s32 e1000_init_nvm_params_82571(struct e1000_hw *hw); 45177867Sjfvstatic s32 e1000_init_mac_params_82571(struct e1000_hw *hw); 46177867Sjfvstatic s32 e1000_acquire_nvm_82571(struct e1000_hw *hw); 47177867Sjfvstatic void e1000_release_nvm_82571(struct e1000_hw *hw); 48177867Sjfvstatic s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, 49169240Sjfv u16 words, u16 *data); 50177867Sjfvstatic s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw); 51177867Sjfvstatic s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw); 52177867Sjfvstatic s32 e1000_get_cfg_done_82571(struct e1000_hw *hw); 53177867Sjfvstatic s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, 54173788Sjfv bool active); 55177867Sjfvstatic s32 e1000_reset_hw_82571(struct e1000_hw *hw); 56177867Sjfvstatic s32 e1000_init_hw_82571(struct e1000_hw *hw); 57177867Sjfvstatic void e1000_clear_vfta_82571(struct e1000_hw *hw); 58181027Sjfvstatic bool e1000_check_mng_mode_82574(struct e1000_hw *hw); 59181027Sjfvstatic s32 e1000_led_on_82574(struct e1000_hw *hw); 60177867Sjfvstatic void e1000_update_mc_addr_list_82571(struct e1000_hw *hw, 61176667Sjfv u8 *mc_addr_list, u32 mc_addr_count, 62176667Sjfv u32 rar_used_count, u32 rar_count); 63177867Sjfvstatic s32 e1000_setup_link_82571(struct e1000_hw *hw); 64177867Sjfvstatic s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); 65177867Sjfvstatic s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); 66177867Sjfvstatic s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data); 67177867Sjfvstatic void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); 68169589Sjfvstatic s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw); 69169240Sjfvstatic s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); 70169240Sjfvstatic s32 e1000_get_phy_id_82571(struct e1000_hw *hw); 71169589Sjfvstatic void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); 72169240Sjfvstatic void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); 73169240Sjfvstatic s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 74169240Sjfv u16 words, u16 *data); 75177867Sjfvstatic s32 e1000_read_mac_addr_82571(struct e1000_hw *hw); 76177867Sjfvstatic void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); 77169240Sjfv 78169240Sjfvstruct e1000_dev_spec_82571 { 79173788Sjfv bool laa_is_present; 80169240Sjfv}; 81169240Sjfv 82169240Sjfv/** 83169240Sjfv * e1000_init_phy_params_82571 - Init PHY func ptrs. 84169589Sjfv * @hw: pointer to the HW structure 85169240Sjfv * 86169240Sjfv * This is a function pointer entry point called by the api module. 87169240Sjfv **/ 88177867Sjfvstatic s32 e1000_init_phy_params_82571(struct e1000_hw *hw) 89169240Sjfv{ 90169240Sjfv struct e1000_phy_info *phy = &hw->phy; 91169240Sjfv s32 ret_val = E1000_SUCCESS; 92169240Sjfv 93169240Sjfv DEBUGFUNC("e1000_init_phy_params_82571"); 94169240Sjfv 95173788Sjfv if (hw->phy.media_type != e1000_media_type_copper) { 96169240Sjfv phy->type = e1000_phy_none; 97169240Sjfv goto out; 98169240Sjfv } 99169240Sjfv 100169240Sjfv phy->addr = 1; 101169240Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 102169240Sjfv phy->reset_delay_us = 100; 103169240Sjfv 104177867Sjfv phy->ops.acquire = e1000_get_hw_semaphore_82571; 105177867Sjfv phy->ops.check_polarity = e1000_check_polarity_igp; 106177867Sjfv phy->ops.check_reset_block = e1000_check_reset_block_generic; 107177867Sjfv phy->ops.release = e1000_put_hw_semaphore_82571; 108177867Sjfv phy->ops.reset = e1000_phy_hw_reset_generic; 109177867Sjfv phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571; 110177867Sjfv phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 111177867Sjfv phy->ops.power_up = e1000_power_up_phy_copper; 112177867Sjfv phy->ops.power_down = e1000_power_down_phy_copper_82571; 113169240Sjfv 114169240Sjfv switch (hw->mac.type) { 115169240Sjfv case e1000_82571: 116169240Sjfv case e1000_82572: 117177867Sjfv phy->type = e1000_phy_igp_2; 118177867Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_82571; 119177867Sjfv phy->ops.get_info = e1000_get_phy_info_igp; 120177867Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 121177867Sjfv phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 122177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_igp; 123177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_igp; 124173788Sjfv 125173788Sjfv /* This uses above function pointers */ 126173788Sjfv ret_val = e1000_get_phy_id_82571(hw); 127173788Sjfv 128173788Sjfv /* Verify PHY ID */ 129173788Sjfv if (phy->id != IGP01E1000_I_PHY_ID) { 130173788Sjfv ret_val = -E1000_ERR_PHY; 131173788Sjfv goto out; 132173788Sjfv } 133169240Sjfv break; 134169240Sjfv case e1000_82573: 135177867Sjfv phy->type = e1000_phy_m88; 136177867Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 137177867Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 138177867Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 139177867Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 140177867Sjfv phy->ops.get_cable_length = e1000_get_cable_length_m88; 141177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_m88; 142177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_m88; 143169240Sjfv 144173788Sjfv /* This uses above function pointers */ 145173788Sjfv ret_val = e1000_get_phy_id_82571(hw); 146169240Sjfv 147173788Sjfv /* Verify PHY ID */ 148169240Sjfv if (phy->id != M88E1111_I_PHY_ID) { 149169240Sjfv ret_val = -E1000_ERR_PHY; 150173788Sjfv DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 151169240Sjfv goto out; 152169240Sjfv } 153169240Sjfv break; 154178523Sjfv case e1000_82574: 155178523Sjfv phy->type = e1000_phy_bm; 156178523Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 157178523Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 158178523Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 159178523Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 160178523Sjfv phy->ops.get_cable_length = e1000_get_cable_length_m88; 161178523Sjfv phy->ops.read_reg = e1000_read_phy_reg_bm2; 162178523Sjfv phy->ops.write_reg = e1000_write_phy_reg_bm2; 163178523Sjfv 164178523Sjfv /* This uses above function pointers */ 165178523Sjfv ret_val = e1000_get_phy_id_82571(hw); 166178523Sjfv /* Verify PHY ID */ 167178523Sjfv if (phy->id != BME1000_E_PHY_ID_R2) { 168178523Sjfv ret_val = -E1000_ERR_PHY; 169178523Sjfv DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 170178523Sjfv goto out; 171178523Sjfv } 172178523Sjfv break; 173169240Sjfv default: 174169240Sjfv ret_val = -E1000_ERR_PHY; 175169240Sjfv goto out; 176169240Sjfv break; 177169240Sjfv } 178169240Sjfv 179169240Sjfvout: 180169240Sjfv return ret_val; 181169240Sjfv} 182169240Sjfv 183169240Sjfv/** 184169240Sjfv * e1000_init_nvm_params_82571 - Init NVM func ptrs. 185169589Sjfv * @hw: pointer to the HW structure 186169240Sjfv * 187169240Sjfv * This is a function pointer entry point called by the api module. 188169240Sjfv **/ 189177867Sjfvstatic s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) 190169240Sjfv{ 191169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 192169240Sjfv u32 eecd = E1000_READ_REG(hw, E1000_EECD); 193169240Sjfv u16 size; 194169240Sjfv 195169240Sjfv DEBUGFUNC("e1000_init_nvm_params_82571"); 196169240Sjfv 197169240Sjfv nvm->opcode_bits = 8; 198169240Sjfv nvm->delay_usec = 1; 199169240Sjfv switch (nvm->override) { 200169240Sjfv case e1000_nvm_override_spi_large: 201169240Sjfv nvm->page_size = 32; 202169240Sjfv nvm->address_bits = 16; 203169240Sjfv break; 204169240Sjfv case e1000_nvm_override_spi_small: 205169240Sjfv nvm->page_size = 8; 206169240Sjfv nvm->address_bits = 8; 207169240Sjfv break; 208169240Sjfv default: 209169240Sjfv nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 210169240Sjfv nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 211169240Sjfv break; 212169240Sjfv } 213169240Sjfv 214169240Sjfv switch (hw->mac.type) { 215169240Sjfv case e1000_82573: 216178523Sjfv case e1000_82574: 217169240Sjfv if (((eecd >> 15) & 0x3) == 0x3) { 218169240Sjfv nvm->type = e1000_nvm_flash_hw; 219169240Sjfv nvm->word_size = 2048; 220173788Sjfv /* 221173788Sjfv * Autonomous Flash update bit must be cleared due 222169240Sjfv * to Flash update issue. 223169240Sjfv */ 224169240Sjfv eecd &= ~E1000_EECD_AUPDEN; 225169240Sjfv E1000_WRITE_REG(hw, E1000_EECD, eecd); 226169240Sjfv break; 227169240Sjfv } 228169240Sjfv /* Fall Through */ 229169240Sjfv default: 230169240Sjfv nvm->type = e1000_nvm_eeprom_spi; 231169240Sjfv size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 232169240Sjfv E1000_EECD_SIZE_EX_SHIFT); 233173788Sjfv /* 234173788Sjfv * Added to a constant, "size" becomes the left-shift value 235169240Sjfv * for setting word_size. 236169240Sjfv */ 237169240Sjfv size += NVM_WORD_SIZE_BASE_SHIFT; 238173788Sjfv 239173788Sjfv /* EEPROM access above 16k is unsupported */ 240173788Sjfv if (size > 14) 241173788Sjfv size = 14; 242169240Sjfv nvm->word_size = 1 << size; 243169240Sjfv break; 244169240Sjfv } 245169240Sjfv 246169240Sjfv /* Function Pointers */ 247177867Sjfv nvm->ops.acquire = e1000_acquire_nvm_82571; 248177867Sjfv nvm->ops.read = e1000_read_nvm_eerd; 249177867Sjfv nvm->ops.release = e1000_release_nvm_82571; 250177867Sjfv nvm->ops.update = e1000_update_nvm_checksum_82571; 251177867Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_82571; 252177867Sjfv nvm->ops.valid_led_default = e1000_valid_led_default_82571; 253177867Sjfv nvm->ops.write = e1000_write_nvm_82571; 254169240Sjfv 255169240Sjfv return E1000_SUCCESS; 256169240Sjfv} 257169240Sjfv 258169240Sjfv/** 259169240Sjfv * e1000_init_mac_params_82571 - Init MAC func ptrs. 260169589Sjfv * @hw: pointer to the HW structure 261169240Sjfv * 262169240Sjfv * This is a function pointer entry point called by the api module. 263169240Sjfv **/ 264177867Sjfvstatic s32 e1000_init_mac_params_82571(struct e1000_hw *hw) 265169240Sjfv{ 266169240Sjfv struct e1000_mac_info *mac = &hw->mac; 267169240Sjfv s32 ret_val = E1000_SUCCESS; 268169240Sjfv 269169240Sjfv DEBUGFUNC("e1000_init_mac_params_82571"); 270169240Sjfv 271169240Sjfv /* Set media type */ 272169240Sjfv switch (hw->device_id) { 273169240Sjfv case E1000_DEV_ID_82571EB_FIBER: 274169240Sjfv case E1000_DEV_ID_82572EI_FIBER: 275169240Sjfv case E1000_DEV_ID_82571EB_QUAD_FIBER: 276173788Sjfv hw->phy.media_type = e1000_media_type_fiber; 277169240Sjfv break; 278169240Sjfv case E1000_DEV_ID_82571EB_SERDES: 279169589Sjfv case E1000_DEV_ID_82571EB_SERDES_DUAL: 280169589Sjfv case E1000_DEV_ID_82571EB_SERDES_QUAD: 281169240Sjfv case E1000_DEV_ID_82572EI_SERDES: 282173788Sjfv hw->phy.media_type = e1000_media_type_internal_serdes; 283169240Sjfv break; 284169240Sjfv default: 285173788Sjfv hw->phy.media_type = e1000_media_type_copper; 286169240Sjfv break; 287169240Sjfv } 288169240Sjfv 289169240Sjfv /* Set mta register count */ 290169240Sjfv mac->mta_reg_count = 128; 291169240Sjfv /* Set rar entry count */ 292169240Sjfv mac->rar_entry_count = E1000_RAR_ENTRIES; 293169240Sjfv /* Set if part includes ASF firmware */ 294169240Sjfv mac->asf_firmware_present = TRUE; 295169240Sjfv /* Set if manageability features are enabled. */ 296169240Sjfv mac->arc_subsystem_valid = 297169240Sjfv (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 298169240Sjfv ? TRUE : FALSE; 299169240Sjfv 300169240Sjfv /* Function pointers */ 301169240Sjfv 302169240Sjfv /* bus type/speed/width */ 303177867Sjfv mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 304169240Sjfv /* reset */ 305177867Sjfv mac->ops.reset_hw = e1000_reset_hw_82571; 306169240Sjfv /* hw initialization */ 307177867Sjfv mac->ops.init_hw = e1000_init_hw_82571; 308169240Sjfv /* link setup */ 309177867Sjfv mac->ops.setup_link = e1000_setup_link_82571; 310169240Sjfv /* physical interface link setup */ 311177867Sjfv mac->ops.setup_physical_interface = 312173788Sjfv (hw->phy.media_type == e1000_media_type_copper) 313169240Sjfv ? e1000_setup_copper_link_82571 314169240Sjfv : e1000_setup_fiber_serdes_link_82571; 315169240Sjfv /* check for link */ 316173788Sjfv switch (hw->phy.media_type) { 317169240Sjfv case e1000_media_type_copper: 318177867Sjfv mac->ops.check_for_link = e1000_check_for_copper_link_generic; 319169240Sjfv break; 320169240Sjfv case e1000_media_type_fiber: 321177867Sjfv mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 322169240Sjfv break; 323169240Sjfv case e1000_media_type_internal_serdes: 324177867Sjfv mac->ops.check_for_link = e1000_check_for_serdes_link_generic; 325169240Sjfv break; 326169240Sjfv default: 327169240Sjfv ret_val = -E1000_ERR_CONFIG; 328169240Sjfv goto out; 329169240Sjfv break; 330169240Sjfv } 331169240Sjfv /* check management mode */ 332181027Sjfv switch (hw->mac.type) { 333181027Sjfv case e1000_82574: 334181027Sjfv mac->ops.check_mng_mode = e1000_check_mng_mode_82574; 335181027Sjfv break; 336181027Sjfv default: 337181027Sjfv mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 338181027Sjfv break; 339181027Sjfv } 340169240Sjfv /* multicast address update */ 341177867Sjfv mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_82571; 342169240Sjfv /* writing VFTA */ 343177867Sjfv mac->ops.write_vfta = e1000_write_vfta_generic; 344169240Sjfv /* clearing VFTA */ 345177867Sjfv mac->ops.clear_vfta = e1000_clear_vfta_82571; 346169240Sjfv /* setting MTA */ 347177867Sjfv mac->ops.mta_set = e1000_mta_set_generic; 348173788Sjfv /* read mac address */ 349177867Sjfv mac->ops.read_mac_addr = e1000_read_mac_addr_82571; 350169240Sjfv /* blink LED */ 351177867Sjfv mac->ops.blink_led = e1000_blink_led_generic; 352169240Sjfv /* setup LED */ 353177867Sjfv mac->ops.setup_led = e1000_setup_led_generic; 354169240Sjfv /* cleanup LED */ 355177867Sjfv mac->ops.cleanup_led = e1000_cleanup_led_generic; 356169240Sjfv /* turn on/off LED */ 357181027Sjfv switch (hw->mac.type) { 358181027Sjfv case e1000_82574: 359181027Sjfv mac->ops.led_on = e1000_led_on_82574; 360181027Sjfv break; 361181027Sjfv default: 362181027Sjfv mac->ops.led_on = e1000_led_on_generic; 363181027Sjfv break; 364181027Sjfv } 365177867Sjfv mac->ops.led_off = e1000_led_off_generic; 366169240Sjfv /* remove device */ 367177867Sjfv mac->ops.remove_device = e1000_remove_device_generic; 368169240Sjfv /* clear hardware counters */ 369177867Sjfv mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571; 370169240Sjfv /* link info */ 371177867Sjfv mac->ops.get_link_up_info = 372173788Sjfv (hw->phy.media_type == e1000_media_type_copper) 373169240Sjfv ? e1000_get_speed_and_duplex_copper_generic 374169240Sjfv : e1000_get_speed_and_duplex_fiber_serdes_generic; 375169240Sjfv 376169240Sjfv hw->dev_spec_size = sizeof(struct e1000_dev_spec_82571); 377169240Sjfv 378169240Sjfv /* Device-specific structure allocation */ 379169240Sjfv ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 380169240Sjfv 381169240Sjfvout: 382169240Sjfv return ret_val; 383169240Sjfv} 384169240Sjfv 385169240Sjfv/** 386169240Sjfv * e1000_init_function_pointers_82571 - Init func ptrs. 387169589Sjfv * @hw: pointer to the HW structure 388169240Sjfv * 389169240Sjfv * The only function explicitly called by the api module to initialize 390169240Sjfv * all function pointers and parameters. 391169240Sjfv **/ 392173788Sjfvvoid e1000_init_function_pointers_82571(struct e1000_hw *hw) 393169240Sjfv{ 394169240Sjfv DEBUGFUNC("e1000_init_function_pointers_82571"); 395169240Sjfv 396177867Sjfv hw->mac.ops.init_params = e1000_init_mac_params_82571; 397177867Sjfv hw->nvm.ops.init_params = e1000_init_nvm_params_82571; 398177867Sjfv hw->phy.ops.init_params = e1000_init_phy_params_82571; 399169240Sjfv} 400169240Sjfv 401169240Sjfv/** 402169240Sjfv * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision 403169589Sjfv * @hw: pointer to the HW structure 404169240Sjfv * 405169240Sjfv * Reads the PHY registers and stores the PHY ID and possibly the PHY 406169240Sjfv * revision in the hardware structure. 407169240Sjfv **/ 408173788Sjfvstatic s32 e1000_get_phy_id_82571(struct e1000_hw *hw) 409169240Sjfv{ 410169240Sjfv struct e1000_phy_info *phy = &hw->phy; 411169240Sjfv s32 ret_val = E1000_SUCCESS; 412178523Sjfv u16 phy_id = 0; 413169240Sjfv 414169240Sjfv DEBUGFUNC("e1000_get_phy_id_82571"); 415169240Sjfv 416169240Sjfv switch (hw->mac.type) { 417169240Sjfv case e1000_82571: 418169240Sjfv case e1000_82572: 419173788Sjfv /* 420173788Sjfv * The 82571 firmware may still be configuring the PHY. 421169240Sjfv * In this case, we cannot access the PHY until the 422169240Sjfv * configuration is done. So we explicitly set the 423173788Sjfv * PHY ID. 424173788Sjfv */ 425169240Sjfv phy->id = IGP01E1000_I_PHY_ID; 426169240Sjfv break; 427169240Sjfv case e1000_82573: 428169240Sjfv ret_val = e1000_get_phy_id(hw); 429169240Sjfv break; 430178523Sjfv case e1000_82574: 431178523Sjfv ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 432178523Sjfv if (ret_val) 433178523Sjfv goto out; 434178523Sjfv 435178523Sjfv phy->id = (u32)(phy_id << 16); 436178523Sjfv usec_delay(20); 437178523Sjfv ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 438178523Sjfv if (ret_val) 439178523Sjfv goto out; 440178523Sjfv 441178523Sjfv phy->id |= (u32)(phy_id); 442178523Sjfv phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 443178523Sjfv break; 444169240Sjfv default: 445169240Sjfv ret_val = -E1000_ERR_PHY; 446169240Sjfv break; 447169240Sjfv } 448169240Sjfv 449178523Sjfvout: 450169240Sjfv return ret_val; 451169240Sjfv} 452169240Sjfv 453169240Sjfv/** 454169589Sjfv * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore 455169589Sjfv * @hw: pointer to the HW structure 456169589Sjfv * 457169589Sjfv * Acquire the HW semaphore to access the PHY or NVM 458169589Sjfv **/ 459176667Sjfvstatic s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 460169589Sjfv{ 461169589Sjfv u32 swsm; 462169589Sjfv s32 ret_val = E1000_SUCCESS; 463169589Sjfv s32 timeout = hw->nvm.word_size + 1; 464169589Sjfv s32 i = 0; 465169589Sjfv 466169589Sjfv DEBUGFUNC("e1000_get_hw_semaphore_82571"); 467169589Sjfv 468169589Sjfv /* Get the FW semaphore. */ 469169589Sjfv for (i = 0; i < timeout; i++) { 470169589Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 471169589Sjfv E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 472169589Sjfv 473169589Sjfv /* Semaphore acquired if bit latched */ 474169589Sjfv if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 475169589Sjfv break; 476169589Sjfv 477169589Sjfv usec_delay(50); 478169589Sjfv } 479169589Sjfv 480169589Sjfv if (i == timeout) { 481169589Sjfv /* Release semaphores */ 482169589Sjfv e1000_put_hw_semaphore_generic(hw); 483169589Sjfv DEBUGOUT("Driver can't access the NVM\n"); 484169589Sjfv ret_val = -E1000_ERR_NVM; 485169589Sjfv goto out; 486169589Sjfv } 487169589Sjfv 488169589Sjfvout: 489169589Sjfv return ret_val; 490169589Sjfv} 491169589Sjfv 492169589Sjfv/** 493169589Sjfv * e1000_put_hw_semaphore_82571 - Release hardware semaphore 494169589Sjfv * @hw: pointer to the HW structure 495169589Sjfv * 496169589Sjfv * Release hardware semaphore used to access the PHY or NVM 497169589Sjfv **/ 498176667Sjfvstatic void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) 499169589Sjfv{ 500169589Sjfv u32 swsm; 501169589Sjfv 502169589Sjfv DEBUGFUNC("e1000_put_hw_semaphore_82571"); 503169589Sjfv 504169589Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 505169589Sjfv 506169589Sjfv swsm &= ~E1000_SWSM_SWESMBI; 507169589Sjfv 508169589Sjfv E1000_WRITE_REG(hw, E1000_SWSM, swsm); 509169589Sjfv} 510169589Sjfv 511169589Sjfv/** 512169240Sjfv * e1000_acquire_nvm_82571 - Request for access to the EEPROM 513169589Sjfv * @hw: pointer to the HW structure 514169240Sjfv * 515169240Sjfv * To gain access to the EEPROM, first we must obtain a hardware semaphore. 516169240Sjfv * Then for non-82573 hardware, set the EEPROM access request bit and wait 517169240Sjfv * for EEPROM access grant bit. If the access grant bit is not set, release 518169240Sjfv * hardware semaphore. 519169240Sjfv **/ 520177867Sjfvstatic s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) 521169240Sjfv{ 522169240Sjfv s32 ret_val; 523169240Sjfv 524169240Sjfv DEBUGFUNC("e1000_acquire_nvm_82571"); 525169240Sjfv 526169589Sjfv ret_val = e1000_get_hw_semaphore_82571(hw); 527169240Sjfv if (ret_val) 528169240Sjfv goto out; 529169240Sjfv 530178523Sjfv if (hw->mac.type != e1000_82573 && hw->mac.type != e1000_82574) 531169240Sjfv ret_val = e1000_acquire_nvm_generic(hw); 532169240Sjfv 533169240Sjfv if (ret_val) 534169589Sjfv e1000_put_hw_semaphore_82571(hw); 535169240Sjfv 536169240Sjfvout: 537169240Sjfv return ret_val; 538169240Sjfv} 539169240Sjfv 540169240Sjfv/** 541169240Sjfv * e1000_release_nvm_82571 - Release exclusive access to EEPROM 542169589Sjfv * @hw: pointer to the HW structure 543169240Sjfv * 544169240Sjfv * Stop any current commands to the EEPROM and clear the EEPROM request bit. 545169240Sjfv **/ 546177867Sjfvstatic void e1000_release_nvm_82571(struct e1000_hw *hw) 547169240Sjfv{ 548169240Sjfv DEBUGFUNC("e1000_release_nvm_82571"); 549169240Sjfv 550169240Sjfv e1000_release_nvm_generic(hw); 551169589Sjfv e1000_put_hw_semaphore_82571(hw); 552169240Sjfv} 553169240Sjfv 554169240Sjfv/** 555169240Sjfv * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface 556169589Sjfv * @hw: pointer to the HW structure 557169589Sjfv * @offset: offset within the EEPROM to be written to 558169589Sjfv * @words: number of words to write 559169589Sjfv * @data: 16 bit word(s) to be written to the EEPROM 560169240Sjfv * 561169240Sjfv * For non-82573 silicon, write data to EEPROM at offset using SPI interface. 562169240Sjfv * 563169240Sjfv * If e1000_update_nvm_checksum is not called after this function, the 564176667Sjfv * EEPROM will most likely contain an invalid checksum. 565169240Sjfv **/ 566177867Sjfvstatic s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, 567173788Sjfv u16 *data) 568169240Sjfv{ 569169240Sjfv s32 ret_val = E1000_SUCCESS; 570169240Sjfv 571169240Sjfv DEBUGFUNC("e1000_write_nvm_82571"); 572169240Sjfv 573169240Sjfv switch (hw->mac.type) { 574169240Sjfv case e1000_82573: 575178523Sjfv case e1000_82574: 576169240Sjfv ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); 577169240Sjfv break; 578169240Sjfv case e1000_82571: 579169240Sjfv case e1000_82572: 580169240Sjfv ret_val = e1000_write_nvm_spi(hw, offset, words, data); 581169240Sjfv break; 582169240Sjfv default: 583169240Sjfv ret_val = -E1000_ERR_NVM; 584169240Sjfv break; 585169240Sjfv } 586169240Sjfv 587169240Sjfv return ret_val; 588169240Sjfv} 589169240Sjfv 590169240Sjfv/** 591169240Sjfv * e1000_update_nvm_checksum_82571 - Update EEPROM checksum 592169589Sjfv * @hw: pointer to the HW structure 593169240Sjfv * 594169240Sjfv * Updates the EEPROM checksum by reading/adding each word of the EEPROM 595169240Sjfv * up to the checksum. Then calculates the EEPROM checksum and writes the 596169240Sjfv * value to the EEPROM. 597169240Sjfv **/ 598177867Sjfvstatic s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 599169240Sjfv{ 600169240Sjfv u32 eecd; 601169240Sjfv s32 ret_val; 602169240Sjfv u16 i; 603169240Sjfv 604169240Sjfv DEBUGFUNC("e1000_update_nvm_checksum_82571"); 605169240Sjfv 606169240Sjfv ret_val = e1000_update_nvm_checksum_generic(hw); 607169240Sjfv if (ret_val) 608169240Sjfv goto out; 609169240Sjfv 610173788Sjfv /* 611173788Sjfv * If our nvm is an EEPROM, then we're done 612173788Sjfv * otherwise, commit the checksum to the flash NVM. 613173788Sjfv */ 614169240Sjfv if (hw->nvm.type != e1000_nvm_flash_hw) 615169240Sjfv goto out; 616169240Sjfv 617169240Sjfv /* Check for pending operations. */ 618169240Sjfv for (i = 0; i < E1000_FLASH_UPDATES; i++) { 619169240Sjfv msec_delay(1); 620169240Sjfv if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 621169240Sjfv break; 622169240Sjfv } 623169240Sjfv 624169240Sjfv if (i == E1000_FLASH_UPDATES) { 625169240Sjfv ret_val = -E1000_ERR_NVM; 626169240Sjfv goto out; 627169240Sjfv } 628169240Sjfv 629169240Sjfv /* Reset the firmware if using STM opcode. */ 630169240Sjfv if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) { 631173788Sjfv /* 632173788Sjfv * The enabling of and the actual reset must be done 633169240Sjfv * in two write cycles. 634169240Sjfv */ 635169240Sjfv E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE); 636169240Sjfv E1000_WRITE_FLUSH(hw); 637169240Sjfv E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET); 638169240Sjfv } 639169240Sjfv 640169240Sjfv /* Commit the write to flash */ 641169240Sjfv eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD; 642169240Sjfv E1000_WRITE_REG(hw, E1000_EECD, eecd); 643169240Sjfv 644169240Sjfv for (i = 0; i < E1000_FLASH_UPDATES; i++) { 645169240Sjfv msec_delay(1); 646169240Sjfv if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 647169240Sjfv break; 648169240Sjfv } 649169240Sjfv 650169240Sjfv if (i == E1000_FLASH_UPDATES) { 651169240Sjfv ret_val = -E1000_ERR_NVM; 652169240Sjfv goto out; 653169240Sjfv } 654169240Sjfv 655169240Sjfvout: 656169240Sjfv return ret_val; 657169240Sjfv} 658169240Sjfv 659169240Sjfv/** 660169240Sjfv * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum 661169589Sjfv * @hw: pointer to the HW structure 662169240Sjfv * 663169240Sjfv * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 664169240Sjfv * and then verifies that the sum of the EEPROM is equal to 0xBABA. 665169240Sjfv **/ 666177867Sjfvstatic s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) 667169240Sjfv{ 668169240Sjfv DEBUGFUNC("e1000_validate_nvm_checksum_82571"); 669169240Sjfv 670169240Sjfv if (hw->nvm.type == e1000_nvm_flash_hw) 671169240Sjfv e1000_fix_nvm_checksum_82571(hw); 672169240Sjfv 673169240Sjfv return e1000_validate_nvm_checksum_generic(hw); 674169240Sjfv} 675169240Sjfv 676169240Sjfv/** 677169240Sjfv * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon 678169589Sjfv * @hw: pointer to the HW structure 679169589Sjfv * @offset: offset within the EEPROM to be written to 680169589Sjfv * @words: number of words to write 681169589Sjfv * @data: 16 bit word(s) to be written to the EEPROM 682169240Sjfv * 683169240Sjfv * After checking for invalid values, poll the EEPROM to ensure the previous 684169240Sjfv * command has completed before trying to write the next word. After write 685169240Sjfv * poll for completion. 686169240Sjfv * 687169240Sjfv * If e1000_update_nvm_checksum is not called after this function, the 688176667Sjfv * EEPROM will most likely contain an invalid checksum. 689169240Sjfv **/ 690173788Sjfvstatic s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 691173788Sjfv u16 words, u16 *data) 692169240Sjfv{ 693169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 694169240Sjfv u32 i, eewr = 0; 695169240Sjfv s32 ret_val = 0; 696169240Sjfv 697169240Sjfv DEBUGFUNC("e1000_write_nvm_eewr_82571"); 698169240Sjfv 699173788Sjfv /* 700173788Sjfv * A check for invalid values: offset too large, too many words, 701173788Sjfv * and not enough words. 702173788Sjfv */ 703169240Sjfv if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 704169240Sjfv (words == 0)) { 705169240Sjfv DEBUGOUT("nvm parameter(s) out of bounds\n"); 706169240Sjfv ret_val = -E1000_ERR_NVM; 707169240Sjfv goto out; 708169240Sjfv } 709169240Sjfv 710169240Sjfv for (i = 0; i < words; i++) { 711169240Sjfv eewr = (data[i] << E1000_NVM_RW_REG_DATA) | 712169240Sjfv ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | 713169240Sjfv E1000_NVM_RW_REG_START; 714169240Sjfv 715169240Sjfv ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 716169240Sjfv if (ret_val) 717169240Sjfv break; 718169240Sjfv 719169240Sjfv E1000_WRITE_REG(hw, E1000_EEWR, eewr); 720169240Sjfv 721169240Sjfv ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 722169240Sjfv if (ret_val) 723169240Sjfv break; 724169240Sjfv } 725169240Sjfv 726169240Sjfvout: 727169240Sjfv return ret_val; 728169240Sjfv} 729169240Sjfv 730169240Sjfv/** 731169240Sjfv * e1000_get_cfg_done_82571 - Poll for configuration done 732169589Sjfv * @hw: pointer to the HW structure 733169240Sjfv * 734169240Sjfv * Reads the management control register for the config done bit to be set. 735169240Sjfv **/ 736177867Sjfvstatic s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) 737169240Sjfv{ 738169240Sjfv s32 timeout = PHY_CFG_TIMEOUT; 739169240Sjfv s32 ret_val = E1000_SUCCESS; 740169240Sjfv 741169240Sjfv DEBUGFUNC("e1000_get_cfg_done_82571"); 742169240Sjfv 743169240Sjfv while (timeout) { 744169240Sjfv if (E1000_READ_REG(hw, E1000_EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0) 745169240Sjfv break; 746169240Sjfv msec_delay(1); 747169240Sjfv timeout--; 748169240Sjfv } 749169240Sjfv if (!timeout) { 750169240Sjfv DEBUGOUT("MNG configuration cycle has not completed.\n"); 751169240Sjfv ret_val = -E1000_ERR_RESET; 752169240Sjfv goto out; 753169240Sjfv } 754169240Sjfv 755169240Sjfvout: 756169240Sjfv return ret_val; 757169240Sjfv} 758169240Sjfv 759169240Sjfv/** 760169240Sjfv * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state 761169589Sjfv * @hw: pointer to the HW structure 762169589Sjfv * @active: TRUE to enable LPLU, FALSE to disable 763169240Sjfv * 764169240Sjfv * Sets the LPLU D0 state according to the active flag. When activating LPLU 765169240Sjfv * this function also disables smart speed and vice versa. LPLU will not be 766169240Sjfv * activated unless the device autonegotiation advertisement meets standards 767169240Sjfv * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function 768169240Sjfv * pointer entry point only called by PHY setup routines. 769169240Sjfv **/ 770177867Sjfvstatic s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) 771169240Sjfv{ 772169240Sjfv struct e1000_phy_info *phy = &hw->phy; 773177867Sjfv s32 ret_val = E1000_SUCCESS; 774169240Sjfv u16 data; 775169240Sjfv 776169240Sjfv DEBUGFUNC("e1000_set_d0_lplu_state_82571"); 777169240Sjfv 778177867Sjfv if (!(phy->ops.read_reg)) 779177867Sjfv goto out; 780177867Sjfv 781177867Sjfv ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 782169240Sjfv if (ret_val) 783169240Sjfv goto out; 784169240Sjfv 785169240Sjfv if (active) { 786169240Sjfv data |= IGP02E1000_PM_D0_LPLU; 787177867Sjfv ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 788177867Sjfv data); 789169240Sjfv if (ret_val) 790169240Sjfv goto out; 791169240Sjfv 792169240Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 793177867Sjfv ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 794177867Sjfv &data); 795169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 796177867Sjfv ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 797177867Sjfv data); 798169240Sjfv if (ret_val) 799169240Sjfv goto out; 800169240Sjfv } else { 801169240Sjfv data &= ~IGP02E1000_PM_D0_LPLU; 802177867Sjfv ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 803177867Sjfv data); 804173788Sjfv /* 805173788Sjfv * LPLU and SmartSpeed are mutually exclusive. LPLU is used 806169240Sjfv * during Dx states where the power conservation is most 807169240Sjfv * important. During driver activity we should enable 808173788Sjfv * SmartSpeed, so performance is maintained. 809173788Sjfv */ 810169240Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 811177867Sjfv ret_val = phy->ops.read_reg(hw, 812177867Sjfv IGP01E1000_PHY_PORT_CONFIG, 813177867Sjfv &data); 814169240Sjfv if (ret_val) 815169240Sjfv goto out; 816169240Sjfv 817169240Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 818177867Sjfv ret_val = phy->ops.write_reg(hw, 819169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 820169240Sjfv data); 821169240Sjfv if (ret_val) 822169240Sjfv goto out; 823169240Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 824177867Sjfv ret_val = phy->ops.read_reg(hw, 825177867Sjfv IGP01E1000_PHY_PORT_CONFIG, 826177867Sjfv &data); 827169240Sjfv if (ret_val) 828169240Sjfv goto out; 829169240Sjfv 830169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 831177867Sjfv ret_val = phy->ops.write_reg(hw, 832169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 833169240Sjfv data); 834169240Sjfv if (ret_val) 835169240Sjfv goto out; 836169240Sjfv } 837169240Sjfv } 838169240Sjfv 839169240Sjfvout: 840169240Sjfv return ret_val; 841169240Sjfv} 842169240Sjfv 843169240Sjfv/** 844169240Sjfv * e1000_reset_hw_82571 - Reset hardware 845169589Sjfv * @hw: pointer to the HW structure 846169240Sjfv * 847169240Sjfv * This resets the hardware into a known state. This is a 848169240Sjfv * function pointer entry point called by the api module. 849169240Sjfv **/ 850177867Sjfvstatic s32 e1000_reset_hw_82571(struct e1000_hw *hw) 851169240Sjfv{ 852169240Sjfv u32 ctrl, extcnf_ctrl, ctrl_ext, icr; 853169240Sjfv s32 ret_val; 854169240Sjfv u16 i = 0; 855169240Sjfv 856169240Sjfv DEBUGFUNC("e1000_reset_hw_82571"); 857169240Sjfv 858173788Sjfv /* 859173788Sjfv * Prevent the PCI-E bus from sticking if there is no TLP connection 860169240Sjfv * on the last TLP read/write transaction when MAC is reset. 861169240Sjfv */ 862169240Sjfv ret_val = e1000_disable_pcie_master_generic(hw); 863169240Sjfv if (ret_val) { 864169240Sjfv DEBUGOUT("PCI-E Master disable polling has failed.\n"); 865169240Sjfv } 866169240Sjfv 867169240Sjfv DEBUGOUT("Masking off all interrupts\n"); 868169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 869169240Sjfv 870169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 871169240Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 872169240Sjfv E1000_WRITE_FLUSH(hw); 873169240Sjfv 874169240Sjfv msec_delay(10); 875169240Sjfv 876173788Sjfv /* 877173788Sjfv * Must acquire the MDIO ownership before MAC reset. 878173788Sjfv * Ownership defaults to firmware after a reset. 879173788Sjfv */ 880178523Sjfv if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) { 881169240Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 882169240Sjfv extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 883169240Sjfv 884169240Sjfv do { 885169240Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 886169240Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 887169240Sjfv 888169240Sjfv if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 889169240Sjfv break; 890169240Sjfv 891169240Sjfv extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 892169240Sjfv 893169240Sjfv msec_delay(2); 894169240Sjfv i++; 895169240Sjfv } while (i < MDIO_OWNERSHIP_TIMEOUT); 896169240Sjfv } 897169240Sjfv 898169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 899169240Sjfv 900169240Sjfv DEBUGOUT("Issuing a global reset to MAC\n"); 901169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 902169240Sjfv 903169240Sjfv if (hw->nvm.type == e1000_nvm_flash_hw) { 904169240Sjfv usec_delay(10); 905169240Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 906169240Sjfv ctrl_ext |= E1000_CTRL_EXT_EE_RST; 907169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 908169240Sjfv E1000_WRITE_FLUSH(hw); 909169240Sjfv } 910169240Sjfv 911169240Sjfv ret_val = e1000_get_auto_rd_done_generic(hw); 912169240Sjfv if (ret_val) 913169240Sjfv /* We don't want to continue accessing MAC registers. */ 914169240Sjfv goto out; 915169240Sjfv 916173788Sjfv /* 917173788Sjfv * Phy configuration from NVM just starts after EECD_AUTO_RD is set. 918169240Sjfv * Need to wait for Phy configuration completion before accessing 919169240Sjfv * NVM and Phy. 920169240Sjfv */ 921178523Sjfv if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) 922169240Sjfv msec_delay(25); 923169240Sjfv 924169240Sjfv /* Clear any pending interrupt events. */ 925169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 926169240Sjfv icr = E1000_READ_REG(hw, E1000_ICR); 927169240Sjfv 928173788Sjfv if (!(e1000_check_alt_mac_addr_generic(hw))) 929173788Sjfv e1000_set_laa_state_82571(hw, TRUE); 930173788Sjfv 931169240Sjfvout: 932169240Sjfv return ret_val; 933169240Sjfv} 934169240Sjfv 935169240Sjfv/** 936169240Sjfv * e1000_init_hw_82571 - Initialize hardware 937169589Sjfv * @hw: pointer to the HW structure 938169240Sjfv * 939169240Sjfv * This inits the hardware readying it for operation. 940169240Sjfv **/ 941177867Sjfvstatic s32 e1000_init_hw_82571(struct e1000_hw *hw) 942169240Sjfv{ 943169240Sjfv struct e1000_mac_info *mac = &hw->mac; 944169240Sjfv u32 reg_data; 945169240Sjfv s32 ret_val; 946169240Sjfv u16 i, rar_count = mac->rar_entry_count; 947169240Sjfv 948169240Sjfv DEBUGFUNC("e1000_init_hw_82571"); 949169240Sjfv 950169240Sjfv e1000_initialize_hw_bits_82571(hw); 951169240Sjfv 952169240Sjfv /* Initialize identification LED */ 953169240Sjfv ret_val = e1000_id_led_init_generic(hw); 954169240Sjfv if (ret_val) { 955169240Sjfv DEBUGOUT("Error initializing identification LED\n"); 956173788Sjfv /* This is not fatal and we should not stop init due to this */ 957169240Sjfv } 958169240Sjfv 959169240Sjfv /* Disabling VLAN filtering */ 960169240Sjfv DEBUGOUT("Initializing the IEEE VLAN\n"); 961177867Sjfv mac->ops.clear_vfta(hw); 962169240Sjfv 963169240Sjfv /* Setup the receive address. */ 964173788Sjfv /* 965173788Sjfv * If, however, a locally administered address was assigned to the 966169240Sjfv * 82571, we must reserve a RAR for it to work around an issue where 967169240Sjfv * resetting one port will reload the MAC on the other port. 968169240Sjfv */ 969173788Sjfv if (e1000_get_laa_state_82571(hw)) 970169240Sjfv rar_count--; 971169240Sjfv e1000_init_rx_addrs_generic(hw, rar_count); 972169240Sjfv 973169240Sjfv /* Zero out the Multicast HASH table */ 974169240Sjfv DEBUGOUT("Zeroing the MTA\n"); 975169240Sjfv for (i = 0; i < mac->mta_reg_count; i++) 976169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 977169240Sjfv 978169240Sjfv /* Setup link and flow control */ 979177867Sjfv ret_val = mac->ops.setup_link(hw); 980169240Sjfv 981169240Sjfv /* Set the transmit descriptor write-back policy */ 982173788Sjfv reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 983169240Sjfv reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 984169240Sjfv E1000_TXDCTL_FULL_TX_DESC_WB | 985169240Sjfv E1000_TXDCTL_COUNT_DESC; 986173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 987169240Sjfv 988169240Sjfv /* ...for both queues. */ 989178523Sjfv if (mac->type != e1000_82573 && mac->type != e1000_82574) { 990173788Sjfv reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 991169240Sjfv reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 992169240Sjfv E1000_TXDCTL_FULL_TX_DESC_WB | 993169240Sjfv E1000_TXDCTL_COUNT_DESC; 994173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 995169240Sjfv } else { 996181027Sjfv e1000_enable_tx_pkt_filtering_generic(hw); 997169240Sjfv reg_data = E1000_READ_REG(hw, E1000_GCR); 998169240Sjfv reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 999169240Sjfv E1000_WRITE_REG(hw, E1000_GCR, reg_data); 1000169240Sjfv } 1001169240Sjfv 1002173788Sjfv /* 1003173788Sjfv * Clear all of the statistics registers (clear on read). It is 1004169240Sjfv * important that we do this after we have tried to establish link 1005169240Sjfv * because the symbol error count will increment wildly if there 1006169240Sjfv * is no link. 1007169240Sjfv */ 1008169240Sjfv e1000_clear_hw_cntrs_82571(hw); 1009169240Sjfv 1010169240Sjfv return ret_val; 1011169240Sjfv} 1012169240Sjfv 1013169240Sjfv/** 1014169240Sjfv * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits 1015169589Sjfv * @hw: pointer to the HW structure 1016169240Sjfv * 1017169240Sjfv * Initializes required hardware-dependent bits needed for normal operation. 1018169240Sjfv **/ 1019173788Sjfvstatic void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 1020169240Sjfv{ 1021169240Sjfv u32 reg; 1022169240Sjfv 1023169240Sjfv DEBUGFUNC("e1000_initialize_hw_bits_82571"); 1024169240Sjfv 1025169240Sjfv if (hw->mac.disable_hw_init_bits) 1026169240Sjfv goto out; 1027169240Sjfv 1028169240Sjfv /* Transmit Descriptor Control 0 */ 1029173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1030169240Sjfv reg |= (1 << 22); 1031173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 1032169240Sjfv 1033169240Sjfv /* Transmit Descriptor Control 1 */ 1034173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1035169240Sjfv reg |= (1 << 22); 1036173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 1037169240Sjfv 1038169240Sjfv /* Transmit Arbitration Control 0 */ 1039173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(0)); 1040169240Sjfv reg &= ~(0xF << 27); /* 30:27 */ 1041169240Sjfv switch (hw->mac.type) { 1042169240Sjfv case e1000_82571: 1043169240Sjfv case e1000_82572: 1044169240Sjfv reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); 1045169240Sjfv break; 1046169240Sjfv default: 1047169240Sjfv break; 1048169240Sjfv } 1049173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(0), reg); 1050169240Sjfv 1051169240Sjfv /* Transmit Arbitration Control 1 */ 1052173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(1)); 1053169240Sjfv switch (hw->mac.type) { 1054169240Sjfv case e1000_82571: 1055169240Sjfv case e1000_82572: 1056169240Sjfv reg &= ~((1 << 29) | (1 << 30)); 1057169589Sjfv reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); 1058169240Sjfv if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1059169240Sjfv reg &= ~(1 << 28); 1060169240Sjfv else 1061169240Sjfv reg |= (1 << 28); 1062173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(1), reg); 1063169240Sjfv break; 1064169240Sjfv default: 1065169240Sjfv break; 1066169240Sjfv } 1067169240Sjfv 1068169240Sjfv /* Device Control */ 1069178523Sjfv if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) { 1070169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL); 1071169240Sjfv reg &= ~(1 << 29); 1072169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, reg); 1073169240Sjfv } 1074169240Sjfv 1075169240Sjfv /* Extended Device Control */ 1076178523Sjfv if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) { 1077169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1078169240Sjfv reg &= ~(1 << 23); 1079169240Sjfv reg |= (1 << 22); 1080169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1081169240Sjfv } 1082169240Sjfv 1083181027Sjfv /* PCI-Ex Control Register */ 1084181027Sjfv if (hw->mac.type == e1000_82574) { 1085181027Sjfv reg = E1000_READ_REG(hw, E1000_GCR); 1086181027Sjfv reg |= (1 << 22); 1087181027Sjfv E1000_WRITE_REG(hw, E1000_GCR, reg); 1088181027Sjfv } 1089181027Sjfv 1090169240Sjfvout: 1091169240Sjfv return; 1092169240Sjfv} 1093169240Sjfv 1094169240Sjfv/** 1095169240Sjfv * e1000_clear_vfta_82571 - Clear VLAN filter table 1096169589Sjfv * @hw: pointer to the HW structure 1097169240Sjfv * 1098169240Sjfv * Clears the register array which contains the VLAN filter table by 1099169240Sjfv * setting all the values to 0. 1100169240Sjfv **/ 1101177867Sjfvstatic void e1000_clear_vfta_82571(struct e1000_hw *hw) 1102169240Sjfv{ 1103169240Sjfv u32 offset; 1104169240Sjfv u32 vfta_value = 0; 1105169240Sjfv u32 vfta_offset = 0; 1106169240Sjfv u32 vfta_bit_in_reg = 0; 1107169240Sjfv 1108169240Sjfv DEBUGFUNC("e1000_clear_vfta_82571"); 1109169240Sjfv 1110178523Sjfv if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) { 1111169240Sjfv if (hw->mng_cookie.vlan_id != 0) { 1112173788Sjfv /* 1113173788Sjfv * The VFTA is a 4096b bit-field, each identifying 1114169240Sjfv * a single VLAN ID. The following operations 1115169240Sjfv * determine which 32b entry (i.e. offset) into the 1116169240Sjfv * array we want to set the VLAN ID (i.e. bit) of 1117169240Sjfv * the manageability unit. 1118169240Sjfv */ 1119169240Sjfv vfta_offset = (hw->mng_cookie.vlan_id >> 1120169240Sjfv E1000_VFTA_ENTRY_SHIFT) & 1121169240Sjfv E1000_VFTA_ENTRY_MASK; 1122169240Sjfv vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 1123169240Sjfv E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 1124169240Sjfv } 1125169240Sjfv } 1126169240Sjfv for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 1127173788Sjfv /* 1128173788Sjfv * If the offset we want to clear is the same offset of the 1129169240Sjfv * manageability VLAN ID, then clear all bits except that of 1130169240Sjfv * the manageability unit. 1131169240Sjfv */ 1132169240Sjfv vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 1133169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); 1134169240Sjfv E1000_WRITE_FLUSH(hw); 1135169240Sjfv } 1136169240Sjfv} 1137169240Sjfv 1138169240Sjfv/** 1139181027Sjfv * e1000_check_mng_mode_82574 - Check manageability is enabled 1140181027Sjfv * @hw: pointer to the HW structure 1141181027Sjfv * 1142181027Sjfv * Reads the NVM Initialization Control Word 2 and returns TRUE 1143181027Sjfv * (>0) if any manageability is enabled, else FALSE (0). 1144181027Sjfv **/ 1145181027Sjfvstatic bool e1000_check_mng_mode_82574(struct e1000_hw *hw) 1146181027Sjfv{ 1147181027Sjfv u16 data; 1148181027Sjfv 1149181027Sjfv DEBUGFUNC("e1000_check_mng_mode_82574"); 1150181027Sjfv 1151181027Sjfv hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1152181027Sjfv return ((data & E1000_NVM_INIT_CTRL2_MNGM) != 0); 1153181027Sjfv} 1154181027Sjfv 1155181027Sjfv/** 1156181027Sjfv * e1000_led_on_82574 - Turn LED on 1157181027Sjfv * @hw: pointer to the HW structure 1158181027Sjfv * 1159181027Sjfv * Turn LED on. 1160181027Sjfv **/ 1161181027Sjfvstatic s32 e1000_led_on_82574(struct e1000_hw *hw) 1162181027Sjfv{ 1163181027Sjfv u32 ctrl; 1164181027Sjfv u32 i; 1165181027Sjfv 1166181027Sjfv DEBUGFUNC("e1000_led_on_82574"); 1167181027Sjfv 1168181027Sjfv ctrl = hw->mac.ledctl_mode2; 1169181027Sjfv if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) { 1170181027Sjfv /* 1171181027Sjfv * If no link, then turn LED on by setting the invert bit 1172181027Sjfv * for each LED that's "on" (0x0E) in ledctl_mode2. 1173181027Sjfv */ 1174181027Sjfv for (i = 0; i < 4; i++) 1175181027Sjfv if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1176181027Sjfv E1000_LEDCTL_MODE_LED_ON) 1177181027Sjfv ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); 1178181027Sjfv } 1179181027Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl); 1180181027Sjfv 1181181027Sjfv return E1000_SUCCESS; 1182181027Sjfv} 1183181027Sjfv 1184181027Sjfv/** 1185173788Sjfv * e1000_update_mc_addr_list_82571 - Update Multicast addresses 1186169589Sjfv * @hw: pointer to the HW structure 1187169589Sjfv * @mc_addr_list: array of multicast addresses to program 1188169589Sjfv * @mc_addr_count: number of multicast addresses to program 1189169589Sjfv * @rar_used_count: the first RAR register free to program 1190169589Sjfv * @rar_count: total number of supported Receive Address Registers 1191169240Sjfv * 1192169240Sjfv * Updates the Receive Address Registers and Multicast Table Array. 1193169240Sjfv * The caller must have a packed mc_addr_list of multicast addresses. 1194169240Sjfv * The parameter rar_count will usually be hw->mac.rar_entry_count 1195169240Sjfv * unless there are workarounds that change this. 1196169240Sjfv **/ 1197177867Sjfvstatic void e1000_update_mc_addr_list_82571(struct e1000_hw *hw, 1198176667Sjfv u8 *mc_addr_list, u32 mc_addr_count, 1199176667Sjfv u32 rar_used_count, u32 rar_count) 1200169240Sjfv{ 1201173788Sjfv DEBUGFUNC("e1000_update_mc_addr_list_82571"); 1202169240Sjfv 1203169240Sjfv if (e1000_get_laa_state_82571(hw)) 1204169240Sjfv rar_count--; 1205169240Sjfv 1206173788Sjfv e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count, 1207169240Sjfv rar_used_count, rar_count); 1208169240Sjfv} 1209169240Sjfv 1210169240Sjfv/** 1211169240Sjfv * e1000_setup_link_82571 - Setup flow control and link settings 1212169589Sjfv * @hw: pointer to the HW structure 1213169240Sjfv * 1214169240Sjfv * Determines which flow control settings to use, then configures flow 1215169240Sjfv * control. Calls the appropriate media-specific link configuration 1216169240Sjfv * function. Assuming the adapter has a valid link partner, a valid link 1217169240Sjfv * should be established. Assumes the hardware has previously been reset 1218169240Sjfv * and the transmitter and receiver are not enabled. 1219169240Sjfv **/ 1220177867Sjfvstatic s32 e1000_setup_link_82571(struct e1000_hw *hw) 1221169240Sjfv{ 1222169240Sjfv DEBUGFUNC("e1000_setup_link_82571"); 1223169240Sjfv 1224173788Sjfv /* 1225173788Sjfv * 82573 does not have a word in the NVM to determine 1226169240Sjfv * the default flow control setting, so we explicitly 1227169240Sjfv * set it to full. 1228169240Sjfv */ 1229178523Sjfv if ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) && 1230178523Sjfv hw->fc.type == e1000_fc_default) 1231173788Sjfv hw->fc.type = e1000_fc_full; 1232169240Sjfv 1233169240Sjfv return e1000_setup_link_generic(hw); 1234169240Sjfv} 1235169240Sjfv 1236169240Sjfv/** 1237169240Sjfv * e1000_setup_copper_link_82571 - Configure copper link settings 1238169589Sjfv * @hw: pointer to the HW structure 1239169240Sjfv * 1240169240Sjfv * Configures the link for auto-neg or forced speed and duplex. Then we check 1241169240Sjfv * for link, once link is established calls to configure collision distance 1242169240Sjfv * and flow control are called. 1243169240Sjfv **/ 1244177867Sjfvstatic s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) 1245169240Sjfv{ 1246169240Sjfv u32 ctrl, led_ctrl; 1247169240Sjfv s32 ret_val; 1248169240Sjfv 1249169240Sjfv DEBUGFUNC("e1000_setup_copper_link_82571"); 1250169240Sjfv 1251169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1252169240Sjfv ctrl |= E1000_CTRL_SLU; 1253169240Sjfv ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1254169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1255169240Sjfv 1256169240Sjfv switch (hw->phy.type) { 1257169240Sjfv case e1000_phy_m88: 1258176667Sjfv case e1000_phy_bm: 1259169240Sjfv ret_val = e1000_copper_link_setup_m88(hw); 1260169240Sjfv break; 1261169240Sjfv case e1000_phy_igp_2: 1262169240Sjfv ret_val = e1000_copper_link_setup_igp(hw); 1263169240Sjfv /* Setup activity LED */ 1264169240Sjfv led_ctrl = E1000_READ_REG(hw, E1000_LEDCTL); 1265169240Sjfv led_ctrl &= IGP_ACTIVITY_LED_MASK; 1266169240Sjfv led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1267169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, led_ctrl); 1268169240Sjfv break; 1269169240Sjfv default: 1270169240Sjfv ret_val = -E1000_ERR_PHY; 1271169240Sjfv break; 1272169240Sjfv } 1273169240Sjfv 1274169240Sjfv if (ret_val) 1275169240Sjfv goto out; 1276169240Sjfv 1277169240Sjfv ret_val = e1000_setup_copper_link_generic(hw); 1278169240Sjfv 1279169240Sjfvout: 1280169240Sjfv return ret_val; 1281169240Sjfv} 1282169240Sjfv 1283169240Sjfv/** 1284169240Sjfv * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes 1285169589Sjfv * @hw: pointer to the HW structure 1286169240Sjfv * 1287169240Sjfv * Configures collision distance and flow control for fiber and serdes links. 1288169240Sjfv * Upon successful setup, poll for link. 1289169240Sjfv **/ 1290177867Sjfvstatic s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) 1291169240Sjfv{ 1292169240Sjfv DEBUGFUNC("e1000_setup_fiber_serdes_link_82571"); 1293169240Sjfv 1294169240Sjfv switch (hw->mac.type) { 1295169240Sjfv case e1000_82571: 1296169240Sjfv case e1000_82572: 1297173788Sjfv /* 1298173788Sjfv * If SerDes loopback mode is entered, there is no form 1299169240Sjfv * of reset to take the adapter out of that mode. So we 1300169240Sjfv * have to explicitly take the adapter out of loopback 1301176667Sjfv * mode. This prevents drivers from twiddling their thumbs 1302169240Sjfv * if another tool failed to take it out of loopback mode. 1303169240Sjfv */ 1304169240Sjfv E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1305169240Sjfv break; 1306169240Sjfv default: 1307169240Sjfv break; 1308169240Sjfv } 1309169240Sjfv 1310169240Sjfv return e1000_setup_fiber_serdes_link_generic(hw); 1311169240Sjfv} 1312169240Sjfv 1313169240Sjfv/** 1314169240Sjfv * e1000_valid_led_default_82571 - Verify a valid default LED config 1315169589Sjfv * @hw: pointer to the HW structure 1316169589Sjfv * @data: pointer to the NVM (EEPROM) 1317169240Sjfv * 1318169240Sjfv * Read the EEPROM for the current default LED configuration. If the 1319169240Sjfv * LED configuration is not valid, set to a valid LED configuration. 1320169240Sjfv **/ 1321177867Sjfvstatic s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) 1322169240Sjfv{ 1323169240Sjfv s32 ret_val; 1324169240Sjfv 1325169240Sjfv DEBUGFUNC("e1000_valid_led_default_82571"); 1326169240Sjfv 1327177867Sjfv ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1328169240Sjfv if (ret_val) { 1329169240Sjfv DEBUGOUT("NVM Read Error\n"); 1330169240Sjfv goto out; 1331169240Sjfv } 1332169240Sjfv 1333178523Sjfv if ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) && 1334169240Sjfv *data == ID_LED_RESERVED_F746) 1335169240Sjfv *data = ID_LED_DEFAULT_82573; 1336178523Sjfv else if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1337169240Sjfv *data = ID_LED_DEFAULT; 1338169240Sjfvout: 1339169240Sjfv return ret_val; 1340169240Sjfv} 1341169240Sjfv 1342169240Sjfv/** 1343169240Sjfv * e1000_get_laa_state_82571 - Get locally administered address state 1344169589Sjfv * @hw: pointer to the HW structure 1345169240Sjfv * 1346176667Sjfv * Retrieve and return the current locally administered address state. 1347169240Sjfv **/ 1348173788Sjfvbool e1000_get_laa_state_82571(struct e1000_hw *hw) 1349169240Sjfv{ 1350169240Sjfv struct e1000_dev_spec_82571 *dev_spec; 1351173788Sjfv bool state = FALSE; 1352169240Sjfv 1353169240Sjfv DEBUGFUNC("e1000_get_laa_state_82571"); 1354169240Sjfv 1355169240Sjfv if (hw->mac.type != e1000_82571) 1356169240Sjfv goto out; 1357169240Sjfv 1358169240Sjfv dev_spec = (struct e1000_dev_spec_82571 *)hw->dev_spec; 1359169240Sjfv 1360169240Sjfv state = dev_spec->laa_is_present; 1361169240Sjfv 1362169240Sjfvout: 1363169240Sjfv return state; 1364169240Sjfv} 1365169240Sjfv 1366169240Sjfv/** 1367169240Sjfv * e1000_set_laa_state_82571 - Set locally administered address state 1368169589Sjfv * @hw: pointer to the HW structure 1369169589Sjfv * @state: enable/disable locally administered address 1370169240Sjfv * 1371176667Sjfv * Enable/Disable the current locally administered address state. 1372169240Sjfv **/ 1373173788Sjfvvoid e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) 1374169240Sjfv{ 1375169240Sjfv struct e1000_dev_spec_82571 *dev_spec; 1376169240Sjfv 1377169240Sjfv DEBUGFUNC("e1000_set_laa_state_82571"); 1378169240Sjfv 1379169240Sjfv if (hw->mac.type != e1000_82571) 1380169240Sjfv goto out; 1381169240Sjfv 1382169240Sjfv dev_spec = (struct e1000_dev_spec_82571 *)hw->dev_spec; 1383169240Sjfv 1384169240Sjfv dev_spec->laa_is_present = state; 1385169240Sjfv 1386169240Sjfv /* If workaround is activated... */ 1387173788Sjfv if (state) { 1388173788Sjfv /* 1389173788Sjfv * Hold a copy of the LAA in RAR[14] This is done so that 1390169240Sjfv * between the time RAR[0] gets clobbered and the time it 1391169240Sjfv * gets fixed, the actual LAA is in one of the RARs and no 1392169240Sjfv * incoming packets directed to this port are dropped. 1393169240Sjfv * Eventually the LAA will be in RAR[0] and RAR[14]. 1394169240Sjfv */ 1395169240Sjfv e1000_rar_set_generic(hw, hw->mac.addr, 1396169240Sjfv hw->mac.rar_entry_count - 1); 1397169240Sjfv } 1398169240Sjfv 1399169240Sjfvout: 1400169240Sjfv return; 1401169240Sjfv} 1402169240Sjfv 1403169240Sjfv/** 1404169240Sjfv * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum 1405169589Sjfv * @hw: pointer to the HW structure 1406169240Sjfv * 1407169240Sjfv * Verifies that the EEPROM has completed the update. After updating the 1408169240Sjfv * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If 1409169240Sjfv * the checksum fix is not implemented, we need to set the bit and update 1410169240Sjfv * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, 1411169240Sjfv * we need to return bad checksum. 1412169240Sjfv **/ 1413173788Sjfvstatic s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 1414169240Sjfv{ 1415169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 1416169240Sjfv s32 ret_val = E1000_SUCCESS; 1417169240Sjfv u16 data; 1418169240Sjfv 1419169240Sjfv DEBUGFUNC("e1000_fix_nvm_checksum_82571"); 1420169240Sjfv 1421169240Sjfv if (nvm->type != e1000_nvm_flash_hw) 1422169240Sjfv goto out; 1423169240Sjfv 1424173788Sjfv /* 1425173788Sjfv * Check bit 4 of word 10h. If it is 0, firmware is done updating 1426169240Sjfv * 10h-12h. Checksum may need to be fixed. 1427169240Sjfv */ 1428177867Sjfv ret_val = nvm->ops.read(hw, 0x10, 1, &data); 1429169240Sjfv if (ret_val) 1430169240Sjfv goto out; 1431169240Sjfv 1432169240Sjfv if (!(data & 0x10)) { 1433173788Sjfv /* 1434173788Sjfv * Read 0x23 and check bit 15. This bit is a 1 1435169240Sjfv * when the checksum has already been fixed. If 1436169240Sjfv * the checksum is still wrong and this bit is a 1437169240Sjfv * 1, we need to return bad checksum. Otherwise, 1438169240Sjfv * we need to set this bit to a 1 and update the 1439169240Sjfv * checksum. 1440169240Sjfv */ 1441177867Sjfv ret_val = nvm->ops.read(hw, 0x23, 1, &data); 1442169240Sjfv if (ret_val) 1443169240Sjfv goto out; 1444169240Sjfv 1445169240Sjfv if (!(data & 0x8000)) { 1446169240Sjfv data |= 0x8000; 1447177867Sjfv ret_val = nvm->ops.write(hw, 0x23, 1, &data); 1448169240Sjfv if (ret_val) 1449169240Sjfv goto out; 1450177867Sjfv ret_val = nvm->ops.update(hw); 1451169240Sjfv } 1452169240Sjfv } 1453169240Sjfv 1454169240Sjfvout: 1455169240Sjfv return ret_val; 1456169240Sjfv} 1457169240Sjfv 1458169240Sjfv/** 1459173788Sjfv * e1000_read_mac_addr_82571 - Read device MAC address 1460173788Sjfv * @hw: pointer to the HW structure 1461173788Sjfv **/ 1462177867Sjfvstatic s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) 1463173788Sjfv{ 1464173788Sjfv s32 ret_val = E1000_SUCCESS; 1465173788Sjfv 1466173788Sjfv DEBUGFUNC("e1000_read_mac_addr_82571"); 1467173788Sjfv if (e1000_check_alt_mac_addr_generic(hw)) 1468173788Sjfv ret_val = e1000_read_mac_addr_generic(hw); 1469173788Sjfv 1470173788Sjfv return ret_val; 1471173788Sjfv} 1472173788Sjfv 1473173788Sjfv/** 1474173788Sjfv * e1000_power_down_phy_copper_82571 - Remove link during PHY power down 1475173788Sjfv * @hw: pointer to the HW structure 1476173788Sjfv * 1477173788Sjfv * In the case of a PHY power down to save power, or to turn off link during a 1478173788Sjfv * driver unload, or wake on lan is not enabled, remove the link. 1479173788Sjfv **/ 1480177867Sjfvstatic void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) 1481173788Sjfv{ 1482177867Sjfv struct e1000_phy_info *phy = &hw->phy; 1483177867Sjfv struct e1000_mac_info *mac = &hw->mac; 1484177867Sjfv 1485177867Sjfv if (!(phy->ops.check_reset_block)) 1486177867Sjfv return; 1487177867Sjfv 1488173788Sjfv /* If the management interface is not enabled, then power down */ 1489177867Sjfv if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 1490173788Sjfv e1000_power_down_phy_copper(hw); 1491173788Sjfv 1492173788Sjfv return; 1493173788Sjfv} 1494173788Sjfv 1495173788Sjfv/** 1496169240Sjfv * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters 1497169589Sjfv * @hw: pointer to the HW structure 1498169240Sjfv * 1499169240Sjfv * Clears the hardware counters by reading the counter registers. 1500169240Sjfv **/ 1501177867Sjfvstatic void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) 1502169240Sjfv{ 1503169240Sjfv volatile u32 temp; 1504169240Sjfv 1505169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_82571"); 1506169240Sjfv 1507169240Sjfv e1000_clear_hw_cntrs_base_generic(hw); 1508169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC64); 1509169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC127); 1510169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC255); 1511169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC511); 1512169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC1023); 1513169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC1522); 1514169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC64); 1515169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC127); 1516169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC255); 1517169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC511); 1518169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC1023); 1519169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC1522); 1520169240Sjfv 1521169240Sjfv temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1522169240Sjfv temp = E1000_READ_REG(hw, E1000_RXERRC); 1523169240Sjfv temp = E1000_READ_REG(hw, E1000_TNCRS); 1524169240Sjfv temp = E1000_READ_REG(hw, E1000_CEXTERR); 1525169240Sjfv temp = E1000_READ_REG(hw, E1000_TSCTC); 1526169240Sjfv temp = E1000_READ_REG(hw, E1000_TSCTFC); 1527169240Sjfv 1528169240Sjfv temp = E1000_READ_REG(hw, E1000_MGTPRC); 1529169240Sjfv temp = E1000_READ_REG(hw, E1000_MGTPDC); 1530169240Sjfv temp = E1000_READ_REG(hw, E1000_MGTPTC); 1531169240Sjfv 1532169240Sjfv temp = E1000_READ_REG(hw, E1000_IAC); 1533169240Sjfv temp = E1000_READ_REG(hw, E1000_ICRXOC); 1534169240Sjfv 1535169240Sjfv temp = E1000_READ_REG(hw, E1000_ICRXPTC); 1536169240Sjfv temp = E1000_READ_REG(hw, E1000_ICRXATC); 1537169240Sjfv temp = E1000_READ_REG(hw, E1000_ICTXPTC); 1538169240Sjfv temp = E1000_READ_REG(hw, E1000_ICTXATC); 1539169240Sjfv temp = E1000_READ_REG(hw, E1000_ICTXQEC); 1540169240Sjfv temp = E1000_READ_REG(hw, E1000_ICTXQMTC); 1541169240Sjfv temp = E1000_READ_REG(hw, E1000_ICRXDMTC); 1542169240Sjfv} 1543