e1000_82571.c revision 178523
1177867Sjfv/****************************************************************************** 2169240Sjfv 3176667Sjfv Copyright (c) 2001-2008, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD: head/sys/dev/em/e1000_82571.c 178523 2008-04-25 21:19:41Z jfv $*/ 34169240Sjfv 35169240Sjfv/* e1000_82571 36169240Sjfv * e1000_82572 37169240Sjfv * e1000_82573 38173788Sjfv * e1000_82574 39169240Sjfv */ 40169240Sjfv 41169589Sjfv#include "e1000_api.h" 42169240Sjfv#include "e1000_82571.h" 43169240Sjfv 44177867Sjfvstatic s32 e1000_init_phy_params_82571(struct e1000_hw *hw); 45177867Sjfvstatic s32 e1000_init_nvm_params_82571(struct e1000_hw *hw); 46177867Sjfvstatic s32 e1000_init_mac_params_82571(struct e1000_hw *hw); 47177867Sjfvstatic s32 e1000_acquire_nvm_82571(struct e1000_hw *hw); 48177867Sjfvstatic void e1000_release_nvm_82571(struct e1000_hw *hw); 49177867Sjfvstatic s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, 50169240Sjfv u16 words, u16 *data); 51177867Sjfvstatic s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw); 52177867Sjfvstatic s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw); 53177867Sjfvstatic s32 e1000_get_cfg_done_82571(struct e1000_hw *hw); 54177867Sjfvstatic s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, 55173788Sjfv bool active); 56177867Sjfvstatic s32 e1000_reset_hw_82571(struct e1000_hw *hw); 57177867Sjfvstatic s32 e1000_init_hw_82571(struct e1000_hw *hw); 58177867Sjfvstatic void e1000_clear_vfta_82571(struct e1000_hw *hw); 59177867Sjfvstatic void e1000_update_mc_addr_list_82571(struct e1000_hw *hw, 60176667Sjfv u8 *mc_addr_list, u32 mc_addr_count, 61176667Sjfv u32 rar_used_count, u32 rar_count); 62177867Sjfvstatic s32 e1000_setup_link_82571(struct e1000_hw *hw); 63177867Sjfvstatic s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); 64177867Sjfvstatic s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); 65177867Sjfvstatic s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data); 66177867Sjfvstatic void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); 67169589Sjfvstatic s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw); 68169240Sjfvstatic s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); 69169240Sjfvstatic s32 e1000_get_phy_id_82571(struct e1000_hw *hw); 70169589Sjfvstatic void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); 71169240Sjfvstatic void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); 72169240Sjfvstatic s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 73169240Sjfv u16 words, u16 *data); 74177867Sjfvstatic s32 e1000_read_mac_addr_82571(struct e1000_hw *hw); 75177867Sjfvstatic void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); 76169240Sjfv 77169240Sjfvstruct e1000_dev_spec_82571 { 78173788Sjfv bool laa_is_present; 79169240Sjfv}; 80169240Sjfv 81169240Sjfv/** 82169240Sjfv * e1000_init_phy_params_82571 - Init PHY func ptrs. 83169589Sjfv * @hw: pointer to the HW structure 84169240Sjfv * 85169240Sjfv * This is a function pointer entry point called by the api module. 86169240Sjfv **/ 87177867Sjfvstatic s32 e1000_init_phy_params_82571(struct e1000_hw *hw) 88169240Sjfv{ 89169240Sjfv struct e1000_phy_info *phy = &hw->phy; 90169240Sjfv s32 ret_val = E1000_SUCCESS; 91169240Sjfv 92169240Sjfv DEBUGFUNC("e1000_init_phy_params_82571"); 93169240Sjfv 94173788Sjfv if (hw->phy.media_type != e1000_media_type_copper) { 95169240Sjfv phy->type = e1000_phy_none; 96169240Sjfv goto out; 97169240Sjfv } 98169240Sjfv 99169240Sjfv phy->addr = 1; 100169240Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 101169240Sjfv phy->reset_delay_us = 100; 102169240Sjfv 103177867Sjfv phy->ops.acquire = e1000_get_hw_semaphore_82571; 104177867Sjfv phy->ops.check_polarity = e1000_check_polarity_igp; 105177867Sjfv phy->ops.check_reset_block = e1000_check_reset_block_generic; 106177867Sjfv phy->ops.release = e1000_put_hw_semaphore_82571; 107177867Sjfv phy->ops.reset = e1000_phy_hw_reset_generic; 108177867Sjfv phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571; 109177867Sjfv phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 110177867Sjfv phy->ops.power_up = e1000_power_up_phy_copper; 111177867Sjfv phy->ops.power_down = e1000_power_down_phy_copper_82571; 112169240Sjfv 113169240Sjfv switch (hw->mac.type) { 114169240Sjfv case e1000_82571: 115169240Sjfv case e1000_82572: 116177867Sjfv phy->type = e1000_phy_igp_2; 117177867Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_82571; 118177867Sjfv phy->ops.get_info = e1000_get_phy_info_igp; 119177867Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 120177867Sjfv phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 121177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_igp; 122177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_igp; 123173788Sjfv 124173788Sjfv /* This uses above function pointers */ 125173788Sjfv ret_val = e1000_get_phy_id_82571(hw); 126173788Sjfv 127173788Sjfv /* Verify PHY ID */ 128173788Sjfv if (phy->id != IGP01E1000_I_PHY_ID) { 129173788Sjfv ret_val = -E1000_ERR_PHY; 130173788Sjfv goto out; 131173788Sjfv } 132169240Sjfv break; 133169240Sjfv case e1000_82573: 134177867Sjfv phy->type = e1000_phy_m88; 135177867Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 136177867Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 137177867Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 138177867Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 139177867Sjfv phy->ops.get_cable_length = e1000_get_cable_length_m88; 140177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_m88; 141177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_m88; 142169240Sjfv 143173788Sjfv /* This uses above function pointers */ 144173788Sjfv ret_val = e1000_get_phy_id_82571(hw); 145169240Sjfv 146173788Sjfv /* Verify PHY ID */ 147169240Sjfv if (phy->id != M88E1111_I_PHY_ID) { 148169240Sjfv ret_val = -E1000_ERR_PHY; 149173788Sjfv DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 150169240Sjfv goto out; 151169240Sjfv } 152169240Sjfv break; 153178523Sjfv case e1000_82574: 154178523Sjfv phy->type = e1000_phy_bm; 155178523Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 156178523Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 157178523Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 158178523Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 159178523Sjfv phy->ops.get_cable_length = e1000_get_cable_length_m88; 160178523Sjfv phy->ops.read_reg = e1000_read_phy_reg_bm2; 161178523Sjfv phy->ops.write_reg = e1000_write_phy_reg_bm2; 162178523Sjfv 163178523Sjfv /* This uses above function pointers */ 164178523Sjfv ret_val = e1000_get_phy_id_82571(hw); 165178523Sjfv /* Verify PHY ID */ 166178523Sjfv if (phy->id != BME1000_E_PHY_ID_R2) { 167178523Sjfv ret_val = -E1000_ERR_PHY; 168178523Sjfv DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 169178523Sjfv goto out; 170178523Sjfv } 171178523Sjfv break; 172169240Sjfv default: 173169240Sjfv ret_val = -E1000_ERR_PHY; 174169240Sjfv goto out; 175169240Sjfv break; 176169240Sjfv } 177169240Sjfv 178169240Sjfvout: 179169240Sjfv return ret_val; 180169240Sjfv} 181169240Sjfv 182169240Sjfv/** 183169240Sjfv * e1000_init_nvm_params_82571 - Init NVM func ptrs. 184169589Sjfv * @hw: pointer to the HW structure 185169240Sjfv * 186169240Sjfv * This is a function pointer entry point called by the api module. 187169240Sjfv **/ 188177867Sjfvstatic s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) 189169240Sjfv{ 190169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 191169240Sjfv u32 eecd = E1000_READ_REG(hw, E1000_EECD); 192169240Sjfv u16 size; 193169240Sjfv 194169240Sjfv DEBUGFUNC("e1000_init_nvm_params_82571"); 195169240Sjfv 196169240Sjfv nvm->opcode_bits = 8; 197169240Sjfv nvm->delay_usec = 1; 198169240Sjfv switch (nvm->override) { 199169240Sjfv case e1000_nvm_override_spi_large: 200169240Sjfv nvm->page_size = 32; 201169240Sjfv nvm->address_bits = 16; 202169240Sjfv break; 203169240Sjfv case e1000_nvm_override_spi_small: 204169240Sjfv nvm->page_size = 8; 205169240Sjfv nvm->address_bits = 8; 206169240Sjfv break; 207169240Sjfv default: 208169240Sjfv nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 209169240Sjfv nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 210169240Sjfv break; 211169240Sjfv } 212169240Sjfv 213169240Sjfv switch (hw->mac.type) { 214169240Sjfv case e1000_82573: 215178523Sjfv case e1000_82574: 216169240Sjfv if (((eecd >> 15) & 0x3) == 0x3) { 217169240Sjfv nvm->type = e1000_nvm_flash_hw; 218169240Sjfv nvm->word_size = 2048; 219173788Sjfv /* 220173788Sjfv * Autonomous Flash update bit must be cleared due 221169240Sjfv * to Flash update issue. 222169240Sjfv */ 223169240Sjfv eecd &= ~E1000_EECD_AUPDEN; 224169240Sjfv E1000_WRITE_REG(hw, E1000_EECD, eecd); 225169240Sjfv break; 226169240Sjfv } 227169240Sjfv /* Fall Through */ 228169240Sjfv default: 229169240Sjfv nvm->type = e1000_nvm_eeprom_spi; 230169240Sjfv size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 231169240Sjfv E1000_EECD_SIZE_EX_SHIFT); 232173788Sjfv /* 233173788Sjfv * Added to a constant, "size" becomes the left-shift value 234169240Sjfv * for setting word_size. 235169240Sjfv */ 236169240Sjfv size += NVM_WORD_SIZE_BASE_SHIFT; 237173788Sjfv 238173788Sjfv /* EEPROM access above 16k is unsupported */ 239173788Sjfv if (size > 14) 240173788Sjfv size = 14; 241169240Sjfv nvm->word_size = 1 << size; 242169240Sjfv break; 243169240Sjfv } 244169240Sjfv 245169240Sjfv /* Function Pointers */ 246177867Sjfv nvm->ops.acquire = e1000_acquire_nvm_82571; 247177867Sjfv nvm->ops.read = e1000_read_nvm_eerd; 248177867Sjfv nvm->ops.release = e1000_release_nvm_82571; 249177867Sjfv nvm->ops.update = e1000_update_nvm_checksum_82571; 250177867Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_82571; 251177867Sjfv nvm->ops.valid_led_default = e1000_valid_led_default_82571; 252177867Sjfv nvm->ops.write = e1000_write_nvm_82571; 253169240Sjfv 254169240Sjfv return E1000_SUCCESS; 255169240Sjfv} 256169240Sjfv 257169240Sjfv/** 258169240Sjfv * e1000_init_mac_params_82571 - Init MAC func ptrs. 259169589Sjfv * @hw: pointer to the HW structure 260169240Sjfv * 261169240Sjfv * This is a function pointer entry point called by the api module. 262169240Sjfv **/ 263177867Sjfvstatic s32 e1000_init_mac_params_82571(struct e1000_hw *hw) 264169240Sjfv{ 265169240Sjfv struct e1000_mac_info *mac = &hw->mac; 266169240Sjfv s32 ret_val = E1000_SUCCESS; 267169240Sjfv 268169240Sjfv DEBUGFUNC("e1000_init_mac_params_82571"); 269169240Sjfv 270169240Sjfv /* Set media type */ 271169240Sjfv switch (hw->device_id) { 272169240Sjfv case E1000_DEV_ID_82571EB_FIBER: 273169240Sjfv case E1000_DEV_ID_82572EI_FIBER: 274169240Sjfv case E1000_DEV_ID_82571EB_QUAD_FIBER: 275173788Sjfv hw->phy.media_type = e1000_media_type_fiber; 276169240Sjfv break; 277169240Sjfv case E1000_DEV_ID_82571EB_SERDES: 278169589Sjfv case E1000_DEV_ID_82571EB_SERDES_DUAL: 279169589Sjfv case E1000_DEV_ID_82571EB_SERDES_QUAD: 280169240Sjfv case E1000_DEV_ID_82572EI_SERDES: 281173788Sjfv hw->phy.media_type = e1000_media_type_internal_serdes; 282169240Sjfv break; 283169240Sjfv default: 284173788Sjfv hw->phy.media_type = e1000_media_type_copper; 285169240Sjfv break; 286169240Sjfv } 287169240Sjfv 288169240Sjfv /* Set mta register count */ 289169240Sjfv mac->mta_reg_count = 128; 290169240Sjfv /* Set rar entry count */ 291169240Sjfv mac->rar_entry_count = E1000_RAR_ENTRIES; 292169240Sjfv /* Set if part includes ASF firmware */ 293169240Sjfv mac->asf_firmware_present = TRUE; 294169240Sjfv /* Set if manageability features are enabled. */ 295169240Sjfv mac->arc_subsystem_valid = 296169240Sjfv (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 297169240Sjfv ? TRUE : FALSE; 298169240Sjfv 299169240Sjfv /* Function pointers */ 300169240Sjfv 301169240Sjfv /* bus type/speed/width */ 302177867Sjfv mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 303169240Sjfv /* reset */ 304177867Sjfv mac->ops.reset_hw = e1000_reset_hw_82571; 305169240Sjfv /* hw initialization */ 306177867Sjfv mac->ops.init_hw = e1000_init_hw_82571; 307169240Sjfv /* link setup */ 308177867Sjfv mac->ops.setup_link = e1000_setup_link_82571; 309169240Sjfv /* physical interface link setup */ 310177867Sjfv mac->ops.setup_physical_interface = 311173788Sjfv (hw->phy.media_type == e1000_media_type_copper) 312169240Sjfv ? e1000_setup_copper_link_82571 313169240Sjfv : e1000_setup_fiber_serdes_link_82571; 314169240Sjfv /* check for link */ 315173788Sjfv switch (hw->phy.media_type) { 316169240Sjfv case e1000_media_type_copper: 317177867Sjfv mac->ops.check_for_link = e1000_check_for_copper_link_generic; 318169240Sjfv break; 319169240Sjfv case e1000_media_type_fiber: 320177867Sjfv mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 321169240Sjfv break; 322169240Sjfv case e1000_media_type_internal_serdes: 323177867Sjfv mac->ops.check_for_link = e1000_check_for_serdes_link_generic; 324169240Sjfv break; 325169240Sjfv default: 326169240Sjfv ret_val = -E1000_ERR_CONFIG; 327169240Sjfv goto out; 328169240Sjfv break; 329169240Sjfv } 330169240Sjfv /* check management mode */ 331177867Sjfv mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 332169240Sjfv /* multicast address update */ 333177867Sjfv mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_82571; 334169240Sjfv /* writing VFTA */ 335177867Sjfv mac->ops.write_vfta = e1000_write_vfta_generic; 336169240Sjfv /* clearing VFTA */ 337177867Sjfv mac->ops.clear_vfta = e1000_clear_vfta_82571; 338169240Sjfv /* setting MTA */ 339177867Sjfv mac->ops.mta_set = e1000_mta_set_generic; 340173788Sjfv /* read mac address */ 341177867Sjfv mac->ops.read_mac_addr = e1000_read_mac_addr_82571; 342169240Sjfv /* blink LED */ 343177867Sjfv mac->ops.blink_led = e1000_blink_led_generic; 344169240Sjfv /* setup LED */ 345177867Sjfv mac->ops.setup_led = e1000_setup_led_generic; 346169240Sjfv /* cleanup LED */ 347177867Sjfv mac->ops.cleanup_led = e1000_cleanup_led_generic; 348169240Sjfv /* turn on/off LED */ 349177867Sjfv mac->ops.led_on = e1000_led_on_generic; 350177867Sjfv mac->ops.led_off = e1000_led_off_generic; 351169240Sjfv /* remove device */ 352177867Sjfv mac->ops.remove_device = e1000_remove_device_generic; 353169240Sjfv /* clear hardware counters */ 354177867Sjfv mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571; 355169240Sjfv /* link info */ 356177867Sjfv mac->ops.get_link_up_info = 357173788Sjfv (hw->phy.media_type == e1000_media_type_copper) 358169240Sjfv ? e1000_get_speed_and_duplex_copper_generic 359169240Sjfv : e1000_get_speed_and_duplex_fiber_serdes_generic; 360169240Sjfv 361169240Sjfv hw->dev_spec_size = sizeof(struct e1000_dev_spec_82571); 362169240Sjfv 363169240Sjfv /* Device-specific structure allocation */ 364169240Sjfv ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 365169240Sjfv 366169240Sjfvout: 367169240Sjfv return ret_val; 368169240Sjfv} 369169240Sjfv 370169240Sjfv/** 371169240Sjfv * e1000_init_function_pointers_82571 - Init func ptrs. 372169589Sjfv * @hw: pointer to the HW structure 373169240Sjfv * 374169240Sjfv * The only function explicitly called by the api module to initialize 375169240Sjfv * all function pointers and parameters. 376169240Sjfv **/ 377173788Sjfvvoid e1000_init_function_pointers_82571(struct e1000_hw *hw) 378169240Sjfv{ 379169240Sjfv DEBUGFUNC("e1000_init_function_pointers_82571"); 380169240Sjfv 381177867Sjfv hw->mac.ops.init_params = e1000_init_mac_params_82571; 382177867Sjfv hw->nvm.ops.init_params = e1000_init_nvm_params_82571; 383177867Sjfv hw->phy.ops.init_params = e1000_init_phy_params_82571; 384169240Sjfv} 385169240Sjfv 386169240Sjfv/** 387169240Sjfv * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision 388169589Sjfv * @hw: pointer to the HW structure 389169240Sjfv * 390169240Sjfv * Reads the PHY registers and stores the PHY ID and possibly the PHY 391169240Sjfv * revision in the hardware structure. 392169240Sjfv **/ 393173788Sjfvstatic s32 e1000_get_phy_id_82571(struct e1000_hw *hw) 394169240Sjfv{ 395169240Sjfv struct e1000_phy_info *phy = &hw->phy; 396169240Sjfv s32 ret_val = E1000_SUCCESS; 397178523Sjfv u16 phy_id = 0; 398169240Sjfv 399169240Sjfv DEBUGFUNC("e1000_get_phy_id_82571"); 400169240Sjfv 401169240Sjfv switch (hw->mac.type) { 402169240Sjfv case e1000_82571: 403169240Sjfv case e1000_82572: 404173788Sjfv /* 405173788Sjfv * The 82571 firmware may still be configuring the PHY. 406169240Sjfv * In this case, we cannot access the PHY until the 407169240Sjfv * configuration is done. So we explicitly set the 408173788Sjfv * PHY ID. 409173788Sjfv */ 410169240Sjfv phy->id = IGP01E1000_I_PHY_ID; 411169240Sjfv break; 412169240Sjfv case e1000_82573: 413169240Sjfv ret_val = e1000_get_phy_id(hw); 414169240Sjfv break; 415178523Sjfv case e1000_82574: 416178523Sjfv ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 417178523Sjfv if (ret_val) 418178523Sjfv goto out; 419178523Sjfv 420178523Sjfv phy->id = (u32)(phy_id << 16); 421178523Sjfv usec_delay(20); 422178523Sjfv ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 423178523Sjfv if (ret_val) 424178523Sjfv goto out; 425178523Sjfv 426178523Sjfv phy->id |= (u32)(phy_id); 427178523Sjfv phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 428178523Sjfv break; 429169240Sjfv default: 430169240Sjfv ret_val = -E1000_ERR_PHY; 431169240Sjfv break; 432169240Sjfv } 433169240Sjfv 434178523Sjfvout: 435169240Sjfv return ret_val; 436169240Sjfv} 437169240Sjfv 438169240Sjfv/** 439169589Sjfv * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore 440169589Sjfv * @hw: pointer to the HW structure 441169589Sjfv * 442169589Sjfv * Acquire the HW semaphore to access the PHY or NVM 443169589Sjfv **/ 444176667Sjfvstatic s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 445169589Sjfv{ 446169589Sjfv u32 swsm; 447169589Sjfv s32 ret_val = E1000_SUCCESS; 448169589Sjfv s32 timeout = hw->nvm.word_size + 1; 449169589Sjfv s32 i = 0; 450169589Sjfv 451169589Sjfv DEBUGFUNC("e1000_get_hw_semaphore_82571"); 452169589Sjfv 453169589Sjfv /* Get the FW semaphore. */ 454169589Sjfv for (i = 0; i < timeout; i++) { 455169589Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 456169589Sjfv E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 457169589Sjfv 458169589Sjfv /* Semaphore acquired if bit latched */ 459169589Sjfv if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 460169589Sjfv break; 461169589Sjfv 462169589Sjfv usec_delay(50); 463169589Sjfv } 464169589Sjfv 465169589Sjfv if (i == timeout) { 466169589Sjfv /* Release semaphores */ 467169589Sjfv e1000_put_hw_semaphore_generic(hw); 468169589Sjfv DEBUGOUT("Driver can't access the NVM\n"); 469169589Sjfv ret_val = -E1000_ERR_NVM; 470169589Sjfv goto out; 471169589Sjfv } 472169589Sjfv 473169589Sjfvout: 474169589Sjfv return ret_val; 475169589Sjfv} 476169589Sjfv 477169589Sjfv/** 478169589Sjfv * e1000_put_hw_semaphore_82571 - Release hardware semaphore 479169589Sjfv * @hw: pointer to the HW structure 480169589Sjfv * 481169589Sjfv * Release hardware semaphore used to access the PHY or NVM 482169589Sjfv **/ 483176667Sjfvstatic void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) 484169589Sjfv{ 485169589Sjfv u32 swsm; 486169589Sjfv 487169589Sjfv DEBUGFUNC("e1000_put_hw_semaphore_82571"); 488169589Sjfv 489169589Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 490169589Sjfv 491169589Sjfv swsm &= ~E1000_SWSM_SWESMBI; 492169589Sjfv 493169589Sjfv E1000_WRITE_REG(hw, E1000_SWSM, swsm); 494169589Sjfv} 495169589Sjfv 496169589Sjfv/** 497169240Sjfv * e1000_acquire_nvm_82571 - Request for access to the EEPROM 498169589Sjfv * @hw: pointer to the HW structure 499169240Sjfv * 500169240Sjfv * To gain access to the EEPROM, first we must obtain a hardware semaphore. 501169240Sjfv * Then for non-82573 hardware, set the EEPROM access request bit and wait 502169240Sjfv * for EEPROM access grant bit. If the access grant bit is not set, release 503169240Sjfv * hardware semaphore. 504169240Sjfv **/ 505177867Sjfvstatic s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) 506169240Sjfv{ 507169240Sjfv s32 ret_val; 508169240Sjfv 509169240Sjfv DEBUGFUNC("e1000_acquire_nvm_82571"); 510169240Sjfv 511169589Sjfv ret_val = e1000_get_hw_semaphore_82571(hw); 512169240Sjfv if (ret_val) 513169240Sjfv goto out; 514169240Sjfv 515178523Sjfv if (hw->mac.type != e1000_82573 && hw->mac.type != e1000_82574) 516169240Sjfv ret_val = e1000_acquire_nvm_generic(hw); 517169240Sjfv 518169240Sjfv if (ret_val) 519169589Sjfv e1000_put_hw_semaphore_82571(hw); 520169240Sjfv 521169240Sjfvout: 522169240Sjfv return ret_val; 523169240Sjfv} 524169240Sjfv 525169240Sjfv/** 526169240Sjfv * e1000_release_nvm_82571 - Release exclusive access to EEPROM 527169589Sjfv * @hw: pointer to the HW structure 528169240Sjfv * 529169240Sjfv * Stop any current commands to the EEPROM and clear the EEPROM request bit. 530169240Sjfv **/ 531177867Sjfvstatic void e1000_release_nvm_82571(struct e1000_hw *hw) 532169240Sjfv{ 533169240Sjfv DEBUGFUNC("e1000_release_nvm_82571"); 534169240Sjfv 535169240Sjfv e1000_release_nvm_generic(hw); 536169589Sjfv e1000_put_hw_semaphore_82571(hw); 537169240Sjfv} 538169240Sjfv 539169240Sjfv/** 540169240Sjfv * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface 541169589Sjfv * @hw: pointer to the HW structure 542169589Sjfv * @offset: offset within the EEPROM to be written to 543169589Sjfv * @words: number of words to write 544169589Sjfv * @data: 16 bit word(s) to be written to the EEPROM 545169240Sjfv * 546169240Sjfv * For non-82573 silicon, write data to EEPROM at offset using SPI interface. 547169240Sjfv * 548169240Sjfv * If e1000_update_nvm_checksum is not called after this function, the 549176667Sjfv * EEPROM will most likely contain an invalid checksum. 550169240Sjfv **/ 551177867Sjfvstatic s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, 552173788Sjfv u16 *data) 553169240Sjfv{ 554169240Sjfv s32 ret_val = E1000_SUCCESS; 555169240Sjfv 556169240Sjfv DEBUGFUNC("e1000_write_nvm_82571"); 557169240Sjfv 558169240Sjfv switch (hw->mac.type) { 559169240Sjfv case e1000_82573: 560178523Sjfv case e1000_82574: 561169240Sjfv ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); 562169240Sjfv break; 563169240Sjfv case e1000_82571: 564169240Sjfv case e1000_82572: 565169240Sjfv ret_val = e1000_write_nvm_spi(hw, offset, words, data); 566169240Sjfv break; 567169240Sjfv default: 568169240Sjfv ret_val = -E1000_ERR_NVM; 569169240Sjfv break; 570169240Sjfv } 571169240Sjfv 572169240Sjfv return ret_val; 573169240Sjfv} 574169240Sjfv 575169240Sjfv/** 576169240Sjfv * e1000_update_nvm_checksum_82571 - Update EEPROM checksum 577169589Sjfv * @hw: pointer to the HW structure 578169240Sjfv * 579169240Sjfv * Updates the EEPROM checksum by reading/adding each word of the EEPROM 580169240Sjfv * up to the checksum. Then calculates the EEPROM checksum and writes the 581169240Sjfv * value to the EEPROM. 582169240Sjfv **/ 583177867Sjfvstatic s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 584169240Sjfv{ 585169240Sjfv u32 eecd; 586169240Sjfv s32 ret_val; 587169240Sjfv u16 i; 588169240Sjfv 589169240Sjfv DEBUGFUNC("e1000_update_nvm_checksum_82571"); 590169240Sjfv 591169240Sjfv ret_val = e1000_update_nvm_checksum_generic(hw); 592169240Sjfv if (ret_val) 593169240Sjfv goto out; 594169240Sjfv 595173788Sjfv /* 596173788Sjfv * If our nvm is an EEPROM, then we're done 597173788Sjfv * otherwise, commit the checksum to the flash NVM. 598173788Sjfv */ 599169240Sjfv if (hw->nvm.type != e1000_nvm_flash_hw) 600169240Sjfv goto out; 601169240Sjfv 602169240Sjfv /* Check for pending operations. */ 603169240Sjfv for (i = 0; i < E1000_FLASH_UPDATES; i++) { 604169240Sjfv msec_delay(1); 605169240Sjfv if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 606169240Sjfv break; 607169240Sjfv } 608169240Sjfv 609169240Sjfv if (i == E1000_FLASH_UPDATES) { 610169240Sjfv ret_val = -E1000_ERR_NVM; 611169240Sjfv goto out; 612169240Sjfv } 613169240Sjfv 614169240Sjfv /* Reset the firmware if using STM opcode. */ 615169240Sjfv if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) { 616173788Sjfv /* 617173788Sjfv * The enabling of and the actual reset must be done 618169240Sjfv * in two write cycles. 619169240Sjfv */ 620169240Sjfv E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE); 621169240Sjfv E1000_WRITE_FLUSH(hw); 622169240Sjfv E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET); 623169240Sjfv } 624169240Sjfv 625169240Sjfv /* Commit the write to flash */ 626169240Sjfv eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD; 627169240Sjfv E1000_WRITE_REG(hw, E1000_EECD, eecd); 628169240Sjfv 629169240Sjfv for (i = 0; i < E1000_FLASH_UPDATES; i++) { 630169240Sjfv msec_delay(1); 631169240Sjfv if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 632169240Sjfv break; 633169240Sjfv } 634169240Sjfv 635169240Sjfv if (i == E1000_FLASH_UPDATES) { 636169240Sjfv ret_val = -E1000_ERR_NVM; 637169240Sjfv goto out; 638169240Sjfv } 639169240Sjfv 640169240Sjfvout: 641169240Sjfv return ret_val; 642169240Sjfv} 643169240Sjfv 644169240Sjfv/** 645169240Sjfv * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum 646169589Sjfv * @hw: pointer to the HW structure 647169240Sjfv * 648169240Sjfv * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 649169240Sjfv * and then verifies that the sum of the EEPROM is equal to 0xBABA. 650169240Sjfv **/ 651177867Sjfvstatic s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) 652169240Sjfv{ 653169240Sjfv DEBUGFUNC("e1000_validate_nvm_checksum_82571"); 654169240Sjfv 655169240Sjfv if (hw->nvm.type == e1000_nvm_flash_hw) 656169240Sjfv e1000_fix_nvm_checksum_82571(hw); 657169240Sjfv 658169240Sjfv return e1000_validate_nvm_checksum_generic(hw); 659169240Sjfv} 660169240Sjfv 661169240Sjfv/** 662169240Sjfv * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon 663169589Sjfv * @hw: pointer to the HW structure 664169589Sjfv * @offset: offset within the EEPROM to be written to 665169589Sjfv * @words: number of words to write 666169589Sjfv * @data: 16 bit word(s) to be written to the EEPROM 667169240Sjfv * 668169240Sjfv * After checking for invalid values, poll the EEPROM to ensure the previous 669169240Sjfv * command has completed before trying to write the next word. After write 670169240Sjfv * poll for completion. 671169240Sjfv * 672169240Sjfv * If e1000_update_nvm_checksum is not called after this function, the 673176667Sjfv * EEPROM will most likely contain an invalid checksum. 674169240Sjfv **/ 675173788Sjfvstatic s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 676173788Sjfv u16 words, u16 *data) 677169240Sjfv{ 678169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 679169240Sjfv u32 i, eewr = 0; 680169240Sjfv s32 ret_val = 0; 681169240Sjfv 682169240Sjfv DEBUGFUNC("e1000_write_nvm_eewr_82571"); 683169240Sjfv 684173788Sjfv /* 685173788Sjfv * A check for invalid values: offset too large, too many words, 686173788Sjfv * and not enough words. 687173788Sjfv */ 688169240Sjfv if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 689169240Sjfv (words == 0)) { 690169240Sjfv DEBUGOUT("nvm parameter(s) out of bounds\n"); 691169240Sjfv ret_val = -E1000_ERR_NVM; 692169240Sjfv goto out; 693169240Sjfv } 694169240Sjfv 695169240Sjfv for (i = 0; i < words; i++) { 696169240Sjfv eewr = (data[i] << E1000_NVM_RW_REG_DATA) | 697169240Sjfv ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | 698169240Sjfv E1000_NVM_RW_REG_START; 699169240Sjfv 700169240Sjfv ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 701169240Sjfv if (ret_val) 702169240Sjfv break; 703169240Sjfv 704169240Sjfv E1000_WRITE_REG(hw, E1000_EEWR, eewr); 705169240Sjfv 706169240Sjfv ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 707169240Sjfv if (ret_val) 708169240Sjfv break; 709169240Sjfv } 710169240Sjfv 711169240Sjfvout: 712169240Sjfv return ret_val; 713169240Sjfv} 714169240Sjfv 715169240Sjfv/** 716169240Sjfv * e1000_get_cfg_done_82571 - Poll for configuration done 717169589Sjfv * @hw: pointer to the HW structure 718169240Sjfv * 719169240Sjfv * Reads the management control register for the config done bit to be set. 720169240Sjfv **/ 721177867Sjfvstatic s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) 722169240Sjfv{ 723169240Sjfv s32 timeout = PHY_CFG_TIMEOUT; 724169240Sjfv s32 ret_val = E1000_SUCCESS; 725169240Sjfv 726169240Sjfv DEBUGFUNC("e1000_get_cfg_done_82571"); 727169240Sjfv 728169240Sjfv while (timeout) { 729169240Sjfv if (E1000_READ_REG(hw, E1000_EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0) 730169240Sjfv break; 731169240Sjfv msec_delay(1); 732169240Sjfv timeout--; 733169240Sjfv } 734169240Sjfv if (!timeout) { 735169240Sjfv DEBUGOUT("MNG configuration cycle has not completed.\n"); 736169240Sjfv ret_val = -E1000_ERR_RESET; 737169240Sjfv goto out; 738169240Sjfv } 739169240Sjfv 740169240Sjfvout: 741169240Sjfv return ret_val; 742169240Sjfv} 743169240Sjfv 744169240Sjfv/** 745169240Sjfv * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state 746169589Sjfv * @hw: pointer to the HW structure 747169589Sjfv * @active: TRUE to enable LPLU, FALSE to disable 748169240Sjfv * 749169240Sjfv * Sets the LPLU D0 state according to the active flag. When activating LPLU 750169240Sjfv * this function also disables smart speed and vice versa. LPLU will not be 751169240Sjfv * activated unless the device autonegotiation advertisement meets standards 752169240Sjfv * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function 753169240Sjfv * pointer entry point only called by PHY setup routines. 754169240Sjfv **/ 755177867Sjfvstatic s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) 756169240Sjfv{ 757169240Sjfv struct e1000_phy_info *phy = &hw->phy; 758177867Sjfv s32 ret_val = E1000_SUCCESS; 759169240Sjfv u16 data; 760169240Sjfv 761169240Sjfv DEBUGFUNC("e1000_set_d0_lplu_state_82571"); 762169240Sjfv 763177867Sjfv if (!(phy->ops.read_reg)) 764177867Sjfv goto out; 765177867Sjfv 766177867Sjfv ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 767169240Sjfv if (ret_val) 768169240Sjfv goto out; 769169240Sjfv 770169240Sjfv if (active) { 771169240Sjfv data |= IGP02E1000_PM_D0_LPLU; 772177867Sjfv ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 773177867Sjfv data); 774169240Sjfv if (ret_val) 775169240Sjfv goto out; 776169240Sjfv 777169240Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 778177867Sjfv ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 779177867Sjfv &data); 780169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 781177867Sjfv ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 782177867Sjfv data); 783169240Sjfv if (ret_val) 784169240Sjfv goto out; 785169240Sjfv } else { 786169240Sjfv data &= ~IGP02E1000_PM_D0_LPLU; 787177867Sjfv ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 788177867Sjfv data); 789173788Sjfv /* 790173788Sjfv * LPLU and SmartSpeed are mutually exclusive. LPLU is used 791169240Sjfv * during Dx states where the power conservation is most 792169240Sjfv * important. During driver activity we should enable 793173788Sjfv * SmartSpeed, so performance is maintained. 794173788Sjfv */ 795169240Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 796177867Sjfv ret_val = phy->ops.read_reg(hw, 797177867Sjfv IGP01E1000_PHY_PORT_CONFIG, 798177867Sjfv &data); 799169240Sjfv if (ret_val) 800169240Sjfv goto out; 801169240Sjfv 802169240Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 803177867Sjfv ret_val = phy->ops.write_reg(hw, 804169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 805169240Sjfv data); 806169240Sjfv if (ret_val) 807169240Sjfv goto out; 808169240Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 809177867Sjfv ret_val = phy->ops.read_reg(hw, 810177867Sjfv IGP01E1000_PHY_PORT_CONFIG, 811177867Sjfv &data); 812169240Sjfv if (ret_val) 813169240Sjfv goto out; 814169240Sjfv 815169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 816177867Sjfv ret_val = phy->ops.write_reg(hw, 817169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 818169240Sjfv data); 819169240Sjfv if (ret_val) 820169240Sjfv goto out; 821169240Sjfv } 822169240Sjfv } 823169240Sjfv 824169240Sjfvout: 825169240Sjfv return ret_val; 826169240Sjfv} 827169240Sjfv 828169240Sjfv/** 829169240Sjfv * e1000_reset_hw_82571 - Reset hardware 830169589Sjfv * @hw: pointer to the HW structure 831169240Sjfv * 832169240Sjfv * This resets the hardware into a known state. This is a 833169240Sjfv * function pointer entry point called by the api module. 834169240Sjfv **/ 835177867Sjfvstatic s32 e1000_reset_hw_82571(struct e1000_hw *hw) 836169240Sjfv{ 837169240Sjfv u32 ctrl, extcnf_ctrl, ctrl_ext, icr; 838169240Sjfv s32 ret_val; 839169240Sjfv u16 i = 0; 840169240Sjfv 841169240Sjfv DEBUGFUNC("e1000_reset_hw_82571"); 842169240Sjfv 843173788Sjfv /* 844173788Sjfv * Prevent the PCI-E bus from sticking if there is no TLP connection 845169240Sjfv * on the last TLP read/write transaction when MAC is reset. 846169240Sjfv */ 847169240Sjfv ret_val = e1000_disable_pcie_master_generic(hw); 848169240Sjfv if (ret_val) { 849169240Sjfv DEBUGOUT("PCI-E Master disable polling has failed.\n"); 850169240Sjfv } 851169240Sjfv 852169240Sjfv DEBUGOUT("Masking off all interrupts\n"); 853169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 854169240Sjfv 855169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 856169240Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 857169240Sjfv E1000_WRITE_FLUSH(hw); 858169240Sjfv 859169240Sjfv msec_delay(10); 860169240Sjfv 861173788Sjfv /* 862173788Sjfv * Must acquire the MDIO ownership before MAC reset. 863173788Sjfv * Ownership defaults to firmware after a reset. 864173788Sjfv */ 865178523Sjfv if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) { 866169240Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 867169240Sjfv extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 868169240Sjfv 869169240Sjfv do { 870169240Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 871169240Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 872169240Sjfv 873169240Sjfv if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 874169240Sjfv break; 875169240Sjfv 876169240Sjfv extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 877169240Sjfv 878169240Sjfv msec_delay(2); 879169240Sjfv i++; 880169240Sjfv } while (i < MDIO_OWNERSHIP_TIMEOUT); 881169240Sjfv } 882169240Sjfv 883169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 884169240Sjfv 885169240Sjfv DEBUGOUT("Issuing a global reset to MAC\n"); 886169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 887169240Sjfv 888169240Sjfv if (hw->nvm.type == e1000_nvm_flash_hw) { 889169240Sjfv usec_delay(10); 890169240Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 891169240Sjfv ctrl_ext |= E1000_CTRL_EXT_EE_RST; 892169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 893169240Sjfv E1000_WRITE_FLUSH(hw); 894169240Sjfv } 895169240Sjfv 896169240Sjfv ret_val = e1000_get_auto_rd_done_generic(hw); 897169240Sjfv if (ret_val) 898169240Sjfv /* We don't want to continue accessing MAC registers. */ 899169240Sjfv goto out; 900169240Sjfv 901173788Sjfv /* 902173788Sjfv * Phy configuration from NVM just starts after EECD_AUTO_RD is set. 903169240Sjfv * Need to wait for Phy configuration completion before accessing 904169240Sjfv * NVM and Phy. 905169240Sjfv */ 906178523Sjfv if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) 907169240Sjfv msec_delay(25); 908169240Sjfv 909169240Sjfv /* Clear any pending interrupt events. */ 910169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 911169240Sjfv icr = E1000_READ_REG(hw, E1000_ICR); 912169240Sjfv 913173788Sjfv if (!(e1000_check_alt_mac_addr_generic(hw))) 914173788Sjfv e1000_set_laa_state_82571(hw, TRUE); 915173788Sjfv 916169240Sjfvout: 917169240Sjfv return ret_val; 918169240Sjfv} 919169240Sjfv 920169240Sjfv/** 921169240Sjfv * e1000_init_hw_82571 - Initialize hardware 922169589Sjfv * @hw: pointer to the HW structure 923169240Sjfv * 924169240Sjfv * This inits the hardware readying it for operation. 925169240Sjfv **/ 926177867Sjfvstatic s32 e1000_init_hw_82571(struct e1000_hw *hw) 927169240Sjfv{ 928169240Sjfv struct e1000_mac_info *mac = &hw->mac; 929169240Sjfv u32 reg_data; 930169240Sjfv s32 ret_val; 931169240Sjfv u16 i, rar_count = mac->rar_entry_count; 932169240Sjfv 933169240Sjfv DEBUGFUNC("e1000_init_hw_82571"); 934169240Sjfv 935169240Sjfv e1000_initialize_hw_bits_82571(hw); 936169240Sjfv 937169240Sjfv /* Initialize identification LED */ 938169240Sjfv ret_val = e1000_id_led_init_generic(hw); 939169240Sjfv if (ret_val) { 940169240Sjfv DEBUGOUT("Error initializing identification LED\n"); 941173788Sjfv /* This is not fatal and we should not stop init due to this */ 942169240Sjfv } 943169240Sjfv 944169240Sjfv /* Disabling VLAN filtering */ 945169240Sjfv DEBUGOUT("Initializing the IEEE VLAN\n"); 946177867Sjfv mac->ops.clear_vfta(hw); 947169240Sjfv 948169240Sjfv /* Setup the receive address. */ 949173788Sjfv /* 950173788Sjfv * If, however, a locally administered address was assigned to the 951169240Sjfv * 82571, we must reserve a RAR for it to work around an issue where 952169240Sjfv * resetting one port will reload the MAC on the other port. 953169240Sjfv */ 954173788Sjfv if (e1000_get_laa_state_82571(hw)) 955169240Sjfv rar_count--; 956169240Sjfv e1000_init_rx_addrs_generic(hw, rar_count); 957169240Sjfv 958169240Sjfv /* Zero out the Multicast HASH table */ 959169240Sjfv DEBUGOUT("Zeroing the MTA\n"); 960169240Sjfv for (i = 0; i < mac->mta_reg_count; i++) 961169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 962169240Sjfv 963169240Sjfv /* Setup link and flow control */ 964177867Sjfv ret_val = mac->ops.setup_link(hw); 965169240Sjfv 966169240Sjfv /* Set the transmit descriptor write-back policy */ 967173788Sjfv reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 968169240Sjfv reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 969169240Sjfv E1000_TXDCTL_FULL_TX_DESC_WB | 970169240Sjfv E1000_TXDCTL_COUNT_DESC; 971173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 972169240Sjfv 973169240Sjfv /* ...for both queues. */ 974178523Sjfv if (mac->type != e1000_82573 && mac->type != e1000_82574) { 975173788Sjfv reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 976169240Sjfv reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 977169240Sjfv E1000_TXDCTL_FULL_TX_DESC_WB | 978169240Sjfv E1000_TXDCTL_COUNT_DESC; 979173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 980169240Sjfv } else { 981169240Sjfv e1000_enable_tx_pkt_filtering(hw); 982169240Sjfv reg_data = E1000_READ_REG(hw, E1000_GCR); 983169240Sjfv reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 984169240Sjfv E1000_WRITE_REG(hw, E1000_GCR, reg_data); 985169240Sjfv } 986169240Sjfv 987173788Sjfv /* 988173788Sjfv * Clear all of the statistics registers (clear on read). It is 989169240Sjfv * important that we do this after we have tried to establish link 990169240Sjfv * because the symbol error count will increment wildly if there 991169240Sjfv * is no link. 992169240Sjfv */ 993169240Sjfv e1000_clear_hw_cntrs_82571(hw); 994169240Sjfv 995169240Sjfv return ret_val; 996169240Sjfv} 997169240Sjfv 998169240Sjfv/** 999169240Sjfv * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits 1000169589Sjfv * @hw: pointer to the HW structure 1001169240Sjfv * 1002169240Sjfv * Initializes required hardware-dependent bits needed for normal operation. 1003169240Sjfv **/ 1004173788Sjfvstatic void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 1005169240Sjfv{ 1006169240Sjfv u32 reg; 1007169240Sjfv 1008169240Sjfv DEBUGFUNC("e1000_initialize_hw_bits_82571"); 1009169240Sjfv 1010169240Sjfv if (hw->mac.disable_hw_init_bits) 1011169240Sjfv goto out; 1012169240Sjfv 1013169240Sjfv /* Transmit Descriptor Control 0 */ 1014173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1015169240Sjfv reg |= (1 << 22); 1016173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 1017169240Sjfv 1018169240Sjfv /* Transmit Descriptor Control 1 */ 1019173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1020169240Sjfv reg |= (1 << 22); 1021173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 1022169240Sjfv 1023169240Sjfv /* Transmit Arbitration Control 0 */ 1024173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(0)); 1025169240Sjfv reg &= ~(0xF << 27); /* 30:27 */ 1026169240Sjfv switch (hw->mac.type) { 1027169240Sjfv case e1000_82571: 1028169240Sjfv case e1000_82572: 1029169240Sjfv reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); 1030169240Sjfv break; 1031169240Sjfv default: 1032169240Sjfv break; 1033169240Sjfv } 1034173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(0), reg); 1035169240Sjfv 1036169240Sjfv /* Transmit Arbitration Control 1 */ 1037173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(1)); 1038169240Sjfv switch (hw->mac.type) { 1039169240Sjfv case e1000_82571: 1040169240Sjfv case e1000_82572: 1041169240Sjfv reg &= ~((1 << 29) | (1 << 30)); 1042169589Sjfv reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); 1043169240Sjfv if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1044169240Sjfv reg &= ~(1 << 28); 1045169240Sjfv else 1046169240Sjfv reg |= (1 << 28); 1047173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(1), reg); 1048169240Sjfv break; 1049169240Sjfv default: 1050169240Sjfv break; 1051169240Sjfv } 1052169240Sjfv 1053169240Sjfv /* Device Control */ 1054178523Sjfv if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) { 1055169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL); 1056169240Sjfv reg &= ~(1 << 29); 1057169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, reg); 1058169240Sjfv } 1059169240Sjfv 1060169240Sjfv /* Extended Device Control */ 1061178523Sjfv if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) { 1062169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1063169240Sjfv reg &= ~(1 << 23); 1064169240Sjfv reg |= (1 << 22); 1065169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1066169240Sjfv } 1067169240Sjfv 1068169240Sjfvout: 1069169240Sjfv return; 1070169240Sjfv} 1071169240Sjfv 1072169240Sjfv/** 1073169240Sjfv * e1000_clear_vfta_82571 - Clear VLAN filter table 1074169589Sjfv * @hw: pointer to the HW structure 1075169240Sjfv * 1076169240Sjfv * Clears the register array which contains the VLAN filter table by 1077169240Sjfv * setting all the values to 0. 1078169240Sjfv **/ 1079177867Sjfvstatic void e1000_clear_vfta_82571(struct e1000_hw *hw) 1080169240Sjfv{ 1081169240Sjfv u32 offset; 1082169240Sjfv u32 vfta_value = 0; 1083169240Sjfv u32 vfta_offset = 0; 1084169240Sjfv u32 vfta_bit_in_reg = 0; 1085169240Sjfv 1086169240Sjfv DEBUGFUNC("e1000_clear_vfta_82571"); 1087169240Sjfv 1088178523Sjfv if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) { 1089169240Sjfv if (hw->mng_cookie.vlan_id != 0) { 1090173788Sjfv /* 1091173788Sjfv * The VFTA is a 4096b bit-field, each identifying 1092169240Sjfv * a single VLAN ID. The following operations 1093169240Sjfv * determine which 32b entry (i.e. offset) into the 1094169240Sjfv * array we want to set the VLAN ID (i.e. bit) of 1095169240Sjfv * the manageability unit. 1096169240Sjfv */ 1097169240Sjfv vfta_offset = (hw->mng_cookie.vlan_id >> 1098169240Sjfv E1000_VFTA_ENTRY_SHIFT) & 1099169240Sjfv E1000_VFTA_ENTRY_MASK; 1100169240Sjfv vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 1101169240Sjfv E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 1102169240Sjfv } 1103169240Sjfv } 1104169240Sjfv for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 1105173788Sjfv /* 1106173788Sjfv * If the offset we want to clear is the same offset of the 1107169240Sjfv * manageability VLAN ID, then clear all bits except that of 1108169240Sjfv * the manageability unit. 1109169240Sjfv */ 1110169240Sjfv vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 1111169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); 1112169240Sjfv E1000_WRITE_FLUSH(hw); 1113169240Sjfv } 1114169240Sjfv} 1115169240Sjfv 1116169240Sjfv/** 1117173788Sjfv * e1000_update_mc_addr_list_82571 - Update Multicast addresses 1118169589Sjfv * @hw: pointer to the HW structure 1119169589Sjfv * @mc_addr_list: array of multicast addresses to program 1120169589Sjfv * @mc_addr_count: number of multicast addresses to program 1121169589Sjfv * @rar_used_count: the first RAR register free to program 1122169589Sjfv * @rar_count: total number of supported Receive Address Registers 1123169240Sjfv * 1124169240Sjfv * Updates the Receive Address Registers and Multicast Table Array. 1125169240Sjfv * The caller must have a packed mc_addr_list of multicast addresses. 1126169240Sjfv * The parameter rar_count will usually be hw->mac.rar_entry_count 1127169240Sjfv * unless there are workarounds that change this. 1128169240Sjfv **/ 1129177867Sjfvstatic void e1000_update_mc_addr_list_82571(struct e1000_hw *hw, 1130176667Sjfv u8 *mc_addr_list, u32 mc_addr_count, 1131176667Sjfv u32 rar_used_count, u32 rar_count) 1132169240Sjfv{ 1133173788Sjfv DEBUGFUNC("e1000_update_mc_addr_list_82571"); 1134169240Sjfv 1135169240Sjfv if (e1000_get_laa_state_82571(hw)) 1136169240Sjfv rar_count--; 1137169240Sjfv 1138173788Sjfv e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count, 1139169240Sjfv rar_used_count, rar_count); 1140169240Sjfv} 1141169240Sjfv 1142169240Sjfv/** 1143169240Sjfv * e1000_setup_link_82571 - Setup flow control and link settings 1144169589Sjfv * @hw: pointer to the HW structure 1145169240Sjfv * 1146169240Sjfv * Determines which flow control settings to use, then configures flow 1147169240Sjfv * control. Calls the appropriate media-specific link configuration 1148169240Sjfv * function. Assuming the adapter has a valid link partner, a valid link 1149169240Sjfv * should be established. Assumes the hardware has previously been reset 1150169240Sjfv * and the transmitter and receiver are not enabled. 1151169240Sjfv **/ 1152177867Sjfvstatic s32 e1000_setup_link_82571(struct e1000_hw *hw) 1153169240Sjfv{ 1154169240Sjfv DEBUGFUNC("e1000_setup_link_82571"); 1155169240Sjfv 1156173788Sjfv /* 1157173788Sjfv * 82573 does not have a word in the NVM to determine 1158169240Sjfv * the default flow control setting, so we explicitly 1159169240Sjfv * set it to full. 1160169240Sjfv */ 1161178523Sjfv if ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) && 1162178523Sjfv hw->fc.type == e1000_fc_default) 1163173788Sjfv hw->fc.type = e1000_fc_full; 1164169240Sjfv 1165169240Sjfv return e1000_setup_link_generic(hw); 1166169240Sjfv} 1167169240Sjfv 1168169240Sjfv/** 1169169240Sjfv * e1000_setup_copper_link_82571 - Configure copper link settings 1170169589Sjfv * @hw: pointer to the HW structure 1171169240Sjfv * 1172169240Sjfv * Configures the link for auto-neg or forced speed and duplex. Then we check 1173169240Sjfv * for link, once link is established calls to configure collision distance 1174169240Sjfv * and flow control are called. 1175169240Sjfv **/ 1176177867Sjfvstatic s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) 1177169240Sjfv{ 1178169240Sjfv u32 ctrl, led_ctrl; 1179169240Sjfv s32 ret_val; 1180169240Sjfv 1181169240Sjfv DEBUGFUNC("e1000_setup_copper_link_82571"); 1182169240Sjfv 1183169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1184169240Sjfv ctrl |= E1000_CTRL_SLU; 1185169240Sjfv ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1186169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1187169240Sjfv 1188169240Sjfv switch (hw->phy.type) { 1189169240Sjfv case e1000_phy_m88: 1190176667Sjfv case e1000_phy_bm: 1191169240Sjfv ret_val = e1000_copper_link_setup_m88(hw); 1192169240Sjfv break; 1193169240Sjfv case e1000_phy_igp_2: 1194169240Sjfv ret_val = e1000_copper_link_setup_igp(hw); 1195169240Sjfv /* Setup activity LED */ 1196169240Sjfv led_ctrl = E1000_READ_REG(hw, E1000_LEDCTL); 1197169240Sjfv led_ctrl &= IGP_ACTIVITY_LED_MASK; 1198169240Sjfv led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1199169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, led_ctrl); 1200169240Sjfv break; 1201169240Sjfv default: 1202169240Sjfv ret_val = -E1000_ERR_PHY; 1203169240Sjfv break; 1204169240Sjfv } 1205169240Sjfv 1206169240Sjfv if (ret_val) 1207169240Sjfv goto out; 1208169240Sjfv 1209169240Sjfv ret_val = e1000_setup_copper_link_generic(hw); 1210169240Sjfv 1211169240Sjfvout: 1212169240Sjfv return ret_val; 1213169240Sjfv} 1214169240Sjfv 1215169240Sjfv/** 1216169240Sjfv * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes 1217169589Sjfv * @hw: pointer to the HW structure 1218169240Sjfv * 1219169240Sjfv * Configures collision distance and flow control for fiber and serdes links. 1220169240Sjfv * Upon successful setup, poll for link. 1221169240Sjfv **/ 1222177867Sjfvstatic s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) 1223169240Sjfv{ 1224169240Sjfv DEBUGFUNC("e1000_setup_fiber_serdes_link_82571"); 1225169240Sjfv 1226169240Sjfv switch (hw->mac.type) { 1227169240Sjfv case e1000_82571: 1228169240Sjfv case e1000_82572: 1229173788Sjfv /* 1230173788Sjfv * If SerDes loopback mode is entered, there is no form 1231169240Sjfv * of reset to take the adapter out of that mode. So we 1232169240Sjfv * have to explicitly take the adapter out of loopback 1233176667Sjfv * mode. This prevents drivers from twiddling their thumbs 1234169240Sjfv * if another tool failed to take it out of loopback mode. 1235169240Sjfv */ 1236169240Sjfv E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1237169240Sjfv break; 1238169240Sjfv default: 1239169240Sjfv break; 1240169240Sjfv } 1241169240Sjfv 1242169240Sjfv return e1000_setup_fiber_serdes_link_generic(hw); 1243169240Sjfv} 1244169240Sjfv 1245169240Sjfv/** 1246169240Sjfv * e1000_valid_led_default_82571 - Verify a valid default LED config 1247169589Sjfv * @hw: pointer to the HW structure 1248169589Sjfv * @data: pointer to the NVM (EEPROM) 1249169240Sjfv * 1250169240Sjfv * Read the EEPROM for the current default LED configuration. If the 1251169240Sjfv * LED configuration is not valid, set to a valid LED configuration. 1252169240Sjfv **/ 1253177867Sjfvstatic s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) 1254169240Sjfv{ 1255169240Sjfv s32 ret_val; 1256169240Sjfv 1257169240Sjfv DEBUGFUNC("e1000_valid_led_default_82571"); 1258169240Sjfv 1259177867Sjfv ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1260169240Sjfv if (ret_val) { 1261169240Sjfv DEBUGOUT("NVM Read Error\n"); 1262169240Sjfv goto out; 1263169240Sjfv } 1264169240Sjfv 1265178523Sjfv if ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) && 1266169240Sjfv *data == ID_LED_RESERVED_F746) 1267169240Sjfv *data = ID_LED_DEFAULT_82573; 1268178523Sjfv else if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1269169240Sjfv *data = ID_LED_DEFAULT; 1270169240Sjfvout: 1271169240Sjfv return ret_val; 1272169240Sjfv} 1273169240Sjfv 1274169240Sjfv/** 1275169240Sjfv * e1000_get_laa_state_82571 - Get locally administered address state 1276169589Sjfv * @hw: pointer to the HW structure 1277169240Sjfv * 1278176667Sjfv * Retrieve and return the current locally administered address state. 1279169240Sjfv **/ 1280173788Sjfvbool e1000_get_laa_state_82571(struct e1000_hw *hw) 1281169240Sjfv{ 1282169240Sjfv struct e1000_dev_spec_82571 *dev_spec; 1283173788Sjfv bool state = FALSE; 1284169240Sjfv 1285169240Sjfv DEBUGFUNC("e1000_get_laa_state_82571"); 1286169240Sjfv 1287169240Sjfv if (hw->mac.type != e1000_82571) 1288169240Sjfv goto out; 1289169240Sjfv 1290169240Sjfv dev_spec = (struct e1000_dev_spec_82571 *)hw->dev_spec; 1291169240Sjfv 1292169240Sjfv state = dev_spec->laa_is_present; 1293169240Sjfv 1294169240Sjfvout: 1295169240Sjfv return state; 1296169240Sjfv} 1297169240Sjfv 1298169240Sjfv/** 1299169240Sjfv * e1000_set_laa_state_82571 - Set locally administered address state 1300169589Sjfv * @hw: pointer to the HW structure 1301169589Sjfv * @state: enable/disable locally administered address 1302169240Sjfv * 1303176667Sjfv * Enable/Disable the current locally administered address state. 1304169240Sjfv **/ 1305173788Sjfvvoid e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) 1306169240Sjfv{ 1307169240Sjfv struct e1000_dev_spec_82571 *dev_spec; 1308169240Sjfv 1309169240Sjfv DEBUGFUNC("e1000_set_laa_state_82571"); 1310169240Sjfv 1311169240Sjfv if (hw->mac.type != e1000_82571) 1312169240Sjfv goto out; 1313169240Sjfv 1314169240Sjfv dev_spec = (struct e1000_dev_spec_82571 *)hw->dev_spec; 1315169240Sjfv 1316169240Sjfv dev_spec->laa_is_present = state; 1317169240Sjfv 1318169240Sjfv /* If workaround is activated... */ 1319173788Sjfv if (state) { 1320173788Sjfv /* 1321173788Sjfv * Hold a copy of the LAA in RAR[14] This is done so that 1322169240Sjfv * between the time RAR[0] gets clobbered and the time it 1323169240Sjfv * gets fixed, the actual LAA is in one of the RARs and no 1324169240Sjfv * incoming packets directed to this port are dropped. 1325169240Sjfv * Eventually the LAA will be in RAR[0] and RAR[14]. 1326169240Sjfv */ 1327169240Sjfv e1000_rar_set_generic(hw, hw->mac.addr, 1328169240Sjfv hw->mac.rar_entry_count - 1); 1329169240Sjfv } 1330169240Sjfv 1331169240Sjfvout: 1332169240Sjfv return; 1333169240Sjfv} 1334169240Sjfv 1335169240Sjfv/** 1336169240Sjfv * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum 1337169589Sjfv * @hw: pointer to the HW structure 1338169240Sjfv * 1339169240Sjfv * Verifies that the EEPROM has completed the update. After updating the 1340169240Sjfv * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If 1341169240Sjfv * the checksum fix is not implemented, we need to set the bit and update 1342169240Sjfv * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, 1343169240Sjfv * we need to return bad checksum. 1344169240Sjfv **/ 1345173788Sjfvstatic s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 1346169240Sjfv{ 1347169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 1348169240Sjfv s32 ret_val = E1000_SUCCESS; 1349169240Sjfv u16 data; 1350169240Sjfv 1351169240Sjfv DEBUGFUNC("e1000_fix_nvm_checksum_82571"); 1352169240Sjfv 1353169240Sjfv if (nvm->type != e1000_nvm_flash_hw) 1354169240Sjfv goto out; 1355169240Sjfv 1356173788Sjfv /* 1357173788Sjfv * Check bit 4 of word 10h. If it is 0, firmware is done updating 1358169240Sjfv * 10h-12h. Checksum may need to be fixed. 1359169240Sjfv */ 1360177867Sjfv ret_val = nvm->ops.read(hw, 0x10, 1, &data); 1361169240Sjfv if (ret_val) 1362169240Sjfv goto out; 1363169240Sjfv 1364169240Sjfv if (!(data & 0x10)) { 1365173788Sjfv /* 1366173788Sjfv * Read 0x23 and check bit 15. This bit is a 1 1367169240Sjfv * when the checksum has already been fixed. If 1368169240Sjfv * the checksum is still wrong and this bit is a 1369169240Sjfv * 1, we need to return bad checksum. Otherwise, 1370169240Sjfv * we need to set this bit to a 1 and update the 1371169240Sjfv * checksum. 1372169240Sjfv */ 1373177867Sjfv ret_val = nvm->ops.read(hw, 0x23, 1, &data); 1374169240Sjfv if (ret_val) 1375169240Sjfv goto out; 1376169240Sjfv 1377169240Sjfv if (!(data & 0x8000)) { 1378169240Sjfv data |= 0x8000; 1379177867Sjfv ret_val = nvm->ops.write(hw, 0x23, 1, &data); 1380169240Sjfv if (ret_val) 1381169240Sjfv goto out; 1382177867Sjfv ret_val = nvm->ops.update(hw); 1383169240Sjfv } 1384169240Sjfv } 1385169240Sjfv 1386169240Sjfvout: 1387169240Sjfv return ret_val; 1388169240Sjfv} 1389169240Sjfv 1390169240Sjfv/** 1391173788Sjfv * e1000_read_mac_addr_82571 - Read device MAC address 1392173788Sjfv * @hw: pointer to the HW structure 1393173788Sjfv **/ 1394177867Sjfvstatic s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) 1395173788Sjfv{ 1396173788Sjfv s32 ret_val = E1000_SUCCESS; 1397173788Sjfv 1398173788Sjfv DEBUGFUNC("e1000_read_mac_addr_82571"); 1399173788Sjfv if (e1000_check_alt_mac_addr_generic(hw)) 1400173788Sjfv ret_val = e1000_read_mac_addr_generic(hw); 1401173788Sjfv 1402173788Sjfv return ret_val; 1403173788Sjfv} 1404173788Sjfv 1405173788Sjfv/** 1406173788Sjfv * e1000_power_down_phy_copper_82571 - Remove link during PHY power down 1407173788Sjfv * @hw: pointer to the HW structure 1408173788Sjfv * 1409173788Sjfv * In the case of a PHY power down to save power, or to turn off link during a 1410173788Sjfv * driver unload, or wake on lan is not enabled, remove the link. 1411173788Sjfv **/ 1412177867Sjfvstatic void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) 1413173788Sjfv{ 1414177867Sjfv struct e1000_phy_info *phy = &hw->phy; 1415177867Sjfv struct e1000_mac_info *mac = &hw->mac; 1416177867Sjfv 1417177867Sjfv if (!(phy->ops.check_reset_block)) 1418177867Sjfv return; 1419177867Sjfv 1420173788Sjfv /* If the management interface is not enabled, then power down */ 1421177867Sjfv if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 1422173788Sjfv e1000_power_down_phy_copper(hw); 1423173788Sjfv 1424173788Sjfv return; 1425173788Sjfv} 1426173788Sjfv 1427173788Sjfv/** 1428169240Sjfv * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters 1429169589Sjfv * @hw: pointer to the HW structure 1430169240Sjfv * 1431169240Sjfv * Clears the hardware counters by reading the counter registers. 1432169240Sjfv **/ 1433177867Sjfvstatic void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) 1434169240Sjfv{ 1435169240Sjfv volatile u32 temp; 1436169240Sjfv 1437169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_82571"); 1438169240Sjfv 1439169240Sjfv e1000_clear_hw_cntrs_base_generic(hw); 1440169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC64); 1441169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC127); 1442169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC255); 1443169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC511); 1444169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC1023); 1445169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC1522); 1446169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC64); 1447169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC127); 1448169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC255); 1449169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC511); 1450169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC1023); 1451169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC1522); 1452169240Sjfv 1453169240Sjfv temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1454169240Sjfv temp = E1000_READ_REG(hw, E1000_RXERRC); 1455169240Sjfv temp = E1000_READ_REG(hw, E1000_TNCRS); 1456169240Sjfv temp = E1000_READ_REG(hw, E1000_CEXTERR); 1457169240Sjfv temp = E1000_READ_REG(hw, E1000_TSCTC); 1458169240Sjfv temp = E1000_READ_REG(hw, E1000_TSCTFC); 1459169240Sjfv 1460169240Sjfv temp = E1000_READ_REG(hw, E1000_MGTPRC); 1461169240Sjfv temp = E1000_READ_REG(hw, E1000_MGTPDC); 1462169240Sjfv temp = E1000_READ_REG(hw, E1000_MGTPTC); 1463169240Sjfv 1464169240Sjfv temp = E1000_READ_REG(hw, E1000_IAC); 1465169240Sjfv temp = E1000_READ_REG(hw, E1000_ICRXOC); 1466169240Sjfv 1467169240Sjfv temp = E1000_READ_REG(hw, E1000_ICRXPTC); 1468169240Sjfv temp = E1000_READ_REG(hw, E1000_ICRXATC); 1469169240Sjfv temp = E1000_READ_REG(hw, E1000_ICTXPTC); 1470169240Sjfv temp = E1000_READ_REG(hw, E1000_ICTXATC); 1471169240Sjfv temp = E1000_READ_REG(hw, E1000_ICTXQEC); 1472169240Sjfv temp = E1000_READ_REG(hw, E1000_ICTXQMTC); 1473169240Sjfv temp = E1000_READ_REG(hw, E1000_ICRXDMTC); 1474169240Sjfv} 1475