e1000_82571.c revision 173788
1169240Sjfv/******************************************************************************* 2169240Sjfv 3169240Sjfv Copyright (c) 2001-2007, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32169240Sjfv*******************************************************************************/ 33173788Sjfv/* $FreeBSD: head/sys/dev/em/e1000_82571.c 173788 2007-11-20 21:41:22Z jfv $ */ 34169240Sjfv 35169240Sjfv 36169240Sjfv/* e1000_82571 37169240Sjfv * e1000_82572 38169240Sjfv * e1000_82573 39173788Sjfv * e1000_82574 40169240Sjfv */ 41169240Sjfv 42169589Sjfv#include "e1000_api.h" 43169240Sjfv#include "e1000_82571.h" 44169240Sjfv 45169240Sjfvvoid e1000_init_function_pointers_82571(struct e1000_hw *hw); 46169240Sjfv 47169240SjfvSTATIC s32 e1000_init_phy_params_82571(struct e1000_hw *hw); 48169240SjfvSTATIC s32 e1000_init_nvm_params_82571(struct e1000_hw *hw); 49169240SjfvSTATIC s32 e1000_init_mac_params_82571(struct e1000_hw *hw); 50169240SjfvSTATIC s32 e1000_acquire_nvm_82571(struct e1000_hw *hw); 51169240SjfvSTATIC void e1000_release_nvm_82571(struct e1000_hw *hw); 52169240SjfvSTATIC s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, 53169240Sjfv u16 words, u16 *data); 54169240SjfvSTATIC s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw); 55169240SjfvSTATIC s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw); 56169240SjfvSTATIC s32 e1000_get_cfg_done_82571(struct e1000_hw *hw); 57169240SjfvSTATIC s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, 58173788Sjfv bool active); 59169240SjfvSTATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw); 60169240SjfvSTATIC s32 e1000_init_hw_82571(struct e1000_hw *hw); 61169240SjfvSTATIC void e1000_clear_vfta_82571(struct e1000_hw *hw); 62173788SjfvSTATIC void e1000_update_mc_addr_list_82571(struct e1000_hw *hw, 63169240Sjfv u8 *mc_addr_list, u32 mc_addr_count, 64169240Sjfv u32 rar_used_count, u32 rar_count); 65169240SjfvSTATIC s32 e1000_setup_link_82571(struct e1000_hw *hw); 66169240SjfvSTATIC s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); 67169240SjfvSTATIC s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); 68169240SjfvSTATIC s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data); 69169240SjfvSTATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); 70169589Sjfvstatic s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw); 71169240Sjfvstatic s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); 72169240Sjfvstatic s32 e1000_get_phy_id_82571(struct e1000_hw *hw); 73169589Sjfvstatic void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); 74169240Sjfvstatic void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); 75169240Sjfvstatic s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 76169240Sjfv u16 words, u16 *data); 77173788SjfvSTATIC s32 e1000_read_mac_addr_82571(struct e1000_hw *hw); 78173788SjfvSTATIC void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); 79169240Sjfv 80169240Sjfvstruct e1000_dev_spec_82571 { 81173788Sjfv bool laa_is_present; 82169240Sjfv}; 83169240Sjfv 84169240Sjfv/** 85169240Sjfv * e1000_init_phy_params_82571 - Init PHY func ptrs. 86169589Sjfv * @hw: pointer to the HW structure 87169240Sjfv * 88169240Sjfv * This is a function pointer entry point called by the api module. 89169240Sjfv **/ 90173788SjfvSTATIC s32 e1000_init_phy_params_82571(struct e1000_hw *hw) 91169240Sjfv{ 92169240Sjfv struct e1000_phy_info *phy = &hw->phy; 93169240Sjfv struct e1000_functions *func = &hw->func; 94169240Sjfv s32 ret_val = E1000_SUCCESS; 95169240Sjfv 96169240Sjfv DEBUGFUNC("e1000_init_phy_params_82571"); 97169240Sjfv 98173788Sjfv if (hw->phy.media_type != e1000_media_type_copper) { 99169240Sjfv phy->type = e1000_phy_none; 100169240Sjfv goto out; 101169240Sjfv } 102169240Sjfv 103169240Sjfv phy->addr = 1; 104169240Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 105169240Sjfv phy->reset_delay_us = 100; 106169240Sjfv 107169589Sjfv func->acquire_phy = e1000_get_hw_semaphore_82571; 108169240Sjfv func->check_polarity = e1000_check_polarity_igp; 109169240Sjfv func->check_reset_block = e1000_check_reset_block_generic; 110169589Sjfv func->release_phy = e1000_put_hw_semaphore_82571; 111169240Sjfv func->reset_phy = e1000_phy_hw_reset_generic; 112169240Sjfv func->set_d0_lplu_state = e1000_set_d0_lplu_state_82571; 113169240Sjfv func->set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 114173788Sjfv func->power_up_phy = e1000_power_up_phy_copper; 115173788Sjfv func->power_down_phy = e1000_power_down_phy_copper_82571; 116169240Sjfv 117169240Sjfv switch (hw->mac.type) { 118169240Sjfv case e1000_82571: 119169240Sjfv case e1000_82572: 120169240Sjfv phy->type = e1000_phy_igp_2; 121169240Sjfv func->get_cfg_done = e1000_get_cfg_done_82571; 122169240Sjfv func->get_phy_info = e1000_get_phy_info_igp; 123169240Sjfv func->force_speed_duplex = e1000_phy_force_speed_duplex_igp; 124169240Sjfv func->get_cable_length = e1000_get_cable_length_igp_2; 125169240Sjfv func->read_phy_reg = e1000_read_phy_reg_igp; 126169240Sjfv func->write_phy_reg = e1000_write_phy_reg_igp; 127173788Sjfv 128173788Sjfv /* This uses above function pointers */ 129173788Sjfv ret_val = e1000_get_phy_id_82571(hw); 130173788Sjfv 131173788Sjfv /* Verify PHY ID */ 132173788Sjfv if (phy->id != IGP01E1000_I_PHY_ID) { 133173788Sjfv ret_val = -E1000_ERR_PHY; 134173788Sjfv goto out; 135173788Sjfv } 136169240Sjfv break; 137169240Sjfv case e1000_82573: 138169240Sjfv phy->type = e1000_phy_m88; 139169240Sjfv func->get_cfg_done = e1000_get_cfg_done_generic; 140169240Sjfv func->get_phy_info = e1000_get_phy_info_m88; 141169240Sjfv func->commit_phy = e1000_phy_sw_reset_generic; 142169240Sjfv func->force_speed_duplex = e1000_phy_force_speed_duplex_m88; 143169240Sjfv func->get_cable_length = e1000_get_cable_length_m88; 144169240Sjfv func->read_phy_reg = e1000_read_phy_reg_m88; 145169240Sjfv func->write_phy_reg = e1000_write_phy_reg_m88; 146169240Sjfv 147173788Sjfv /* This uses above function pointers */ 148173788Sjfv ret_val = e1000_get_phy_id_82571(hw); 149169240Sjfv 150173788Sjfv /* Verify PHY ID */ 151169240Sjfv if (phy->id != M88E1111_I_PHY_ID) { 152169240Sjfv ret_val = -E1000_ERR_PHY; 153173788Sjfv DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 154169240Sjfv goto out; 155169240Sjfv } 156169240Sjfv break; 157169240Sjfv default: 158169240Sjfv ret_val = -E1000_ERR_PHY; 159169240Sjfv goto out; 160169240Sjfv break; 161169240Sjfv } 162169240Sjfv 163169240Sjfvout: 164169240Sjfv return ret_val; 165169240Sjfv} 166169240Sjfv 167169240Sjfv/** 168169240Sjfv * e1000_init_nvm_params_82571 - Init NVM func ptrs. 169169589Sjfv * @hw: pointer to the HW structure 170169240Sjfv * 171169240Sjfv * This is a function pointer entry point called by the api module. 172169240Sjfv **/ 173173788SjfvSTATIC s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) 174169240Sjfv{ 175169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 176169240Sjfv struct e1000_functions *func = &hw->func; 177169240Sjfv u32 eecd = E1000_READ_REG(hw, E1000_EECD); 178169240Sjfv u16 size; 179169240Sjfv 180169240Sjfv DEBUGFUNC("e1000_init_nvm_params_82571"); 181169240Sjfv 182169240Sjfv nvm->opcode_bits = 8; 183169240Sjfv nvm->delay_usec = 1; 184169240Sjfv switch (nvm->override) { 185169240Sjfv case e1000_nvm_override_spi_large: 186169240Sjfv nvm->page_size = 32; 187169240Sjfv nvm->address_bits = 16; 188169240Sjfv break; 189169240Sjfv case e1000_nvm_override_spi_small: 190169240Sjfv nvm->page_size = 8; 191169240Sjfv nvm->address_bits = 8; 192169240Sjfv break; 193169240Sjfv default: 194169240Sjfv nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 195169240Sjfv nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 196169240Sjfv break; 197169240Sjfv } 198169240Sjfv 199169240Sjfv switch (hw->mac.type) { 200169240Sjfv case e1000_82573: 201169240Sjfv if (((eecd >> 15) & 0x3) == 0x3) { 202169240Sjfv nvm->type = e1000_nvm_flash_hw; 203169240Sjfv nvm->word_size = 2048; 204173788Sjfv /* 205173788Sjfv * Autonomous Flash update bit must be cleared due 206169240Sjfv * to Flash update issue. 207169240Sjfv */ 208169240Sjfv eecd &= ~E1000_EECD_AUPDEN; 209169240Sjfv E1000_WRITE_REG(hw, E1000_EECD, eecd); 210169240Sjfv break; 211169240Sjfv } 212169240Sjfv /* Fall Through */ 213169240Sjfv default: 214169240Sjfv nvm->type = e1000_nvm_eeprom_spi; 215169240Sjfv size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 216169240Sjfv E1000_EECD_SIZE_EX_SHIFT); 217173788Sjfv /* 218173788Sjfv * Added to a constant, "size" becomes the left-shift value 219169240Sjfv * for setting word_size. 220169240Sjfv */ 221169240Sjfv size += NVM_WORD_SIZE_BASE_SHIFT; 222173788Sjfv 223173788Sjfv /* EEPROM access above 16k is unsupported */ 224173788Sjfv if (size > 14) 225173788Sjfv size = 14; 226169240Sjfv nvm->word_size = 1 << size; 227169240Sjfv break; 228169240Sjfv } 229169240Sjfv 230169240Sjfv /* Function Pointers */ 231169240Sjfv func->acquire_nvm = e1000_acquire_nvm_82571; 232169240Sjfv func->read_nvm = (hw->mac.type == e1000_82573) 233169240Sjfv ? e1000_read_nvm_eerd 234169240Sjfv : e1000_read_nvm_spi; 235169240Sjfv func->release_nvm = e1000_release_nvm_82571; 236169240Sjfv func->update_nvm = e1000_update_nvm_checksum_82571; 237169240Sjfv func->validate_nvm = e1000_validate_nvm_checksum_82571; 238169240Sjfv func->valid_led_default = e1000_valid_led_default_82571; 239169240Sjfv func->write_nvm = e1000_write_nvm_82571; 240169240Sjfv 241169240Sjfv return E1000_SUCCESS; 242169240Sjfv} 243169240Sjfv 244169240Sjfv/** 245169240Sjfv * e1000_init_mac_params_82571 - Init MAC func ptrs. 246169589Sjfv * @hw: pointer to the HW structure 247169240Sjfv * 248169240Sjfv * This is a function pointer entry point called by the api module. 249169240Sjfv **/ 250173788SjfvSTATIC s32 e1000_init_mac_params_82571(struct e1000_hw *hw) 251169240Sjfv{ 252169240Sjfv struct e1000_mac_info *mac = &hw->mac; 253169240Sjfv struct e1000_functions *func = &hw->func; 254169240Sjfv s32 ret_val = E1000_SUCCESS; 255169240Sjfv 256169240Sjfv DEBUGFUNC("e1000_init_mac_params_82571"); 257169240Sjfv 258169240Sjfv /* Set media type */ 259169240Sjfv switch (hw->device_id) { 260169240Sjfv case E1000_DEV_ID_82571EB_FIBER: 261169240Sjfv case E1000_DEV_ID_82572EI_FIBER: 262169240Sjfv case E1000_DEV_ID_82571EB_QUAD_FIBER: 263173788Sjfv hw->phy.media_type = e1000_media_type_fiber; 264169240Sjfv break; 265169240Sjfv case E1000_DEV_ID_82571EB_SERDES: 266169589Sjfv case E1000_DEV_ID_82571EB_SERDES_DUAL: 267169589Sjfv case E1000_DEV_ID_82571EB_SERDES_QUAD: 268169240Sjfv case E1000_DEV_ID_82572EI_SERDES: 269173788Sjfv hw->phy.media_type = e1000_media_type_internal_serdes; 270169240Sjfv break; 271169240Sjfv default: 272173788Sjfv hw->phy.media_type = e1000_media_type_copper; 273169240Sjfv break; 274169240Sjfv } 275169240Sjfv 276169240Sjfv /* Set mta register count */ 277169240Sjfv mac->mta_reg_count = 128; 278169240Sjfv /* Set rar entry count */ 279169240Sjfv mac->rar_entry_count = E1000_RAR_ENTRIES; 280169240Sjfv /* Set if part includes ASF firmware */ 281169240Sjfv mac->asf_firmware_present = TRUE; 282169240Sjfv /* Set if manageability features are enabled. */ 283169240Sjfv mac->arc_subsystem_valid = 284169240Sjfv (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 285169240Sjfv ? TRUE : FALSE; 286169240Sjfv 287169240Sjfv /* Function pointers */ 288169240Sjfv 289169240Sjfv /* bus type/speed/width */ 290169240Sjfv func->get_bus_info = e1000_get_bus_info_pcie_generic; 291169240Sjfv /* reset */ 292169240Sjfv func->reset_hw = e1000_reset_hw_82571; 293169240Sjfv /* hw initialization */ 294169240Sjfv func->init_hw = e1000_init_hw_82571; 295169240Sjfv /* link setup */ 296169240Sjfv func->setup_link = e1000_setup_link_82571; 297169240Sjfv /* physical interface link setup */ 298169240Sjfv func->setup_physical_interface = 299173788Sjfv (hw->phy.media_type == e1000_media_type_copper) 300169240Sjfv ? e1000_setup_copper_link_82571 301169240Sjfv : e1000_setup_fiber_serdes_link_82571; 302169240Sjfv /* check for link */ 303173788Sjfv switch (hw->phy.media_type) { 304169240Sjfv case e1000_media_type_copper: 305169240Sjfv func->check_for_link = e1000_check_for_copper_link_generic; 306169240Sjfv break; 307169240Sjfv case e1000_media_type_fiber: 308169240Sjfv func->check_for_link = e1000_check_for_fiber_link_generic; 309169240Sjfv break; 310169240Sjfv case e1000_media_type_internal_serdes: 311169240Sjfv func->check_for_link = e1000_check_for_serdes_link_generic; 312169240Sjfv break; 313169240Sjfv default: 314169240Sjfv ret_val = -E1000_ERR_CONFIG; 315169240Sjfv goto out; 316169240Sjfv break; 317169240Sjfv } 318169240Sjfv /* check management mode */ 319169240Sjfv func->check_mng_mode = e1000_check_mng_mode_generic; 320169240Sjfv /* multicast address update */ 321173788Sjfv func->update_mc_addr_list = e1000_update_mc_addr_list_82571; 322169240Sjfv /* writing VFTA */ 323169240Sjfv func->write_vfta = e1000_write_vfta_generic; 324169240Sjfv /* clearing VFTA */ 325169240Sjfv func->clear_vfta = e1000_clear_vfta_82571; 326169240Sjfv /* setting MTA */ 327169240Sjfv func->mta_set = e1000_mta_set_generic; 328173788Sjfv /* read mac address */ 329173788Sjfv func->read_mac_addr = e1000_read_mac_addr_82571; 330169240Sjfv /* blink LED */ 331169240Sjfv func->blink_led = e1000_blink_led_generic; 332169240Sjfv /* setup LED */ 333169240Sjfv func->setup_led = e1000_setup_led_generic; 334169240Sjfv /* cleanup LED */ 335169240Sjfv func->cleanup_led = e1000_cleanup_led_generic; 336169240Sjfv /* turn on/off LED */ 337169240Sjfv func->led_on = e1000_led_on_generic; 338169240Sjfv func->led_off = e1000_led_off_generic; 339169240Sjfv /* remove device */ 340169240Sjfv func->remove_device = e1000_remove_device_generic; 341169240Sjfv /* clear hardware counters */ 342169240Sjfv func->clear_hw_cntrs = e1000_clear_hw_cntrs_82571; 343169240Sjfv /* link info */ 344169240Sjfv func->get_link_up_info = 345173788Sjfv (hw->phy.media_type == e1000_media_type_copper) 346169240Sjfv ? e1000_get_speed_and_duplex_copper_generic 347169240Sjfv : e1000_get_speed_and_duplex_fiber_serdes_generic; 348169240Sjfv 349169240Sjfv hw->dev_spec_size = sizeof(struct e1000_dev_spec_82571); 350169240Sjfv 351169240Sjfv /* Device-specific structure allocation */ 352169240Sjfv ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 353169240Sjfv 354169240Sjfvout: 355169240Sjfv return ret_val; 356169240Sjfv} 357169240Sjfv 358169240Sjfv/** 359169240Sjfv * e1000_init_function_pointers_82571 - Init func ptrs. 360169589Sjfv * @hw: pointer to the HW structure 361169240Sjfv * 362169240Sjfv * The only function explicitly called by the api module to initialize 363169240Sjfv * all function pointers and parameters. 364169240Sjfv **/ 365173788Sjfvvoid e1000_init_function_pointers_82571(struct e1000_hw *hw) 366169240Sjfv{ 367169240Sjfv DEBUGFUNC("e1000_init_function_pointers_82571"); 368169240Sjfv 369169240Sjfv hw->func.init_mac_params = e1000_init_mac_params_82571; 370169240Sjfv hw->func.init_nvm_params = e1000_init_nvm_params_82571; 371169240Sjfv hw->func.init_phy_params = e1000_init_phy_params_82571; 372169240Sjfv} 373169240Sjfv 374169240Sjfv/** 375169240Sjfv * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision 376169589Sjfv * @hw: pointer to the HW structure 377169240Sjfv * 378169240Sjfv * Reads the PHY registers and stores the PHY ID and possibly the PHY 379169240Sjfv * revision in the hardware structure. 380169240Sjfv **/ 381173788Sjfvstatic s32 e1000_get_phy_id_82571(struct e1000_hw *hw) 382169240Sjfv{ 383169240Sjfv struct e1000_phy_info *phy = &hw->phy; 384169240Sjfv s32 ret_val = E1000_SUCCESS; 385169240Sjfv 386169240Sjfv DEBUGFUNC("e1000_get_phy_id_82571"); 387169240Sjfv 388169240Sjfv switch (hw->mac.type) { 389169240Sjfv case e1000_82571: 390169240Sjfv case e1000_82572: 391173788Sjfv /* 392173788Sjfv * The 82571 firmware may still be configuring the PHY. 393169240Sjfv * In this case, we cannot access the PHY until the 394169240Sjfv * configuration is done. So we explicitly set the 395173788Sjfv * PHY ID. 396173788Sjfv */ 397169240Sjfv phy->id = IGP01E1000_I_PHY_ID; 398169240Sjfv break; 399169240Sjfv case e1000_82573: 400169240Sjfv ret_val = e1000_get_phy_id(hw); 401169240Sjfv break; 402169240Sjfv default: 403169240Sjfv ret_val = -E1000_ERR_PHY; 404169240Sjfv break; 405169240Sjfv } 406169240Sjfv 407169240Sjfv return ret_val; 408169240Sjfv} 409169240Sjfv 410169240Sjfv/** 411169589Sjfv * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore 412169589Sjfv * @hw: pointer to the HW structure 413169589Sjfv * 414169589Sjfv * Acquire the HW semaphore to access the PHY or NVM 415169589Sjfv **/ 416173788Sjfvs32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 417169589Sjfv{ 418169589Sjfv u32 swsm; 419169589Sjfv s32 ret_val = E1000_SUCCESS; 420169589Sjfv s32 timeout = hw->nvm.word_size + 1; 421169589Sjfv s32 i = 0; 422169589Sjfv 423169589Sjfv DEBUGFUNC("e1000_get_hw_semaphore_82571"); 424169589Sjfv 425169589Sjfv /* Get the FW semaphore. */ 426169589Sjfv for (i = 0; i < timeout; i++) { 427169589Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 428169589Sjfv E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 429169589Sjfv 430169589Sjfv /* Semaphore acquired if bit latched */ 431169589Sjfv if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 432169589Sjfv break; 433169589Sjfv 434169589Sjfv usec_delay(50); 435169589Sjfv } 436169589Sjfv 437169589Sjfv if (i == timeout) { 438169589Sjfv /* Release semaphores */ 439169589Sjfv e1000_put_hw_semaphore_generic(hw); 440169589Sjfv DEBUGOUT("Driver can't access the NVM\n"); 441169589Sjfv ret_val = -E1000_ERR_NVM; 442169589Sjfv goto out; 443169589Sjfv } 444169589Sjfv 445169589Sjfvout: 446169589Sjfv return ret_val; 447169589Sjfv} 448169589Sjfv 449169589Sjfv/** 450169589Sjfv * e1000_put_hw_semaphore_82571 - Release hardware semaphore 451169589Sjfv * @hw: pointer to the HW structure 452169589Sjfv * 453169589Sjfv * Release hardware semaphore used to access the PHY or NVM 454169589Sjfv **/ 455173788Sjfvvoid e1000_put_hw_semaphore_82571(struct e1000_hw *hw) 456169589Sjfv{ 457169589Sjfv u32 swsm; 458169589Sjfv 459169589Sjfv DEBUGFUNC("e1000_put_hw_semaphore_82571"); 460169589Sjfv 461169589Sjfv swsm = E1000_READ_REG(hw, E1000_SWSM); 462169589Sjfv 463169589Sjfv swsm &= ~E1000_SWSM_SWESMBI; 464169589Sjfv 465169589Sjfv E1000_WRITE_REG(hw, E1000_SWSM, swsm); 466169589Sjfv} 467169589Sjfv 468169589Sjfv/** 469169240Sjfv * e1000_acquire_nvm_82571 - Request for access to the EEPROM 470169589Sjfv * @hw: pointer to the HW structure 471169240Sjfv * 472169240Sjfv * To gain access to the EEPROM, first we must obtain a hardware semaphore. 473169240Sjfv * Then for non-82573 hardware, set the EEPROM access request bit and wait 474169240Sjfv * for EEPROM access grant bit. If the access grant bit is not set, release 475169240Sjfv * hardware semaphore. 476169240Sjfv **/ 477173788SjfvSTATIC s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) 478169240Sjfv{ 479169240Sjfv s32 ret_val; 480169240Sjfv 481169240Sjfv DEBUGFUNC("e1000_acquire_nvm_82571"); 482169240Sjfv 483169589Sjfv ret_val = e1000_get_hw_semaphore_82571(hw); 484169240Sjfv if (ret_val) 485169240Sjfv goto out; 486169240Sjfv 487169240Sjfv if (hw->mac.type != e1000_82573) 488169240Sjfv ret_val = e1000_acquire_nvm_generic(hw); 489169240Sjfv 490169240Sjfv if (ret_val) 491169589Sjfv e1000_put_hw_semaphore_82571(hw); 492169240Sjfv 493169240Sjfvout: 494169240Sjfv return ret_val; 495169240Sjfv} 496169240Sjfv 497169240Sjfv/** 498169240Sjfv * e1000_release_nvm_82571 - Release exclusive access to EEPROM 499169589Sjfv * @hw: pointer to the HW structure 500169240Sjfv * 501169240Sjfv * Stop any current commands to the EEPROM and clear the EEPROM request bit. 502169240Sjfv **/ 503173788SjfvSTATIC void e1000_release_nvm_82571(struct e1000_hw *hw) 504169240Sjfv{ 505169240Sjfv DEBUGFUNC("e1000_release_nvm_82571"); 506169240Sjfv 507169240Sjfv e1000_release_nvm_generic(hw); 508169589Sjfv e1000_put_hw_semaphore_82571(hw); 509169240Sjfv} 510169240Sjfv 511169240Sjfv/** 512169240Sjfv * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface 513169589Sjfv * @hw: pointer to the HW structure 514169589Sjfv * @offset: offset within the EEPROM to be written to 515169589Sjfv * @words: number of words to write 516169589Sjfv * @data: 16 bit word(s) to be written to the EEPROM 517169240Sjfv * 518169240Sjfv * For non-82573 silicon, write data to EEPROM at offset using SPI interface. 519169240Sjfv * 520169240Sjfv * If e1000_update_nvm_checksum is not called after this function, the 521169240Sjfv * EEPROM will most likley contain an invalid checksum. 522169240Sjfv **/ 523173788SjfvSTATIC s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, 524173788Sjfv u16 *data) 525169240Sjfv{ 526169240Sjfv s32 ret_val = E1000_SUCCESS; 527169240Sjfv 528169240Sjfv DEBUGFUNC("e1000_write_nvm_82571"); 529169240Sjfv 530169240Sjfv switch (hw->mac.type) { 531169240Sjfv case e1000_82573: 532169240Sjfv ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); 533169240Sjfv break; 534169240Sjfv case e1000_82571: 535169240Sjfv case e1000_82572: 536169240Sjfv ret_val = e1000_write_nvm_spi(hw, offset, words, data); 537169240Sjfv break; 538169240Sjfv default: 539169240Sjfv ret_val = -E1000_ERR_NVM; 540169240Sjfv break; 541169240Sjfv } 542169240Sjfv 543169240Sjfv return ret_val; 544169240Sjfv} 545169240Sjfv 546169240Sjfv/** 547169240Sjfv * e1000_update_nvm_checksum_82571 - Update EEPROM checksum 548169589Sjfv * @hw: pointer to the HW structure 549169240Sjfv * 550169240Sjfv * Updates the EEPROM checksum by reading/adding each word of the EEPROM 551169240Sjfv * up to the checksum. Then calculates the EEPROM checksum and writes the 552169240Sjfv * value to the EEPROM. 553169240Sjfv **/ 554173788SjfvSTATIC s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 555169240Sjfv{ 556169240Sjfv u32 eecd; 557169240Sjfv s32 ret_val; 558169240Sjfv u16 i; 559169240Sjfv 560169240Sjfv DEBUGFUNC("e1000_update_nvm_checksum_82571"); 561169240Sjfv 562169240Sjfv ret_val = e1000_update_nvm_checksum_generic(hw); 563169240Sjfv if (ret_val) 564169240Sjfv goto out; 565169240Sjfv 566173788Sjfv /* 567173788Sjfv * If our nvm is an EEPROM, then we're done 568173788Sjfv * otherwise, commit the checksum to the flash NVM. 569173788Sjfv */ 570169240Sjfv if (hw->nvm.type != e1000_nvm_flash_hw) 571169240Sjfv goto out; 572169240Sjfv 573169240Sjfv /* Check for pending operations. */ 574169240Sjfv for (i = 0; i < E1000_FLASH_UPDATES; i++) { 575169240Sjfv msec_delay(1); 576169240Sjfv if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 577169240Sjfv break; 578169240Sjfv } 579169240Sjfv 580169240Sjfv if (i == E1000_FLASH_UPDATES) { 581169240Sjfv ret_val = -E1000_ERR_NVM; 582169240Sjfv goto out; 583169240Sjfv } 584169240Sjfv 585169240Sjfv /* Reset the firmware if using STM opcode. */ 586169240Sjfv if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) { 587173788Sjfv /* 588173788Sjfv * The enabling of and the actual reset must be done 589169240Sjfv * in two write cycles. 590169240Sjfv */ 591169240Sjfv E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE); 592169240Sjfv E1000_WRITE_FLUSH(hw); 593169240Sjfv E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET); 594169240Sjfv } 595169240Sjfv 596169240Sjfv /* Commit the write to flash */ 597169240Sjfv eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD; 598169240Sjfv E1000_WRITE_REG(hw, E1000_EECD, eecd); 599169240Sjfv 600169240Sjfv for (i = 0; i < E1000_FLASH_UPDATES; i++) { 601169240Sjfv msec_delay(1); 602169240Sjfv if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 603169240Sjfv break; 604169240Sjfv } 605169240Sjfv 606169240Sjfv if (i == E1000_FLASH_UPDATES) { 607169240Sjfv ret_val = -E1000_ERR_NVM; 608169240Sjfv goto out; 609169240Sjfv } 610169240Sjfv 611169240Sjfvout: 612169240Sjfv return ret_val; 613169240Sjfv} 614169240Sjfv 615169240Sjfv/** 616169240Sjfv * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum 617169589Sjfv * @hw: pointer to the HW structure 618169240Sjfv * 619169240Sjfv * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 620169240Sjfv * and then verifies that the sum of the EEPROM is equal to 0xBABA. 621169240Sjfv **/ 622173788SjfvSTATIC s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) 623169240Sjfv{ 624169240Sjfv DEBUGFUNC("e1000_validate_nvm_checksum_82571"); 625169240Sjfv 626169240Sjfv if (hw->nvm.type == e1000_nvm_flash_hw) 627169240Sjfv e1000_fix_nvm_checksum_82571(hw); 628169240Sjfv 629169240Sjfv return e1000_validate_nvm_checksum_generic(hw); 630169240Sjfv} 631169240Sjfv 632169240Sjfv/** 633169240Sjfv * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon 634169589Sjfv * @hw: pointer to the HW structure 635169589Sjfv * @offset: offset within the EEPROM to be written to 636169589Sjfv * @words: number of words to write 637169589Sjfv * @data: 16 bit word(s) to be written to the EEPROM 638169240Sjfv * 639169240Sjfv * After checking for invalid values, poll the EEPROM to ensure the previous 640169240Sjfv * command has completed before trying to write the next word. After write 641169240Sjfv * poll for completion. 642169240Sjfv * 643169240Sjfv * If e1000_update_nvm_checksum is not called after this function, the 644169240Sjfv * EEPROM will most likley contain an invalid checksum. 645169240Sjfv **/ 646173788Sjfvstatic s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 647173788Sjfv u16 words, u16 *data) 648169240Sjfv{ 649169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 650169240Sjfv u32 i, eewr = 0; 651169240Sjfv s32 ret_val = 0; 652169240Sjfv 653169240Sjfv DEBUGFUNC("e1000_write_nvm_eewr_82571"); 654169240Sjfv 655173788Sjfv /* 656173788Sjfv * A check for invalid values: offset too large, too many words, 657173788Sjfv * and not enough words. 658173788Sjfv */ 659169240Sjfv if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 660169240Sjfv (words == 0)) { 661169240Sjfv DEBUGOUT("nvm parameter(s) out of bounds\n"); 662169240Sjfv ret_val = -E1000_ERR_NVM; 663169240Sjfv goto out; 664169240Sjfv } 665169240Sjfv 666169240Sjfv for (i = 0; i < words; i++) { 667169240Sjfv eewr = (data[i] << E1000_NVM_RW_REG_DATA) | 668169240Sjfv ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | 669169240Sjfv E1000_NVM_RW_REG_START; 670169240Sjfv 671169240Sjfv ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 672169240Sjfv if (ret_val) 673169240Sjfv break; 674169240Sjfv 675169240Sjfv E1000_WRITE_REG(hw, E1000_EEWR, eewr); 676169240Sjfv 677169240Sjfv ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 678169240Sjfv if (ret_val) 679169240Sjfv break; 680169240Sjfv } 681169240Sjfv 682169240Sjfvout: 683169240Sjfv return ret_val; 684169240Sjfv} 685169240Sjfv 686169240Sjfv/** 687169240Sjfv * e1000_get_cfg_done_82571 - Poll for configuration done 688169589Sjfv * @hw: pointer to the HW structure 689169240Sjfv * 690169240Sjfv * Reads the management control register for the config done bit to be set. 691169240Sjfv **/ 692173788SjfvSTATIC s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) 693169240Sjfv{ 694169240Sjfv s32 timeout = PHY_CFG_TIMEOUT; 695169240Sjfv s32 ret_val = E1000_SUCCESS; 696169240Sjfv 697169240Sjfv DEBUGFUNC("e1000_get_cfg_done_82571"); 698169240Sjfv 699169240Sjfv while (timeout) { 700169240Sjfv if (E1000_READ_REG(hw, E1000_EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0) 701169240Sjfv break; 702169240Sjfv msec_delay(1); 703169240Sjfv timeout--; 704169240Sjfv } 705169240Sjfv if (!timeout) { 706169240Sjfv DEBUGOUT("MNG configuration cycle has not completed.\n"); 707169240Sjfv ret_val = -E1000_ERR_RESET; 708169240Sjfv goto out; 709169240Sjfv } 710169240Sjfv 711169240Sjfvout: 712169240Sjfv return ret_val; 713169240Sjfv} 714169240Sjfv 715169240Sjfv/** 716169240Sjfv * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state 717169589Sjfv * @hw: pointer to the HW structure 718169589Sjfv * @active: TRUE to enable LPLU, FALSE to disable 719169240Sjfv * 720169240Sjfv * Sets the LPLU D0 state according to the active flag. When activating LPLU 721169240Sjfv * this function also disables smart speed and vice versa. LPLU will not be 722169240Sjfv * activated unless the device autonegotiation advertisement meets standards 723169240Sjfv * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function 724169240Sjfv * pointer entry point only called by PHY setup routines. 725169240Sjfv **/ 726173788SjfvSTATIC s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) 727169240Sjfv{ 728169240Sjfv struct e1000_phy_info *phy = &hw->phy; 729169240Sjfv s32 ret_val; 730169240Sjfv u16 data; 731169240Sjfv 732169240Sjfv DEBUGFUNC("e1000_set_d0_lplu_state_82571"); 733169240Sjfv 734169240Sjfv ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 735169240Sjfv if (ret_val) 736169240Sjfv goto out; 737169240Sjfv 738169240Sjfv if (active) { 739169240Sjfv data |= IGP02E1000_PM_D0_LPLU; 740169240Sjfv ret_val = e1000_write_phy_reg(hw, 741169240Sjfv IGP02E1000_PHY_POWER_MGMT, 742169240Sjfv data); 743169240Sjfv if (ret_val) 744169240Sjfv goto out; 745169240Sjfv 746169240Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 747169240Sjfv ret_val = e1000_read_phy_reg(hw, 748169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 749169240Sjfv &data); 750169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 751169240Sjfv ret_val = e1000_write_phy_reg(hw, 752169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 753169240Sjfv data); 754169240Sjfv if (ret_val) 755169240Sjfv goto out; 756169240Sjfv } else { 757169240Sjfv data &= ~IGP02E1000_PM_D0_LPLU; 758169240Sjfv ret_val = e1000_write_phy_reg(hw, 759169240Sjfv IGP02E1000_PHY_POWER_MGMT, 760169240Sjfv data); 761173788Sjfv /* 762173788Sjfv * LPLU and SmartSpeed are mutually exclusive. LPLU is used 763169240Sjfv * during Dx states where the power conservation is most 764169240Sjfv * important. During driver activity we should enable 765173788Sjfv * SmartSpeed, so performance is maintained. 766173788Sjfv */ 767169240Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 768169240Sjfv ret_val = e1000_read_phy_reg(hw, 769169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 770169240Sjfv &data); 771169240Sjfv if (ret_val) 772169240Sjfv goto out; 773169240Sjfv 774169240Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 775169240Sjfv ret_val = e1000_write_phy_reg(hw, 776169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 777169240Sjfv data); 778169240Sjfv if (ret_val) 779169240Sjfv goto out; 780169240Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 781169240Sjfv ret_val = e1000_read_phy_reg(hw, 782169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 783169240Sjfv &data); 784169240Sjfv if (ret_val) 785169240Sjfv goto out; 786169240Sjfv 787169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 788169240Sjfv ret_val = e1000_write_phy_reg(hw, 789169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 790169240Sjfv data); 791169240Sjfv if (ret_val) 792169240Sjfv goto out; 793169240Sjfv } 794169240Sjfv } 795169240Sjfv 796169240Sjfvout: 797169240Sjfv return ret_val; 798169240Sjfv} 799169240Sjfv 800169240Sjfv/** 801169240Sjfv * e1000_reset_hw_82571 - Reset hardware 802169589Sjfv * @hw: pointer to the HW structure 803169240Sjfv * 804169240Sjfv * This resets the hardware into a known state. This is a 805169240Sjfv * function pointer entry point called by the api module. 806169240Sjfv **/ 807173788SjfvSTATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw) 808169240Sjfv{ 809169240Sjfv u32 ctrl, extcnf_ctrl, ctrl_ext, icr; 810169240Sjfv s32 ret_val; 811169240Sjfv u16 i = 0; 812169240Sjfv 813169240Sjfv DEBUGFUNC("e1000_reset_hw_82571"); 814169240Sjfv 815173788Sjfv /* 816173788Sjfv * Prevent the PCI-E bus from sticking if there is no TLP connection 817169240Sjfv * on the last TLP read/write transaction when MAC is reset. 818169240Sjfv */ 819169240Sjfv ret_val = e1000_disable_pcie_master_generic(hw); 820169240Sjfv if (ret_val) { 821169240Sjfv DEBUGOUT("PCI-E Master disable polling has failed.\n"); 822169240Sjfv } 823169240Sjfv 824169240Sjfv DEBUGOUT("Masking off all interrupts\n"); 825169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 826169240Sjfv 827169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 828169240Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 829169240Sjfv E1000_WRITE_FLUSH(hw); 830169240Sjfv 831169240Sjfv msec_delay(10); 832169240Sjfv 833173788Sjfv /* 834173788Sjfv * Must acquire the MDIO ownership before MAC reset. 835173788Sjfv * Ownership defaults to firmware after a reset. 836173788Sjfv */ 837169240Sjfv if (hw->mac.type == e1000_82573) { 838169240Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 839169240Sjfv extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 840169240Sjfv 841169240Sjfv do { 842169240Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 843169240Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 844169240Sjfv 845169240Sjfv if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 846169240Sjfv break; 847169240Sjfv 848169240Sjfv extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 849169240Sjfv 850169240Sjfv msec_delay(2); 851169240Sjfv i++; 852169240Sjfv } while (i < MDIO_OWNERSHIP_TIMEOUT); 853169240Sjfv } 854169240Sjfv 855169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 856169240Sjfv 857169240Sjfv DEBUGOUT("Issuing a global reset to MAC\n"); 858169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 859169240Sjfv 860169240Sjfv if (hw->nvm.type == e1000_nvm_flash_hw) { 861169240Sjfv usec_delay(10); 862169240Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 863169240Sjfv ctrl_ext |= E1000_CTRL_EXT_EE_RST; 864169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 865169240Sjfv E1000_WRITE_FLUSH(hw); 866169240Sjfv } 867169240Sjfv 868169240Sjfv ret_val = e1000_get_auto_rd_done_generic(hw); 869169240Sjfv if (ret_val) 870169240Sjfv /* We don't want to continue accessing MAC registers. */ 871169240Sjfv goto out; 872169240Sjfv 873173788Sjfv /* 874173788Sjfv * Phy configuration from NVM just starts after EECD_AUTO_RD is set. 875169240Sjfv * Need to wait for Phy configuration completion before accessing 876169240Sjfv * NVM and Phy. 877169240Sjfv */ 878169240Sjfv if (hw->mac.type == e1000_82573) 879169240Sjfv msec_delay(25); 880169240Sjfv 881169240Sjfv /* Clear any pending interrupt events. */ 882169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 883169240Sjfv icr = E1000_READ_REG(hw, E1000_ICR); 884169240Sjfv 885173788Sjfv if (!(e1000_check_alt_mac_addr_generic(hw))) 886173788Sjfv e1000_set_laa_state_82571(hw, TRUE); 887173788Sjfv 888169240Sjfvout: 889169240Sjfv return ret_val; 890169240Sjfv} 891169240Sjfv 892169240Sjfv/** 893169240Sjfv * e1000_init_hw_82571 - Initialize hardware 894169589Sjfv * @hw: pointer to the HW structure 895169240Sjfv * 896169240Sjfv * This inits the hardware readying it for operation. 897169240Sjfv **/ 898173788SjfvSTATIC s32 e1000_init_hw_82571(struct e1000_hw *hw) 899169240Sjfv{ 900169240Sjfv struct e1000_mac_info *mac = &hw->mac; 901169240Sjfv u32 reg_data; 902169240Sjfv s32 ret_val; 903169240Sjfv u16 i, rar_count = mac->rar_entry_count; 904169240Sjfv 905169240Sjfv DEBUGFUNC("e1000_init_hw_82571"); 906169240Sjfv 907169240Sjfv e1000_initialize_hw_bits_82571(hw); 908169240Sjfv 909169240Sjfv /* Initialize identification LED */ 910169240Sjfv ret_val = e1000_id_led_init_generic(hw); 911169240Sjfv if (ret_val) { 912169240Sjfv DEBUGOUT("Error initializing identification LED\n"); 913173788Sjfv /* This is not fatal and we should not stop init due to this */ 914169240Sjfv } 915169240Sjfv 916169240Sjfv /* Disabling VLAN filtering */ 917169240Sjfv DEBUGOUT("Initializing the IEEE VLAN\n"); 918169240Sjfv e1000_clear_vfta(hw); 919169240Sjfv 920169240Sjfv /* Setup the receive address. */ 921173788Sjfv /* 922173788Sjfv * If, however, a locally administered address was assigned to the 923169240Sjfv * 82571, we must reserve a RAR for it to work around an issue where 924169240Sjfv * resetting one port will reload the MAC on the other port. 925169240Sjfv */ 926173788Sjfv if (e1000_get_laa_state_82571(hw)) 927169240Sjfv rar_count--; 928169240Sjfv e1000_init_rx_addrs_generic(hw, rar_count); 929169240Sjfv 930169240Sjfv /* Zero out the Multicast HASH table */ 931169240Sjfv DEBUGOUT("Zeroing the MTA\n"); 932169240Sjfv for (i = 0; i < mac->mta_reg_count; i++) 933169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 934169240Sjfv 935169240Sjfv /* Setup link and flow control */ 936169240Sjfv ret_val = e1000_setup_link(hw); 937169240Sjfv 938169240Sjfv /* Set the transmit descriptor write-back policy */ 939173788Sjfv reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 940169240Sjfv reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 941169240Sjfv E1000_TXDCTL_FULL_TX_DESC_WB | 942169240Sjfv E1000_TXDCTL_COUNT_DESC; 943173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 944169240Sjfv 945169240Sjfv /* ...for both queues. */ 946169240Sjfv if (mac->type != e1000_82573) { 947173788Sjfv reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 948169240Sjfv reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 949169240Sjfv E1000_TXDCTL_FULL_TX_DESC_WB | 950169240Sjfv E1000_TXDCTL_COUNT_DESC; 951173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 952169240Sjfv } else { 953169240Sjfv e1000_enable_tx_pkt_filtering(hw); 954169240Sjfv reg_data = E1000_READ_REG(hw, E1000_GCR); 955169240Sjfv reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 956169240Sjfv E1000_WRITE_REG(hw, E1000_GCR, reg_data); 957169240Sjfv } 958169240Sjfv 959173788Sjfv /* 960173788Sjfv * Clear all of the statistics registers (clear on read). It is 961169240Sjfv * important that we do this after we have tried to establish link 962169240Sjfv * because the symbol error count will increment wildly if there 963169240Sjfv * is no link. 964169240Sjfv */ 965169240Sjfv e1000_clear_hw_cntrs_82571(hw); 966169240Sjfv 967169240Sjfv return ret_val; 968169240Sjfv} 969169240Sjfv 970169240Sjfv/** 971169240Sjfv * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits 972169589Sjfv * @hw: pointer to the HW structure 973169240Sjfv * 974169240Sjfv * Initializes required hardware-dependent bits needed for normal operation. 975169240Sjfv **/ 976173788Sjfvstatic void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 977169240Sjfv{ 978169240Sjfv u32 reg; 979169240Sjfv 980169240Sjfv DEBUGFUNC("e1000_initialize_hw_bits_82571"); 981169240Sjfv 982169240Sjfv if (hw->mac.disable_hw_init_bits) 983169240Sjfv goto out; 984169240Sjfv 985169240Sjfv /* Transmit Descriptor Control 0 */ 986173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 987169240Sjfv reg |= (1 << 22); 988173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 989169240Sjfv 990169240Sjfv /* Transmit Descriptor Control 1 */ 991173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 992169240Sjfv reg |= (1 << 22); 993173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 994169240Sjfv 995169240Sjfv /* Transmit Arbitration Control 0 */ 996173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(0)); 997169240Sjfv reg &= ~(0xF << 27); /* 30:27 */ 998169240Sjfv switch (hw->mac.type) { 999169240Sjfv case e1000_82571: 1000169240Sjfv case e1000_82572: 1001169240Sjfv reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); 1002169240Sjfv break; 1003169240Sjfv default: 1004169240Sjfv break; 1005169240Sjfv } 1006173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(0), reg); 1007169240Sjfv 1008169240Sjfv /* Transmit Arbitration Control 1 */ 1009173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(1)); 1010169240Sjfv switch (hw->mac.type) { 1011169240Sjfv case e1000_82571: 1012169240Sjfv case e1000_82572: 1013169240Sjfv reg &= ~((1 << 29) | (1 << 30)); 1014169589Sjfv reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); 1015169240Sjfv if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1016169240Sjfv reg &= ~(1 << 28); 1017169240Sjfv else 1018169240Sjfv reg |= (1 << 28); 1019173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(1), reg); 1020169240Sjfv break; 1021169240Sjfv default: 1022169240Sjfv break; 1023169240Sjfv } 1024169240Sjfv 1025169240Sjfv /* Device Control */ 1026169240Sjfv if (hw->mac.type == e1000_82573) { 1027169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL); 1028169240Sjfv reg &= ~(1 << 29); 1029169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, reg); 1030169240Sjfv } 1031169240Sjfv 1032169240Sjfv /* Extended Device Control */ 1033169240Sjfv if (hw->mac.type == e1000_82573) { 1034169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1035169240Sjfv reg &= ~(1 << 23); 1036169240Sjfv reg |= (1 << 22); 1037169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1038169240Sjfv } 1039169240Sjfv 1040169240Sjfvout: 1041169240Sjfv return; 1042169240Sjfv} 1043169240Sjfv 1044169240Sjfv/** 1045169240Sjfv * e1000_clear_vfta_82571 - Clear VLAN filter table 1046169589Sjfv * @hw: pointer to the HW structure 1047169240Sjfv * 1048169240Sjfv * Clears the register array which contains the VLAN filter table by 1049169240Sjfv * setting all the values to 0. 1050169240Sjfv **/ 1051173788SjfvSTATIC void e1000_clear_vfta_82571(struct e1000_hw *hw) 1052169240Sjfv{ 1053169240Sjfv u32 offset; 1054169240Sjfv u32 vfta_value = 0; 1055169240Sjfv u32 vfta_offset = 0; 1056169240Sjfv u32 vfta_bit_in_reg = 0; 1057169240Sjfv 1058169240Sjfv DEBUGFUNC("e1000_clear_vfta_82571"); 1059169240Sjfv 1060169240Sjfv if (hw->mac.type == e1000_82573) { 1061169240Sjfv if (hw->mng_cookie.vlan_id != 0) { 1062173788Sjfv /* 1063173788Sjfv * The VFTA is a 4096b bit-field, each identifying 1064169240Sjfv * a single VLAN ID. The following operations 1065169240Sjfv * determine which 32b entry (i.e. offset) into the 1066169240Sjfv * array we want to set the VLAN ID (i.e. bit) of 1067169240Sjfv * the manageability unit. 1068169240Sjfv */ 1069169240Sjfv vfta_offset = (hw->mng_cookie.vlan_id >> 1070169240Sjfv E1000_VFTA_ENTRY_SHIFT) & 1071169240Sjfv E1000_VFTA_ENTRY_MASK; 1072169240Sjfv vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 1073169240Sjfv E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 1074169240Sjfv } 1075169240Sjfv } 1076169240Sjfv for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 1077173788Sjfv /* 1078173788Sjfv * If the offset we want to clear is the same offset of the 1079169240Sjfv * manageability VLAN ID, then clear all bits except that of 1080169240Sjfv * the manageability unit. 1081169240Sjfv */ 1082169240Sjfv vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 1083169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); 1084169240Sjfv E1000_WRITE_FLUSH(hw); 1085169240Sjfv } 1086169240Sjfv} 1087169240Sjfv 1088169240Sjfv/** 1089173788Sjfv * e1000_update_mc_addr_list_82571 - Update Multicast addresses 1090169589Sjfv * @hw: pointer to the HW structure 1091169589Sjfv * @mc_addr_list: array of multicast addresses to program 1092169589Sjfv * @mc_addr_count: number of multicast addresses to program 1093169589Sjfv * @rar_used_count: the first RAR register free to program 1094169589Sjfv * @rar_count: total number of supported Receive Address Registers 1095169240Sjfv * 1096169240Sjfv * Updates the Receive Address Registers and Multicast Table Array. 1097169240Sjfv * The caller must have a packed mc_addr_list of multicast addresses. 1098169240Sjfv * The parameter rar_count will usually be hw->mac.rar_entry_count 1099169240Sjfv * unless there are workarounds that change this. 1100169240Sjfv **/ 1101173788SjfvSTATIC void e1000_update_mc_addr_list_82571(struct e1000_hw *hw, 1102173788Sjfv u8 *mc_addr_list, u32 mc_addr_count, 1103173788Sjfv u32 rar_used_count, u32 rar_count) 1104169240Sjfv{ 1105173788Sjfv DEBUGFUNC("e1000_update_mc_addr_list_82571"); 1106169240Sjfv 1107169240Sjfv if (e1000_get_laa_state_82571(hw)) 1108169240Sjfv rar_count--; 1109169240Sjfv 1110173788Sjfv e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count, 1111169240Sjfv rar_used_count, rar_count); 1112169240Sjfv} 1113169240Sjfv 1114169240Sjfv/** 1115169240Sjfv * e1000_setup_link_82571 - Setup flow control and link settings 1116169589Sjfv * @hw: pointer to the HW structure 1117169240Sjfv * 1118169240Sjfv * Determines which flow control settings to use, then configures flow 1119169240Sjfv * control. Calls the appropriate media-specific link configuration 1120169240Sjfv * function. Assuming the adapter has a valid link partner, a valid link 1121169240Sjfv * should be established. Assumes the hardware has previously been reset 1122169240Sjfv * and the transmitter and receiver are not enabled. 1123169240Sjfv **/ 1124173788SjfvSTATIC s32 e1000_setup_link_82571(struct e1000_hw *hw) 1125169240Sjfv{ 1126169240Sjfv DEBUGFUNC("e1000_setup_link_82571"); 1127169240Sjfv 1128173788Sjfv /* 1129173788Sjfv * 82573 does not have a word in the NVM to determine 1130169240Sjfv * the default flow control setting, so we explicitly 1131169240Sjfv * set it to full. 1132169240Sjfv */ 1133169240Sjfv if (hw->mac.type == e1000_82573) 1134173788Sjfv hw->fc.type = e1000_fc_full; 1135169240Sjfv 1136169240Sjfv return e1000_setup_link_generic(hw); 1137169240Sjfv} 1138169240Sjfv 1139169240Sjfv/** 1140169240Sjfv * e1000_setup_copper_link_82571 - Configure copper link settings 1141169589Sjfv * @hw: pointer to the HW structure 1142169240Sjfv * 1143169240Sjfv * Configures the link for auto-neg or forced speed and duplex. Then we check 1144169240Sjfv * for link, once link is established calls to configure collision distance 1145169240Sjfv * and flow control are called. 1146169240Sjfv **/ 1147173788SjfvSTATIC s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) 1148169240Sjfv{ 1149169240Sjfv u32 ctrl, led_ctrl; 1150169240Sjfv s32 ret_val; 1151169240Sjfv 1152169240Sjfv DEBUGFUNC("e1000_setup_copper_link_82571"); 1153169240Sjfv 1154169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1155169240Sjfv ctrl |= E1000_CTRL_SLU; 1156169240Sjfv ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1157169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1158169240Sjfv 1159169240Sjfv switch (hw->phy.type) { 1160169240Sjfv case e1000_phy_m88: 1161169240Sjfv ret_val = e1000_copper_link_setup_m88(hw); 1162169240Sjfv break; 1163169240Sjfv case e1000_phy_igp_2: 1164169240Sjfv ret_val = e1000_copper_link_setup_igp(hw); 1165169240Sjfv /* Setup activity LED */ 1166169240Sjfv led_ctrl = E1000_READ_REG(hw, E1000_LEDCTL); 1167169240Sjfv led_ctrl &= IGP_ACTIVITY_LED_MASK; 1168169240Sjfv led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1169169240Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, led_ctrl); 1170169240Sjfv break; 1171169240Sjfv default: 1172169240Sjfv ret_val = -E1000_ERR_PHY; 1173169240Sjfv break; 1174169240Sjfv } 1175169240Sjfv 1176169240Sjfv if (ret_val) 1177169240Sjfv goto out; 1178169240Sjfv 1179169240Sjfv ret_val = e1000_setup_copper_link_generic(hw); 1180169240Sjfv 1181169240Sjfvout: 1182169240Sjfv return ret_val; 1183169240Sjfv} 1184169240Sjfv 1185169240Sjfv/** 1186169240Sjfv * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes 1187169589Sjfv * @hw: pointer to the HW structure 1188169240Sjfv * 1189169240Sjfv * Configures collision distance and flow control for fiber and serdes links. 1190169240Sjfv * Upon successful setup, poll for link. 1191169240Sjfv **/ 1192173788SjfvSTATIC s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) 1193169240Sjfv{ 1194169240Sjfv DEBUGFUNC("e1000_setup_fiber_serdes_link_82571"); 1195169240Sjfv 1196169240Sjfv switch (hw->mac.type) { 1197169240Sjfv case e1000_82571: 1198169240Sjfv case e1000_82572: 1199173788Sjfv /* 1200173788Sjfv * If SerDes loopback mode is entered, there is no form 1201169240Sjfv * of reset to take the adapter out of that mode. So we 1202169240Sjfv * have to explicitly take the adapter out of loopback 1203169240Sjfv * mode. This prevents drivers from twidling their thumbs 1204169240Sjfv * if another tool failed to take it out of loopback mode. 1205169240Sjfv */ 1206169240Sjfv E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1207169240Sjfv break; 1208169240Sjfv default: 1209169240Sjfv break; 1210169240Sjfv } 1211169240Sjfv 1212169240Sjfv return e1000_setup_fiber_serdes_link_generic(hw); 1213169240Sjfv} 1214169240Sjfv 1215169240Sjfv/** 1216169240Sjfv * e1000_valid_led_default_82571 - Verify a valid default LED config 1217169589Sjfv * @hw: pointer to the HW structure 1218169589Sjfv * @data: pointer to the NVM (EEPROM) 1219169240Sjfv * 1220169240Sjfv * Read the EEPROM for the current default LED configuration. If the 1221169240Sjfv * LED configuration is not valid, set to a valid LED configuration. 1222169240Sjfv **/ 1223173788SjfvSTATIC s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) 1224169240Sjfv{ 1225169240Sjfv s32 ret_val; 1226169240Sjfv 1227169240Sjfv DEBUGFUNC("e1000_valid_led_default_82571"); 1228169240Sjfv 1229169240Sjfv ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 1230169240Sjfv if (ret_val) { 1231169240Sjfv DEBUGOUT("NVM Read Error\n"); 1232169240Sjfv goto out; 1233169240Sjfv } 1234169240Sjfv 1235169240Sjfv if (hw->mac.type == e1000_82573 && 1236169240Sjfv *data == ID_LED_RESERVED_F746) 1237169240Sjfv *data = ID_LED_DEFAULT_82573; 1238169240Sjfv else if (*data == ID_LED_RESERVED_0000 || 1239169240Sjfv *data == ID_LED_RESERVED_FFFF) 1240169240Sjfv *data = ID_LED_DEFAULT; 1241169240Sjfvout: 1242169240Sjfv return ret_val; 1243169240Sjfv} 1244169240Sjfv 1245169240Sjfv/** 1246169240Sjfv * e1000_get_laa_state_82571 - Get locally administered address state 1247169589Sjfv * @hw: pointer to the HW structure 1248169240Sjfv * 1249169240Sjfv * Retrieve and return the current locally administed address state. 1250169240Sjfv **/ 1251173788Sjfvbool e1000_get_laa_state_82571(struct e1000_hw *hw) 1252169240Sjfv{ 1253169240Sjfv struct e1000_dev_spec_82571 *dev_spec; 1254173788Sjfv bool state = FALSE; 1255169240Sjfv 1256169240Sjfv DEBUGFUNC("e1000_get_laa_state_82571"); 1257169240Sjfv 1258169240Sjfv if (hw->mac.type != e1000_82571) 1259169240Sjfv goto out; 1260169240Sjfv 1261169240Sjfv dev_spec = (struct e1000_dev_spec_82571 *)hw->dev_spec; 1262169240Sjfv 1263169240Sjfv state = dev_spec->laa_is_present; 1264169240Sjfv 1265169240Sjfvout: 1266169240Sjfv return state; 1267169240Sjfv} 1268169240Sjfv 1269169240Sjfv/** 1270169240Sjfv * e1000_set_laa_state_82571 - Set locally administered address state 1271169589Sjfv * @hw: pointer to the HW structure 1272169589Sjfv * @state: enable/disable locally administered address 1273169240Sjfv * 1274169240Sjfv * Enable/Disable the current locally administed address state. 1275169240Sjfv **/ 1276173788Sjfvvoid e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) 1277169240Sjfv{ 1278169240Sjfv struct e1000_dev_spec_82571 *dev_spec; 1279169240Sjfv 1280169240Sjfv DEBUGFUNC("e1000_set_laa_state_82571"); 1281169240Sjfv 1282169240Sjfv if (hw->mac.type != e1000_82571) 1283169240Sjfv goto out; 1284169240Sjfv 1285169240Sjfv dev_spec = (struct e1000_dev_spec_82571 *)hw->dev_spec; 1286169240Sjfv 1287169240Sjfv dev_spec->laa_is_present = state; 1288169240Sjfv 1289169240Sjfv /* If workaround is activated... */ 1290173788Sjfv if (state) { 1291173788Sjfv /* 1292173788Sjfv * Hold a copy of the LAA in RAR[14] This is done so that 1293169240Sjfv * between the time RAR[0] gets clobbered and the time it 1294169240Sjfv * gets fixed, the actual LAA is in one of the RARs and no 1295169240Sjfv * incoming packets directed to this port are dropped. 1296169240Sjfv * Eventually the LAA will be in RAR[0] and RAR[14]. 1297169240Sjfv */ 1298169240Sjfv e1000_rar_set_generic(hw, hw->mac.addr, 1299169240Sjfv hw->mac.rar_entry_count - 1); 1300169240Sjfv } 1301169240Sjfv 1302169240Sjfvout: 1303169240Sjfv return; 1304169240Sjfv} 1305169240Sjfv 1306169240Sjfv/** 1307169240Sjfv * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum 1308169589Sjfv * @hw: pointer to the HW structure 1309169240Sjfv * 1310169240Sjfv * Verifies that the EEPROM has completed the update. After updating the 1311169240Sjfv * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If 1312169240Sjfv * the checksum fix is not implemented, we need to set the bit and update 1313169240Sjfv * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, 1314169240Sjfv * we need to return bad checksum. 1315169240Sjfv **/ 1316173788Sjfvstatic s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 1317169240Sjfv{ 1318169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 1319169240Sjfv s32 ret_val = E1000_SUCCESS; 1320169240Sjfv u16 data; 1321169240Sjfv 1322169240Sjfv DEBUGFUNC("e1000_fix_nvm_checksum_82571"); 1323169240Sjfv 1324169240Sjfv if (nvm->type != e1000_nvm_flash_hw) 1325169240Sjfv goto out; 1326169240Sjfv 1327173788Sjfv /* 1328173788Sjfv * Check bit 4 of word 10h. If it is 0, firmware is done updating 1329169240Sjfv * 10h-12h. Checksum may need to be fixed. 1330169240Sjfv */ 1331169240Sjfv ret_val = e1000_read_nvm(hw, 0x10, 1, &data); 1332169240Sjfv if (ret_val) 1333169240Sjfv goto out; 1334169240Sjfv 1335169240Sjfv if (!(data & 0x10)) { 1336173788Sjfv /* 1337173788Sjfv * Read 0x23 and check bit 15. This bit is a 1 1338169240Sjfv * when the checksum has already been fixed. If 1339169240Sjfv * the checksum is still wrong and this bit is a 1340169240Sjfv * 1, we need to return bad checksum. Otherwise, 1341169240Sjfv * we need to set this bit to a 1 and update the 1342169240Sjfv * checksum. 1343169240Sjfv */ 1344169240Sjfv ret_val = e1000_read_nvm(hw, 0x23, 1, &data); 1345169240Sjfv if (ret_val) 1346169240Sjfv goto out; 1347169240Sjfv 1348169240Sjfv if (!(data & 0x8000)) { 1349169240Sjfv data |= 0x8000; 1350169240Sjfv ret_val = e1000_write_nvm(hw, 0x23, 1, &data); 1351169240Sjfv if (ret_val) 1352169240Sjfv goto out; 1353169240Sjfv ret_val = e1000_update_nvm_checksum(hw); 1354169240Sjfv } 1355169240Sjfv } 1356169240Sjfv 1357169240Sjfvout: 1358169240Sjfv return ret_val; 1359169240Sjfv} 1360169240Sjfv 1361169240Sjfv/** 1362173788Sjfv * e1000_read_mac_addr_82571 - Read device MAC address 1363173788Sjfv * @hw: pointer to the HW structure 1364173788Sjfv **/ 1365173788SjfvSTATIC s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) 1366173788Sjfv{ 1367173788Sjfv s32 ret_val = E1000_SUCCESS; 1368173788Sjfv 1369173788Sjfv DEBUGFUNC("e1000_read_mac_addr_82571"); 1370173788Sjfv if (e1000_check_alt_mac_addr_generic(hw)) 1371173788Sjfv ret_val = e1000_read_mac_addr_generic(hw); 1372173788Sjfv 1373173788Sjfv return ret_val; 1374173788Sjfv} 1375173788Sjfv 1376173788Sjfv/** 1377173788Sjfv * e1000_power_down_phy_copper_82571 - Remove link during PHY power down 1378173788Sjfv * @hw: pointer to the HW structure 1379173788Sjfv * 1380173788Sjfv * In the case of a PHY power down to save power, or to turn off link during a 1381173788Sjfv * driver unload, or wake on lan is not enabled, remove the link. 1382173788Sjfv **/ 1383173788SjfvSTATIC void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) 1384173788Sjfv{ 1385173788Sjfv /* If the management interface is not enabled, then power down */ 1386173788Sjfv if (!(e1000_check_mng_mode(hw) || e1000_check_reset_block(hw))) 1387173788Sjfv e1000_power_down_phy_copper(hw); 1388173788Sjfv 1389173788Sjfv return; 1390173788Sjfv} 1391173788Sjfv 1392173788Sjfv/** 1393169240Sjfv * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters 1394169589Sjfv * @hw: pointer to the HW structure 1395169240Sjfv * 1396169240Sjfv * Clears the hardware counters by reading the counter registers. 1397169240Sjfv **/ 1398173788SjfvSTATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) 1399169240Sjfv{ 1400169240Sjfv volatile u32 temp; 1401169240Sjfv 1402169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_82571"); 1403169240Sjfv 1404169240Sjfv e1000_clear_hw_cntrs_base_generic(hw); 1405169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC64); 1406169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC127); 1407169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC255); 1408169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC511); 1409169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC1023); 1410169240Sjfv temp = E1000_READ_REG(hw, E1000_PRC1522); 1411169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC64); 1412169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC127); 1413169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC255); 1414169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC511); 1415169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC1023); 1416169240Sjfv temp = E1000_READ_REG(hw, E1000_PTC1522); 1417169240Sjfv 1418169240Sjfv temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1419169240Sjfv temp = E1000_READ_REG(hw, E1000_RXERRC); 1420169240Sjfv temp = E1000_READ_REG(hw, E1000_TNCRS); 1421169240Sjfv temp = E1000_READ_REG(hw, E1000_CEXTERR); 1422169240Sjfv temp = E1000_READ_REG(hw, E1000_TSCTC); 1423169240Sjfv temp = E1000_READ_REG(hw, E1000_TSCTFC); 1424169240Sjfv 1425169240Sjfv temp = E1000_READ_REG(hw, E1000_MGTPRC); 1426169240Sjfv temp = E1000_READ_REG(hw, E1000_MGTPDC); 1427169240Sjfv temp = E1000_READ_REG(hw, E1000_MGTPTC); 1428169240Sjfv 1429169240Sjfv temp = E1000_READ_REG(hw, E1000_IAC); 1430169240Sjfv temp = E1000_READ_REG(hw, E1000_ICRXOC); 1431169240Sjfv 1432169240Sjfv temp = E1000_READ_REG(hw, E1000_ICRXPTC); 1433169240Sjfv temp = E1000_READ_REG(hw, E1000_ICRXATC); 1434169240Sjfv temp = E1000_READ_REG(hw, E1000_ICTXPTC); 1435169240Sjfv temp = E1000_READ_REG(hw, E1000_ICTXATC); 1436169240Sjfv temp = E1000_READ_REG(hw, E1000_ICTXQEC); 1437169240Sjfv temp = E1000_READ_REG(hw, E1000_ICTXQMTC); 1438169240Sjfv temp = E1000_READ_REG(hw, E1000_ICRXDMTC); 1439169240Sjfv} 1440