e1000_82543.c revision 176667
1/******************************************************************************* 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33/* $FreeBSD: head/sys/dev/em/e1000_82543.c 176667 2008-02-29 21:50:11Z jfv $ */ 34 35 36/* e1000_82543 37 * e1000_82544 38 */ 39 40#include "e1000_api.h" 41#include "e1000_82543.h" 42 43STATIC s32 e1000_init_phy_params_82543(struct e1000_hw *hw); 44STATIC s32 e1000_init_nvm_params_82543(struct e1000_hw *hw); 45STATIC s32 e1000_init_mac_params_82543(struct e1000_hw *hw); 46STATIC s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, 47 u16 *data); 48STATIC s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, 49 u16 data); 50STATIC s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw); 51STATIC s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw); 52STATIC s32 e1000_reset_hw_82543(struct e1000_hw *hw); 53STATIC s32 e1000_init_hw_82543(struct e1000_hw *hw); 54STATIC s32 e1000_setup_link_82543(struct e1000_hw *hw); 55STATIC s32 e1000_setup_copper_link_82543(struct e1000_hw *hw); 56STATIC s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw); 57STATIC s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw); 58STATIC s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw); 59STATIC s32 e1000_led_on_82543(struct e1000_hw *hw); 60STATIC s32 e1000_led_off_82543(struct e1000_hw *hw); 61STATIC void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, 62 u32 value); 63STATIC void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value); 64STATIC void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw); 65static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw); 66static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw); 67static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 68static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw); 69static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 70static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw); 71static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 72 u16 count); 73static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw); 74static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state); 75 76struct e1000_dev_spec_82543 { 77 u32 tbi_compatibility; 78 bool dma_fairness; 79 bool init_phy_disabled; 80}; 81 82/** 83 * e1000_init_phy_params_82543 - Init PHY func ptrs. 84 * @hw: pointer to the HW structure 85 * 86 * This is a function pointer entry point called by the api module. 87 **/ 88STATIC s32 e1000_init_phy_params_82543(struct e1000_hw *hw) 89{ 90 struct e1000_phy_info *phy = &hw->phy; 91 struct e1000_functions *func = &hw->func; 92 s32 ret_val = E1000_SUCCESS; 93 94 DEBUGFUNC("e1000_init_phy_params_82543"); 95 96 if (hw->phy.media_type != e1000_media_type_copper) { 97 phy->type = e1000_phy_none; 98 goto out; 99 } else { 100 func->power_up_phy = e1000_power_up_phy_copper; 101 func->power_down_phy = e1000_power_down_phy_copper; 102 } 103 104 phy->addr = 1; 105 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 106 phy->reset_delay_us = 10000; 107 phy->type = e1000_phy_m88; 108 109 /* Function Pointers */ 110 func->check_polarity = e1000_check_polarity_m88; 111 func->commit_phy = e1000_phy_sw_reset_generic; 112 func->force_speed_duplex = e1000_phy_force_speed_duplex_82543; 113 func->get_cable_length = e1000_get_cable_length_m88; 114 func->get_cfg_done = e1000_get_cfg_done_generic; 115 func->read_phy_reg = (hw->mac.type == e1000_82543) 116 ? e1000_read_phy_reg_82543 117 : e1000_read_phy_reg_m88; 118 func->reset_phy = (hw->mac.type == e1000_82543) 119 ? e1000_phy_hw_reset_82543 120 : e1000_phy_hw_reset_generic; 121 func->write_phy_reg = (hw->mac.type == e1000_82543) 122 ? e1000_write_phy_reg_82543 123 : e1000_write_phy_reg_m88; 124 func->get_phy_info = e1000_get_phy_info_m88; 125 126 /* 127 * The external PHY of the 82543 can be in a funky state. 128 * Resetting helps us read the PHY registers for acquiring 129 * the PHY ID. 130 */ 131 if (!e1000_init_phy_disabled_82543(hw)) { 132 ret_val = e1000_phy_hw_reset(hw); 133 if (ret_val) { 134 DEBUGOUT("Resetting PHY during init failed.\n"); 135 goto out; 136 } 137 msec_delay(20); 138 } 139 140 ret_val = e1000_get_phy_id(hw); 141 if (ret_val) 142 goto out; 143 144 /* Verify phy id */ 145 switch (hw->mac.type) { 146 case e1000_82543: 147 if (phy->id != M88E1000_E_PHY_ID) { 148 ret_val = -E1000_ERR_PHY; 149 goto out; 150 } 151 break; 152 case e1000_82544: 153 if (phy->id != M88E1000_I_PHY_ID) { 154 ret_val = -E1000_ERR_PHY; 155 goto out; 156 } 157 break; 158 default: 159 ret_val = -E1000_ERR_PHY; 160 goto out; 161 break; 162 } 163 164out: 165 return ret_val; 166} 167 168/** 169 * e1000_init_nvm_params_82543 - Init NVM func ptrs. 170 * @hw: pointer to the HW structure 171 * 172 * This is a function pointer entry point called by the api module. 173 **/ 174STATIC s32 e1000_init_nvm_params_82543(struct e1000_hw *hw) 175{ 176 struct e1000_nvm_info *nvm = &hw->nvm; 177 struct e1000_functions *func = &hw->func; 178 179 DEBUGFUNC("e1000_init_nvm_params_82543"); 180 181 nvm->type = e1000_nvm_eeprom_microwire; 182 nvm->word_size = 64; 183 nvm->delay_usec = 50; 184 nvm->address_bits = 6; 185 nvm->opcode_bits = 3; 186 187 /* Function Pointers */ 188 func->read_nvm = e1000_read_nvm_microwire; 189 func->update_nvm = e1000_update_nvm_checksum_generic; 190 func->valid_led_default = e1000_valid_led_default_generic; 191 func->validate_nvm = e1000_validate_nvm_checksum_generic; 192 func->write_nvm = e1000_write_nvm_microwire; 193 194 return E1000_SUCCESS; 195} 196 197/** 198 * e1000_init_mac_params_82543 - Init MAC func ptrs. 199 * @hw: pointer to the HW structure 200 * 201 * This is a function pointer entry point called by the api module. 202 **/ 203STATIC s32 e1000_init_mac_params_82543(struct e1000_hw *hw) 204{ 205 struct e1000_mac_info *mac = &hw->mac; 206 struct e1000_functions *func = &hw->func; 207 s32 ret_val; 208 209 DEBUGFUNC("e1000_init_mac_params_82543"); 210 211 /* Set media type */ 212 switch (hw->device_id) { 213 case E1000_DEV_ID_82543GC_FIBER: 214 case E1000_DEV_ID_82544EI_FIBER: 215 hw->phy.media_type = e1000_media_type_fiber; 216 break; 217 default: 218 hw->phy.media_type = e1000_media_type_copper; 219 break; 220 } 221 222 /* Set mta register count */ 223 mac->mta_reg_count = 128; 224 /* Set rar entry count */ 225 mac->rar_entry_count = E1000_RAR_ENTRIES; 226 227 /* Function pointers */ 228 229 /* bus type/speed/width */ 230 func->get_bus_info = e1000_get_bus_info_pci_generic; 231 /* reset */ 232 func->reset_hw = e1000_reset_hw_82543; 233 /* hw initialization */ 234 func->init_hw = e1000_init_hw_82543; 235 /* link setup */ 236 func->setup_link = e1000_setup_link_82543; 237 /* physical interface setup */ 238 func->setup_physical_interface = 239 (hw->phy.media_type == e1000_media_type_copper) 240 ? e1000_setup_copper_link_82543 241 : e1000_setup_fiber_link_82543; 242 /* check for link */ 243 func->check_for_link = 244 (hw->phy.media_type == e1000_media_type_copper) 245 ? e1000_check_for_copper_link_82543 246 : e1000_check_for_fiber_link_82543; 247 /* link info */ 248 func->get_link_up_info = 249 (hw->phy.media_type == e1000_media_type_copper) 250 ? e1000_get_speed_and_duplex_copper_generic 251 : e1000_get_speed_and_duplex_fiber_serdes_generic; 252 /* multicast address update */ 253 func->update_mc_addr_list = e1000_update_mc_addr_list_generic; 254 /* writing VFTA */ 255 func->write_vfta = e1000_write_vfta_82543; 256 /* clearing VFTA */ 257 func->clear_vfta = e1000_clear_vfta_generic; 258 /* setting MTA */ 259 func->mta_set = e1000_mta_set_82543; 260 /* turn on/off LED */ 261 func->led_on = e1000_led_on_82543; 262 func->led_off = e1000_led_off_82543; 263 /* remove device */ 264 func->remove_device = e1000_remove_device_generic; 265 /* clear hardware counters */ 266 func->clear_hw_cntrs = e1000_clear_hw_cntrs_82543; 267 268 hw->dev_spec_size = sizeof(struct e1000_dev_spec_82543); 269 270 /* Device-specific structure allocation */ 271 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 272 if (ret_val) 273 goto out; 274 275 /* Set tbi compatibility */ 276 if ((hw->mac.type != e1000_82543) || 277 (hw->phy.media_type == e1000_media_type_fiber)) 278 e1000_set_tbi_compatibility_82543(hw, FALSE); 279 280out: 281 return ret_val; 282} 283 284/** 285 * e1000_init_function_pointers_82543 - Init func ptrs. 286 * @hw: pointer to the HW structure 287 * 288 * The only function explicitly called by the api module to initialize 289 * all function pointers and parameters. 290 **/ 291void e1000_init_function_pointers_82543(struct e1000_hw *hw) 292{ 293 DEBUGFUNC("e1000_init_function_pointers_82543"); 294 295 hw->func.init_mac_params = e1000_init_mac_params_82543; 296 hw->func.init_nvm_params = e1000_init_nvm_params_82543; 297 hw->func.init_phy_params = e1000_init_phy_params_82543; 298} 299 300/** 301 * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status 302 * @hw: pointer to the HW structure 303 * 304 * Returns the current status of 10-bit Interface (TBI) compatibility 305 * (enabled/disabled). 306 **/ 307static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw) 308{ 309 struct e1000_dev_spec_82543 *dev_spec; 310 bool state = FALSE; 311 312 DEBUGFUNC("e1000_tbi_compatibility_enabled_82543"); 313 314 if (hw->mac.type != e1000_82543) { 315 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 316 goto out; 317 } 318 319 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 320 321 if (!dev_spec) { 322 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 323 goto out; 324 } 325 326 state = (dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED) 327 ? TRUE : FALSE; 328 329out: 330 return state; 331} 332 333/** 334 * e1000_set_tbi_compatibility_82543 - Set TBI compatibility 335 * @hw: pointer to the HW structure 336 * @state: enable/disable TBI compatibility 337 * 338 * Enables or disabled 10-bit Interface (TBI) compatibility. 339 **/ 340void e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state) 341{ 342 struct e1000_dev_spec_82543 *dev_spec; 343 344 DEBUGFUNC("e1000_set_tbi_compatibility_82543"); 345 346 if (hw->mac.type != e1000_82543) { 347 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 348 goto out; 349 } 350 351 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 352 353 if (!dev_spec) { 354 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 355 goto out; 356 } 357 358 if (state) 359 dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED; 360 else 361 dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED; 362 363out: 364 return; 365} 366 367/** 368 * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status 369 * @hw: pointer to the HW structure 370 * 371 * Returns the current status of 10-bit Interface (TBI) store bad packet (SBP) 372 * (enabled/disabled). 373 **/ 374bool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw) 375{ 376 struct e1000_dev_spec_82543 *dev_spec; 377 bool state = FALSE; 378 379 DEBUGFUNC("e1000_tbi_sbp_enabled_82543"); 380 381 if (hw->mac.type != e1000_82543) { 382 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 383 goto out; 384 } 385 386 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 387 388 if (!dev_spec) { 389 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 390 goto out; 391 } 392 393 state = (dev_spec->tbi_compatibility & TBI_SBP_ENABLED) 394 ? TRUE : FALSE; 395 396out: 397 return state; 398} 399 400/** 401 * e1000_set_tbi_sbp_82543 - Set TBI SBP 402 * @hw: pointer to the HW structure 403 * @state: enable/disable TBI store bad packet 404 * 405 * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP). 406 **/ 407static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state) 408{ 409 struct e1000_dev_spec_82543 *dev_spec; 410 411 DEBUGFUNC("e1000_set_tbi_sbp_82543"); 412 413 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 414 415 if (state && e1000_tbi_compatibility_enabled_82543(hw)) 416 dev_spec->tbi_compatibility |= TBI_SBP_ENABLED; 417 else 418 dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED; 419 420 return; 421} 422 423/** 424 * e1000_init_phy_disabled_82543 - Returns init PHY status 425 * @hw: pointer to the HW structure 426 * 427 * Returns the current status of whether PHY initialization is disabled. 428 * True if PHY initialization is disabled else false. 429 **/ 430static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw) 431{ 432 struct e1000_dev_spec_82543 *dev_spec; 433 bool ret_val; 434 435 DEBUGFUNC("e1000_init_phy_disabled_82543"); 436 437 if (hw->mac.type != e1000_82543) { 438 ret_val = FALSE; 439 goto out; 440 } 441 442 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 443 444 if (!dev_spec) { 445 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 446 ret_val = FALSE; 447 goto out; 448 } 449 450 ret_val = dev_spec->init_phy_disabled; 451 452out: 453 return ret_val; 454} 455 456/** 457 * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled 458 * @hw: pointer to the HW structure 459 * @stats: Struct containing statistic register values 460 * @frame_len: The length of the frame in question 461 * @mac_addr: The Ethernet destination address of the frame in question 462 * @max_frame_size: The maximum frame size 463 * 464 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 465 **/ 466void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw, 467 struct e1000_hw_stats *stats, u32 frame_len, 468 u8 *mac_addr, u32 max_frame_size) 469{ 470 if (!(e1000_tbi_sbp_enabled_82543(hw))) 471 goto out; 472 473 /* First adjust the frame length. */ 474 frame_len--; 475 /* 476 * We need to adjust the statistics counters, since the hardware 477 * counters overcount this packet as a CRC error and undercount 478 * the packet as a good packet 479 */ 480 /* This packet should not be counted as a CRC error. */ 481 stats->crcerrs--; 482 /* This packet does count as a Good Packet Received. */ 483 stats->gprc++; 484 485 /* Adjust the Good Octets received counters */ 486 stats->gorc += frame_len; 487 488 /* 489 * Is this a broadcast or multicast? Check broadcast first, 490 * since the test for a multicast frame will test positive on 491 * a broadcast frame. 492 */ 493 if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff)) 494 /* Broadcast packet */ 495 stats->bprc++; 496 else if (*mac_addr & 0x01) 497 /* Multicast packet */ 498 stats->mprc++; 499 500 /* 501 * In this case, the hardware has overcounted the number of 502 * oversize frames. 503 */ 504 if ((frame_len == max_frame_size) && (stats->roc > 0)) 505 stats->roc--; 506 507 /* 508 * Adjust the bin counters when the extra byte put the frame in the 509 * wrong bin. Remember that the frame_len was adjusted above. 510 */ 511 if (frame_len == 64) { 512 stats->prc64++; 513 stats->prc127--; 514 } else if (frame_len == 127) { 515 stats->prc127++; 516 stats->prc255--; 517 } else if (frame_len == 255) { 518 stats->prc255++; 519 stats->prc511--; 520 } else if (frame_len == 511) { 521 stats->prc511++; 522 stats->prc1023--; 523 } else if (frame_len == 1023) { 524 stats->prc1023++; 525 stats->prc1522--; 526 } else if (frame_len == 1522) { 527 stats->prc1522++; 528 } 529 530out: 531 return; 532} 533 534/** 535 * e1000_read_phy_reg_82543 - Read PHY register 536 * @hw: pointer to the HW structure 537 * @offset: register offset to be read 538 * @data: pointer to the read data 539 * 540 * Reads the PHY at offset and stores the information read to data. 541 **/ 542STATIC s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data) 543{ 544 u32 mdic; 545 s32 ret_val = E1000_SUCCESS; 546 547 DEBUGFUNC("e1000_read_phy_reg_82543"); 548 549 if (offset > MAX_PHY_REG_ADDRESS) { 550 DEBUGOUT1("PHY Address %d is out of range\n", offset); 551 ret_val = -E1000_ERR_PARAM; 552 goto out; 553 } 554 555 /* 556 * We must first send a preamble through the MDIO pin to signal the 557 * beginning of an MII instruction. This is done by sending 32 558 * consecutive "1" bits. 559 */ 560 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 561 562 /* 563 * Now combine the next few fields that are required for a read 564 * operation. We use this method instead of calling the 565 * e1000_shift_out_mdi_bits routine five different times. The format 566 * of an MII read instruction consists of a shift out of 14 bits and 567 * is defined as follows: 568 * <Preamble><SOF><Op Code><Phy Addr><Offset> 569 * followed by a shift in of 18 bits. This first two bits shifted in 570 * are TurnAround bits used to avoid contention on the MDIO pin when a 571 * READ operation is performed. These two bits are thrown away 572 * followed by a shift in of 16 bits which contains the desired data. 573 */ 574 mdic = (offset | (hw->phy.addr << 5) | 575 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 576 577 e1000_shift_out_mdi_bits_82543(hw, mdic, 14); 578 579 /* 580 * Now that we've shifted out the read command to the MII, we need to 581 * "shift in" the 16-bit value (18 total bits) of the requested PHY 582 * register address. 583 */ 584 *data = e1000_shift_in_mdi_bits_82543(hw); 585 586out: 587 return ret_val; 588} 589 590/** 591 * e1000_write_phy_reg_82543 - Write PHY register 592 * @hw: pointer to the HW structure 593 * @offset: register offset to be written 594 * @data: pointer to the data to be written at offset 595 * 596 * Writes data to the PHY at offset. 597 **/ 598STATIC s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data) 599{ 600 u32 mdic; 601 s32 ret_val = E1000_SUCCESS; 602 603 DEBUGFUNC("e1000_write_phy_reg_82543"); 604 605 if (offset > MAX_PHY_REG_ADDRESS) { 606 DEBUGOUT1("PHY Address %d is out of range\n", offset); 607 ret_val = -E1000_ERR_PARAM; 608 goto out; 609 } 610 611 /* 612 * We'll need to use the SW defined pins to shift the write command 613 * out to the PHY. We first send a preamble to the PHY to signal the 614 * beginning of the MII instruction. This is done by sending 32 615 * consecutive "1" bits. 616 */ 617 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 618 619 /* 620 * Now combine the remaining required fields that will indicate a 621 * write operation. We use this method instead of calling the 622 * e1000_shift_out_mdi_bits routine for each field in the command. The 623 * format of a MII write instruction is as follows: 624 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 625 */ 626 mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) | 627 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 628 mdic <<= 16; 629 mdic |= (u32) data; 630 631 e1000_shift_out_mdi_bits_82543(hw, mdic, 32); 632 633out: 634 return ret_val; 635} 636 637/** 638 * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock 639 * @hw: pointer to the HW structure 640 * @ctrl: pointer to the control register 641 * 642 * Raise the management data input clock by setting the MDC bit in the control 643 * register. 644 **/ 645static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 646{ 647 /* 648 * Raise the clock input to the Management Data Clock (by setting the 649 * MDC bit), and then delay a sufficient amount of time. 650 */ 651 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC)); 652 E1000_WRITE_FLUSH(hw); 653 usec_delay(10); 654} 655 656/** 657 * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock 658 * @hw: pointer to the HW structure 659 * @ctrl: pointer to the control register 660 * 661 * Lower the management data input clock by clearing the MDC bit in the 662 * control register. 663 **/ 664static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 665{ 666 /* 667 * Lower the clock input to the Management Data Clock (by clearing the 668 * MDC bit), and then delay a sufficient amount of time. 669 */ 670 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC)); 671 E1000_WRITE_FLUSH(hw); 672 usec_delay(10); 673} 674 675/** 676 * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY 677 * @hw: pointer to the HW structure 678 * @data: data to send to the PHY 679 * @count: number of bits to shift out 680 * 681 * We need to shift 'count' bits out to the PHY. So, the value in the 682 * "data" parameter will be shifted out to the PHY one bit at a time. 683 * In order to do this, "data" must be broken down into bits. 684 **/ 685static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 686 u16 count) 687{ 688 u32 ctrl, mask; 689 690 /* 691 * We need to shift "count" number of bits out to the PHY. So, the 692 * value in the "data" parameter will be shifted out to the PHY one 693 * bit at a time. In order to do this, "data" must be broken down 694 * into bits. 695 */ 696 mask = 0x01; 697 mask <<= (count -1); 698 699 ctrl = E1000_READ_REG(hw, E1000_CTRL); 700 701 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 702 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 703 704 while (mask) { 705 /* 706 * A "1" is shifted out to the PHY by setting the MDIO bit to 707 * "1" and then raising and lowering the Management Data Clock. 708 * A "0" is shifted out to the PHY by setting the MDIO bit to 709 * "0" and then raising and lowering the clock. 710 */ 711 if (data & mask) ctrl |= E1000_CTRL_MDIO; 712 else ctrl &= ~E1000_CTRL_MDIO; 713 714 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 715 E1000_WRITE_FLUSH(hw); 716 717 usec_delay(10); 718 719 e1000_raise_mdi_clk_82543(hw, &ctrl); 720 e1000_lower_mdi_clk_82543(hw, &ctrl); 721 722 mask >>= 1; 723 } 724} 725 726/** 727 * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY 728 * @hw: pointer to the HW structure 729 * 730 * In order to read a register from the PHY, we need to shift 18 bits 731 * in from the PHY. Bits are "shifted in" by raising the clock input to 732 * the PHY (setting the MDC bit), and then reading the value of the data out 733 * MDIO bit. 734 **/ 735static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw) 736{ 737 u32 ctrl; 738 u16 data = 0; 739 u8 i; 740 741 /* 742 * In order to read a register from the PHY, we need to shift in a 743 * total of 18 bits from the PHY. The first two bit (turnaround) 744 * times are used to avoid contention on the MDIO pin when a read 745 * operation is performed. These two bits are ignored by us and 746 * thrown away. Bits are "shifted in" by raising the input to the 747 * Management Data Clock (setting the MDC bit) and then reading the 748 * value of the MDIO bit. 749 */ 750 ctrl = E1000_READ_REG(hw, E1000_CTRL); 751 752 /* 753 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 754 * input. 755 */ 756 ctrl &= ~E1000_CTRL_MDIO_DIR; 757 ctrl &= ~E1000_CTRL_MDIO; 758 759 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 760 E1000_WRITE_FLUSH(hw); 761 762 /* 763 * Raise and lower the clock before reading in the data. This accounts 764 * for the turnaround bits. The first clock occurred when we clocked 765 * out the last bit of the Register Address. 766 */ 767 e1000_raise_mdi_clk_82543(hw, &ctrl); 768 e1000_lower_mdi_clk_82543(hw, &ctrl); 769 770 for (data = 0, i = 0; i < 16; i++) { 771 data <<= 1; 772 e1000_raise_mdi_clk_82543(hw, &ctrl); 773 ctrl = E1000_READ_REG(hw, E1000_CTRL); 774 /* Check to see if we shifted in a "1". */ 775 if (ctrl & E1000_CTRL_MDIO) 776 data |= 1; 777 e1000_lower_mdi_clk_82543(hw, &ctrl); 778 } 779 780 e1000_raise_mdi_clk_82543(hw, &ctrl); 781 e1000_lower_mdi_clk_82543(hw, &ctrl); 782 783 return data; 784} 785 786/** 787 * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY 788 * @hw: pointer to the HW structure 789 * 790 * Calls the function to force speed and duplex for the m88 PHY, and 791 * if the PHY is not auto-negotiating and the speed is forced to 10Mbit, 792 * then call the function for polarity reversal workaround. 793 **/ 794STATIC s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw) 795{ 796 s32 ret_val; 797 798 DEBUGFUNC("e1000_phy_force_speed_duplex_82543"); 799 800 ret_val = e1000_phy_force_speed_duplex_m88(hw); 801 if (ret_val) 802 goto out; 803 804 if (!hw->mac.autoneg && 805 (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)) 806 ret_val = e1000_polarity_reversal_workaround_82543(hw); 807 808out: 809 return ret_val; 810} 811 812/** 813 * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal 814 * @hw: pointer to the HW structure 815 * 816 * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity 817 * inadvertently. To workaround the issue, we disable the transmitter on 818 * the PHY until we have established the link partner's link parameters. 819 **/ 820static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw) 821{ 822 s32 ret_val; 823 u16 mii_status_reg; 824 u16 i; 825 bool link; 826 827 /* Polarity reversal workaround for forced 10F/10H links. */ 828 829 /* Disable the transmitter on the PHY */ 830 831 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 832 if (ret_val) 833 goto out; 834 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 835 if (ret_val) 836 goto out; 837 838 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 839 if (ret_val) 840 goto out; 841 842 /* 843 * This loop will early-out if the NO link condition has been met. 844 * In other words, DO NOT use e1000_phy_has_link_generic() here. 845 */ 846 for (i = PHY_FORCE_TIME; i > 0; i--) { 847 /* 848 * Read the MII Status Register and wait for Link Status bit 849 * to be clear. 850 */ 851 852 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 853 if (ret_val) 854 goto out; 855 856 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 857 if (ret_val) 858 goto out; 859 860 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 861 break; 862 msec_delay_irq(100); 863 } 864 865 /* Recommended delay time after link has been lost */ 866 msec_delay_irq(1000); 867 868 /* Now we will re-enable the transmitter on the PHY */ 869 870 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 871 if (ret_val) 872 goto out; 873 msec_delay_irq(50); 874 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 875 if (ret_val) 876 goto out; 877 msec_delay_irq(50); 878 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 879 if (ret_val) 880 goto out; 881 msec_delay_irq(50); 882 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 883 if (ret_val) 884 goto out; 885 886 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 887 if (ret_val) 888 goto out; 889 890 /* 891 * Read the MII Status Register and wait for Link Status bit 892 * to be set. 893 */ 894 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link); 895 if (ret_val) 896 goto out; 897 898out: 899 return ret_val; 900} 901 902/** 903 * e1000_phy_hw_reset_82543 - PHY hardware reset 904 * @hw: pointer to the HW structure 905 * 906 * Sets the PHY_RESET_DIR bit in the extended device control register 907 * to put the PHY into a reset and waits for completion. Once the reset 908 * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out 909 * of reset. This is a function pointer entry point called by the api module. 910 **/ 911STATIC s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw) 912{ 913 struct e1000_functions *func = &hw->func; 914 u32 ctrl_ext; 915 s32 ret_val; 916 917 DEBUGFUNC("e1000_phy_hw_reset_82543"); 918 919 /* 920 * Read the Extended Device Control Register, assert the PHY_RESET_DIR 921 * bit to put the PHY into reset... 922 */ 923 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 924 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 925 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 926 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 927 E1000_WRITE_FLUSH(hw); 928 929 msec_delay(10); 930 931 /* ...then take it out of reset. */ 932 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 933 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 934 E1000_WRITE_FLUSH(hw); 935 936 usec_delay(150); 937 938 ret_val = func->get_cfg_done(hw); 939 940 return ret_val; 941} 942 943/** 944 * e1000_reset_hw_82543 - Reset hardware 945 * @hw: pointer to the HW structure 946 * 947 * This resets the hardware into a known state. This is a 948 * function pointer entry point called by the api module. 949 **/ 950STATIC s32 e1000_reset_hw_82543(struct e1000_hw *hw) 951{ 952 u32 ctrl, icr; 953 s32 ret_val = E1000_SUCCESS; 954 955 DEBUGFUNC("e1000_reset_hw_82543"); 956 957 DEBUGOUT("Masking off all interrupts\n"); 958 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 959 960 E1000_WRITE_REG(hw, E1000_RCTL, 0); 961 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 962 E1000_WRITE_FLUSH(hw); 963 964 e1000_set_tbi_sbp_82543(hw, FALSE); 965 966 /* 967 * Delay to allow any outstanding PCI transactions to complete before 968 * resetting the device 969 */ 970 msec_delay(10); 971 972 ctrl = E1000_READ_REG(hw, E1000_CTRL); 973 974 DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n"); 975 if (hw->mac.type == e1000_82543) { 976 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 977 } else { 978 /* 979 * The 82544 can't ACK the 64-bit write when issuing the 980 * reset, so use IO-mapping as a workaround. 981 */ 982 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 983 } 984 985 /* 986 * After MAC reset, force reload of NVM to restore power-on 987 * settings to device. 988 */ 989 e1000_reload_nvm(hw); 990 msec_delay(2); 991 992 /* Masking off and clearing any pending interrupts */ 993 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 994 icr = E1000_READ_REG(hw, E1000_ICR); 995 996 return ret_val; 997} 998 999/** 1000 * e1000_init_hw_82543 - Initialize hardware 1001 * @hw: pointer to the HW structure 1002 * 1003 * This inits the hardware readying it for operation. 1004 **/ 1005STATIC s32 e1000_init_hw_82543(struct e1000_hw *hw) 1006{ 1007 struct e1000_mac_info *mac = &hw->mac; 1008 struct e1000_dev_spec_82543 *dev_spec; 1009 u32 ctrl; 1010 s32 ret_val; 1011 u16 i; 1012 1013 DEBUGFUNC("e1000_init_hw_82543"); 1014 1015 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 1016 1017 if (!dev_spec) { 1018 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 1019 ret_val = -E1000_ERR_CONFIG; 1020 goto out; 1021 } 1022 1023 /* Disabling VLAN filtering */ 1024 E1000_WRITE_REG(hw, E1000_VET, 0); 1025 e1000_clear_vfta(hw); 1026 1027 /* Setup the receive address. */ 1028 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 1029 1030 /* Zero out the Multicast HASH table */ 1031 DEBUGOUT("Zeroing the MTA\n"); 1032 for (i = 0; i < mac->mta_reg_count; i++) { 1033 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1034 E1000_WRITE_FLUSH(hw); 1035 } 1036 1037 /* 1038 * Set the PCI priority bit correctly in the CTRL register. This 1039 * determines if the adapter gives priority to receives, or if it 1040 * gives equal priority to transmits and receives. 1041 */ 1042 if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) { 1043 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1044 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); 1045 } 1046 1047 e1000_pcix_mmrbc_workaround_generic(hw); 1048 1049 /* Setup link and flow control */ 1050 ret_val = e1000_setup_link(hw); 1051 1052 /* 1053 * Clear all of the statistics registers (clear on read). It is 1054 * important that we do this after we have tried to establish link 1055 * because the symbol error count will increment wildly if there 1056 * is no link. 1057 */ 1058 e1000_clear_hw_cntrs_82543(hw); 1059 1060out: 1061 return ret_val; 1062} 1063 1064/** 1065 * e1000_setup_link_82543 - Setup flow control and link settings 1066 * @hw: pointer to the HW structure 1067 * 1068 * Read the EEPROM to determine the initial polarity value and write the 1069 * extended device control register with the information before calling 1070 * the generic setup link function, which does the following: 1071 * Determines which flow control settings to use, then configures flow 1072 * control. Calls the appropriate media-specific link configuration 1073 * function. Assuming the adapter has a valid link partner, a valid link 1074 * should be established. Assumes the hardware has previously been reset 1075 * and the transmitter and receiver are not enabled. 1076 **/ 1077STATIC s32 e1000_setup_link_82543(struct e1000_hw *hw) 1078{ 1079 u32 ctrl_ext; 1080 s32 ret_val; 1081 u16 data; 1082 1083 DEBUGFUNC("e1000_setup_link_82543"); 1084 1085 /* 1086 * Take the 4 bits from NVM word 0xF that determine the initial 1087 * polarity value for the SW controlled pins, and setup the 1088 * Extended Device Control reg with that info. 1089 * This is needed because one of the SW controlled pins is used for 1090 * signal detection. So this should be done before phy setup. 1091 */ 1092 if (hw->mac.type == e1000_82543) { 1093 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1094 if (ret_val) { 1095 DEBUGOUT("NVM Read Error\n"); 1096 ret_val = -E1000_ERR_NVM; 1097 goto out; 1098 } 1099 ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) << 1100 NVM_SWDPIO_EXT_SHIFT); 1101 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1102 } 1103 1104 ret_val = e1000_setup_link_generic(hw); 1105 1106out: 1107 return ret_val; 1108} 1109 1110/** 1111 * e1000_setup_copper_link_82543 - Configure copper link settings 1112 * @hw: pointer to the HW structure 1113 * 1114 * Configures the link for auto-neg or forced speed and duplex. Then we check 1115 * for link, once link is established calls to configure collision distance 1116 * and flow control are called. 1117 **/ 1118STATIC s32 e1000_setup_copper_link_82543(struct e1000_hw *hw) 1119{ 1120 u32 ctrl; 1121 s32 ret_val; 1122 bool link; 1123 1124 DEBUGFUNC("e1000_setup_copper_link_82543"); 1125 1126 ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU; 1127 /* 1128 * With 82543, we need to force speed and duplex on the MAC 1129 * equal to what the PHY speed and duplex configuration is. 1130 * In addition, we need to perform a hardware reset on the 1131 * PHY to take it out of reset. 1132 */ 1133 if (hw->mac.type == e1000_82543) { 1134 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1135 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1136 ret_val = e1000_phy_hw_reset(hw); 1137 if (ret_val) 1138 goto out; 1139 hw->phy.reset_disable = FALSE; 1140 } else { 1141 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1142 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1143 } 1144 1145 /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */ 1146 ret_val = e1000_copper_link_setup_m88(hw); 1147 if (ret_val) 1148 goto out; 1149 1150 if (hw->mac.autoneg) { 1151 /* 1152 * Setup autoneg and flow control advertisement and perform 1153 * autonegotiation. 1154 */ 1155 ret_val = e1000_copper_link_autoneg(hw); 1156 if (ret_val) 1157 goto out; 1158 } else { 1159 /* 1160 * PHY will be set to 10H, 10F, 100H or 100F 1161 * depending on user settings. 1162 */ 1163 DEBUGOUT("Forcing Speed and Duplex\n"); 1164 ret_val = e1000_phy_force_speed_duplex_82543(hw); 1165 if (ret_val) { 1166 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1167 goto out; 1168 } 1169 } 1170 1171 /* 1172 * Check link status. Wait up to 100 microseconds for link to become 1173 * valid. 1174 */ 1175 ret_val = e1000_phy_has_link_generic(hw, 1176 COPPER_LINK_UP_LIMIT, 1177 10, 1178 &link); 1179 if (ret_val) 1180 goto out; 1181 1182 1183 if (link) { 1184 DEBUGOUT("Valid link established!!!\n"); 1185 /* Config the MAC and PHY after link is up */ 1186 if (hw->mac.type == e1000_82544) { 1187 e1000_config_collision_dist_generic(hw); 1188 } else { 1189 ret_val = e1000_config_mac_to_phy_82543(hw); 1190 if (ret_val) 1191 goto out; 1192 } 1193 ret_val = e1000_config_fc_after_link_up_generic(hw); 1194 } else { 1195 DEBUGOUT("Unable to establish link!!!\n"); 1196 } 1197 1198out: 1199 return ret_val; 1200} 1201 1202/** 1203 * e1000_setup_fiber_link_82543 - Setup link for fiber 1204 * @hw: pointer to the HW structure 1205 * 1206 * Configures collision distance and flow control for fiber links. Upon 1207 * successful setup, poll for link. 1208 **/ 1209STATIC s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw) 1210{ 1211 u32 ctrl; 1212 s32 ret_val; 1213 1214 DEBUGFUNC("e1000_setup_fiber_link_82543"); 1215 1216 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1217 1218 /* Take the link out of reset */ 1219 ctrl &= ~E1000_CTRL_LRST; 1220 1221 e1000_config_collision_dist_generic(hw); 1222 1223 ret_val = e1000_commit_fc_settings_generic(hw); 1224 if (ret_val) 1225 goto out; 1226 1227 DEBUGOUT("Auto-negotiation enabled\n"); 1228 1229 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1230 E1000_WRITE_FLUSH(hw); 1231 msec_delay(1); 1232 1233 /* 1234 * For these adapters, the SW definable pin 1 is cleared when the 1235 * optics detect a signal. If we have a signal, then poll for a 1236 * "Link-Up" indication. 1237 */ 1238 if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1239 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1240 } else { 1241 DEBUGOUT("No signal detected\n"); 1242 } 1243 1244out: 1245 return ret_val; 1246} 1247 1248/** 1249 * e1000_check_for_copper_link_82543 - Check for link (Copper) 1250 * @hw: pointer to the HW structure 1251 * 1252 * Checks the phy for link, if link exists, do the following: 1253 * - check for downshift 1254 * - do polarity workaround (if necessary) 1255 * - configure collision distance 1256 * - configure flow control after link up 1257 * - configure tbi compatibility 1258 **/ 1259STATIC s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw) 1260{ 1261 struct e1000_mac_info *mac = &hw->mac; 1262 u32 icr, rctl; 1263 s32 ret_val; 1264 u16 speed, duplex; 1265 bool link; 1266 1267 DEBUGFUNC("e1000_check_for_copper_link_82543"); 1268 1269 if (!mac->get_link_status) { 1270 ret_val = E1000_SUCCESS; 1271 goto out; 1272 } 1273 1274 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1275 if (ret_val) 1276 goto out; 1277 1278 if (!link) 1279 goto out; /* No link detected */ 1280 1281 mac->get_link_status = FALSE; 1282 1283 e1000_check_downshift_generic(hw); 1284 1285 /* 1286 * If we are forcing speed/duplex, then we can return since 1287 * we have already determined whether we have link or not. 1288 */ 1289 if (!mac->autoneg) { 1290 /* 1291 * If speed and duplex are forced to 10H or 10F, then we will 1292 * implement the polarity reversal workaround. We disable 1293 * interrupts first, and upon returning, place the devices 1294 * interrupt state to its previous value except for the link 1295 * status change interrupt which will happened due to the 1296 * execution of this workaround. 1297 */ 1298 if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) { 1299 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 1300 ret_val = e1000_polarity_reversal_workaround_82543(hw); 1301 icr = E1000_READ_REG(hw, E1000_ICR); 1302 E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC)); 1303 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 1304 } 1305 1306 ret_val = -E1000_ERR_CONFIG; 1307 goto out; 1308 } 1309 1310 /* 1311 * We have a M88E1000 PHY and Auto-Neg is enabled. If we 1312 * have Si on board that is 82544 or newer, Auto 1313 * Speed Detection takes care of MAC speed/duplex 1314 * configuration. So we only need to configure Collision 1315 * Distance in the MAC. Otherwise, we need to force 1316 * speed/duplex on the MAC to the current PHY speed/duplex 1317 * settings. 1318 */ 1319 if (mac->type == e1000_82544) 1320 e1000_config_collision_dist_generic(hw); 1321 else { 1322 ret_val = e1000_config_mac_to_phy_82543(hw); 1323 if (ret_val) { 1324 DEBUGOUT("Error configuring MAC to PHY settings\n"); 1325 goto out; 1326 } 1327 } 1328 1329 /* 1330 * Configure Flow Control now that Auto-Neg has completed. 1331 * First, we need to restore the desired flow control 1332 * settings because we may have had to re-autoneg with a 1333 * different link partner. 1334 */ 1335 ret_val = e1000_config_fc_after_link_up_generic(hw); 1336 if (ret_val) { 1337 DEBUGOUT("Error configuring flow control\n"); 1338 } 1339 1340 /* 1341 * At this point we know that we are on copper and we have 1342 * auto-negotiated link. These are conditions for checking the link 1343 * partner capability register. We use the link speed to determine if 1344 * TBI compatibility needs to be turned on or off. If the link is not 1345 * at gigabit speed, then TBI compatibility is not needed. If we are 1346 * at gigabit speed, we turn on TBI compatibility. 1347 */ 1348 if (e1000_tbi_compatibility_enabled_82543(hw)) { 1349 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 1350 if (ret_val) { 1351 DEBUGOUT("Error getting link speed and duplex\n"); 1352 return ret_val; 1353 } 1354 if (speed != SPEED_1000) { 1355 /* 1356 * If link speed is not set to gigabit speed, 1357 * we do not need to enable TBI compatibility. 1358 */ 1359 if (e1000_tbi_sbp_enabled_82543(hw)) { 1360 /* 1361 * If we previously were in the mode, 1362 * turn it off. 1363 */ 1364 e1000_set_tbi_sbp_82543(hw, FALSE); 1365 rctl = E1000_READ_REG(hw, E1000_RCTL); 1366 rctl &= ~E1000_RCTL_SBP; 1367 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1368 } 1369 } else { 1370 /* 1371 * If TBI compatibility is was previously off, 1372 * turn it on. For compatibility with a TBI link 1373 * partner, we will store bad packets. Some 1374 * frames have an additional byte on the end and 1375 * will look like CRC errors to to the hardware. 1376 */ 1377 if (!e1000_tbi_sbp_enabled_82543(hw)) { 1378 e1000_set_tbi_sbp_82543(hw, TRUE); 1379 rctl = E1000_READ_REG(hw, E1000_RCTL); 1380 rctl |= E1000_RCTL_SBP; 1381 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1382 } 1383 } 1384 } 1385out: 1386 return ret_val; 1387} 1388 1389/** 1390 * e1000_check_for_fiber_link_82543 - Check for link (Fiber) 1391 * @hw: pointer to the HW structure 1392 * 1393 * Checks for link up on the hardware. If link is not up and we have 1394 * a signal, then we need to force link up. 1395 **/ 1396STATIC s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw) 1397{ 1398 struct e1000_mac_info *mac = &hw->mac; 1399 u32 rxcw, ctrl, status; 1400 s32 ret_val = E1000_SUCCESS; 1401 1402 DEBUGFUNC("e1000_check_for_fiber_link_82543"); 1403 1404 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1405 status = E1000_READ_REG(hw, E1000_STATUS); 1406 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1407 1408 /* 1409 * If we don't have link (auto-negotiation failed or link partner 1410 * cannot auto-negotiate), the cable is plugged in (we have signal), 1411 * and our link partner is not trying to auto-negotiate with us (we 1412 * are receiving idles or data), we need to force link up. We also 1413 * need to give auto-negotiation time to complete, in case the cable 1414 * was just plugged in. The autoneg_failed flag does this. 1415 */ 1416 /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */ 1417 if ((!(ctrl & E1000_CTRL_SWDPIN1)) && 1418 (!(status & E1000_STATUS_LU)) && 1419 (!(rxcw & E1000_RXCW_C))) { 1420 if (mac->autoneg_failed == 0) { 1421 mac->autoneg_failed = 1; 1422 ret_val = 0; 1423 goto out; 1424 } 1425 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 1426 1427 /* Disable auto-negotiation in the TXCW register */ 1428 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 1429 1430 /* Force link-up and also force full-duplex. */ 1431 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1432 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1433 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1434 1435 /* Configure Flow Control after forcing link up. */ 1436 ret_val = e1000_config_fc_after_link_up_generic(hw); 1437 if (ret_val) { 1438 DEBUGOUT("Error configuring flow control\n"); 1439 goto out; 1440 } 1441 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 1442 /* 1443 * If we are forcing link and we are receiving /C/ ordered 1444 * sets, re-enable auto-negotiation in the TXCW register 1445 * and disable forced link in the Device Control register 1446 * in an attempt to auto-negotiate with our link partner. 1447 */ 1448 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 1449 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1450 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 1451 1452 mac->serdes_has_link = TRUE; 1453 } 1454 1455out: 1456 return ret_val; 1457} 1458 1459/** 1460 * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings 1461 * @hw: pointer to the HW structure 1462 * 1463 * For the 82543 silicon, we need to set the MAC to match the settings 1464 * of the PHY, even if the PHY is auto-negotiating. 1465 **/ 1466static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw) 1467{ 1468 u32 ctrl; 1469 s32 ret_val; 1470 u16 phy_data; 1471 1472 DEBUGFUNC("e1000_config_mac_to_phy_82543"); 1473 1474 /* Set the bits to force speed and duplex */ 1475 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1476 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1477 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1478 1479 /* 1480 * Set up duplex in the Device Control and Transmit Control 1481 * registers depending on negotiated values. 1482 */ 1483 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1484 if (ret_val) 1485 goto out; 1486 1487 ctrl &= ~E1000_CTRL_FD; 1488 if (phy_data & M88E1000_PSSR_DPLX) 1489 ctrl |= E1000_CTRL_FD; 1490 1491 e1000_config_collision_dist_generic(hw); 1492 1493 /* 1494 * Set up speed in the Device Control register depending on 1495 * negotiated values. 1496 */ 1497 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1498 ctrl |= E1000_CTRL_SPD_1000; 1499 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 1500 ctrl |= E1000_CTRL_SPD_100; 1501 1502 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1503 1504out: 1505 return ret_val; 1506} 1507 1508/** 1509 * e1000_write_vfta_82543 - Write value to VLAN filter table 1510 * @hw: pointer to the HW structure 1511 * @offset: the 32-bit offset in which to write the value to. 1512 * @value: the 32-bit value to write at location offset. 1513 * 1514 * This writes a 32-bit value to a 32-bit offset in the VLAN filter 1515 * table. 1516 **/ 1517STATIC void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value) 1518{ 1519 u32 temp; 1520 1521 DEBUGFUNC("e1000_write_vfta_82543"); 1522 1523 if ((hw->mac.type == e1000_82544) && (offset & 1)) { 1524 temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1); 1525 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 1526 E1000_WRITE_FLUSH(hw); 1527 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp); 1528 E1000_WRITE_FLUSH(hw); 1529 } else { 1530 e1000_write_vfta_generic(hw, offset, value); 1531 } 1532} 1533 1534/** 1535 * e1000_mta_set_82543 - Set multicast filter table address 1536 * @hw: pointer to the HW structure 1537 * @hash_value: determines the MTA register and bit to set 1538 * 1539 * The multicast table address is a register array of 32-bit registers. 1540 * The hash_value is used to determine what register the bit is in, the 1541 * current value is read, the new bit is OR'd in and the new value is 1542 * written back into the register. 1543 **/ 1544STATIC void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value) 1545{ 1546 u32 hash_bit, hash_reg, mta, temp; 1547 1548 DEBUGFUNC("e1000_mta_set_82543"); 1549 1550 hash_reg = (hash_value >> 5); 1551 1552 /* 1553 * If we are on an 82544 and we are trying to write an odd offset 1554 * in the MTA, save off the previous entry before writing and 1555 * restore the old value after writing. 1556 */ 1557 if ((hw->mac.type == e1000_82544) && (hash_reg & 1)) { 1558 hash_reg &= (hw->mac.mta_reg_count - 1); 1559 hash_bit = hash_value & 0x1F; 1560 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 1561 mta |= (1 << hash_bit); 1562 temp = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg - 1); 1563 1564 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 1565 E1000_WRITE_FLUSH(hw); 1566 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg - 1, temp); 1567 E1000_WRITE_FLUSH(hw); 1568 } else { 1569 e1000_mta_set_generic(hw, hash_value); 1570 } 1571} 1572 1573/** 1574 * e1000_led_on_82543 - Turn on SW controllable LED 1575 * @hw: pointer to the HW structure 1576 * 1577 * Turns the SW defined LED on. This is a function pointer entry point 1578 * called by the api module. 1579 **/ 1580STATIC s32 e1000_led_on_82543(struct e1000_hw *hw) 1581{ 1582 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1583 1584 DEBUGFUNC("e1000_led_on_82543"); 1585 1586 if (hw->mac.type == e1000_82544 && 1587 hw->phy.media_type == e1000_media_type_copper) { 1588 /* Clear SW-definable Pin 0 to turn on the LED */ 1589 ctrl &= ~E1000_CTRL_SWDPIN0; 1590 ctrl |= E1000_CTRL_SWDPIO0; 1591 } else { 1592 /* Fiber 82544 and all 82543 use this method */ 1593 ctrl |= E1000_CTRL_SWDPIN0; 1594 ctrl |= E1000_CTRL_SWDPIO0; 1595 } 1596 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1597 1598 return E1000_SUCCESS; 1599} 1600 1601/** 1602 * e1000_led_off_82543 - Turn off SW controllable LED 1603 * @hw: pointer to the HW structure 1604 * 1605 * Turns the SW defined LED off. This is a function pointer entry point 1606 * called by the api module. 1607 **/ 1608STATIC s32 e1000_led_off_82543(struct e1000_hw *hw) 1609{ 1610 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1611 1612 DEBUGFUNC("e1000_led_off_82543"); 1613 1614 if (hw->mac.type == e1000_82544 && 1615 hw->phy.media_type == e1000_media_type_copper) { 1616 /* Set SW-definable Pin 0 to turn off the LED */ 1617 ctrl |= E1000_CTRL_SWDPIN0; 1618 ctrl |= E1000_CTRL_SWDPIO0; 1619 } else { 1620 ctrl &= ~E1000_CTRL_SWDPIN0; 1621 ctrl |= E1000_CTRL_SWDPIO0; 1622 } 1623 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1624 1625 return E1000_SUCCESS; 1626} 1627 1628/** 1629 * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters 1630 * @hw: pointer to the HW structure 1631 * 1632 * Clears the hardware counters by reading the counter registers. 1633 **/ 1634STATIC void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw) 1635{ 1636 volatile u32 temp; 1637 1638 DEBUGFUNC("e1000_clear_hw_cntrs_82543"); 1639 1640 e1000_clear_hw_cntrs_base_generic(hw); 1641 1642 temp = E1000_READ_REG(hw, E1000_PRC64); 1643 temp = E1000_READ_REG(hw, E1000_PRC127); 1644 temp = E1000_READ_REG(hw, E1000_PRC255); 1645 temp = E1000_READ_REG(hw, E1000_PRC511); 1646 temp = E1000_READ_REG(hw, E1000_PRC1023); 1647 temp = E1000_READ_REG(hw, E1000_PRC1522); 1648 temp = E1000_READ_REG(hw, E1000_PTC64); 1649 temp = E1000_READ_REG(hw, E1000_PTC127); 1650 temp = E1000_READ_REG(hw, E1000_PTC255); 1651 temp = E1000_READ_REG(hw, E1000_PTC511); 1652 temp = E1000_READ_REG(hw, E1000_PTC1023); 1653 temp = E1000_READ_REG(hw, E1000_PTC1522); 1654 1655 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1656 temp = E1000_READ_REG(hw, E1000_RXERRC); 1657 temp = E1000_READ_REG(hw, E1000_TNCRS); 1658 temp = E1000_READ_REG(hw, E1000_CEXTERR); 1659 temp = E1000_READ_REG(hw, E1000_TSCTC); 1660 temp = E1000_READ_REG(hw, E1000_TSCTFC); 1661} 1662