e1000_82543.c revision 173788
1/******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33/* $FreeBSD: head/sys/dev/em/e1000_82543.c 173788 2007-11-20 21:41:22Z jfv $ */ 34 35 36/* e1000_82543 37 * e1000_82544 38 */ 39 40#include "e1000_api.h" 41#include "e1000_82543.h" 42 43void e1000_init_function_pointers_82543(struct e1000_hw *hw); 44 45STATIC s32 e1000_init_phy_params_82543(struct e1000_hw *hw); 46STATIC s32 e1000_init_nvm_params_82543(struct e1000_hw *hw); 47STATIC s32 e1000_init_mac_params_82543(struct e1000_hw *hw); 48STATIC s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, 49 u16 *data); 50STATIC s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, 51 u16 data); 52STATIC s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw); 53STATIC s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw); 54STATIC s32 e1000_reset_hw_82543(struct e1000_hw *hw); 55STATIC s32 e1000_init_hw_82543(struct e1000_hw *hw); 56STATIC s32 e1000_setup_link_82543(struct e1000_hw *hw); 57STATIC s32 e1000_setup_copper_link_82543(struct e1000_hw *hw); 58STATIC s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw); 59STATIC s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw); 60STATIC s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw); 61STATIC s32 e1000_led_on_82543(struct e1000_hw *hw); 62STATIC s32 e1000_led_off_82543(struct e1000_hw *hw); 63STATIC void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, 64 u32 value); 65STATIC void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value); 66STATIC void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw); 67static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw); 68static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw); 69static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 70static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw); 71static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 72static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw); 73static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 74 u16 count); 75static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw); 76static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state); 77 78struct e1000_dev_spec_82543 { 79 u32 tbi_compatibility; 80 bool dma_fairness; 81 bool init_phy_disabled; 82}; 83 84/** 85 * e1000_init_phy_params_82543 - Init PHY func ptrs. 86 * @hw: pointer to the HW structure 87 * 88 * This is a function pointer entry point called by the api module. 89 **/ 90STATIC s32 e1000_init_phy_params_82543(struct e1000_hw *hw) 91{ 92 struct e1000_phy_info *phy = &hw->phy; 93 struct e1000_functions *func = &hw->func; 94 s32 ret_val = E1000_SUCCESS; 95 96 DEBUGFUNC("e1000_init_phy_params_82543"); 97 98 if (hw->phy.media_type != e1000_media_type_copper) { 99 phy->type = e1000_phy_none; 100 goto out; 101 } else { 102 func->power_up_phy = e1000_power_up_phy_copper; 103 func->power_down_phy = e1000_power_down_phy_copper; 104 } 105 106 phy->addr = 1; 107 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 108 phy->reset_delay_us = 10000; 109 phy->type = e1000_phy_m88; 110 111 /* Function Pointers */ 112 func->check_polarity = e1000_check_polarity_m88; 113 func->commit_phy = e1000_phy_sw_reset_generic; 114 func->force_speed_duplex = e1000_phy_force_speed_duplex_82543; 115 func->get_cable_length = e1000_get_cable_length_m88; 116 func->get_cfg_done = e1000_get_cfg_done_generic; 117 func->read_phy_reg = (hw->mac.type == e1000_82543) 118 ? e1000_read_phy_reg_82543 119 : e1000_read_phy_reg_m88; 120 func->reset_phy = (hw->mac.type == e1000_82543) 121 ? e1000_phy_hw_reset_82543 122 : e1000_phy_hw_reset_generic; 123 func->write_phy_reg = (hw->mac.type == e1000_82543) 124 ? e1000_write_phy_reg_82543 125 : e1000_write_phy_reg_m88; 126 func->get_phy_info = e1000_get_phy_info_m88; 127 128 /* 129 * The external PHY of the 82543 can be in a funky state. 130 * Resetting helps us read the PHY registers for acquiring 131 * the PHY ID. 132 */ 133 if (!e1000_init_phy_disabled_82543(hw)) { 134 ret_val = e1000_phy_hw_reset(hw); 135 if (ret_val) { 136 DEBUGOUT("Resetting PHY during init failed.\n"); 137 goto out; 138 } 139 msec_delay(20); 140 } 141 142 ret_val = e1000_get_phy_id(hw); 143 if (ret_val) 144 goto out; 145 146 /* Verify phy id */ 147 switch (hw->mac.type) { 148 case e1000_82543: 149 if (phy->id != M88E1000_E_PHY_ID) { 150 ret_val = -E1000_ERR_PHY; 151 goto out; 152 } 153 break; 154 case e1000_82544: 155 if (phy->id != M88E1000_I_PHY_ID) { 156 ret_val = -E1000_ERR_PHY; 157 goto out; 158 } 159 break; 160 default: 161 ret_val = -E1000_ERR_PHY; 162 goto out; 163 break; 164 } 165 166out: 167 return ret_val; 168} 169 170/** 171 * e1000_init_nvm_params_82543 - Init NVM func ptrs. 172 * @hw: pointer to the HW structure 173 * 174 * This is a function pointer entry point called by the api module. 175 **/ 176STATIC s32 e1000_init_nvm_params_82543(struct e1000_hw *hw) 177{ 178 struct e1000_nvm_info *nvm = &hw->nvm; 179 struct e1000_functions *func = &hw->func; 180 181 DEBUGFUNC("e1000_init_nvm_params_82543"); 182 183 nvm->type = e1000_nvm_eeprom_microwire; 184 nvm->word_size = 64; 185 nvm->delay_usec = 50; 186 nvm->address_bits = 6; 187 nvm->opcode_bits = 3; 188 189 /* Function Pointers */ 190 func->read_nvm = e1000_read_nvm_microwire; 191 func->update_nvm = e1000_update_nvm_checksum_generic; 192 func->valid_led_default = e1000_valid_led_default_generic; 193 func->validate_nvm = e1000_validate_nvm_checksum_generic; 194 func->write_nvm = e1000_write_nvm_microwire; 195 196 return E1000_SUCCESS; 197} 198 199/** 200 * e1000_init_mac_params_82543 - Init MAC func ptrs. 201 * @hw: pointer to the HW structure 202 * 203 * This is a function pointer entry point called by the api module. 204 **/ 205STATIC s32 e1000_init_mac_params_82543(struct e1000_hw *hw) 206{ 207 struct e1000_mac_info *mac = &hw->mac; 208 struct e1000_functions *func = &hw->func; 209 s32 ret_val; 210 211 DEBUGFUNC("e1000_init_mac_params_82543"); 212 213 /* Set media type */ 214 switch (hw->device_id) { 215 case E1000_DEV_ID_82543GC_FIBER: 216 case E1000_DEV_ID_82544EI_FIBER: 217 hw->phy.media_type = e1000_media_type_fiber; 218 break; 219 default: 220 hw->phy.media_type = e1000_media_type_copper; 221 break; 222 } 223 224 /* Set mta register count */ 225 mac->mta_reg_count = 128; 226 /* Set rar entry count */ 227 mac->rar_entry_count = E1000_RAR_ENTRIES; 228 229 /* Function pointers */ 230 231 /* bus type/speed/width */ 232 func->get_bus_info = e1000_get_bus_info_pci_generic; 233 /* reset */ 234 func->reset_hw = e1000_reset_hw_82543; 235 /* hw initialization */ 236 func->init_hw = e1000_init_hw_82543; 237 /* link setup */ 238 func->setup_link = e1000_setup_link_82543; 239 /* physical interface setup */ 240 func->setup_physical_interface = 241 (hw->phy.media_type == e1000_media_type_copper) 242 ? e1000_setup_copper_link_82543 243 : e1000_setup_fiber_link_82543; 244 /* check for link */ 245 func->check_for_link = 246 (hw->phy.media_type == e1000_media_type_copper) 247 ? e1000_check_for_copper_link_82543 248 : e1000_check_for_fiber_link_82543; 249 /* link info */ 250 func->get_link_up_info = 251 (hw->phy.media_type == e1000_media_type_copper) 252 ? e1000_get_speed_and_duplex_copper_generic 253 : e1000_get_speed_and_duplex_fiber_serdes_generic; 254 /* multicast address update */ 255 func->update_mc_addr_list = e1000_update_mc_addr_list_generic; 256 /* writing VFTA */ 257 func->write_vfta = e1000_write_vfta_82543; 258 /* clearing VFTA */ 259 func->clear_vfta = e1000_clear_vfta_generic; 260 /* setting MTA */ 261 func->mta_set = e1000_mta_set_82543; 262 /* turn on/off LED */ 263 func->led_on = e1000_led_on_82543; 264 func->led_off = e1000_led_off_82543; 265 /* remove device */ 266 func->remove_device = e1000_remove_device_generic; 267 /* clear hardware counters */ 268 func->clear_hw_cntrs = e1000_clear_hw_cntrs_82543; 269 270 hw->dev_spec_size = sizeof(struct e1000_dev_spec_82543); 271 272 /* Device-specific structure allocation */ 273 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 274 if (ret_val) 275 goto out; 276 277 /* Set tbi compatibility */ 278 if ((hw->mac.type != e1000_82543) || 279 (hw->phy.media_type == e1000_media_type_fiber)) 280 e1000_set_tbi_compatibility_82543(hw, FALSE); 281 282out: 283 return ret_val; 284} 285 286/** 287 * e1000_init_function_pointers_82543 - Init func ptrs. 288 * @hw: pointer to the HW structure 289 * 290 * The only function explicitly called by the api module to initialize 291 * all function pointers and parameters. 292 **/ 293void e1000_init_function_pointers_82543(struct e1000_hw *hw) 294{ 295 DEBUGFUNC("e1000_init_function_pointers_82543"); 296 297 hw->func.init_mac_params = e1000_init_mac_params_82543; 298 hw->func.init_nvm_params = e1000_init_nvm_params_82543; 299 hw->func.init_phy_params = e1000_init_phy_params_82543; 300} 301 302/** 303 * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status 304 * @hw: pointer to the HW structure 305 * 306 * Returns the curent status of 10-bit Interface (TBI) compatibility 307 * (enabled/disabled). 308 **/ 309static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw) 310{ 311 struct e1000_dev_spec_82543 *dev_spec; 312 bool state = FALSE; 313 314 DEBUGFUNC("e1000_tbi_compatibility_enabled_82543"); 315 316 if (hw->mac.type != e1000_82543) { 317 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 318 goto out; 319 } 320 321 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 322 323 if (!dev_spec) { 324 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 325 goto out; 326 } 327 328 state = (dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED) 329 ? TRUE : FALSE; 330 331out: 332 return state; 333} 334 335/** 336 * e1000_set_tbi_compatibility_82543 - Set TBI compatibility 337 * @hw: pointer to the HW structure 338 * @state: enable/disable TBI compatibility 339 * 340 * Enables or disabled 10-bit Interface (TBI) compatibility. 341 **/ 342void e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state) 343{ 344 struct e1000_dev_spec_82543 *dev_spec; 345 346 DEBUGFUNC("e1000_set_tbi_compatibility_82543"); 347 348 if (hw->mac.type != e1000_82543) { 349 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 350 goto out; 351 } 352 353 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 354 355 if (!dev_spec) { 356 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 357 goto out; 358 } 359 360 if (state) 361 dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED; 362 else 363 dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED; 364 365out: 366 return; 367} 368 369/** 370 * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status 371 * @hw: pointer to the HW structure 372 * 373 * Returns the curent status of 10-bit Interface (TBI) store bad packet (SBP) 374 * (enabled/disabled). 375 **/ 376bool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw) 377{ 378 struct e1000_dev_spec_82543 *dev_spec; 379 bool state = FALSE; 380 381 DEBUGFUNC("e1000_tbi_sbp_enabled_82543"); 382 383 if (hw->mac.type != e1000_82543) { 384 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 385 goto out; 386 } 387 388 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 389 390 if (!dev_spec) { 391 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 392 goto out; 393 } 394 395 state = (dev_spec->tbi_compatibility & TBI_SBP_ENABLED) 396 ? TRUE : FALSE; 397 398out: 399 return state; 400} 401 402/** 403 * e1000_set_tbi_sbp_82543 - Set TBI SBP 404 * @hw: pointer to the HW structure 405 * @state: enable/disable TBI store bad packet 406 * 407 * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP). 408 **/ 409static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state) 410{ 411 struct e1000_dev_spec_82543 *dev_spec; 412 413 DEBUGFUNC("e1000_set_tbi_sbp_82543"); 414 415 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 416 417 if (state && e1000_tbi_compatibility_enabled_82543(hw)) 418 dev_spec->tbi_compatibility |= TBI_SBP_ENABLED; 419 else 420 dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED; 421 422 return; 423} 424 425/** 426 * e1000_init_phy_disabled_82543 - Returns init PHY status 427 * @hw: pointer to the HW structure 428 * 429 * Returns the current status of whether PHY initialization is disabled. 430 * True if PHY initialization is disabled else false. 431 **/ 432static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw) 433{ 434 struct e1000_dev_spec_82543 *dev_spec; 435 bool ret_val; 436 437 DEBUGFUNC("e1000_init_phy_disabled_82543"); 438 439 if (hw->mac.type != e1000_82543) { 440 ret_val = FALSE; 441 goto out; 442 } 443 444 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 445 446 if (!dev_spec) { 447 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 448 ret_val = FALSE; 449 goto out; 450 } 451 452 ret_val = dev_spec->init_phy_disabled; 453 454out: 455 return ret_val; 456} 457 458/** 459 * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled 460 * @hw: pointer to the HW structure 461 * @stats: Struct containing statistic register values 462 * @frame_len: The length of the frame in question 463 * @mac_addr: The Ethernet destination address of the frame in question 464 * @max_frame_size: The maximum frame size 465 * 466 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 467 **/ 468void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw, 469 struct e1000_hw_stats *stats, u32 frame_len, 470 u8 *mac_addr, u32 max_frame_size) 471{ 472 if (!(e1000_tbi_sbp_enabled_82543(hw))) 473 goto out; 474 475 /* First adjust the frame length. */ 476 frame_len--; 477 /* 478 * We need to adjust the statistics counters, since the hardware 479 * counters overcount this packet as a CRC error and undercount 480 * the packet as a good packet 481 */ 482 /* This packet should not be counted as a CRC error. */ 483 stats->crcerrs--; 484 /* This packet does count as a Good Packet Received. */ 485 stats->gprc++; 486 487 /* Adjust the Good Octets received counters */ 488 stats->gorc += frame_len; 489 490 /* 491 * Is this a broadcast or multicast? Check broadcast first, 492 * since the test for a multicast frame will test positive on 493 * a broadcast frame. 494 */ 495 if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff)) 496 /* Broadcast packet */ 497 stats->bprc++; 498 else if (*mac_addr & 0x01) 499 /* Multicast packet */ 500 stats->mprc++; 501 502 /* 503 * In this case, the hardware has overcounted the number of 504 * oversize frames. 505 */ 506 if ((frame_len == max_frame_size) && (stats->roc > 0)) 507 stats->roc--; 508 509 /* 510 * Adjust the bin counters when the extra byte put the frame in the 511 * wrong bin. Remember that the frame_len was adjusted above. 512 */ 513 if (frame_len == 64) { 514 stats->prc64++; 515 stats->prc127--; 516 } else if (frame_len == 127) { 517 stats->prc127++; 518 stats->prc255--; 519 } else if (frame_len == 255) { 520 stats->prc255++; 521 stats->prc511--; 522 } else if (frame_len == 511) { 523 stats->prc511++; 524 stats->prc1023--; 525 } else if (frame_len == 1023) { 526 stats->prc1023++; 527 stats->prc1522--; 528 } else if (frame_len == 1522) { 529 stats->prc1522++; 530 } 531 532out: 533 return; 534} 535 536/** 537 * e1000_read_phy_reg_82543 - Read PHY register 538 * @hw: pointer to the HW structure 539 * @offset: register offset to be read 540 * @data: pointer to the read data 541 * 542 * Reads the PHY at offset and stores the information read to data. 543 **/ 544STATIC s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data) 545{ 546 u32 mdic; 547 s32 ret_val = E1000_SUCCESS; 548 549 DEBUGFUNC("e1000_read_phy_reg_82543"); 550 551 if (offset > MAX_PHY_REG_ADDRESS) { 552 DEBUGOUT1("PHY Address %d is out of range\n", offset); 553 ret_val = -E1000_ERR_PARAM; 554 goto out; 555 } 556 557 /* 558 * We must first send a preamble through the MDIO pin to signal the 559 * beginning of an MII instruction. This is done by sending 32 560 * consecutive "1" bits. 561 */ 562 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 563 564 /* 565 * Now combine the next few fields that are required for a read 566 * operation. We use this method instead of calling the 567 * e1000_shift_out_mdi_bits routine five different times. The format 568 * of an MII read instruction consists of a shift out of 14 bits and 569 * is defined as follows: 570 * <Preamble><SOF><Op Code><Phy Addr><Offset> 571 * followed by a shift in of 18 bits. This first two bits shifted in 572 * are TurnAround bits used to avoid contention on the MDIO pin when a 573 * READ operation is performed. These two bits are thrown away 574 * followed by a shift in of 16 bits which contains the desired data. 575 */ 576 mdic = (offset | (hw->phy.addr << 5) | 577 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 578 579 e1000_shift_out_mdi_bits_82543(hw, mdic, 14); 580 581 /* 582 * Now that we've shifted out the read command to the MII, we need to 583 * "shift in" the 16-bit value (18 total bits) of the requested PHY 584 * register address. 585 */ 586 *data = e1000_shift_in_mdi_bits_82543(hw); 587 588out: 589 return ret_val; 590} 591 592/** 593 * e1000_write_phy_reg_82543 - Write PHY register 594 * @hw: pointer to the HW structure 595 * @offset: register offset to be written 596 * @data: pointer to the data to be written at offset 597 * 598 * Writes data to the PHY at offset. 599 **/ 600STATIC s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data) 601{ 602 u32 mdic; 603 s32 ret_val = E1000_SUCCESS; 604 605 DEBUGFUNC("e1000_write_phy_reg_82543"); 606 607 if (offset > MAX_PHY_REG_ADDRESS) { 608 DEBUGOUT1("PHY Address %d is out of range\n", offset); 609 ret_val = -E1000_ERR_PARAM; 610 goto out; 611 } 612 613 /* 614 * We'll need to use the SW defined pins to shift the write command 615 * out to the PHY. We first send a preamble to the PHY to signal the 616 * beginning of the MII instruction. This is done by sending 32 617 * consecutive "1" bits. 618 */ 619 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 620 621 /* 622 * Now combine the remaining required fields that will indicate a 623 * write operation. We use this method instead of calling the 624 * e1000_shift_out_mdi_bits routine for each field in the command. The 625 * format of a MII write instruction is as follows: 626 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 627 */ 628 mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) | 629 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 630 mdic <<= 16; 631 mdic |= (u32) data; 632 633 e1000_shift_out_mdi_bits_82543(hw, mdic, 32); 634 635out: 636 return ret_val; 637} 638 639/** 640 * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock 641 * @hw: pointer to the HW structure 642 * @ctrl: pointer to the control register 643 * 644 * Raise the management data input clock by setting the MDC bit in the control 645 * register. 646 **/ 647static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 648{ 649 /* 650 * Raise the clock input to the Management Data Clock (by setting the 651 * MDC bit), and then delay a sufficient amount of time. 652 */ 653 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC)); 654 E1000_WRITE_FLUSH(hw); 655 usec_delay(10); 656} 657 658/** 659 * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock 660 * @hw: pointer to the HW structure 661 * @ctrl: pointer to the control register 662 * 663 * Lower the management data input clock by clearing the MDC bit in the control 664 * register. 665 **/ 666static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 667{ 668 /* 669 * Lower the clock input to the Management Data Clock (by clearing the 670 * MDC bit), and then delay a sufficient amount of time. 671 */ 672 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC)); 673 E1000_WRITE_FLUSH(hw); 674 usec_delay(10); 675} 676 677/** 678 * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY 679 * @hw: pointer to the HW structure 680 * @data: data to send to the PHY 681 * @count: number of bits to shift out 682 * 683 * We need to shift 'count' bits out to the PHY. So, the value in the 684 * "data" parameter will be shifted out to the PHY one bit at a time. 685 * In order to do this, "data" must be broken down into bits. 686 **/ 687static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 688 u16 count) 689{ 690 u32 ctrl, mask; 691 692 /* 693 * We need to shift "count" number of bits out to the PHY. So, the 694 * value in the "data" parameter will be shifted out to the PHY one 695 * bit at a time. In order to do this, "data" must be broken down 696 * into bits. 697 */ 698 mask = 0x01; 699 mask <<= (count -1); 700 701 ctrl = E1000_READ_REG(hw, E1000_CTRL); 702 703 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 704 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 705 706 while (mask) { 707 /* 708 * A "1" is shifted out to the PHY by setting the MDIO bit to 709 * "1" and then raising and lowering the Management Data Clock. 710 * A "0" is shifted out to the PHY by setting the MDIO bit to 711 * "0" and then raising and lowering the clock. 712 */ 713 if (data & mask) ctrl |= E1000_CTRL_MDIO; 714 else ctrl &= ~E1000_CTRL_MDIO; 715 716 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 717 E1000_WRITE_FLUSH(hw); 718 719 usec_delay(10); 720 721 e1000_raise_mdi_clk_82543(hw, &ctrl); 722 e1000_lower_mdi_clk_82543(hw, &ctrl); 723 724 mask >>= 1; 725 } 726} 727 728/** 729 * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY 730 * @hw: pointer to the HW structure 731 * 732 * In order to read a register from the PHY, we need to shift 18 bits 733 * in from the PHY. Bits are "shifted in" by raising the clock input to 734 * the PHY (setting the MDC bit), and then reading the value of the data out 735 * MDIO bit. 736 **/ 737static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw) 738{ 739 u32 ctrl; 740 u16 data = 0; 741 u8 i; 742 743 /* 744 * In order to read a register from the PHY, we need to shift in a 745 * total of 18 bits from the PHY. The first two bit (turnaround) 746 * times are used to avoid contention on the MDIO pin when a read 747 * operation is performed. These two bits are ignored by us and 748 * thrown away. Bits are "shifted in" by raising the input to the 749 * Management Data Clock (setting the MDC bit) and then reading the 750 * value of the MDIO bit. 751 */ 752 ctrl = E1000_READ_REG(hw, E1000_CTRL); 753 754 /* 755 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 756 * input. 757 */ 758 ctrl &= ~E1000_CTRL_MDIO_DIR; 759 ctrl &= ~E1000_CTRL_MDIO; 760 761 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 762 E1000_WRITE_FLUSH(hw); 763 764 /* 765 * Raise and lower the clock before reading in the data. This accounts 766 * for the turnaround bits. The first clock occurred when we clocked 767 * out the last bit of the Register Address. 768 */ 769 e1000_raise_mdi_clk_82543(hw, &ctrl); 770 e1000_lower_mdi_clk_82543(hw, &ctrl); 771 772 for (data = 0, i = 0; i < 16; i++) { 773 data <<= 1; 774 e1000_raise_mdi_clk_82543(hw, &ctrl); 775 ctrl = E1000_READ_REG(hw, E1000_CTRL); 776 /* Check to see if we shifted in a "1". */ 777 if (ctrl & E1000_CTRL_MDIO) 778 data |= 1; 779 e1000_lower_mdi_clk_82543(hw, &ctrl); 780 } 781 782 e1000_raise_mdi_clk_82543(hw, &ctrl); 783 e1000_lower_mdi_clk_82543(hw, &ctrl); 784 785 return data; 786} 787 788/** 789 * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY 790 * @hw: pointer to the HW structure 791 * 792 * Calls the function to force speed and duplex for the m88 PHY, and 793 * if the PHY is not auto-negotiating and the speed is forced to 10Mbit, 794 * then call the function for polarity reversal workaround. 795 **/ 796STATIC s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw) 797{ 798 s32 ret_val; 799 800 DEBUGFUNC("e1000_phy_force_speed_duplex_82543"); 801 802 ret_val = e1000_phy_force_speed_duplex_m88(hw); 803 if (ret_val) 804 goto out; 805 806 if (!hw->mac.autoneg && 807 (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)) 808 ret_val = e1000_polarity_reversal_workaround_82543(hw); 809 810out: 811 return ret_val; 812} 813 814/** 815 * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal 816 * @hw: pointer to the HW structure 817 * 818 * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity 819 * inadvertantly. To workaround the issue, we disable the transmitter on 820 * the PHY until we have established the link partner's link parameters. 821 **/ 822static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw) 823{ 824 s32 ret_val; 825 u16 mii_status_reg; 826 u16 i; 827 bool link; 828 829 /* Polarity reversal workaround for forced 10F/10H links. */ 830 831 /* Disable the transmitter on the PHY */ 832 833 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 834 if (ret_val) 835 goto out; 836 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 837 if (ret_val) 838 goto out; 839 840 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 841 if (ret_val) 842 goto out; 843 844 /* 845 * This loop will early-out if the NO link condition has been met. 846 * In other words, DO NOT use e1000_phy_has_link_generic() here. 847 */ 848 for (i = PHY_FORCE_TIME; i > 0; i--) { 849 /* 850 * Read the MII Status Register and wait for Link Status bit 851 * to be clear. 852 */ 853 854 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 855 if (ret_val) 856 goto out; 857 858 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 859 if (ret_val) 860 goto out; 861 862 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 863 break; 864 msec_delay_irq(100); 865 } 866 867 /* Recommended delay time after link has been lost */ 868 msec_delay_irq(1000); 869 870 /* Now we will re-enable the transmitter on the PHY */ 871 872 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 873 if (ret_val) 874 goto out; 875 msec_delay_irq(50); 876 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 877 if (ret_val) 878 goto out; 879 msec_delay_irq(50); 880 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 881 if (ret_val) 882 goto out; 883 msec_delay_irq(50); 884 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 885 if (ret_val) 886 goto out; 887 888 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 889 if (ret_val) 890 goto out; 891 892 /* 893 * Read the MII Status Register and wait for Link Status bit 894 * to be set. 895 */ 896 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link); 897 if (ret_val) 898 goto out; 899 900out: 901 return ret_val; 902} 903 904/** 905 * e1000_phy_hw_reset_82543 - PHY hardware reset 906 * @hw: pointer to the HW structure 907 * 908 * Sets the PHY_RESET_DIR bit in the extended device control register 909 * to put the PHY into a reset and waits for completion. Once the reset 910 * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out 911 * of reset. This is a function pointer entry point called by the api module. 912 **/ 913STATIC s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw) 914{ 915 struct e1000_functions *func = &hw->func; 916 u32 ctrl_ext; 917 s32 ret_val; 918 919 DEBUGFUNC("e1000_phy_hw_reset_82543"); 920 921 /* 922 * Read the Extended Device Control Register, assert the PHY_RESET_DIR 923 * bit to put the PHY into reset... 924 */ 925 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 926 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 927 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 928 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 929 E1000_WRITE_FLUSH(hw); 930 931 msec_delay(10); 932 933 /* ...then take it out of reset. */ 934 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 935 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 936 E1000_WRITE_FLUSH(hw); 937 938 usec_delay(150); 939 940 ret_val = func->get_cfg_done(hw); 941 942 return ret_val; 943} 944 945/** 946 * e1000_reset_hw_82543 - Reset hardware 947 * @hw: pointer to the HW structure 948 * 949 * This resets the hardware into a known state. This is a 950 * function pointer entry point called by the api module. 951 **/ 952STATIC s32 e1000_reset_hw_82543(struct e1000_hw *hw) 953{ 954 u32 ctrl, icr; 955 s32 ret_val = E1000_SUCCESS; 956 957 DEBUGFUNC("e1000_reset_hw_82543"); 958 959 DEBUGOUT("Masking off all interrupts\n"); 960 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 961 962 E1000_WRITE_REG(hw, E1000_RCTL, 0); 963 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 964 E1000_WRITE_FLUSH(hw); 965 966 e1000_set_tbi_sbp_82543(hw, FALSE); 967 968 /* 969 * Delay to allow any outstanding PCI transactions to complete before 970 * resetting the device 971 */ 972 msec_delay(10); 973 974 ctrl = E1000_READ_REG(hw, E1000_CTRL); 975 976 DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n"); 977 if (hw->mac.type == e1000_82543) { 978 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 979 } else { 980 /* 981 * The 82544 can't ACK the 64-bit write when issuing the 982 * reset, so use IO-mapping as a workaround. 983 */ 984 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 985 } 986 987 /* 988 * After MAC reset, force reload of NVM to restore power-on 989 * settings to device. 990 */ 991 e1000_reload_nvm(hw); 992 msec_delay(2); 993 994 /* Masking off and clearing any pending interrupts */ 995 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 996 icr = E1000_READ_REG(hw, E1000_ICR); 997 998 return ret_val; 999} 1000 1001/** 1002 * e1000_init_hw_82543 - Initialize hardware 1003 * @hw: pointer to the HW structure 1004 * 1005 * This inits the hardware readying it for operation. 1006 **/ 1007STATIC s32 e1000_init_hw_82543(struct e1000_hw *hw) 1008{ 1009 struct e1000_mac_info *mac = &hw->mac; 1010 struct e1000_dev_spec_82543 *dev_spec; 1011 u32 ctrl; 1012 s32 ret_val; 1013 u16 i; 1014 1015 DEBUGFUNC("e1000_init_hw_82543"); 1016 1017 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 1018 1019 if (!dev_spec) { 1020 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 1021 ret_val = -E1000_ERR_CONFIG; 1022 goto out; 1023 } 1024 1025 /* Disabling VLAN filtering */ 1026 E1000_WRITE_REG(hw, E1000_VET, 0); 1027 e1000_clear_vfta(hw); 1028 1029 /* Setup the receive address. */ 1030 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 1031 1032 /* Zero out the Multicast HASH table */ 1033 DEBUGOUT("Zeroing the MTA\n"); 1034 for (i = 0; i < mac->mta_reg_count; i++) { 1035 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1036 E1000_WRITE_FLUSH(hw); 1037 } 1038 1039 /* 1040 * Set the PCI priority bit correctly in the CTRL register. This 1041 * determines if the adapter gives priority to receives, or if it 1042 * gives equal priority to transmits and receives. 1043 */ 1044 if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) { 1045 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1046 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); 1047 } 1048 1049 e1000_pcix_mmrbc_workaround_generic(hw); 1050 1051 /* Setup link and flow control */ 1052 ret_val = e1000_setup_link(hw); 1053 1054 /* 1055 * Clear all of the statistics registers (clear on read). It is 1056 * important that we do this after we have tried to establish link 1057 * because the symbol error count will increment wildly if there 1058 * is no link. 1059 */ 1060 e1000_clear_hw_cntrs_82543(hw); 1061 1062out: 1063 return ret_val; 1064} 1065 1066/** 1067 * e1000_setup_link_82543 - Setup flow control and link settings 1068 * @hw: pointer to the HW structure 1069 * 1070 * Read the EEPROM to determine the initial polarity value and write the 1071 * extended device control register with the information before calling 1072 * the generic setup link function, which does the following: 1073 * Determines which flow control settings to use, then configures flow 1074 * control. Calls the appropriate media-specific link configuration 1075 * function. Assuming the adapter has a valid link partner, a valid link 1076 * should be established. Assumes the hardware has previously been reset 1077 * and the transmitter and receiver are not enabled. 1078 **/ 1079STATIC s32 e1000_setup_link_82543(struct e1000_hw *hw) 1080{ 1081 u32 ctrl_ext; 1082 s32 ret_val; 1083 u16 data; 1084 1085 DEBUGFUNC("e1000_setup_link_82543"); 1086 1087 /* 1088 * Take the 4 bits from NVM word 0xF that determine the initial 1089 * polarity value for the SW controlled pins, and setup the 1090 * Extended Device Control reg with that info. 1091 * This is needed because one of the SW controlled pins is used for 1092 * signal detection. So this should be done before phy setup. 1093 */ 1094 if (hw->mac.type == e1000_82543) { 1095 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1096 if (ret_val) { 1097 DEBUGOUT("NVM Read Error\n"); 1098 ret_val = -E1000_ERR_NVM; 1099 goto out; 1100 } 1101 ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) << 1102 NVM_SWDPIO_EXT_SHIFT); 1103 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1104 } 1105 1106 ret_val = e1000_setup_link_generic(hw); 1107 1108out: 1109 return ret_val; 1110} 1111 1112/** 1113 * e1000_setup_copper_link_82543 - Configure copper link settings 1114 * @hw: pointer to the HW structure 1115 * 1116 * Configures the link for auto-neg or forced speed and duplex. Then we check 1117 * for link, once link is established calls to configure collision distance 1118 * and flow control are called. 1119 **/ 1120STATIC s32 e1000_setup_copper_link_82543(struct e1000_hw *hw) 1121{ 1122 u32 ctrl; 1123 s32 ret_val; 1124 bool link; 1125 1126 DEBUGFUNC("e1000_setup_copper_link_82543"); 1127 1128 ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU; 1129 /* 1130 * With 82543, we need to force speed and duplex on the MAC 1131 * equal to what the PHY speed and duplex configuration is. 1132 * In addition, we need to perform a hardware reset on the 1133 * PHY to take it out of reset. 1134 */ 1135 if (hw->mac.type == e1000_82543) { 1136 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1137 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1138 ret_val = e1000_phy_hw_reset(hw); 1139 if (ret_val) 1140 goto out; 1141 hw->phy.reset_disable = FALSE; 1142 } else { 1143 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1144 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1145 } 1146 1147 /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */ 1148 ret_val = e1000_copper_link_setup_m88(hw); 1149 if (ret_val) 1150 goto out; 1151 1152 if (hw->mac.autoneg) { 1153 /* 1154 * Setup autoneg and flow control advertisement and perform 1155 * autonegotiation. 1156 */ 1157 ret_val = e1000_copper_link_autoneg(hw); 1158 if (ret_val) 1159 goto out; 1160 } else { 1161 /* 1162 * PHY will be set to 10H, 10F, 100H or 100F 1163 * depending on user settings. 1164 */ 1165 DEBUGOUT("Forcing Speed and Duplex\n"); 1166 ret_val = e1000_phy_force_speed_duplex_82543(hw); 1167 if (ret_val) { 1168 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1169 goto out; 1170 } 1171 } 1172 1173 /* 1174 * Check link status. Wait up to 100 microseconds for link to become 1175 * valid. 1176 */ 1177 ret_val = e1000_phy_has_link_generic(hw, 1178 COPPER_LINK_UP_LIMIT, 1179 10, 1180 &link); 1181 if (ret_val) 1182 goto out; 1183 1184 1185 if (link) { 1186 DEBUGOUT("Valid link established!!!\n"); 1187 /* Config the MAC and PHY after link is up */ 1188 if (hw->mac.type == e1000_82544) { 1189 e1000_config_collision_dist_generic(hw); 1190 } else { 1191 ret_val = e1000_config_mac_to_phy_82543(hw); 1192 if (ret_val) 1193 goto out; 1194 } 1195 ret_val = e1000_config_fc_after_link_up_generic(hw); 1196 } else { 1197 DEBUGOUT("Unable to establish link!!!\n"); 1198 } 1199 1200out: 1201 return ret_val; 1202} 1203 1204/** 1205 * e1000_setup_fiber_link_82543 - Setup link for fiber 1206 * @hw: pointer to the HW structure 1207 * 1208 * Configures collision distance and flow control for fiber links. Upon 1209 * successful setup, poll for link. 1210 **/ 1211STATIC s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw) 1212{ 1213 u32 ctrl; 1214 s32 ret_val; 1215 1216 DEBUGFUNC("e1000_setup_fiber_link_82543"); 1217 1218 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1219 1220 /* Take the link out of reset */ 1221 ctrl &= ~E1000_CTRL_LRST; 1222 1223 e1000_config_collision_dist_generic(hw); 1224 1225 ret_val = e1000_commit_fc_settings_generic(hw); 1226 if (ret_val) 1227 goto out; 1228 1229 DEBUGOUT("Auto-negotiation enabled\n"); 1230 1231 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1232 E1000_WRITE_FLUSH(hw); 1233 msec_delay(1); 1234 1235 /* 1236 * For these adapters, the SW defineable pin 1 is cleared when the 1237 * optics detect a signal. If we have a signal, then poll for a 1238 * "Link-Up" indication. 1239 */ 1240 if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1241 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1242 } else { 1243 DEBUGOUT("No signal detected\n"); 1244 } 1245 1246out: 1247 return ret_val; 1248} 1249 1250/** 1251 * e1000_check_for_copper_link_82543 - Check for link (Copper) 1252 * @hw: pointer to the HW structure 1253 * 1254 * Checks the phy for link, if link exists, do the following: 1255 * - check for downshift 1256 * - do polarity workaround (if necessary) 1257 * - configure collision distance 1258 * - configure flow control after link up 1259 * - configure tbi compatibility 1260 **/ 1261STATIC s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw) 1262{ 1263 struct e1000_mac_info *mac = &hw->mac; 1264 u32 icr, rctl; 1265 s32 ret_val; 1266 u16 speed, duplex; 1267 bool link; 1268 1269 DEBUGFUNC("e1000_check_for_copper_link_82543"); 1270 1271 if (!mac->get_link_status) { 1272 ret_val = E1000_SUCCESS; 1273 goto out; 1274 } 1275 1276 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1277 if (ret_val) 1278 goto out; 1279 1280 if (!link) 1281 goto out; /* No link detected */ 1282 1283 mac->get_link_status = FALSE; 1284 1285 e1000_check_downshift_generic(hw); 1286 1287 /* 1288 * If we are forcing speed/duplex, then we can return since 1289 * we have already determined whether we have link or not. 1290 */ 1291 if (!mac->autoneg) { 1292 /* 1293 * If speed and duplex are forced to 10H or 10F, then we will 1294 * implement the polarity reversal workaround. We disable 1295 * interrupts first, and upon returning, place the devices 1296 * interrupt state to its previous value except for the link 1297 * status change interrupt which will happened due to the 1298 * execution of this workaround. 1299 */ 1300 if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) { 1301 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 1302 ret_val = e1000_polarity_reversal_workaround_82543(hw); 1303 icr = E1000_READ_REG(hw, E1000_ICR); 1304 E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC)); 1305 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 1306 } 1307 1308 ret_val = -E1000_ERR_CONFIG; 1309 goto out; 1310 } 1311 1312 /* 1313 * We have a M88E1000 PHY and Auto-Neg is enabled. If we 1314 * have Si on board that is 82544 or newer, Auto 1315 * Speed Detection takes care of MAC speed/duplex 1316 * configuration. So we only need to configure Collision 1317 * Distance in the MAC. Otherwise, we need to force 1318 * speed/duplex on the MAC to the current PHY speed/duplex 1319 * settings. 1320 */ 1321 if (mac->type == e1000_82544) 1322 e1000_config_collision_dist_generic(hw); 1323 else { 1324 ret_val = e1000_config_mac_to_phy_82543(hw); 1325 if (ret_val) { 1326 DEBUGOUT("Error configuring MAC to PHY settings\n"); 1327 goto out; 1328 } 1329 } 1330 1331 /* 1332 * Configure Flow Control now that Auto-Neg has completed. 1333 * First, we need to restore the desired flow control 1334 * settings because we may have had to re-autoneg with a 1335 * different link partner. 1336 */ 1337 ret_val = e1000_config_fc_after_link_up_generic(hw); 1338 if (ret_val) { 1339 DEBUGOUT("Error configuring flow control\n"); 1340 } 1341 1342 /* 1343 * At this point we know that we are on copper and we have 1344 * auto-negotiated link. These are conditions for checking the link 1345 * partner capability register. We use the link speed to determine if 1346 * TBI compatibility needs to be turned on or off. If the link is not 1347 * at gigabit speed, then TBI compatibility is not needed. If we are 1348 * at gigabit speed, we turn on TBI compatibility. 1349 */ 1350 if (e1000_tbi_compatibility_enabled_82543(hw)) { 1351 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 1352 if (ret_val) { 1353 DEBUGOUT("Error getting link speed and duplex\n"); 1354 return ret_val; 1355 } 1356 if (speed != SPEED_1000) { 1357 /* 1358 * If link speed is not set to gigabit speed, 1359 * we do not need to enable TBI compatibility. 1360 */ 1361 if (e1000_tbi_sbp_enabled_82543(hw)) { 1362 /* 1363 * If we previously were in the mode, 1364 * turn it off. 1365 */ 1366 e1000_set_tbi_sbp_82543(hw, FALSE); 1367 rctl = E1000_READ_REG(hw, E1000_RCTL); 1368 rctl &= ~E1000_RCTL_SBP; 1369 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1370 } 1371 } else { 1372 /* 1373 * If TBI compatibility is was previously off, 1374 * turn it on. For compatibility with a TBI link 1375 * partner, we will store bad packets. Some 1376 * frames have an additional byte on the end and 1377 * will look like CRC errors to to the hardware. 1378 */ 1379 if (!e1000_tbi_sbp_enabled_82543(hw)) { 1380 e1000_set_tbi_sbp_82543(hw, TRUE); 1381 rctl = E1000_READ_REG(hw, E1000_RCTL); 1382 rctl |= E1000_RCTL_SBP; 1383 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1384 } 1385 } 1386 } 1387out: 1388 return ret_val; 1389} 1390 1391/** 1392 * e1000_check_for_fiber_link_82543 - Check for link (Fiber) 1393 * @hw: pointer to the HW structure 1394 * 1395 * Checks for link up on the hardware. If link is not up and we have 1396 * a signal, then we need to force link up. 1397 **/ 1398STATIC s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw) 1399{ 1400 struct e1000_mac_info *mac = &hw->mac; 1401 u32 rxcw, ctrl, status; 1402 s32 ret_val = E1000_SUCCESS; 1403 1404 DEBUGFUNC("e1000_check_for_fiber_link_82543"); 1405 1406 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1407 status = E1000_READ_REG(hw, E1000_STATUS); 1408 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1409 1410 /* 1411 * If we don't have link (auto-negotiation failed or link partner 1412 * cannot auto-negotiate), the cable is plugged in (we have signal), 1413 * and our link partner is not trying to auto-negotiate with us (we 1414 * are receiving idles or data), we need to force link up. We also 1415 * need to give auto-negotiation time to complete, in case the cable 1416 * was just plugged in. The autoneg_failed flag does this. 1417 */ 1418 /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */ 1419 if ((!(ctrl & E1000_CTRL_SWDPIN1)) && 1420 (!(status & E1000_STATUS_LU)) && 1421 (!(rxcw & E1000_RXCW_C))) { 1422 if (mac->autoneg_failed == 0) { 1423 mac->autoneg_failed = 1; 1424 ret_val = 0; 1425 goto out; 1426 } 1427 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 1428 1429 /* Disable auto-negotiation in the TXCW register */ 1430 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 1431 1432 /* Force link-up and also force full-duplex. */ 1433 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1434 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1435 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1436 1437 /* Configure Flow Control after forcing link up. */ 1438 ret_val = e1000_config_fc_after_link_up_generic(hw); 1439 if (ret_val) { 1440 DEBUGOUT("Error configuring flow control\n"); 1441 goto out; 1442 } 1443 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 1444 /* 1445 * If we are forcing link and we are receiving /C/ ordered 1446 * sets, re-enable auto-negotiation in the TXCW register 1447 * and disable forced link in the Device Control register 1448 * in an attempt to auto-negotiate with our link partner. 1449 */ 1450 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 1451 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1452 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 1453 1454 mac->serdes_has_link = TRUE; 1455 } 1456 1457out: 1458 return ret_val; 1459} 1460 1461/** 1462 * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings 1463 * @hw: pointer to the HW structure 1464 * 1465 * For the 82543 silicon, we need to set the MAC to match the settings 1466 * of the PHY, even if the PHY is auto-negotiating. 1467 **/ 1468static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw) 1469{ 1470 u32 ctrl; 1471 s32 ret_val; 1472 u16 phy_data; 1473 1474 DEBUGFUNC("e1000_config_mac_to_phy_82543"); 1475 1476 /* Set the bits to force speed and duplex */ 1477 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1478 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1479 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1480 1481 /* 1482 * Set up duplex in the Device Control and Transmit Control 1483 * registers depending on negotiated values. 1484 */ 1485 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1486 if (ret_val) 1487 goto out; 1488 1489 ctrl &= ~E1000_CTRL_FD; 1490 if (phy_data & M88E1000_PSSR_DPLX) 1491 ctrl |= E1000_CTRL_FD; 1492 1493 e1000_config_collision_dist_generic(hw); 1494 1495 /* 1496 * Set up speed in the Device Control register depending on 1497 * negotiated values. 1498 */ 1499 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1500 ctrl |= E1000_CTRL_SPD_1000; 1501 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 1502 ctrl |= E1000_CTRL_SPD_100; 1503 1504 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1505 1506out: 1507 return ret_val; 1508} 1509 1510/** 1511 * e1000_write_vfta_82543 - Write value to VLAN filter table 1512 * @hw: pointer to the HW structure 1513 * @offset: the 32-bit offset in which to write the value to. 1514 * @value: the 32-bit value to write at location offset. 1515 * 1516 * This writes a 32-bit value to a 32-bit offset in the VLAN filter 1517 * table. 1518 **/ 1519STATIC void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value) 1520{ 1521 u32 temp; 1522 1523 DEBUGFUNC("e1000_write_vfta_82543"); 1524 1525 if ((hw->mac.type == e1000_82544) && (offset & 1)) { 1526 temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1); 1527 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 1528 E1000_WRITE_FLUSH(hw); 1529 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp); 1530 E1000_WRITE_FLUSH(hw); 1531 } else { 1532 e1000_write_vfta_generic(hw, offset, value); 1533 } 1534} 1535 1536/** 1537 * e1000_mta_set_82543 - Set multicast filter table address 1538 * @hw: pointer to the HW structure 1539 * @hash_value: determines the MTA register and bit to set 1540 * 1541 * The multicast table address is a register array of 32-bit registers. 1542 * The hash_value is used to determine what register the bit is in, the 1543 * current value is read, the new bit is OR'd in and the new value is 1544 * written back into the register. 1545 **/ 1546STATIC void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value) 1547{ 1548 u32 hash_bit, hash_reg, mta, temp; 1549 1550 DEBUGFUNC("e1000_mta_set_82543"); 1551 1552 hash_reg = (hash_value >> 5); 1553 1554 /* 1555 * If we are on an 82544 and we are trying to write an odd offset 1556 * in the MTA, save off the previous entry before writing and 1557 * restore the old value after writing. 1558 */ 1559 if ((hw->mac.type == e1000_82544) && (hash_reg & 1)) { 1560 hash_reg &= (hw->mac.mta_reg_count - 1); 1561 hash_bit = hash_value & 0x1F; 1562 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 1563 mta |= (1 << hash_bit); 1564 temp = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg - 1); 1565 1566 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 1567 E1000_WRITE_FLUSH(hw); 1568 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg - 1, temp); 1569 E1000_WRITE_FLUSH(hw); 1570 } else { 1571 e1000_mta_set_generic(hw, hash_value); 1572 } 1573} 1574 1575/** 1576 * e1000_led_on_82543 - Turn on SW controllable LED 1577 * @hw: pointer to the HW structure 1578 * 1579 * Turns the SW defined LED on. This is a function pointer entry point 1580 * called by the api module. 1581 **/ 1582STATIC s32 e1000_led_on_82543(struct e1000_hw *hw) 1583{ 1584 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1585 1586 DEBUGFUNC("e1000_led_on_82543"); 1587 1588 if (hw->mac.type == e1000_82544 && 1589 hw->phy.media_type == e1000_media_type_copper) { 1590 /* Clear SW-defineable Pin 0 to turn on the LED */ 1591 ctrl &= ~E1000_CTRL_SWDPIN0; 1592 ctrl |= E1000_CTRL_SWDPIO0; 1593 } else { 1594 /* Fiber 82544 and all 82543 use this method */ 1595 ctrl |= E1000_CTRL_SWDPIN0; 1596 ctrl |= E1000_CTRL_SWDPIO0; 1597 } 1598 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1599 1600 return E1000_SUCCESS; 1601} 1602 1603/** 1604 * e1000_led_off_82543 - Turn off SW controllable LED 1605 * @hw: pointer to the HW structure 1606 * 1607 * Turns the SW defined LED off. This is a function pointer entry point 1608 * called by the api module. 1609 **/ 1610STATIC s32 e1000_led_off_82543(struct e1000_hw *hw) 1611{ 1612 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1613 1614 DEBUGFUNC("e1000_led_off_82543"); 1615 1616 if (hw->mac.type == e1000_82544 && 1617 hw->phy.media_type == e1000_media_type_copper) { 1618 /* Set SW-defineable Pin 0 to turn off the LED */ 1619 ctrl |= E1000_CTRL_SWDPIN0; 1620 ctrl |= E1000_CTRL_SWDPIO0; 1621 } else { 1622 ctrl &= ~E1000_CTRL_SWDPIN0; 1623 ctrl |= E1000_CTRL_SWDPIO0; 1624 } 1625 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1626 1627 return E1000_SUCCESS; 1628} 1629 1630/** 1631 * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters 1632 * @hw: pointer to the HW structure 1633 * 1634 * Clears the hardware counters by reading the counter registers. 1635 **/ 1636STATIC void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw) 1637{ 1638 volatile u32 temp; 1639 1640 DEBUGFUNC("e1000_clear_hw_cntrs_82543"); 1641 1642 e1000_clear_hw_cntrs_base_generic(hw); 1643 1644 temp = E1000_READ_REG(hw, E1000_PRC64); 1645 temp = E1000_READ_REG(hw, E1000_PRC127); 1646 temp = E1000_READ_REG(hw, E1000_PRC255); 1647 temp = E1000_READ_REG(hw, E1000_PRC511); 1648 temp = E1000_READ_REG(hw, E1000_PRC1023); 1649 temp = E1000_READ_REG(hw, E1000_PRC1522); 1650 temp = E1000_READ_REG(hw, E1000_PTC64); 1651 temp = E1000_READ_REG(hw, E1000_PTC127); 1652 temp = E1000_READ_REG(hw, E1000_PTC255); 1653 temp = E1000_READ_REG(hw, E1000_PTC511); 1654 temp = E1000_READ_REG(hw, E1000_PTC1023); 1655 temp = E1000_READ_REG(hw, E1000_PTC1522); 1656 1657 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1658 temp = E1000_READ_REG(hw, E1000_RXERRC); 1659 temp = E1000_READ_REG(hw, E1000_TNCRS); 1660 temp = E1000_READ_REG(hw, E1000_CEXTERR); 1661 temp = E1000_READ_REG(hw, E1000_TSCTC); 1662 temp = E1000_READ_REG(hw, E1000_TSCTFC); 1663} 1664