e1000_82543.c revision 169589
1/******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33/*$FreeBSD: head/sys/dev/em/e1000_82543.c 169589 2007-05-16 00:14:23Z jfv $*/ 34 35 36/* e1000_82543 37 * e1000_82544 38 */ 39 40#include "e1000_api.h" 41#include "e1000_82543.h" 42 43void e1000_init_function_pointers_82543(struct e1000_hw *hw); 44 45STATIC s32 e1000_init_phy_params_82543(struct e1000_hw *hw); 46STATIC s32 e1000_init_nvm_params_82543(struct e1000_hw *hw); 47STATIC s32 e1000_init_mac_params_82543(struct e1000_hw *hw); 48STATIC s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, 49 u16 *data); 50STATIC s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, 51 u16 data); 52STATIC s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw); 53STATIC s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw); 54STATIC s32 e1000_reset_hw_82543(struct e1000_hw *hw); 55STATIC s32 e1000_init_hw_82543(struct e1000_hw *hw); 56STATIC s32 e1000_setup_link_82543(struct e1000_hw *hw); 57STATIC s32 e1000_setup_copper_link_82543(struct e1000_hw *hw); 58STATIC s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw); 59STATIC s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw); 60STATIC s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw); 61STATIC s32 e1000_led_on_82543(struct e1000_hw *hw); 62STATIC s32 e1000_led_off_82543(struct e1000_hw *hw); 63STATIC void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, 64 u32 value); 65STATIC void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value); 66STATIC void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw); 67static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw); 68static boolean_t e1000_init_phy_disabled_82543(struct e1000_hw *hw); 69static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 70static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw); 71static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 72static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw); 73static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 74 u16 count); 75static boolean_t e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw); 76static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, boolean_t state); 77 78struct e1000_dev_spec_82543 { 79 u32 tbi_compatibility; 80 boolean_t dma_fairness; 81 boolean_t init_phy_disabled; 82}; 83 84/** 85 * e1000_init_phy_params_82543 - Init PHY func ptrs. 86 * @hw: pointer to the HW structure 87 * 88 * This is a function pointer entry point called by the api module. 89 **/ 90STATIC s32 91e1000_init_phy_params_82543(struct e1000_hw *hw) 92{ 93 struct e1000_phy_info *phy = &hw->phy; 94 struct e1000_functions *func = &hw->func; 95 s32 ret_val = E1000_SUCCESS; 96 97 DEBUGFUNC("e1000_init_phy_params_82543"); 98 99 if (hw->media_type != e1000_media_type_copper) { 100 phy->type = e1000_phy_none; 101 goto out; 102 } 103 104 phy->addr = 1; 105 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 106 phy->reset_delay_us = 10000; 107 phy->type = e1000_phy_m88; 108 109 /* Function Pointers */ 110 func->check_polarity = e1000_check_polarity_m88; 111 func->commit_phy = e1000_phy_sw_reset_generic; 112 func->force_speed_duplex = e1000_phy_force_speed_duplex_82543; 113 func->get_cable_length = e1000_get_cable_length_m88; 114 func->get_cfg_done = e1000_get_cfg_done_generic; 115 func->read_phy_reg = (hw->mac.type == e1000_82543) 116 ? e1000_read_phy_reg_82543 117 : e1000_read_phy_reg_m88; 118 func->reset_phy = (hw->mac.type == e1000_82543) 119 ? e1000_phy_hw_reset_82543 120 : e1000_phy_hw_reset_generic; 121 func->write_phy_reg = (hw->mac.type == e1000_82543) 122 ? e1000_write_phy_reg_82543 123 : e1000_write_phy_reg_m88; 124 func->get_phy_info = e1000_get_phy_info_m88; 125 126 /* The external PHY of the 82543 can be in a funky state. 127 * Resetting helps us read the PHY registers for acquiring 128 * the PHY ID. 129 */ 130 if (!e1000_init_phy_disabled_82543(hw)) { 131 ret_val = e1000_phy_hw_reset(hw); 132 if (ret_val) { 133 DEBUGOUT("Resetting PHY during init failed.\n"); 134 goto out; 135 } 136 msec_delay(20); 137 } 138 139 ret_val = e1000_get_phy_id(hw); 140 if (ret_val) 141 goto out; 142 143 /* Verify phy id */ 144 switch (hw->mac.type) { 145 case e1000_82543: 146 if (phy->id != M88E1000_E_PHY_ID) { 147 ret_val = -E1000_ERR_PHY; 148 goto out; 149 } 150 break; 151 case e1000_82544: 152 if (phy->id != M88E1000_I_PHY_ID) { 153 ret_val = -E1000_ERR_PHY; 154 goto out; 155 } 156 break; 157 default: 158 ret_val = -E1000_ERR_PHY; 159 goto out; 160 break; 161 } 162 163out: 164 return ret_val; 165} 166 167/** 168 * e1000_init_nvm_params_82543 - Init NVM func ptrs. 169 * @hw: pointer to the HW structure 170 * 171 * This is a function pointer entry point called by the api module. 172 **/ 173STATIC s32 174e1000_init_nvm_params_82543(struct e1000_hw *hw) 175{ 176 struct e1000_nvm_info *nvm = &hw->nvm; 177 struct e1000_functions *func = &hw->func; 178 179 DEBUGFUNC("e1000_init_nvm_params_82543"); 180 181 nvm->type = e1000_nvm_eeprom_microwire; 182 nvm->word_size = 64; 183 nvm->delay_usec = 50; 184 nvm->address_bits = 6; 185 nvm->opcode_bits = 3; 186 187 /* Function Pointers */ 188 func->read_nvm = e1000_read_nvm_microwire; 189 func->update_nvm = e1000_update_nvm_checksum_generic; 190 func->valid_led_default = e1000_valid_led_default_generic; 191 func->validate_nvm = e1000_validate_nvm_checksum_generic; 192 func->write_nvm = e1000_write_nvm_microwire; 193 194 return E1000_SUCCESS; 195} 196 197/** 198 * e1000_init_mac_params_82543 - Init MAC func ptrs. 199 * @hw: pointer to the HW structure 200 * 201 * This is a function pointer entry point called by the api module. 202 **/ 203STATIC s32 204e1000_init_mac_params_82543(struct e1000_hw *hw) 205{ 206 struct e1000_mac_info *mac = &hw->mac; 207 struct e1000_functions *func = &hw->func; 208 s32 ret_val; 209 210 DEBUGFUNC("e1000_init_mac_params_82543"); 211 212 /* Set media type */ 213 switch (hw->device_id) { 214 case E1000_DEV_ID_82543GC_FIBER: 215 case E1000_DEV_ID_82544EI_FIBER: 216 hw->media_type = e1000_media_type_fiber; 217 break; 218 default: 219 hw->media_type = e1000_media_type_copper; 220 break; 221 } 222 223 /* Set mta register count */ 224 mac->mta_reg_count = 128; 225 /* Set rar entry count */ 226 mac->rar_entry_count = E1000_RAR_ENTRIES; 227 228 /* Function pointers */ 229 230 /* bus type/speed/width */ 231 func->get_bus_info = e1000_get_bus_info_pci_generic; 232 /* reset */ 233 func->reset_hw = e1000_reset_hw_82543; 234 /* hw initialization */ 235 func->init_hw = e1000_init_hw_82543; 236 /* link setup */ 237 func->setup_link = e1000_setup_link_82543; 238 /* physical interface setup */ 239 func->setup_physical_interface = 240 (hw->media_type == e1000_media_type_copper) 241 ? e1000_setup_copper_link_82543 242 : e1000_setup_fiber_link_82543; 243 /* check for link */ 244 func->check_for_link = 245 (hw->media_type == e1000_media_type_copper) 246 ? e1000_check_for_copper_link_82543 247 : e1000_check_for_fiber_link_82543; 248 /* link info */ 249 func->get_link_up_info = 250 (hw->media_type == e1000_media_type_copper) 251 ? e1000_get_speed_and_duplex_copper_generic 252 : e1000_get_speed_and_duplex_fiber_serdes_generic; 253 /* multicast address update */ 254 func->mc_addr_list_update = e1000_mc_addr_list_update_generic; 255 /* writing VFTA */ 256 func->write_vfta = e1000_write_vfta_82543; 257 /* clearing VFTA */ 258 func->clear_vfta = e1000_clear_vfta_generic; 259 /* setting MTA */ 260 func->mta_set = e1000_mta_set_82543; 261 /* turn on/off LED */ 262 func->led_on = e1000_led_on_82543; 263 func->led_off = e1000_led_off_82543; 264 /* remove device */ 265 func->remove_device = e1000_remove_device_generic; 266 /* clear hardware counters */ 267 func->clear_hw_cntrs = e1000_clear_hw_cntrs_82543; 268 269 hw->dev_spec_size = sizeof(struct e1000_dev_spec_82543); 270 271 /* Device-specific structure allocation */ 272 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 273 if (ret_val) 274 goto out; 275 276 /* Set tbi compatibility */ 277 if ((hw->mac.type != e1000_82543) || 278 (hw->media_type == e1000_media_type_fiber)) 279 e1000_set_tbi_compatibility_82543(hw, FALSE); 280 281out: 282 return ret_val; 283} 284 285/** 286 * e1000_init_function_pointers_82543 - Init func ptrs. 287 * @hw: pointer to the HW structure 288 * 289 * The only function explicitly called by the api module to initialize 290 * all function pointers and parameters. 291 **/ 292void 293e1000_init_function_pointers_82543(struct e1000_hw *hw) 294{ 295 DEBUGFUNC("e1000_init_function_pointers_82543"); 296 297 hw->func.init_mac_params = e1000_init_mac_params_82543; 298 hw->func.init_nvm_params = e1000_init_nvm_params_82543; 299 hw->func.init_phy_params = e1000_init_phy_params_82543; 300} 301 302/** 303 * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status 304 * @hw: pointer to the HW structure 305 * 306 * Returns the curent status of 10-bit Interface (TBI) compatibility 307 * (enabled/disabled). 308 **/ 309static boolean_t 310e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw) 311{ 312 struct e1000_dev_spec_82543 *dev_spec; 313 boolean_t state = FALSE; 314 315 DEBUGFUNC("e1000_tbi_compatibility_enabled_82543"); 316 317 if (hw->mac.type != e1000_82543) { 318 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 319 goto out; 320 } 321 322 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 323 324 if (dev_spec == NULL) { 325 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 326 goto out; 327 } 328 329 state = (dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED) 330 ? TRUE : FALSE; 331 332out: 333 return state; 334} 335 336/** 337 * e1000_set_tbi_compatibility_82543 - Set TBI compatibility 338 * @hw: pointer to the HW structure 339 * @state: enable/disable TBI compatibility 340 * 341 * Enables or disabled 10-bit Interface (TBI) compatibility. 342 **/ 343void 344e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, boolean_t state) 345{ 346 struct e1000_dev_spec_82543 *dev_spec; 347 348 DEBUGFUNC("e1000_set_tbi_compatibility_82543"); 349 350 if (hw->mac.type != e1000_82543) { 351 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 352 goto out; 353 } 354 355 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 356 357 if (dev_spec == NULL) { 358 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 359 goto out; 360 } 361 362 if (state) 363 dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED; 364 else 365 dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED; 366 367out: 368 return; 369} 370 371/** 372 * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status 373 * @hw: pointer to the HW structure 374 * 375 * Returns the curent status of 10-bit Interface (TBI) store bad packet (SBP) 376 * (enabled/disabled). 377 **/ 378boolean_t 379e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw) 380{ 381 struct e1000_dev_spec_82543 *dev_spec; 382 boolean_t state = FALSE; 383 384 DEBUGFUNC("e1000_tbi_sbp_enabled_82543"); 385 386 if (hw->mac.type != e1000_82543) { 387 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 388 goto out; 389 } 390 391 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 392 393 if (dev_spec == NULL) { 394 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 395 goto out; 396 } 397 398 state = (dev_spec->tbi_compatibility & TBI_SBP_ENABLED) 399 ? TRUE : FALSE; 400 401out: 402 return state; 403} 404 405/** 406 * e1000_set_tbi_sbp_82543 - Set TBI SBP 407 * @hw: pointer to the HW structure 408 * @state: enable/disable TBI store bad packet 409 * 410 * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP). 411 **/ 412static void 413e1000_set_tbi_sbp_82543(struct e1000_hw *hw, boolean_t state) 414{ 415 struct e1000_dev_spec_82543 *dev_spec; 416 417 DEBUGFUNC("e1000_set_tbi_sbp_82543"); 418 419 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 420 421 if (state && e1000_tbi_compatibility_enabled_82543(hw)) 422 dev_spec->tbi_compatibility |= TBI_SBP_ENABLED; 423 else 424 dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED; 425 426 return; 427} 428 429/** 430 * e1000_init_phy_disabled_82543 - Returns init PHY status 431 * @hw: pointer to the HW structure 432 * 433 * Returns the current status of whether PHY initialization is disabled. 434 * True if PHY initialization is disabled else false. 435 **/ 436static boolean_t 437e1000_init_phy_disabled_82543(struct e1000_hw *hw) 438{ 439 struct e1000_dev_spec_82543 *dev_spec; 440 boolean_t ret_val; 441 442 DEBUGFUNC("e1000_init_phy_disabled_82543"); 443 444 if (hw->mac.type != e1000_82543) { 445 ret_val = FALSE; 446 goto out; 447 } 448 449 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 450 451 if (dev_spec == NULL) { 452 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 453 ret_val = FALSE; 454 goto out; 455 } 456 457 ret_val = dev_spec->init_phy_disabled; 458 459out: 460 return ret_val; 461} 462 463/** 464 * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled 465 * @hw: pointer to the HW structure 466 * @stats: Struct containing statistic register values 467 * @frame_len: The length of the frame in question 468 * @mac_addr: The Ethernet destination address of the frame in question 469 * 470 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 471 **/ 472void 473e1000_tbi_adjust_stats_82543(struct e1000_hw *hw, struct e1000_hw_stats *stats, 474 u32 frame_len, u8 *mac_addr) 475{ 476 u64 carry_bit; 477 478 if (e1000_tbi_sbp_enabled_82543(hw) == FALSE) 479 goto out; 480 481 /* First adjust the frame length. */ 482 frame_len--; 483 /* We need to adjust the statistics counters, since the hardware 484 * counters overcount this packet as a CRC error and undercount 485 * the packet as a good packet 486 */ 487 /* This packet should not be counted as a CRC error. */ 488 stats->crcerrs--; 489 /* This packet does count as a Good Packet Received. */ 490 stats->gprc++; 491 492 /* Adjust the Good Octets received counters */ 493 carry_bit = 0x80000000 & stats->gorcl; 494 stats->gorcl += frame_len; 495 /* If the high bit of Gorcl (the low 32 bits of the Good Octets 496 * Received Count) was one before the addition, 497 * AND it is zero after, then we lost the carry out, 498 * need to add one to Gorch (Good Octets Received Count High). 499 * This could be simplified if all environments supported 500 * 64-bit integers. 501 */ 502 if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) 503 stats->gorch++; 504 /* Is this a broadcast or multicast? Check broadcast first, 505 * since the test for a multicast frame will test positive on 506 * a broadcast frame. 507 */ 508 if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff)) 509 /* Broadcast packet */ 510 stats->bprc++; 511 else if (*mac_addr & 0x01) 512 /* Multicast packet */ 513 stats->mprc++; 514 515 /* In this case, the hardware has overcounted the number of 516 * oversize frames. 517 */ 518 if ((frame_len == hw->mac.max_frame_size) && (stats->roc > 0)) 519 stats->roc--; 520 521 /* Adjust the bin counters when the extra byte put the frame in the 522 * wrong bin. Remember that the frame_len was adjusted above. 523 */ 524 if (frame_len == 64) { 525 stats->prc64++; 526 stats->prc127--; 527 } else if (frame_len == 127) { 528 stats->prc127++; 529 stats->prc255--; 530 } else if (frame_len == 255) { 531 stats->prc255++; 532 stats->prc511--; 533 } else if (frame_len == 511) { 534 stats->prc511++; 535 stats->prc1023--; 536 } else if (frame_len == 1023) { 537 stats->prc1023++; 538 stats->prc1522--; 539 } else if (frame_len == 1522) { 540 stats->prc1522++; 541 } 542 543out: 544 return; 545} 546 547/** 548 * e1000_read_phy_reg_82543 - Read PHY register 549 * @hw: pointer to the HW structure 550 * @offset: register offset to be read 551 * @data: pointer to the read data 552 * 553 * Reads the PHY at offset and stores the information read to data. 554 **/ 555STATIC s32 556e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data) 557{ 558 u32 mdic; 559 s32 ret_val = E1000_SUCCESS; 560 561 DEBUGFUNC("e1000_read_phy_reg_82543"); 562 563 if (offset > MAX_PHY_REG_ADDRESS) { 564 DEBUGOUT1("PHY Address %d is out of range\n", offset); 565 ret_val = -E1000_ERR_PARAM; 566 goto out; 567 } 568 569 /* We must first send a preamble through the MDIO pin to signal the 570 * beginning of an MII instruction. This is done by sending 32 571 * consecutive "1" bits. 572 */ 573 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 574 575 /* Now combine the next few fields that are required for a read 576 * operation. We use this method instead of calling the 577 * e1000_shift_out_mdi_bits routine five different times. The format 578 * of an MII read instruction consists of a shift out of 14 bits and 579 * is defined as follows: 580 * <Preamble><SOF><Op Code><Phy Addr><Offset> 581 * followed by a shift in of 18 bits. This first two bits shifted in 582 * are TurnAround bits used to avoid contention on the MDIO pin when a 583 * READ operation is performed. These two bits are thrown away 584 * followed by a shift in of 16 bits which contains the desired data. 585 */ 586 mdic = (offset | (hw->phy.addr << 5) | 587 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 588 589 e1000_shift_out_mdi_bits_82543(hw, mdic, 14); 590 591 /* Now that we've shifted out the read command to the MII, we need to 592 * "shift in" the 16-bit value (18 total bits) of the requested PHY 593 * register address. 594 */ 595 *data = e1000_shift_in_mdi_bits_82543(hw); 596 597out: 598 return ret_val; 599} 600 601/** 602 * e1000_write_phy_reg_82543 - Write PHY register 603 * @hw: pointer to the HW structure 604 * @offset: register offset to be written 605 * @data: pointer to the data to be written at offset 606 * 607 * Writes data to the PHY at offset. 608 **/ 609STATIC s32 610e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data) 611{ 612 u32 mdic; 613 s32 ret_val = E1000_SUCCESS; 614 615 DEBUGFUNC("e1000_write_phy_reg_82543"); 616 617 if (offset > MAX_PHY_REG_ADDRESS) { 618 DEBUGOUT1("PHY Address %d is out of range\n", offset); 619 ret_val = -E1000_ERR_PARAM; 620 goto out; 621 } 622 623 /* We'll need to use the SW defined pins to shift the write command 624 * out to the PHY. We first send a preamble to the PHY to signal the 625 * beginning of the MII instruction. This is done by sending 32 626 * consecutive "1" bits. 627 */ 628 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 629 630 /* Now combine the remaining required fields that will indicate a 631 * write operation. We use this method instead of calling the 632 * e1000_shift_out_mdi_bits routine for each field in the command. The 633 * format of a MII write instruction is as follows: 634 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 635 */ 636 mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) | 637 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 638 mdic <<= 16; 639 mdic |= (u32) data; 640 641 e1000_shift_out_mdi_bits_82543(hw, mdic, 32); 642 643out: 644 return ret_val; 645} 646 647/** 648 * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock 649 * @hw: pointer to the HW structure 650 * @ctrl: pointer to the control register 651 * 652 * Raise the management data input clock by setting the MDC bit in the control 653 * register. 654 **/ 655static void 656e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 657{ 658 /* Raise the clock input to the Management Data Clock (by setting the 659 * MDC bit), and then delay a sufficient amount of time. 660 */ 661 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC)); 662 E1000_WRITE_FLUSH(hw); 663 usec_delay(10); 664} 665 666/** 667 * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock 668 * @hw: pointer to the HW structure 669 * @ctrl: pointer to the control register 670 * 671 * Lower the management data input clock by clearing the MDC bit in the control 672 * register. 673 **/ 674static void 675e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 676{ 677 /* Lower the clock input to the Management Data Clock (by clearing the 678 * MDC bit), and then delay a sufficient amount of time. 679 */ 680 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC)); 681 E1000_WRITE_FLUSH(hw); 682 usec_delay(10); 683} 684 685/** 686 * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY 687 * @hw: pointer to the HW structure 688 * @data: data to send to the PHY 689 * @count: number of bits to shift out 690 * 691 * We need to shift 'count' bits out to the PHY. So, the value in the 692 * "data" parameter will be shifted out to the PHY one bit at a time. 693 * In order to do this, "data" must be broken down into bits. 694 **/ 695static void 696e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, u16 count) 697{ 698 u32 ctrl, mask; 699 700 /* We need to shift "count" number of bits out to the PHY. So, the 701 * value in the "data" parameter will be shifted out to the PHY one 702 * bit at a time. In order to do this, "data" must be broken down 703 * into bits. 704 */ 705 mask = 0x01; 706 mask <<= (count -1); 707 708 ctrl = E1000_READ_REG(hw, E1000_CTRL); 709 710 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 711 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 712 713 while (mask) { 714 /* A "1" is shifted out to the PHY by setting the MDIO bit to 715 * "1" and then raising and lowering the Management Data Clock. 716 * A "0" is shifted out to the PHY by setting the MDIO bit to 717 * "0" and then raising and lowering the clock. 718 */ 719 if (data & mask) ctrl |= E1000_CTRL_MDIO; 720 else ctrl &= ~E1000_CTRL_MDIO; 721 722 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 723 E1000_WRITE_FLUSH(hw); 724 725 usec_delay(10); 726 727 e1000_raise_mdi_clk_82543(hw, &ctrl); 728 e1000_lower_mdi_clk_82543(hw, &ctrl); 729 730 mask >>= 1; 731 } 732} 733 734/** 735 * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY 736 * @hw: pointer to the HW structure 737 * 738 * In order to read a register from the PHY, we need to shift 18 bits 739 * in from the PHY. Bits are "shifted in" by raising the clock input to 740 * the PHY (setting the MDC bit), and then reading the value of the data out 741 * MDIO bit. 742 **/ 743static u16 744e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw) 745{ 746 u32 ctrl; 747 u16 data = 0; 748 u8 i; 749 750 /* In order to read a register from the PHY, we need to shift in a 751 * total of 18 bits from the PHY. The first two bit (turnaround) 752 * times are used to avoid contention on the MDIO pin when a read 753 * operation is performed. These two bits are ignored by us and 754 * thrown away. Bits are "shifted in" by raising the input to the 755 * Management Data Clock (setting the MDC bit) and then reading the 756 * value of the MDIO bit. 757 */ 758 ctrl = E1000_READ_REG(hw, E1000_CTRL); 759 760 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 761 * input. 762 */ 763 ctrl &= ~E1000_CTRL_MDIO_DIR; 764 ctrl &= ~E1000_CTRL_MDIO; 765 766 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 767 E1000_WRITE_FLUSH(hw); 768 769 /* Raise and lower the clock before reading in the data. This accounts 770 * for the turnaround bits. The first clock occurred when we clocked 771 * out the last bit of the Register Address. 772 */ 773 e1000_raise_mdi_clk_82543(hw, &ctrl); 774 e1000_lower_mdi_clk_82543(hw, &ctrl); 775 776 for (data = 0, i = 0; i < 16; i++) { 777 data <<= 1; 778 e1000_raise_mdi_clk_82543(hw, &ctrl); 779 ctrl = E1000_READ_REG(hw, E1000_CTRL); 780 /* Check to see if we shifted in a "1". */ 781 if (ctrl & E1000_CTRL_MDIO) 782 data |= 1; 783 e1000_lower_mdi_clk_82543(hw, &ctrl); 784 } 785 786 e1000_raise_mdi_clk_82543(hw, &ctrl); 787 e1000_lower_mdi_clk_82543(hw, &ctrl); 788 789 return data; 790} 791 792/** 793 * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY 794 * @hw: pointer to the HW structure 795 * 796 * Calls the function to force speed and duplex for the m88 PHY, and 797 * if the PHY is not auto-negotiating and the speed is forced to 10Mbit, 798 * then call the function for polarity reversal workaround. 799 **/ 800STATIC s32 801e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw) 802{ 803 s32 ret_val; 804 805 DEBUGFUNC("e1000_phy_force_speed_duplex_82543"); 806 807 ret_val = e1000_phy_force_speed_duplex_m88(hw); 808 if (ret_val) 809 goto out; 810 811 if (!hw->mac.autoneg && 812 (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)) 813 ret_val = e1000_polarity_reversal_workaround_82543(hw); 814 815out: 816 return ret_val; 817} 818 819/** 820 * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal 821 * @hw: pointer to the HW structure 822 * 823 * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity 824 * inadvertantly. To workaround the issue, we disable the transmitter on 825 * the PHY until we have established the link partner's link parameters. 826 **/ 827static s32 828e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw) 829{ 830 s32 ret_val; 831 u16 mii_status_reg; 832 u16 i; 833 boolean_t link; 834 835 /* Polarity reversal workaround for forced 10F/10H links. */ 836 837 /* Disable the transmitter on the PHY */ 838 839 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 840 if (ret_val) 841 goto out; 842 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 843 if (ret_val) 844 goto out; 845 846 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 847 if (ret_val) 848 goto out; 849 850 /* This loop will early-out if the NO link condition has been met. 851 * In other words, DO NOT use e1000_phy_has_link_generic() here. 852 */ 853 for (i = PHY_FORCE_TIME; i > 0; i--) { 854 /* Read the MII Status Register and wait for Link Status bit 855 * to be clear. 856 */ 857 858 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 859 if (ret_val) 860 goto out; 861 862 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 863 if (ret_val) 864 goto out; 865 866 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 867 break; 868 msec_delay_irq(100); 869 } 870 871 /* Recommended delay time after link has been lost */ 872 msec_delay_irq(1000); 873 874 /* Now we will re-enable the transmitter on the PHY */ 875 876 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 877 if (ret_val) 878 goto out; 879 msec_delay_irq(50); 880 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 881 if (ret_val) 882 goto out; 883 msec_delay_irq(50); 884 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 885 if (ret_val) 886 goto out; 887 msec_delay_irq(50); 888 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 889 if (ret_val) 890 goto out; 891 892 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 893 if (ret_val) 894 goto out; 895 896 /* Read the MII Status Register and wait for Link Status bit 897 * to be set. 898 */ 899 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link); 900 if (ret_val) 901 goto out; 902 903out: 904 return ret_val; 905} 906 907/** 908 * e1000_phy_hw_reset_82543 - PHY hardware reset 909 * @hw: pointer to the HW structure 910 * 911 * Sets the PHY_RESET_DIR bit in the extended device control register 912 * to put the PHY into a reset and waits for completion. Once the reset 913 * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out 914 * of reset. This is a function pointer entry point called by the api module. 915 **/ 916STATIC s32 917e1000_phy_hw_reset_82543(struct e1000_hw *hw) 918{ 919 struct e1000_functions *func = &hw->func; 920 u32 ctrl_ext; 921 s32 ret_val; 922 923 DEBUGFUNC("e1000_phy_hw_reset_82543"); 924 925 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 926 * bit to put the PHY into reset... 927 */ 928 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 929 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 930 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 931 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 932 E1000_WRITE_FLUSH(hw); 933 934 msec_delay(10); 935 936 /* ...then take it out of reset. */ 937 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 938 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 939 E1000_WRITE_FLUSH(hw); 940 941 usec_delay(150); 942 943 ret_val = func->get_cfg_done(hw); 944 945 return ret_val; 946} 947 948/** 949 * e1000_reset_hw_82543 - Reset hardware 950 * @hw: pointer to the HW structure 951 * 952 * This resets the hardware into a known state. This is a 953 * function pointer entry point called by the api module. 954 **/ 955STATIC s32 956e1000_reset_hw_82543(struct e1000_hw *hw) 957{ 958 u32 ctrl, icr; 959 s32 ret_val = E1000_SUCCESS; 960 961 DEBUGFUNC("e1000_reset_hw_82543"); 962 963 DEBUGOUT("Masking off all interrupts\n"); 964 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 965 966 E1000_WRITE_REG(hw, E1000_RCTL, 0); 967 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 968 E1000_WRITE_FLUSH(hw); 969 970 e1000_set_tbi_sbp_82543(hw, FALSE); 971 972 /* Delay to allow any outstanding PCI transactions to complete before 973 * resetting the device 974 */ 975 msec_delay(10); 976 977 ctrl = E1000_READ_REG(hw, E1000_CTRL); 978 979 DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n"); 980 if (hw->mac.type == e1000_82543) { 981 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 982 } else { 983 /* The 82544 can't ACK the 64-bit write when issuing the 984 * reset, so use IO-mapping as a workaround. 985 */ 986 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 987 } 988 989 /* After MAC reset, force reload of NVM to restore power-on 990 * settings to device. 991 */ 992 e1000_reload_nvm(hw); 993 msec_delay(2); 994 995 /* Masking off and clearing any pending interrupts */ 996 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 997 icr = E1000_READ_REG(hw, E1000_ICR); 998 999 return ret_val; 1000} 1001 1002/** 1003 * e1000_init_hw_82543 - Initialize hardware 1004 * @hw: pointer to the HW structure 1005 * 1006 * This inits the hardware readying it for operation. 1007 **/ 1008STATIC s32 1009e1000_init_hw_82543(struct e1000_hw *hw) 1010{ 1011 struct e1000_mac_info *mac = &hw->mac; 1012 struct e1000_dev_spec_82543 *dev_spec; 1013 u32 ctrl; 1014 s32 ret_val; 1015 u16 i; 1016 1017 DEBUGFUNC("e1000_init_hw_82543"); 1018 1019 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 1020 1021 if (dev_spec == NULL) { 1022 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 1023 ret_val = -E1000_ERR_CONFIG; 1024 goto out; 1025 } 1026 1027 /* Disabling VLAN filtering */ 1028 E1000_WRITE_REG(hw, E1000_VET, 0); 1029 e1000_clear_vfta(hw); 1030 1031 /* Setup the receive address. */ 1032 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 1033 1034 /* Zero out the Multicast HASH table */ 1035 DEBUGOUT("Zeroing the MTA\n"); 1036 for (i = 0; i < mac->mta_reg_count; i++) { 1037 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1038 E1000_WRITE_FLUSH(hw); 1039 } 1040 1041 /* Set the PCI priority bit correctly in the CTRL register. This 1042 * determines if the adapter gives priority to receives, or if it 1043 * gives equal priority to transmits and receives. 1044 */ 1045 if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) { 1046 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1047 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); 1048 } 1049 1050 e1000_pcix_mmrbc_workaround_generic(hw); 1051 1052 /* Setup link and flow control */ 1053 ret_val = e1000_setup_link(hw); 1054 1055 /* Clear all of the statistics registers (clear on read). It is 1056 * important that we do this after we have tried to establish link 1057 * because the symbol error count will increment wildly if there 1058 * is no link. 1059 */ 1060 e1000_clear_hw_cntrs_82543(hw); 1061 1062out: 1063 return ret_val; 1064} 1065 1066/** 1067 * e1000_setup_link_82543 - Setup flow control and link settings 1068 * @hw: pointer to the HW structure 1069 * 1070 * Read the EEPROM to determine the initial polarity value and write the 1071 * extended device control register with the information before calling 1072 * the generic setup link function, which does the following: 1073 * Determines which flow control settings to use, then configures flow 1074 * control. Calls the appropriate media-specific link configuration 1075 * function. Assuming the adapter has a valid link partner, a valid link 1076 * should be established. Assumes the hardware has previously been reset 1077 * and the transmitter and receiver are not enabled. 1078 **/ 1079STATIC s32 1080e1000_setup_link_82543(struct e1000_hw *hw) 1081{ 1082 u32 ctrl_ext; 1083 s32 ret_val; 1084 u16 data; 1085 1086 DEBUGFUNC("e1000_setup_link_82543"); 1087 1088 /* Take the 4 bits from NVM word 0xF that determine the initial 1089 * polarity value for the SW controlled pins, and setup the 1090 * Extended Device Control reg with that info. 1091 * This is needed because one of the SW controlled pins is used for 1092 * signal detection. So this should be done before phy setup. 1093 */ 1094 if (hw->mac.type == e1000_82543) { 1095 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1096 if (ret_val) { 1097 DEBUGOUT("NVM Read Error\n"); 1098 ret_val = -E1000_ERR_NVM; 1099 goto out; 1100 } 1101 ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) << 1102 NVM_SWDPIO_EXT_SHIFT); 1103 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1104 } 1105 1106 ret_val = e1000_setup_link_generic(hw); 1107 1108out: 1109 return ret_val; 1110} 1111 1112/** 1113 * e1000_setup_copper_link_82543 - Configure copper link settings 1114 * @hw: pointer to the HW structure 1115 * 1116 * Configures the link for auto-neg or forced speed and duplex. Then we check 1117 * for link, once link is established calls to configure collision distance 1118 * and flow control are called. 1119 **/ 1120STATIC s32 1121e1000_setup_copper_link_82543(struct e1000_hw *hw) 1122{ 1123 u32 ctrl; 1124 s32 ret_val; 1125 boolean_t link; 1126 1127 DEBUGFUNC("e1000_setup_copper_link_82543"); 1128 1129 ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU; 1130 /* With 82543, we need to force speed and duplex on the MAC 1131 * equal to what the PHY speed and duplex configuration is. 1132 * In addition, we need to perform a hardware reset on the 1133 * PHY to take it out of reset. 1134 */ 1135 if (hw->mac.type == e1000_82543) { 1136 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1137 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1138 ret_val = e1000_phy_hw_reset(hw); 1139 if (ret_val) 1140 goto out; 1141 hw->phy.reset_disable = FALSE; 1142 } else { 1143 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1144 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1145 } 1146 1147 /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */ 1148 ret_val = e1000_copper_link_setup_m88(hw); 1149 if (ret_val) 1150 goto out; 1151 1152 if (hw->mac.autoneg) { 1153 /* Setup autoneg and flow control advertisement and perform 1154 * autonegotiation. */ 1155 ret_val = e1000_copper_link_autoneg(hw); 1156 if (ret_val) 1157 goto out; 1158 } else { 1159 /* PHY will be set to 10H, 10F, 100H or 100F 1160 * depending on user settings. */ 1161 DEBUGOUT("Forcing Speed and Duplex\n"); 1162 ret_val = e1000_phy_force_speed_duplex_82543(hw); 1163 if (ret_val) { 1164 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1165 goto out; 1166 } 1167 } 1168 1169 /* Check link status. Wait up to 100 microseconds for link to become 1170 * valid. 1171 */ 1172 ret_val = e1000_phy_has_link_generic(hw, 1173 COPPER_LINK_UP_LIMIT, 1174 10, 1175 &link); 1176 if (ret_val) 1177 goto out; 1178 1179 1180 if (link) { 1181 DEBUGOUT("Valid link established!!!\n"); 1182 /* Config the MAC and PHY after link is up */ 1183 if (hw->mac.type == e1000_82544) 1184 e1000_config_collision_dist_generic(hw); 1185 else { 1186 ret_val = e1000_config_mac_to_phy_82543(hw); 1187 if (ret_val) 1188 goto out; 1189 } 1190 ret_val = e1000_config_fc_after_link_up_generic(hw); 1191 } else { 1192 DEBUGOUT("Unable to establish link!!!\n"); 1193 } 1194 1195out: 1196 return ret_val; 1197} 1198 1199/** 1200 * e1000_setup_fiber_link_82543 - Setup link for fiber 1201 * @hw: pointer to the HW structure 1202 * 1203 * Configures collision distance and flow control for fiber links. Upon 1204 * successful setup, poll for link. 1205 **/ 1206STATIC s32 1207e1000_setup_fiber_link_82543(struct e1000_hw *hw) 1208{ 1209 u32 ctrl; 1210 s32 ret_val; 1211 1212 DEBUGFUNC("e1000_setup_fiber_link_82543"); 1213 1214 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1215 1216 /* Take the link out of reset */ 1217 ctrl &= ~E1000_CTRL_LRST; 1218 1219 e1000_config_collision_dist_generic(hw); 1220 1221 ret_val = e1000_commit_fc_settings_generic(hw); 1222 if (ret_val) 1223 goto out; 1224 1225 DEBUGOUT("Auto-negotiation enabled\n"); 1226 1227 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1228 E1000_WRITE_FLUSH(hw); 1229 msec_delay(1); 1230 1231 /* For these adapters, the SW defineable pin 1 is cleared when the 1232 * optics detect a signal. If we have a signal, then poll for a 1233 * "Link-Up" indication. 1234 */ 1235 if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1236 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1237 } else { 1238 DEBUGOUT("No signal detected\n"); 1239 } 1240 1241out: 1242 return ret_val; 1243} 1244 1245/** 1246 * e1000_check_for_copper_link_82543 - Check for link (Copper) 1247 * @hw: pointer to the HW structure 1248 * 1249 * Checks the phy for link, if link exists, do the following: 1250 * - check for downshift 1251 * - do polarity workaround (if necessary) 1252 * - configure collision distance 1253 * - configure flow control after link up 1254 * - configure tbi compatibility 1255 **/ 1256STATIC s32 1257e1000_check_for_copper_link_82543(struct e1000_hw *hw) 1258{ 1259 struct e1000_mac_info *mac = &hw->mac; 1260 u32 icr, rctl; 1261 s32 ret_val; 1262 u16 speed, duplex; 1263 boolean_t link; 1264 1265 DEBUGFUNC("e1000_check_for_copper_link_82543"); 1266 1267 if (!mac->get_link_status) { 1268 ret_val = E1000_SUCCESS; 1269 goto out; 1270 } 1271 1272 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1273 if (ret_val) 1274 goto out; 1275 1276 if (!link) 1277 goto out; /* No link detected */ 1278 1279 mac->get_link_status = FALSE; 1280 1281 e1000_check_downshift_generic(hw); 1282 1283 /* If we are forcing speed/duplex, then we can return since 1284 * we have already determined whether we have link or not. 1285 */ 1286 if (!mac->autoneg) { 1287 /* If speed and duplex are forced to 10H or 10F, then we will 1288 * implement the polarity reversal workaround. We disable 1289 * interrupts first, and upon returning, place the devices 1290 * interrupt state to its previous value except for the link 1291 * status change interrupt which will happened due to the 1292 * execution of this workaround. 1293 */ 1294 if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) { 1295 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 1296 ret_val = e1000_polarity_reversal_workaround_82543(hw); 1297 icr = E1000_READ_REG(hw, E1000_ICR); 1298 E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC)); 1299 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 1300 } 1301 1302 ret_val = -E1000_ERR_CONFIG; 1303 goto out; 1304 } 1305 1306 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 1307 * have Si on board that is 82544 or newer, Auto 1308 * Speed Detection takes care of MAC speed/duplex 1309 * configuration. So we only need to configure Collision 1310 * Distance in the MAC. Otherwise, we need to force 1311 * speed/duplex on the MAC to the current PHY speed/duplex 1312 * settings. 1313 */ 1314 if (mac->type == e1000_82544) 1315 e1000_config_collision_dist_generic(hw); 1316 else { 1317 ret_val = e1000_config_mac_to_phy_82543(hw); 1318 if (ret_val) { 1319 DEBUGOUT("Error configuring MAC to PHY settings\n"); 1320 goto out; 1321 } 1322 } 1323 1324 /* Configure Flow Control now that Auto-Neg has completed. 1325 * First, we need to restore the desired flow control 1326 * settings because we may have had to re-autoneg with a 1327 * different link partner. 1328 */ 1329 ret_val = e1000_config_fc_after_link_up_generic(hw); 1330 if (ret_val) { 1331 DEBUGOUT("Error configuring flow control\n"); 1332 } 1333 1334 /* At this point we know that we are on copper and we have 1335 * auto-negotiated link. These are conditions for checking the link 1336 * partner capability register. We use the link speed to determine if 1337 * TBI compatibility needs to be turned on or off. If the link is not 1338 * at gigabit speed, then TBI compatibility is not needed. If we are 1339 * at gigabit speed, we turn on TBI compatibility. 1340 */ 1341 if (e1000_tbi_compatibility_enabled_82543(hw)) { 1342 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 1343 if (ret_val) { 1344 DEBUGOUT("Error getting link speed and duplex\n"); 1345 return ret_val; 1346 } 1347 if (speed != SPEED_1000) { 1348 /* If link speed is not set to gigabit speed, 1349 * we do not need to enable TBI compatibility. 1350 */ 1351 if (e1000_tbi_sbp_enabled_82543(hw)) { 1352 /* If we previously were in the mode, 1353 * turn it off. 1354 */ 1355 e1000_set_tbi_sbp_82543(hw, FALSE); 1356 rctl = E1000_READ_REG(hw, E1000_RCTL); 1357 rctl &= ~E1000_RCTL_SBP; 1358 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1359 } 1360 } else { 1361 /* If TBI compatibility is was previously off, 1362 * turn it on. For compatibility with a TBI link 1363 * partner, we will store bad packets. Some 1364 * frames have an additional byte on the end and 1365 * will look like CRC errors to to the hardware. 1366 */ 1367 if (!e1000_tbi_sbp_enabled_82543(hw)) { 1368 e1000_set_tbi_sbp_82543(hw, TRUE); 1369 rctl = E1000_READ_REG(hw, E1000_RCTL); 1370 rctl |= E1000_RCTL_SBP; 1371 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1372 } 1373 } 1374 } 1375out: 1376 return ret_val; 1377} 1378 1379/** 1380 * e1000_check_for_fiber_link_82543 - Check for link (Fiber) 1381 * @hw: pointer to the HW structure 1382 * 1383 * Checks for link up on the hardware. If link is not up and we have 1384 * a signal, then we need to force link up. 1385 **/ 1386STATIC s32 1387e1000_check_for_fiber_link_82543(struct e1000_hw *hw) 1388{ 1389 struct e1000_mac_info *mac = &hw->mac; 1390 u32 rxcw, ctrl, status; 1391 s32 ret_val = E1000_SUCCESS; 1392 1393 DEBUGFUNC("e1000_check_for_fiber_link_82543"); 1394 1395 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1396 status = E1000_READ_REG(hw, E1000_CTRL); 1397 rxcw = E1000_READ_REG(hw, E1000_CTRL); 1398 1399 /* If we don't have link (auto-negotiation failed or link partner 1400 * cannot auto-negotiate), the cable is plugged in (we have signal), 1401 * and our link partner is not trying to auto-negotiate with us (we 1402 * are receiving idles or data), we need to force link up. We also 1403 * need to give auto-negotiation time to complete, in case the cable 1404 * was just plugged in. The autoneg_failed flag does this. 1405 */ 1406 /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */ 1407 if ((!(ctrl & E1000_CTRL_SWDPIN1)) && 1408 (!(status & E1000_STATUS_LU)) && 1409 (!(rxcw & E1000_RXCW_C))) { 1410 if (mac->autoneg_failed == 0) { 1411 mac->autoneg_failed = 1; 1412 ret_val = 0; 1413 goto out; 1414 } 1415 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 1416 1417 /* Disable auto-negotiation in the TXCW register */ 1418 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 1419 1420 /* Force link-up and also force full-duplex. */ 1421 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1422 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1423 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1424 1425 /* Configure Flow Control after forcing link up. */ 1426 ret_val = e1000_config_fc_after_link_up_generic(hw); 1427 if (ret_val) { 1428 DEBUGOUT("Error configuring flow control\n"); 1429 goto out; 1430 } 1431 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 1432 /* If we are forcing link and we are receiving /C/ ordered 1433 * sets, re-enable auto-negotiation in the TXCW register 1434 * and disable forced link in the Device Control register 1435 * in an attempt to auto-negotiate with our link partner. 1436 */ 1437 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 1438 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1439 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 1440 1441 mac->serdes_has_link = TRUE; 1442 } 1443 1444out: 1445 return ret_val; 1446} 1447 1448/** 1449 * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings 1450 * @hw: pointer to the HW structure 1451 * 1452 * For the 82543 silicon, we need to set the MAC to match the settings 1453 * of the PHY, even if the PHY is auto-negotiating. 1454 **/ 1455static s32 1456e1000_config_mac_to_phy_82543(struct e1000_hw *hw) 1457{ 1458 u32 ctrl; 1459 s32 ret_val; 1460 u16 phy_data; 1461 1462 DEBUGFUNC("e1000_config_mac_to_phy_82543"); 1463 1464 /* Set the bits to force speed and duplex */ 1465 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1466 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1467 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1468 1469 /* Set up duplex in the Device Control and Transmit Control 1470 * registers depending on negotiated values. 1471 */ 1472 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1473 if (ret_val) 1474 goto out; 1475 1476 ctrl &= ~E1000_CTRL_FD; 1477 if (phy_data & M88E1000_PSSR_DPLX) 1478 ctrl |= E1000_CTRL_FD; 1479 1480 e1000_config_collision_dist_generic(hw); 1481 1482 /* Set up speed in the Device Control register depending on 1483 * negotiated values. 1484 */ 1485 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1486 ctrl |= E1000_CTRL_SPD_1000; 1487 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 1488 ctrl |= E1000_CTRL_SPD_100; 1489 1490 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1491 1492out: 1493 return ret_val; 1494} 1495 1496/** 1497 * e1000_write_vfta_82543 - Write value to VLAN filter table 1498 * @hw: pointer to the HW structure 1499 * @offset: the 32-bit offset in which to write the value to. 1500 * @value: the 32-bit value to write at location offset. 1501 * 1502 * This writes a 32-bit value to a 32-bit offset in the VLAN filter 1503 * table. 1504 **/ 1505STATIC void 1506e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value) 1507{ 1508 u32 temp; 1509 1510 DEBUGFUNC("e1000_write_vfta_82543"); 1511 1512 if ((hw->mac.type == e1000_82544) && (offset & 1)) { 1513 temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1); 1514 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 1515 E1000_WRITE_FLUSH(hw); 1516 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp); 1517 E1000_WRITE_FLUSH(hw); 1518 } else 1519 e1000_write_vfta_generic(hw, offset, value); 1520} 1521 1522/** 1523 * e1000_mta_set_82543 - Set multicast filter table address 1524 * @hw: pointer to the HW structure 1525 * @hash_value: determines the MTA register and bit to set 1526 * 1527 * The multicast table address is a register array of 32-bit registers. 1528 * The hash_value is used to determine what register the bit is in, the 1529 * current value is read, the new bit is OR'd in and the new value is 1530 * written back into the register. 1531 **/ 1532STATIC void 1533e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value) 1534{ 1535 u32 hash_bit, hash_reg, mta, temp; 1536 1537 DEBUGFUNC("e1000_mta_set_82543"); 1538 1539 hash_reg = (hash_value >> 5); 1540 1541 /* If we are on an 82544 and we are trying to write an odd offset 1542 * in the MTA, save off the previous entry before writing and 1543 * restore the old value after writing. 1544 */ 1545 if ((hw->mac.type == e1000_82544) && (hash_reg & 1)) { 1546 hash_reg &= (hw->mac.mta_reg_count - 1); 1547 hash_bit = hash_value & 0x1F; 1548 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 1549 mta |= (1 << hash_bit); 1550 temp = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg - 1); 1551 1552 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 1553 E1000_WRITE_FLUSH(hw); 1554 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg - 1, temp); 1555 E1000_WRITE_FLUSH(hw); 1556 } else 1557 e1000_mta_set_generic(hw, hash_value); 1558} 1559 1560/** 1561 * e1000_led_on_82543 - Turn on SW controllable LED 1562 * @hw: pointer to the HW structure 1563 * 1564 * Turns the SW defined LED on. This is a function pointer entry point 1565 * called by the api module. 1566 **/ 1567STATIC s32 1568e1000_led_on_82543(struct e1000_hw *hw) 1569{ 1570 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1571 1572 DEBUGFUNC("e1000_led_on_82543"); 1573 1574 if (hw->mac.type == e1000_82544 && 1575 hw->media_type == e1000_media_type_copper) { 1576 /* Clear SW-defineable Pin 0 to turn on the LED */ 1577 ctrl &= ~E1000_CTRL_SWDPIN0; 1578 ctrl |= E1000_CTRL_SWDPIO0; 1579 } else { 1580 /* Fiber 82544 and all 82543 use this method */ 1581 ctrl |= E1000_CTRL_SWDPIN0; 1582 ctrl |= E1000_CTRL_SWDPIO0; 1583 } 1584 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1585 1586 return E1000_SUCCESS; 1587} 1588 1589/** 1590 * e1000_led_off_82543 - Turn off SW controllable LED 1591 * @hw: pointer to the HW structure 1592 * 1593 * Turns the SW defined LED off. This is a function pointer entry point 1594 * called by the api module. 1595 **/ 1596STATIC s32 1597e1000_led_off_82543(struct e1000_hw *hw) 1598{ 1599 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1600 1601 DEBUGFUNC("e1000_led_off_82543"); 1602 1603 if (hw->mac.type == e1000_82544 && 1604 hw->media_type == e1000_media_type_copper) { 1605 /* Set SW-defineable Pin 0 to turn off the LED */ 1606 ctrl |= E1000_CTRL_SWDPIN0; 1607 ctrl |= E1000_CTRL_SWDPIO0; 1608 } else { 1609 ctrl &= ~E1000_CTRL_SWDPIN0; 1610 ctrl |= E1000_CTRL_SWDPIO0; 1611 } 1612 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1613 1614 return E1000_SUCCESS; 1615} 1616 1617/** 1618 * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters 1619 * @hw: pointer to the HW structure 1620 * 1621 * Clears the hardware counters by reading the counter registers. 1622 **/ 1623STATIC void 1624e1000_clear_hw_cntrs_82543(struct e1000_hw *hw) 1625{ 1626 volatile u32 temp; 1627 1628 DEBUGFUNC("e1000_clear_hw_cntrs_82543"); 1629 1630 e1000_clear_hw_cntrs_base_generic(hw); 1631 1632 temp = E1000_READ_REG(hw, E1000_PRC64); 1633 temp = E1000_READ_REG(hw, E1000_PRC127); 1634 temp = E1000_READ_REG(hw, E1000_PRC255); 1635 temp = E1000_READ_REG(hw, E1000_PRC511); 1636 temp = E1000_READ_REG(hw, E1000_PRC1023); 1637 temp = E1000_READ_REG(hw, E1000_PRC1522); 1638 temp = E1000_READ_REG(hw, E1000_PTC64); 1639 temp = E1000_READ_REG(hw, E1000_PTC127); 1640 temp = E1000_READ_REG(hw, E1000_PTC255); 1641 temp = E1000_READ_REG(hw, E1000_PTC511); 1642 temp = E1000_READ_REG(hw, E1000_PTC1023); 1643 temp = E1000_READ_REG(hw, E1000_PTC1522); 1644 1645 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1646 temp = E1000_READ_REG(hw, E1000_RXERRC); 1647 temp = E1000_READ_REG(hw, E1000_TNCRS); 1648 temp = E1000_READ_REG(hw, E1000_CEXTERR); 1649 temp = E1000_READ_REG(hw, E1000_TSCTC); 1650 temp = E1000_READ_REG(hw, E1000_TSCTFC); 1651} 1652