e1000_82543.c revision 169240
1/******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33$FreeBSD: head/sys/dev/em/e1000_82543.c 169240 2007-05-04 00:00:12Z jfv $ 34 35 36/* e1000_82543 37 * e1000_82544 38 */ 39 40#include "e1000_82543.h" 41 42void e1000_init_function_pointers_82543(struct e1000_hw *hw); 43 44STATIC s32 e1000_init_phy_params_82543(struct e1000_hw *hw); 45STATIC s32 e1000_init_nvm_params_82543(struct e1000_hw *hw); 46STATIC s32 e1000_init_mac_params_82543(struct e1000_hw *hw); 47STATIC s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, 48 u16 *data); 49STATIC s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, 50 u16 data); 51STATIC s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw); 52STATIC s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw); 53STATIC s32 e1000_reset_hw_82543(struct e1000_hw *hw); 54STATIC s32 e1000_init_hw_82543(struct e1000_hw *hw); 55STATIC s32 e1000_setup_link_82543(struct e1000_hw *hw); 56STATIC s32 e1000_setup_copper_link_82543(struct e1000_hw *hw); 57STATIC s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw); 58STATIC s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw); 59STATIC s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw); 60STATIC s32 e1000_led_on_82543(struct e1000_hw *hw); 61STATIC s32 e1000_led_off_82543(struct e1000_hw *hw); 62STATIC void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, 63 u32 value); 64STATIC void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value); 65STATIC void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw); 66static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw); 67static boolean_t e1000_init_phy_disabled_82543(struct e1000_hw *hw); 68static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 69static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw); 70static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 71static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw); 72static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 73 u16 count); 74static boolean_t e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw); 75static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, boolean_t state); 76 77struct e1000_dev_spec_82543 { 78 u32 tbi_compatibility; 79 boolean_t dma_fairness; 80 boolean_t init_phy_disabled; 81}; 82 83/** 84 * e1000_init_phy_params_82543 - Init PHY func ptrs. 85 * @hw - pointer to the HW structure 86 * 87 * This is a function pointer entry point called by the api module. 88 **/ 89STATIC s32 90e1000_init_phy_params_82543(struct e1000_hw *hw) 91{ 92 struct e1000_phy_info *phy = &hw->phy; 93 struct e1000_functions *func = &hw->func; 94 s32 ret_val = E1000_SUCCESS; 95 96 DEBUGFUNC("e1000_init_phy_params_82543"); 97 98 if (hw->media_type != e1000_media_type_copper) { 99 phy->type = e1000_phy_none; 100 goto out; 101 } 102 103 phy->addr = 1; 104 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 105 phy->reset_delay_us = 10000; 106 phy->type = e1000_phy_m88; 107 108 /* Function Pointers */ 109 func->check_polarity = e1000_check_polarity_m88; 110 func->commit_phy = e1000_phy_sw_reset_generic; 111 func->force_speed_duplex = e1000_phy_force_speed_duplex_82543; 112 func->get_cable_length = e1000_get_cable_length_m88; 113 func->get_cfg_done = e1000_get_cfg_done_generic; 114 func->read_phy_reg = (hw->mac.type == e1000_82543) 115 ? e1000_read_phy_reg_82543 116 : e1000_read_phy_reg_m88; 117 func->reset_phy = (hw->mac.type == e1000_82543) 118 ? e1000_phy_hw_reset_82543 119 : e1000_phy_hw_reset_generic; 120 func->write_phy_reg = (hw->mac.type == e1000_82543) 121 ? e1000_write_phy_reg_82543 122 : e1000_write_phy_reg_m88; 123 func->get_phy_info = e1000_get_phy_info_m88; 124 125 /* The external PHY of the 82543 can be in a funky state. 126 * Resetting helps us read the PHY registers for acquiring 127 * the PHY ID. 128 */ 129 if (!e1000_init_phy_disabled_82543(hw)) { 130 ret_val = e1000_phy_hw_reset(hw); 131 if (ret_val) { 132 DEBUGOUT("Resetting PHY during init failed.\n"); 133 goto out; 134 } 135 msec_delay(20); 136 } 137 138 ret_val = e1000_get_phy_id(hw); 139 if (ret_val) 140 goto out; 141 142 /* Verify phy id */ 143 switch (hw->mac.type) { 144 case e1000_82543: 145 if (phy->id != M88E1000_E_PHY_ID) { 146 ret_val = -E1000_ERR_PHY; 147 goto out; 148 } 149 break; 150 case e1000_82544: 151 if (phy->id != M88E1000_I_PHY_ID) { 152 ret_val = -E1000_ERR_PHY; 153 goto out; 154 } 155 break; 156 default: 157 ret_val = -E1000_ERR_PHY; 158 goto out; 159 break; 160 } 161 162out: 163 return ret_val; 164} 165 166/** 167 * e1000_init_nvm_params_82543 - Init NVM func ptrs. 168 * @hw - pointer to the HW structure 169 * 170 * This is a function pointer entry point called by the api module. 171 **/ 172STATIC s32 173e1000_init_nvm_params_82543(struct e1000_hw *hw) 174{ 175 struct e1000_nvm_info *nvm = &hw->nvm; 176 struct e1000_functions *func = &hw->func; 177 178 DEBUGFUNC("e1000_init_nvm_params_82543"); 179 180 nvm->type = e1000_nvm_eeprom_microwire; 181 nvm->word_size = 64; 182 nvm->delay_usec = 50; 183 nvm->address_bits = 6; 184 nvm->opcode_bits = 3; 185 186 /* Function Pointers */ 187 func->read_nvm = e1000_read_nvm_microwire; 188 func->update_nvm = e1000_update_nvm_checksum_generic; 189 func->valid_led_default = e1000_valid_led_default_generic; 190 func->validate_nvm = e1000_validate_nvm_checksum_generic; 191 func->write_nvm = e1000_write_nvm_microwire; 192 193 return E1000_SUCCESS; 194} 195 196/** 197 * e1000_init_mac_params_82543 - Init MAC func ptrs. 198 * @hw - pointer to the HW structure 199 * 200 * This is a function pointer entry point called by the api module. 201 **/ 202STATIC s32 203e1000_init_mac_params_82543(struct e1000_hw *hw) 204{ 205 struct e1000_mac_info *mac = &hw->mac; 206 struct e1000_functions *func = &hw->func; 207 s32 ret_val; 208 209 DEBUGFUNC("e1000_init_mac_params_82543"); 210 211 /* Set media type */ 212 switch (hw->device_id) { 213 case E1000_DEV_ID_82543GC_FIBER: 214 case E1000_DEV_ID_82544EI_FIBER: 215 hw->media_type = e1000_media_type_fiber; 216 break; 217 default: 218 hw->media_type = e1000_media_type_copper; 219 break; 220 } 221 222 /* Set mta register count */ 223 mac->mta_reg_count = 128; 224 /* Set rar entry count */ 225 mac->rar_entry_count = E1000_RAR_ENTRIES; 226 227 /* Function pointers */ 228 229 /* bus type/speed/width */ 230 func->get_bus_info = e1000_get_bus_info_pci_generic; 231 /* reset */ 232 func->reset_hw = e1000_reset_hw_82543; 233 /* hw initialization */ 234 func->init_hw = e1000_init_hw_82543; 235 /* link setup */ 236 func->setup_link = e1000_setup_link_82543; 237 /* physical interface setup */ 238 func->setup_physical_interface = 239 (hw->media_type == e1000_media_type_copper) 240 ? e1000_setup_copper_link_82543 241 : e1000_setup_fiber_link_82543; 242 /* check for link */ 243 func->check_for_link = 244 (hw->media_type == e1000_media_type_copper) 245 ? e1000_check_for_copper_link_82543 246 : e1000_check_for_fiber_link_82543; 247 /* link info */ 248 func->get_link_up_info = 249 (hw->media_type == e1000_media_type_copper) 250 ? e1000_get_speed_and_duplex_copper_generic 251 : e1000_get_speed_and_duplex_fiber_serdes_generic; 252 /* multicast address update */ 253 func->mc_addr_list_update = e1000_mc_addr_list_update_generic; 254 /* writing VFTA */ 255 func->write_vfta = e1000_write_vfta_82543; 256 /* clearing VFTA */ 257 func->clear_vfta = e1000_clear_vfta_generic; 258 /* setting MTA */ 259 func->mta_set = e1000_mta_set_82543; 260 /* turn on/off LED */ 261 func->led_on = e1000_led_on_82543; 262 func->led_off = e1000_led_off_82543; 263 /* remove device */ 264 func->remove_device = e1000_remove_device_generic; 265 /* clear hardware counters */ 266 func->clear_hw_cntrs = e1000_clear_hw_cntrs_82543; 267 268 hw->dev_spec_size = sizeof(struct e1000_dev_spec_82543); 269 270 /* Device-specific structure allocation */ 271 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 272 if (ret_val) 273 goto out; 274 275 /* Set tbi compatibility */ 276 if ((hw->mac.type != e1000_82543) || 277 (hw->media_type == e1000_media_type_fiber)) 278 e1000_set_tbi_compatibility_82543(hw, FALSE); 279 280out: 281 return ret_val; 282} 283 284/** 285 * e1000_init_function_pointers_82543 - Init func ptrs. 286 * @hw - pointer to the HW structure 287 * 288 * The only function explicitly called by the api module to initialize 289 * all function pointers and parameters. 290 **/ 291void 292e1000_init_function_pointers_82543(struct e1000_hw *hw) 293{ 294 DEBUGFUNC("e1000_init_function_pointers_82543"); 295 296 hw->func.init_mac_params = e1000_init_mac_params_82543; 297 hw->func.init_nvm_params = e1000_init_nvm_params_82543; 298 hw->func.init_phy_params = e1000_init_phy_params_82543; 299} 300 301/** 302 * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status 303 * @hw - pointer to the HW structure 304 * 305 * Returns the curent status of 10-bit Interface (TBI) compatibility 306 * (enabled/disabled). 307 **/ 308static boolean_t 309e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw) 310{ 311 struct e1000_dev_spec_82543 *dev_spec; 312 boolean_t state = FALSE; 313 314 DEBUGFUNC("e1000_tbi_compatibility_enabled_82543"); 315 316 if (hw->mac.type != e1000_82543) { 317 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 318 goto out; 319 } 320 321 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 322 323 if (dev_spec == NULL) { 324 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 325 goto out; 326 } 327 328 state = (dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED) 329 ? TRUE : FALSE; 330 331out: 332 return state; 333} 334 335/** 336 * e1000_set_tbi_compatibility_82543 - Set TBI compatibility 337 * @hw - pointer to the HW structure 338 * @state - enable/disable TBI compatibility 339 * 340 * Enables or disabled 10-bit Interface (TBI) compatibility. 341 **/ 342void 343e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, boolean_t state) 344{ 345 struct e1000_dev_spec_82543 *dev_spec; 346 347 DEBUGFUNC("e1000_set_tbi_compatibility_82543"); 348 349 if (hw->mac.type != e1000_82543) { 350 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 351 goto out; 352 } 353 354 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 355 356 if (dev_spec == NULL) { 357 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 358 goto out; 359 } 360 361 if (state) 362 dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED; 363 else 364 dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED; 365 366out: 367 return; 368} 369 370/** 371 * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status 372 * @hw - pointer to the HW structure 373 * 374 * Returns the curent status of 10-bit Interface (TBI) store bad packet (SBP) 375 * (enabled/disabled). 376 **/ 377boolean_t 378e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw) 379{ 380 struct e1000_dev_spec_82543 *dev_spec; 381 boolean_t state = FALSE; 382 383 DEBUGFUNC("e1000_tbi_sbp_enabled_82543"); 384 385 if (hw->mac.type != e1000_82543) { 386 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 387 goto out; 388 } 389 390 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 391 392 if (dev_spec == NULL) { 393 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 394 goto out; 395 } 396 397 state = (dev_spec->tbi_compatibility & TBI_SBP_ENABLED) 398 ? TRUE : FALSE; 399 400out: 401 return state; 402} 403 404/** 405 * e1000_set_tbi_sbp_82543 - Set TBI SBP 406 * @hw - pointer to the HW structure 407 * @state - enable/disable TBI store bad packet 408 * 409 * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP). 410 **/ 411static void 412e1000_set_tbi_sbp_82543(struct e1000_hw *hw, boolean_t state) 413{ 414 struct e1000_dev_spec_82543 *dev_spec; 415 416 DEBUGFUNC("e1000_set_tbi_sbp_82543"); 417 418 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 419 420 if (state && e1000_tbi_compatibility_enabled_82543(hw)) 421 dev_spec->tbi_compatibility |= TBI_SBP_ENABLED; 422 else 423 dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED; 424 425 return; 426} 427 428/** 429 * e1000_init_phy_disabled_82543 - Returns init PHY status 430 * @hw - pointer to the HW structure 431 * 432 * Returns the current status of whether PHY initialization is disabled. 433 * True if PHY initialization is disabled else false. 434 **/ 435static boolean_t 436e1000_init_phy_disabled_82543(struct e1000_hw *hw) 437{ 438 struct e1000_dev_spec_82543 *dev_spec; 439 boolean_t ret_val; 440 441 DEBUGFUNC("e1000_init_phy_disabled_82543"); 442 443 if (hw->mac.type != e1000_82543) { 444 ret_val = FALSE; 445 goto out; 446 } 447 448 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 449 450 if (dev_spec == NULL) { 451 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 452 ret_val = FALSE; 453 goto out; 454 } 455 456 ret_val = dev_spec->init_phy_disabled; 457 458out: 459 return ret_val; 460} 461 462/** 463 * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled 464 * @hw - pointer to the HW structure 465 * @stats - Struct containing statistic register values 466 * @frame_len - The length of the frame in question 467 * @mac_addr - The Ethernet destination address of the frame in question 468 * 469 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 470 **/ 471void 472e1000_tbi_adjust_stats_82543(struct e1000_hw *hw, struct e1000_hw_stats *stats, 473 u32 frame_len, u8 *mac_addr) 474{ 475 u64 carry_bit; 476 477 if (e1000_tbi_sbp_enabled_82543(hw) == FALSE) 478 goto out; 479 480 /* First adjust the frame length. */ 481 frame_len--; 482 /* We need to adjust the statistics counters, since the hardware 483 * counters overcount this packet as a CRC error and undercount 484 * the packet as a good packet 485 */ 486 /* This packet should not be counted as a CRC error. */ 487 stats->crcerrs--; 488 /* This packet does count as a Good Packet Received. */ 489 stats->gprc++; 490 491 /* Adjust the Good Octets received counters */ 492 carry_bit = 0x80000000 & stats->gorcl; 493 stats->gorcl += frame_len; 494 /* If the high bit of Gorcl (the low 32 bits of the Good Octets 495 * Received Count) was one before the addition, 496 * AND it is zero after, then we lost the carry out, 497 * need to add one to Gorch (Good Octets Received Count High). 498 * This could be simplified if all environments supported 499 * 64-bit integers. 500 */ 501 if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) 502 stats->gorch++; 503 /* Is this a broadcast or multicast? Check broadcast first, 504 * since the test for a multicast frame will test positive on 505 * a broadcast frame. 506 */ 507 if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff)) 508 /* Broadcast packet */ 509 stats->bprc++; 510 else if (*mac_addr & 0x01) 511 /* Multicast packet */ 512 stats->mprc++; 513 514 /* In this case, the hardware has overcounted the number of 515 * oversize frames. 516 */ 517 if ((frame_len == hw->mac.max_frame_size) && (stats->roc > 0)) 518 stats->roc--; 519 520 /* Adjust the bin counters when the extra byte put the frame in the 521 * wrong bin. Remember that the frame_len was adjusted above. 522 */ 523 if (frame_len == 64) { 524 stats->prc64++; 525 stats->prc127--; 526 } else if (frame_len == 127) { 527 stats->prc127++; 528 stats->prc255--; 529 } else if (frame_len == 255) { 530 stats->prc255++; 531 stats->prc511--; 532 } else if (frame_len == 511) { 533 stats->prc511++; 534 stats->prc1023--; 535 } else if (frame_len == 1023) { 536 stats->prc1023++; 537 stats->prc1522--; 538 } else if (frame_len == 1522) { 539 stats->prc1522++; 540 } 541 542out: 543 return; 544} 545 546/** 547 * e1000_read_phy_reg_82543 - Read PHY register 548 * @hw - pointer to the HW structure 549 * @offset - register offset to be read 550 * @data - pointer to the read data 551 * 552 * Reads the PHY at offset and stores the information read to data. 553 **/ 554STATIC s32 555e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data) 556{ 557 u32 mdic; 558 s32 ret_val = E1000_SUCCESS; 559 560 DEBUGFUNC("e1000_read_phy_reg_82543"); 561 562 if (offset > MAX_PHY_REG_ADDRESS) { 563 DEBUGOUT1("PHY Address %d is out of range\n", offset); 564 ret_val = -E1000_ERR_PARAM; 565 goto out; 566 } 567 568 /* We must first send a preamble through the MDIO pin to signal the 569 * beginning of an MII instruction. This is done by sending 32 570 * consecutive "1" bits. 571 */ 572 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 573 574 /* Now combine the next few fields that are required for a read 575 * operation. We use this method instead of calling the 576 * e1000_shift_out_mdi_bits routine five different times. The format 577 * of an MII read instruction consists of a shift out of 14 bits and 578 * is defined as follows: 579 * <Preamble><SOF><Op Code><Phy Addr><Offset> 580 * followed by a shift in of 18 bits. This first two bits shifted in 581 * are TurnAround bits used to avoid contention on the MDIO pin when a 582 * READ operation is performed. These two bits are thrown away 583 * followed by a shift in of 16 bits which contains the desired data. 584 */ 585 mdic = (offset | (hw->phy.addr << 5) | 586 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 587 588 e1000_shift_out_mdi_bits_82543(hw, mdic, 14); 589 590 /* Now that we've shifted out the read command to the MII, we need to 591 * "shift in" the 16-bit value (18 total bits) of the requested PHY 592 * register address. 593 */ 594 *data = e1000_shift_in_mdi_bits_82543(hw); 595 596out: 597 return ret_val; 598} 599 600/** 601 * e1000_write_phy_reg_82543 - Write PHY register 602 * @hw - pointer to the HW structure 603 * @offset - register offset to be written 604 * @data - pointer to the data to be written at offset 605 * 606 * Writes data to the PHY at offset. 607 **/ 608STATIC s32 609e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data) 610{ 611 u32 mdic; 612 s32 ret_val = E1000_SUCCESS; 613 614 DEBUGFUNC("e1000_write_phy_reg_82543"); 615 616 if (offset > MAX_PHY_REG_ADDRESS) { 617 DEBUGOUT1("PHY Address %d is out of range\n", offset); 618 ret_val = -E1000_ERR_PARAM; 619 goto out; 620 } 621 622 /* We'll need to use the SW defined pins to shift the write command 623 * out to the PHY. We first send a preamble to the PHY to signal the 624 * beginning of the MII instruction. This is done by sending 32 625 * consecutive "1" bits. 626 */ 627 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 628 629 /* Now combine the remaining required fields that will indicate a 630 * write operation. We use this method instead of calling the 631 * e1000_shift_out_mdi_bits routine for each field in the command. The 632 * format of a MII write instruction is as follows: 633 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 634 */ 635 mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) | 636 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 637 mdic <<= 16; 638 mdic |= (u32) data; 639 640 e1000_shift_out_mdi_bits_82543(hw, mdic, 32); 641 642out: 643 return ret_val; 644} 645 646/** 647 * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock 648 * @hw - pointer to the HW structure 649 * @ctrl - pointer to the control register 650 * 651 * Raise the management data input clock by setting the MDC bit in the control 652 * register. 653 **/ 654static void 655e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 656{ 657 /* Raise the clock input to the Management Data Clock (by setting the 658 * MDC bit), and then delay a sufficient amount of time. 659 */ 660 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC)); 661 E1000_WRITE_FLUSH(hw); 662 usec_delay(10); 663} 664 665/** 666 * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock 667 * @hw - pointer to the HW structure 668 * @ctrl - pointer to the control register 669 * 670 * Lower the management data input clock by clearing the MDC bit in the control 671 * register. 672 **/ 673static void 674e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 675{ 676 /* Lower the clock input to the Management Data Clock (by clearing the 677 * MDC bit), and then delay a sufficient amount of time. 678 */ 679 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC)); 680 E1000_WRITE_FLUSH(hw); 681 usec_delay(10); 682} 683 684/** 685 * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY 686 * @hw - pointer to the HW structure 687 * @data - data to send to the PHY 688 * @count - number of bits to shift out 689 * 690 * We need to shift 'count' bits out to the PHY. So, the value in the 691 * "data" parameter will be shifted out to the PHY one bit at a time. 692 * In order to do this, "data" must be broken down into bits. 693 **/ 694static void 695e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, u16 count) 696{ 697 u32 ctrl, mask; 698 699 /* We need to shift "count" number of bits out to the PHY. So, the 700 * value in the "data" parameter will be shifted out to the PHY one 701 * bit at a time. In order to do this, "data" must be broken down 702 * into bits. 703 */ 704 mask = 0x01; 705 mask <<= (count -1); 706 707 ctrl = E1000_READ_REG(hw, E1000_CTRL); 708 709 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 710 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 711 712 while (mask) { 713 /* A "1" is shifted out to the PHY by setting the MDIO bit to 714 * "1" and then raising and lowering the Management Data Clock. 715 * A "0" is shifted out to the PHY by setting the MDIO bit to 716 * "0" and then raising and lowering the clock. 717 */ 718 if (data & mask) ctrl |= E1000_CTRL_MDIO; 719 else ctrl &= ~E1000_CTRL_MDIO; 720 721 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 722 E1000_WRITE_FLUSH(hw); 723 724 usec_delay(10); 725 726 e1000_raise_mdi_clk_82543(hw, &ctrl); 727 e1000_lower_mdi_clk_82543(hw, &ctrl); 728 729 mask >>= 1; 730 } 731} 732 733/** 734 * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY 735 * @hw - pointer to the HW structure 736 * 737 * In order to read a register from the PHY, we need to shift 18 bits 738 * in from the PHY. Bits are "shifted in" by raising the clock input to 739 * the PHY (setting the MDC bit), and then reading the value of the data out 740 * MDIO bit. 741 **/ 742static u16 743e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw) 744{ 745 u32 ctrl; 746 u16 data = 0; 747 u8 i; 748 749 /* In order to read a register from the PHY, we need to shift in a 750 * total of 18 bits from the PHY. The first two bit (turnaround) 751 * times are used to avoid contention on the MDIO pin when a read 752 * operation is performed. These two bits are ignored by us and 753 * thrown away. Bits are "shifted in" by raising the input to the 754 * Management Data Clock (setting the MDC bit) and then reading the 755 * value of the MDIO bit. 756 */ 757 ctrl = E1000_READ_REG(hw, E1000_CTRL); 758 759 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 760 * input. 761 */ 762 ctrl &= ~E1000_CTRL_MDIO_DIR; 763 ctrl &= ~E1000_CTRL_MDIO; 764 765 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 766 E1000_WRITE_FLUSH(hw); 767 768 /* Raise and lower the clock before reading in the data. This accounts 769 * for the turnaround bits. The first clock occurred when we clocked 770 * out the last bit of the Register Address. 771 */ 772 e1000_raise_mdi_clk_82543(hw, &ctrl); 773 e1000_lower_mdi_clk_82543(hw, &ctrl); 774 775 for (data = 0, i = 0; i < 16; i++) { 776 data <<= 1; 777 e1000_raise_mdi_clk_82543(hw, &ctrl); 778 ctrl = E1000_READ_REG(hw, E1000_CTRL); 779 /* Check to see if we shifted in a "1". */ 780 if (ctrl & E1000_CTRL_MDIO) 781 data |= 1; 782 e1000_lower_mdi_clk_82543(hw, &ctrl); 783 } 784 785 e1000_raise_mdi_clk_82543(hw, &ctrl); 786 e1000_lower_mdi_clk_82543(hw, &ctrl); 787 788 return data; 789} 790 791/** 792 * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY 793 * @hw - pointer to the HW structure 794 * 795 * Calls the function to force speed and duplex for the m88 PHY, and 796 * if the PHY is not auto-negotiating and the speed is forced to 10Mbit, 797 * then call the function for polarity reversal workaround. 798 **/ 799STATIC s32 800e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw) 801{ 802 s32 ret_val; 803 804 DEBUGFUNC("e1000_phy_force_speed_duplex_82543"); 805 806 ret_val = e1000_phy_force_speed_duplex_m88(hw); 807 if (ret_val) 808 goto out; 809 810 if (!hw->mac.autoneg && 811 (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)) 812 ret_val = e1000_polarity_reversal_workaround_82543(hw); 813 814out: 815 return ret_val; 816} 817 818/** 819 * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal 820 * @hw - pointer to the HW structure 821 * 822 * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity 823 * inadvertantly. To workaround the issue, we disable the transmitter on 824 * the PHY until we have established the link partner's link parameters. 825 **/ 826static s32 827e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw) 828{ 829 s32 ret_val; 830 u16 mii_status_reg; 831 u16 i; 832 boolean_t link; 833 834 /* Polarity reversal workaround for forced 10F/10H links. */ 835 836 /* Disable the transmitter on the PHY */ 837 838 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 839 if (ret_val) 840 goto out; 841 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 842 if (ret_val) 843 goto out; 844 845 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 846 if (ret_val) 847 goto out; 848 849 /* This loop will early-out if the NO link condition has been met. 850 * In other words, DO NOT use e1000_phy_has_link_generic() here. 851 */ 852 for (i = PHY_FORCE_TIME; i > 0; i--) { 853 /* Read the MII Status Register and wait for Link Status bit 854 * to be clear. 855 */ 856 857 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 858 if (ret_val) 859 goto out; 860 861 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 862 if (ret_val) 863 goto out; 864 865 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 866 break; 867 msec_delay_irq(100); 868 } 869 870 /* Recommended delay time after link has been lost */ 871 msec_delay_irq(1000); 872 873 /* Now we will re-enable the transmitter on the PHY */ 874 875 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 876 if (ret_val) 877 goto out; 878 msec_delay_irq(50); 879 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 880 if (ret_val) 881 goto out; 882 msec_delay_irq(50); 883 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 884 if (ret_val) 885 goto out; 886 msec_delay_irq(50); 887 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 888 if (ret_val) 889 goto out; 890 891 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 892 if (ret_val) 893 goto out; 894 895 /* Read the MII Status Register and wait for Link Status bit 896 * to be set. 897 */ 898 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link); 899 if (ret_val) 900 goto out; 901 902out: 903 return ret_val; 904} 905 906/** 907 * e1000_phy_hw_reset_82543 - PHY hardware reset 908 * @hw - pointer to the HW structure 909 * 910 * Sets the PHY_RESET_DIR bit in the extended device control register 911 * to put the PHY into a reset and waits for completion. Once the reset 912 * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out 913 * of reset. This is a function pointer entry point called by the api module. 914 **/ 915STATIC s32 916e1000_phy_hw_reset_82543(struct e1000_hw *hw) 917{ 918 struct e1000_functions *func = &hw->func; 919 u32 ctrl_ext; 920 s32 ret_val; 921 922 DEBUGFUNC("e1000_phy_hw_reset_82543"); 923 924 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 925 * bit to put the PHY into reset... 926 */ 927 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 928 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 929 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 930 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 931 E1000_WRITE_FLUSH(hw); 932 933 msec_delay(10); 934 935 /* ...then take it out of reset. */ 936 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 937 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 938 E1000_WRITE_FLUSH(hw); 939 940 usec_delay(150); 941 942 ret_val = func->get_cfg_done(hw); 943 944 return ret_val; 945} 946 947/** 948 * e1000_reset_hw_82543 - Reset hardware 949 * @hw - pointer to the HW structure 950 * 951 * This resets the hardware into a known state. This is a 952 * function pointer entry point called by the api module. 953 **/ 954STATIC s32 955e1000_reset_hw_82543(struct e1000_hw *hw) 956{ 957 u32 ctrl, icr; 958 s32 ret_val = E1000_SUCCESS; 959 960 DEBUGFUNC("e1000_reset_hw_82543"); 961 962 DEBUGOUT("Masking off all interrupts\n"); 963 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 964 965 E1000_WRITE_REG(hw, E1000_RCTL, 0); 966 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 967 E1000_WRITE_FLUSH(hw); 968 969 e1000_set_tbi_sbp_82543(hw, FALSE); 970 971 /* Delay to allow any outstanding PCI transactions to complete before 972 * resetting the device 973 */ 974 msec_delay(10); 975 976 ctrl = E1000_READ_REG(hw, E1000_CTRL); 977 978 DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n"); 979 if (hw->mac.type == e1000_82543) { 980 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 981 } else { 982 /* The 82544 can't ACK the 64-bit write when issuing the 983 * reset, so use IO-mapping as a workaround. 984 */ 985 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 986 } 987 988 /* After MAC reset, force reload of NVM to restore power-on 989 * settings to device. 990 */ 991 e1000_reload_nvm(hw); 992 msec_delay(2); 993 994 /* Masking off and clearing any pending interrupts */ 995 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 996 icr = E1000_READ_REG(hw, E1000_ICR); 997 998 return ret_val; 999} 1000 1001/** 1002 * e1000_init_hw_82543 - Initialize hardware 1003 * @hw - pointer to the HW structure 1004 * 1005 * This inits the hardware readying it for operation. 1006 **/ 1007STATIC s32 1008e1000_init_hw_82543(struct e1000_hw *hw) 1009{ 1010 struct e1000_mac_info *mac = &hw->mac; 1011 struct e1000_dev_spec_82543 *dev_spec; 1012 u32 ctrl; 1013 s32 ret_val; 1014 u16 i; 1015 1016 DEBUGFUNC("e1000_init_hw_82543"); 1017 1018 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 1019 1020 if (dev_spec == NULL) { 1021 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 1022 ret_val = -E1000_ERR_CONFIG; 1023 goto out; 1024 } 1025 1026 /* Disabling VLAN filtering */ 1027 E1000_WRITE_REG(hw, E1000_VET, 0); 1028 e1000_clear_vfta(hw); 1029 1030 /* Setup the receive address. */ 1031 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 1032 1033 /* Zero out the Multicast HASH table */ 1034 DEBUGOUT("Zeroing the MTA\n"); 1035 for (i = 0; i < mac->mta_reg_count; i++) { 1036 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1037 E1000_WRITE_FLUSH(hw); 1038 } 1039 1040 /* Set the PCI priority bit correctly in the CTRL register. This 1041 * determines if the adapter gives priority to receives, or if it 1042 * gives equal priority to transmits and receives. 1043 */ 1044 if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) { 1045 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1046 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); 1047 } 1048 1049 e1000_pcix_mmrbc_workaround_generic(hw); 1050 1051 /* Setup link and flow control */ 1052 ret_val = e1000_setup_link(hw); 1053 1054 /* Clear all of the statistics registers (clear on read). It is 1055 * important that we do this after we have tried to establish link 1056 * because the symbol error count will increment wildly if there 1057 * is no link. 1058 */ 1059 e1000_clear_hw_cntrs_82543(hw); 1060 1061out: 1062 return ret_val; 1063} 1064 1065/** 1066 * e1000_setup_link_82543 - Setup flow control and link settings 1067 * @hw - pointer to the HW structure 1068 * 1069 * Read the EEPROM to determine the initial polarity value and write the 1070 * extended device control register with the information before calling 1071 * the generic setup link function, which does the following: 1072 * Determines which flow control settings to use, then configures flow 1073 * control. Calls the appropriate media-specific link configuration 1074 * function. Assuming the adapter has a valid link partner, a valid link 1075 * should be established. Assumes the hardware has previously been reset 1076 * and the transmitter and receiver are not enabled. 1077 **/ 1078STATIC s32 1079e1000_setup_link_82543(struct e1000_hw *hw) 1080{ 1081 u32 ctrl_ext; 1082 s32 ret_val; 1083 u16 data; 1084 1085 DEBUGFUNC("e1000_setup_link_82543"); 1086 1087 /* Take the 4 bits from NVM word 0xF that determine the initial 1088 * polarity value for the SW controlled pins, and setup the 1089 * Extended Device Control reg with that info. 1090 * This is needed because one of the SW controlled pins is used for 1091 * signal detection. So this should be done before phy setup. 1092 */ 1093 if (hw->mac.type == e1000_82543) { 1094 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1095 if (ret_val) { 1096 DEBUGOUT("NVM Read Error\n"); 1097 ret_val = -E1000_ERR_NVM; 1098 goto out; 1099 } 1100 ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) << 1101 NVM_SWDPIO_EXT_SHIFT); 1102 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1103 } 1104 1105 ret_val = e1000_setup_link_generic(hw); 1106 1107out: 1108 return ret_val; 1109} 1110 1111/** 1112 * e1000_setup_copper_link_82543 - Configure copper link settings 1113 * @hw - pointer to the HW structure 1114 * 1115 * Configures the link for auto-neg or forced speed and duplex. Then we check 1116 * for link, once link is established calls to configure collision distance 1117 * and flow control are called. 1118 **/ 1119STATIC s32 1120e1000_setup_copper_link_82543(struct e1000_hw *hw) 1121{ 1122 u32 ctrl; 1123 s32 ret_val; 1124 boolean_t link; 1125 1126 DEBUGFUNC("e1000_setup_copper_link_82543"); 1127 1128 ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU; 1129 /* With 82543, we need to force speed and duplex on the MAC 1130 * equal to what the PHY speed and duplex configuration is. 1131 * In addition, we need to perform a hardware reset on the 1132 * PHY to take it out of reset. 1133 */ 1134 if (hw->mac.type == e1000_82543) { 1135 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1136 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1137 ret_val = e1000_phy_hw_reset(hw); 1138 if (ret_val) 1139 goto out; 1140 hw->phy.reset_disable = FALSE; 1141 } else { 1142 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1143 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1144 } 1145 1146 /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */ 1147 ret_val = e1000_copper_link_setup_m88(hw); 1148 if (ret_val) 1149 goto out; 1150 1151 if (hw->mac.autoneg) { 1152 /* Setup autoneg and flow control advertisement and perform 1153 * autonegotiation. */ 1154 ret_val = e1000_copper_link_autoneg(hw); 1155 if (ret_val) 1156 goto out; 1157 } else { 1158 /* PHY will be set to 10H, 10F, 100H or 100F 1159 * depending on user settings. */ 1160 DEBUGOUT("Forcing Speed and Duplex\n"); 1161 ret_val = e1000_phy_force_speed_duplex_82543(hw); 1162 if (ret_val) { 1163 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1164 goto out; 1165 } 1166 } 1167 1168 /* Check link status. Wait up to 100 microseconds for link to become 1169 * valid. 1170 */ 1171 ret_val = e1000_phy_has_link_generic(hw, 1172 COPPER_LINK_UP_LIMIT, 1173 10, 1174 &link); 1175 if (ret_val) 1176 goto out; 1177 1178 1179 if (link) { 1180 DEBUGOUT("Valid link established!!!\n"); 1181 /* Config the MAC and PHY after link is up */ 1182 if (hw->mac.type == e1000_82544) 1183 e1000_config_collision_dist_generic(hw); 1184 else { 1185 ret_val = e1000_config_mac_to_phy_82543(hw); 1186 if (ret_val) 1187 goto out; 1188 } 1189 ret_val = e1000_config_fc_after_link_up_generic(hw); 1190 } else { 1191 DEBUGOUT("Unable to establish link!!!\n"); 1192 } 1193 1194out: 1195 return ret_val; 1196} 1197 1198/** 1199 * e1000_setup_fiber_link_82543 - Setup link for fiber 1200 * @hw - pointer to the HW structure 1201 * 1202 * Configures collision distance and flow control for fiber links. Upon 1203 * successful setup, poll for link. 1204 **/ 1205STATIC s32 1206e1000_setup_fiber_link_82543(struct e1000_hw *hw) 1207{ 1208 u32 ctrl; 1209 s32 ret_val; 1210 1211 DEBUGFUNC("e1000_setup_fiber_link_82543"); 1212 1213 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1214 1215 /* Take the link out of reset */ 1216 ctrl &= ~E1000_CTRL_LRST; 1217 1218 e1000_config_collision_dist_generic(hw); 1219 1220 ret_val = e1000_commit_fc_settings_generic(hw); 1221 if (ret_val) 1222 goto out; 1223 1224 DEBUGOUT("Auto-negotiation enabled\n"); 1225 1226 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1227 E1000_WRITE_FLUSH(hw); 1228 msec_delay(1); 1229 1230 /* For these adapters, the SW defineable pin 1 is cleared when the 1231 * optics detect a signal. If we have a signal, then poll for a 1232 * "Link-Up" indication. 1233 */ 1234 if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1235 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1236 } else { 1237 DEBUGOUT("No signal detected\n"); 1238 } 1239 1240out: 1241 return ret_val; 1242} 1243 1244/** 1245 * e1000_check_for_copper_link_82543 - Check for link (Copper) 1246 * @hw - pointer to the HW structure 1247 * 1248 * Checks the phy for link, if link exists, do the following: 1249 * - check for downshift 1250 * - do polarity workaround (if necessary) 1251 * - configure collision distance 1252 * - configure flow control after link up 1253 * - configure tbi compatibility 1254 **/ 1255STATIC s32 1256e1000_check_for_copper_link_82543(struct e1000_hw *hw) 1257{ 1258 struct e1000_mac_info *mac = &hw->mac; 1259 u32 icr, rctl; 1260 s32 ret_val; 1261 u16 speed, duplex; 1262 boolean_t link; 1263 1264 DEBUGFUNC("e1000_check_for_copper_link_82543"); 1265 1266 if (!mac->get_link_status) { 1267 ret_val = E1000_SUCCESS; 1268 goto out; 1269 } 1270 1271 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1272 if (ret_val) 1273 goto out; 1274 1275 if (!link) 1276 goto out; /* No link detected */ 1277 1278 mac->get_link_status = FALSE; 1279 1280 e1000_check_downshift_generic(hw); 1281 1282 /* If we are forcing speed/duplex, then we can return since 1283 * we have already determined whether we have link or not. 1284 */ 1285 if (!mac->autoneg) { 1286 /* If speed and duplex are forced to 10H or 10F, then we will 1287 * implement the polarity reversal workaround. We disable 1288 * interrupts first, and upon returning, place the devices 1289 * interrupt state to its previous value except for the link 1290 * status change interrupt which will happened due to the 1291 * execution of this workaround. 1292 */ 1293 if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) { 1294 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 1295 ret_val = e1000_polarity_reversal_workaround_82543(hw); 1296 icr = E1000_READ_REG(hw, E1000_ICR); 1297 E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC)); 1298 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 1299 } 1300 1301 ret_val = -E1000_ERR_CONFIG; 1302 goto out; 1303 } 1304 1305 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 1306 * have Si on board that is 82544 or newer, Auto 1307 * Speed Detection takes care of MAC speed/duplex 1308 * configuration. So we only need to configure Collision 1309 * Distance in the MAC. Otherwise, we need to force 1310 * speed/duplex on the MAC to the current PHY speed/duplex 1311 * settings. 1312 */ 1313 if (mac->type == e1000_82544) 1314 e1000_config_collision_dist_generic(hw); 1315 else { 1316 ret_val = e1000_config_mac_to_phy_82543(hw); 1317 if (ret_val) { 1318 DEBUGOUT("Error configuring MAC to PHY settings\n"); 1319 goto out; 1320 } 1321 } 1322 1323 /* Configure Flow Control now that Auto-Neg has completed. 1324 * First, we need to restore the desired flow control 1325 * settings because we may have had to re-autoneg with a 1326 * different link partner. 1327 */ 1328 ret_val = e1000_config_fc_after_link_up_generic(hw); 1329 if (ret_val) { 1330 DEBUGOUT("Error configuring flow control\n"); 1331 } 1332 1333 /* At this point we know that we are on copper and we have 1334 * auto-negotiated link. These are conditions for checking the link 1335 * partner capability register. We use the link speed to determine if 1336 * TBI compatibility needs to be turned on or off. If the link is not 1337 * at gigabit speed, then TBI compatibility is not needed. If we are 1338 * at gigabit speed, we turn on TBI compatibility. 1339 */ 1340 if (e1000_tbi_compatibility_enabled_82543(hw)) { 1341 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 1342 if (ret_val) { 1343 DEBUGOUT("Error getting link speed and duplex\n"); 1344 return ret_val; 1345 } 1346 if (speed != SPEED_1000) { 1347 /* If link speed is not set to gigabit speed, 1348 * we do not need to enable TBI compatibility. 1349 */ 1350 if (e1000_tbi_sbp_enabled_82543(hw)) { 1351 /* If we previously were in the mode, 1352 * turn it off. 1353 */ 1354 e1000_set_tbi_sbp_82543(hw, FALSE); 1355 rctl = E1000_READ_REG(hw, E1000_RCTL); 1356 rctl &= ~E1000_RCTL_SBP; 1357 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1358 } 1359 } else { 1360 /* If TBI compatibility is was previously off, 1361 * turn it on. For compatibility with a TBI link 1362 * partner, we will store bad packets. Some 1363 * frames have an additional byte on the end and 1364 * will look like CRC errors to to the hardware. 1365 */ 1366 if (!e1000_tbi_sbp_enabled_82543(hw)) { 1367 e1000_set_tbi_sbp_82543(hw, TRUE); 1368 rctl = E1000_READ_REG(hw, E1000_RCTL); 1369 rctl |= E1000_RCTL_SBP; 1370 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1371 } 1372 } 1373 } 1374out: 1375 return ret_val; 1376} 1377 1378/** 1379 * e1000_check_for_fiber_link_82543 - Check for link (Fiber) 1380 * @hw - pointer to the HW structure 1381 * 1382 * Checks for link up on the hardware. If link is not up and we have 1383 * a signal, then we need to force link up. 1384 **/ 1385STATIC s32 1386e1000_check_for_fiber_link_82543(struct e1000_hw *hw) 1387{ 1388 struct e1000_mac_info *mac = &hw->mac; 1389 u32 rxcw, ctrl, status; 1390 s32 ret_val = E1000_SUCCESS; 1391 1392 DEBUGFUNC("e1000_check_for_fiber_link_82543"); 1393 1394 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1395 status = E1000_READ_REG(hw, E1000_CTRL); 1396 rxcw = E1000_READ_REG(hw, E1000_CTRL); 1397 1398 /* If we don't have link (auto-negotiation failed or link partner 1399 * cannot auto-negotiate), the cable is plugged in (we have signal), 1400 * and our link partner is not trying to auto-negotiate with us (we 1401 * are receiving idles or data), we need to force link up. We also 1402 * need to give auto-negotiation time to complete, in case the cable 1403 * was just plugged in. The autoneg_failed flag does this. 1404 */ 1405 /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */ 1406 if ((!(ctrl & E1000_CTRL_SWDPIN1)) && 1407 (!(status & E1000_STATUS_LU)) && 1408 (!(rxcw & E1000_RXCW_C))) { 1409 if (mac->autoneg_failed == 0) { 1410 mac->autoneg_failed = 1; 1411 ret_val = 0; 1412 goto out; 1413 } 1414 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 1415 1416 /* Disable auto-negotiation in the TXCW register */ 1417 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 1418 1419 /* Force link-up and also force full-duplex. */ 1420 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1421 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1422 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1423 1424 /* Configure Flow Control after forcing link up. */ 1425 ret_val = e1000_config_fc_after_link_up_generic(hw); 1426 if (ret_val) { 1427 DEBUGOUT("Error configuring flow control\n"); 1428 goto out; 1429 } 1430 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 1431 /* If we are forcing link and we are receiving /C/ ordered 1432 * sets, re-enable auto-negotiation in the TXCW register 1433 * and disable forced link in the Device Control register 1434 * in an attempt to auto-negotiate with our link partner. 1435 */ 1436 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 1437 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1438 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 1439 1440 mac->serdes_has_link = TRUE; 1441 } 1442 1443out: 1444 return ret_val; 1445} 1446 1447/** 1448 * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings 1449 * @hw - pointer to the HW structure 1450 * 1451 * For the 82543 silicon, we need to set the MAC to match the settings 1452 * of the PHY, even if the PHY is auto-negotiating. 1453 **/ 1454static s32 1455e1000_config_mac_to_phy_82543(struct e1000_hw *hw) 1456{ 1457 u32 ctrl; 1458 s32 ret_val; 1459 u16 phy_data; 1460 1461 DEBUGFUNC("e1000_config_mac_to_phy_82543"); 1462 1463 /* Set the bits to force speed and duplex */ 1464 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1465 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1466 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1467 1468 /* Set up duplex in the Device Control and Transmit Control 1469 * registers depending on negotiated values. 1470 */ 1471 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1472 if (ret_val) 1473 goto out; 1474 1475 ctrl &= ~E1000_CTRL_FD; 1476 if (phy_data & M88E1000_PSSR_DPLX) 1477 ctrl |= E1000_CTRL_FD; 1478 1479 e1000_config_collision_dist_generic(hw); 1480 1481 /* Set up speed in the Device Control register depending on 1482 * negotiated values. 1483 */ 1484 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1485 ctrl |= E1000_CTRL_SPD_1000; 1486 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 1487 ctrl |= E1000_CTRL_SPD_100; 1488 1489 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1490 1491out: 1492 return ret_val; 1493} 1494 1495/** 1496 * e1000_write_vfta_82543 - Write value to VLAN filter table 1497 * @hw - pointer to the HW structure 1498 * @offset - the 32-bit offset in which to write the value to. 1499 * @value - the 32-bit value to write at location offset. 1500 * 1501 * This writes a 32-bit value to a 32-bit offset in the VLAN filter 1502 * table. 1503 **/ 1504STATIC void 1505e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value) 1506{ 1507 u32 temp; 1508 1509 DEBUGFUNC("e1000_write_vfta_82543"); 1510 1511 if ((hw->mac.type == e1000_82544) && (offset & 1)) { 1512 temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1); 1513 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 1514 E1000_WRITE_FLUSH(hw); 1515 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp); 1516 E1000_WRITE_FLUSH(hw); 1517 } else 1518 e1000_write_vfta_generic(hw, offset, value); 1519} 1520 1521/** 1522 * e1000_mta_set_82543 - Set multicast filter table address 1523 * @hw - pointer to the HW structure 1524 * @hash_value - determines the MTA register and bit to set 1525 * 1526 * The multicast table address is a register array of 32-bit registers. 1527 * The hash_value is used to determine what register the bit is in, the 1528 * current value is read, the new bit is OR'd in and the new value is 1529 * written back into the register. 1530 **/ 1531STATIC void 1532e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value) 1533{ 1534 u32 hash_bit, hash_reg, mta, temp; 1535 1536 DEBUGFUNC("e1000_mta_set_82543"); 1537 1538 hash_reg = (hash_value >> 5); 1539 1540 /* If we are on an 82544 and we are trying to write an odd offset 1541 * in the MTA, save off the previous entry before writing and 1542 * restore the old value after writing. 1543 */ 1544 if ((hw->mac.type == e1000_82544) && (hash_reg & 1)) { 1545 hash_reg &= (hw->mac.mta_reg_count - 1); 1546 hash_bit = hash_value & 0x1F; 1547 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 1548 mta |= (1 << hash_bit); 1549 temp = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg - 1); 1550 1551 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 1552 E1000_WRITE_FLUSH(hw); 1553 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg - 1, temp); 1554 E1000_WRITE_FLUSH(hw); 1555 } else 1556 e1000_mta_set_generic(hw, hash_value); 1557} 1558 1559/** 1560 * e1000_led_on_82543 - Turn on SW controllable LED 1561 * @hw - pointer to the HW structure 1562 * 1563 * Turns the SW defined LED on. This is a function pointer entry point 1564 * called by the api module. 1565 **/ 1566STATIC s32 1567e1000_led_on_82543(struct e1000_hw *hw) 1568{ 1569 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1570 1571 DEBUGFUNC("e1000_led_on_82543"); 1572 1573 if (hw->mac.type == e1000_82544 && 1574 hw->media_type == e1000_media_type_copper) { 1575 /* Clear SW-defineable Pin 0 to turn on the LED */ 1576 ctrl &= ~E1000_CTRL_SWDPIN0; 1577 ctrl |= E1000_CTRL_SWDPIO0; 1578 } else { 1579 /* Fiber 82544 and all 82543 use this method */ 1580 ctrl |= E1000_CTRL_SWDPIN0; 1581 ctrl |= E1000_CTRL_SWDPIO0; 1582 } 1583 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1584 1585 return E1000_SUCCESS; 1586} 1587 1588/** 1589 * e1000_led_off_82543 - Turn off SW controllable LED 1590 * @hw - pointer to the HW structure 1591 * 1592 * Turns the SW defined LED off. This is a function pointer entry point 1593 * called by the api module. 1594 **/ 1595STATIC s32 1596e1000_led_off_82543(struct e1000_hw *hw) 1597{ 1598 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1599 1600 DEBUGFUNC("e1000_led_off_82543"); 1601 1602 if (hw->mac.type == e1000_82544 && 1603 hw->media_type == e1000_media_type_copper) { 1604 /* Set SW-defineable Pin 0 to turn off the LED */ 1605 ctrl |= E1000_CTRL_SWDPIN0; 1606 ctrl |= E1000_CTRL_SWDPIO0; 1607 } else { 1608 ctrl &= ~E1000_CTRL_SWDPIN0; 1609 ctrl |= E1000_CTRL_SWDPIO0; 1610 } 1611 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1612 1613 return E1000_SUCCESS; 1614} 1615 1616/** 1617 * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters 1618 * @hw - pointer to the HW structure 1619 * 1620 * Clears the hardware counters by reading the counter registers. 1621 **/ 1622STATIC void 1623e1000_clear_hw_cntrs_82543(struct e1000_hw *hw) 1624{ 1625 volatile u32 temp; 1626 1627 DEBUGFUNC("e1000_clear_hw_cntrs_82543"); 1628 1629 e1000_clear_hw_cntrs_base_generic(hw); 1630 1631 temp = E1000_READ_REG(hw, E1000_PRC64); 1632 temp = E1000_READ_REG(hw, E1000_PRC127); 1633 temp = E1000_READ_REG(hw, E1000_PRC255); 1634 temp = E1000_READ_REG(hw, E1000_PRC511); 1635 temp = E1000_READ_REG(hw, E1000_PRC1023); 1636 temp = E1000_READ_REG(hw, E1000_PRC1522); 1637 temp = E1000_READ_REG(hw, E1000_PTC64); 1638 temp = E1000_READ_REG(hw, E1000_PTC127); 1639 temp = E1000_READ_REG(hw, E1000_PTC255); 1640 temp = E1000_READ_REG(hw, E1000_PTC511); 1641 temp = E1000_READ_REG(hw, E1000_PTC1023); 1642 temp = E1000_READ_REG(hw, E1000_PTC1522); 1643 1644 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1645 temp = E1000_READ_REG(hw, E1000_RXERRC); 1646 temp = E1000_READ_REG(hw, E1000_TNCRS); 1647 temp = E1000_READ_REG(hw, E1000_CEXTERR); 1648 temp = E1000_READ_REG(hw, E1000_TSCTC); 1649 temp = E1000_READ_REG(hw, E1000_TSCTFC); 1650} 1651