1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Christian König. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Christian König 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include <dev/drm2/drmP.h> 31#include <dev/drm2/radeon/radeon_drm.h> 32#include "radeon.h" 33#include "radeon_asic.h" 34#include "r600d.h" 35#include "atom.h" 36 37/* 38 * HDMI color format 39 */ 40enum r600_hdmi_color_format { 41 RGB = 0, 42 YCC_422 = 1, 43 YCC_444 = 2 44}; 45 46/* 47 * IEC60958 status bits 48 */ 49enum r600_hdmi_iec_status_bits { 50 AUDIO_STATUS_DIG_ENABLE = 0x01, 51 AUDIO_STATUS_V = 0x02, 52 AUDIO_STATUS_VCFG = 0x04, 53 AUDIO_STATUS_EMPHASIS = 0x08, 54 AUDIO_STATUS_COPYRIGHT = 0x10, 55 AUDIO_STATUS_NONAUDIO = 0x20, 56 AUDIO_STATUS_PROFESSIONAL = 0x40, 57 AUDIO_STATUS_LEVEL = 0x80 58}; 59 60static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = { 61 /* 32kHz 44.1kHz 48kHz */ 62 /* Clock N CTS N CTS N CTS */ 63 { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */ 64 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ 65 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ 66 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ 67 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ 68 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ 69 { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */ 70 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ 71 { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */ 72 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ 73 { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */ 74}; 75 76/* 77 * calculate CTS value if it's not found in the table 78 */ 79static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq) 80{ 81 if (*CTS == 0) 82 *CTS = clock * N / (128 * freq) * 1000; 83 DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n", 84 N, *CTS, freq); 85} 86 87struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock) 88{ 89 struct radeon_hdmi_acr res; 90 u8 i; 91 92 for (i = 0; r600_hdmi_predefined_acr[i].clock != clock && 93 r600_hdmi_predefined_acr[i].clock != 0; i++) 94 ; 95 res = r600_hdmi_predefined_acr[i]; 96 97 /* In case some CTS are missing */ 98 r600_hdmi_calc_cts(clock, &res.cts_32khz, res.n_32khz, 32000); 99 r600_hdmi_calc_cts(clock, &res.cts_44_1khz, res.n_44_1khz, 44100); 100 r600_hdmi_calc_cts(clock, &res.cts_48khz, res.n_48khz, 48000); 101 102 return res; 103} 104 105/* 106 * update the N and CTS parameters for a given pixel clock rate 107 */ 108static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) 109{ 110 struct drm_device *dev = encoder->dev; 111 struct radeon_device *rdev = dev->dev_private; 112 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); 113 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 114 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 115 uint32_t offset = dig->afmt->offset; 116 117 WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz)); 118 WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz); 119 120 WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz)); 121 WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz); 122 123 WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz)); 124 WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz); 125} 126 127/* 128 * calculate the crc for a given info frame 129 */ 130static void r600_hdmi_infoframe_checksum(uint8_t packetType, 131 uint8_t versionNumber, 132 uint8_t length, 133 uint8_t *frame) 134{ 135 int i; 136 frame[0] = packetType + versionNumber + length; 137 for (i = 1; i <= length; i++) 138 frame[0] += frame[i]; 139 frame[0] = 0x100 - frame[0]; 140} 141 142/* 143 * build a HDMI Video Info Frame 144 */ 145static void r600_hdmi_videoinfoframe( 146 struct drm_encoder *encoder, 147 enum r600_hdmi_color_format color_format, 148 int active_information_present, 149 uint8_t active_format_aspect_ratio, 150 uint8_t scan_information, 151 uint8_t colorimetry, 152 uint8_t ex_colorimetry, 153 uint8_t quantization, 154 int ITC, 155 uint8_t picture_aspect_ratio, 156 uint8_t video_format_identification, 157 uint8_t pixel_repetition, 158 uint8_t non_uniform_picture_scaling, 159 uint8_t bar_info_data_valid, 160 uint16_t top_bar, 161 uint16_t bottom_bar, 162 uint16_t left_bar, 163 uint16_t right_bar 164) 165{ 166 struct drm_device *dev = encoder->dev; 167 struct radeon_device *rdev = dev->dev_private; 168 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 169 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 170 uint32_t offset = dig->afmt->offset; 171 172 uint8_t frame[14]; 173 174 frame[0x0] = 0; 175 frame[0x1] = 176 (scan_information & 0x3) | 177 ((bar_info_data_valid & 0x3) << 2) | 178 ((active_information_present & 0x1) << 4) | 179 ((color_format & 0x3) << 5); 180 frame[0x2] = 181 (active_format_aspect_ratio & 0xF) | 182 ((picture_aspect_ratio & 0x3) << 4) | 183 ((colorimetry & 0x3) << 6); 184 frame[0x3] = 185 (non_uniform_picture_scaling & 0x3) | 186 ((quantization & 0x3) << 2) | 187 ((ex_colorimetry & 0x7) << 4) | 188 ((ITC & 0x1) << 7); 189 frame[0x4] = (video_format_identification & 0x7F); 190 frame[0x5] = (pixel_repetition & 0xF); 191 frame[0x6] = (top_bar & 0xFF); 192 frame[0x7] = (top_bar >> 8); 193 frame[0x8] = (bottom_bar & 0xFF); 194 frame[0x9] = (bottom_bar >> 8); 195 frame[0xA] = (left_bar & 0xFF); 196 frame[0xB] = (left_bar >> 8); 197 frame[0xC] = (right_bar & 0xFF); 198 frame[0xD] = (right_bar >> 8); 199 200 r600_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame); 201 /* Our header values (type, version, length) should be alright, Intel 202 * is using the same. Checksum function also seems to be OK, it works 203 * fine for audio infoframe. However calculated value is always lower 204 * by 2 in comparison to fglrx. It breaks displaying anything in case 205 * of TVs that strictly check the checksum. Hack it manually here to 206 * workaround this issue. */ 207 frame[0x0] += 2; 208 209 WREG32(HDMI0_AVI_INFO0 + offset, 210 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 211 WREG32(HDMI0_AVI_INFO1 + offset, 212 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 213 WREG32(HDMI0_AVI_INFO2 + offset, 214 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 215 WREG32(HDMI0_AVI_INFO3 + offset, 216 frame[0xC] | (frame[0xD] << 8)); 217} 218 219/* 220 * build a Audio Info Frame 221 */ 222static void r600_hdmi_audioinfoframe( 223 struct drm_encoder *encoder, 224 uint8_t channel_count, 225 uint8_t coding_type, 226 uint8_t sample_size, 227 uint8_t sample_frequency, 228 uint8_t format, 229 uint8_t channel_allocation, 230 uint8_t level_shift, 231 int downmix_inhibit 232) 233{ 234 struct drm_device *dev = encoder->dev; 235 struct radeon_device *rdev = dev->dev_private; 236 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 237 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 238 uint32_t offset = dig->afmt->offset; 239 240 uint8_t frame[11]; 241 242 frame[0x0] = 0; 243 frame[0x1] = (channel_count & 0x7) | ((coding_type & 0xF) << 4); 244 frame[0x2] = (sample_size & 0x3) | ((sample_frequency & 0x7) << 2); 245 frame[0x3] = format; 246 frame[0x4] = channel_allocation; 247 frame[0x5] = ((level_shift & 0xF) << 3) | ((downmix_inhibit & 0x1) << 7); 248 frame[0x6] = 0; 249 frame[0x7] = 0; 250 frame[0x8] = 0; 251 frame[0x9] = 0; 252 frame[0xA] = 0; 253 254 r600_hdmi_infoframe_checksum(0x84, 0x01, 0x0A, frame); 255 256 WREG32(HDMI0_AUDIO_INFO0 + offset, 257 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 258 WREG32(HDMI0_AUDIO_INFO1 + offset, 259 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24)); 260} 261 262/* 263 * test if audio buffer is filled enough to start playing 264 */ 265static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder) 266{ 267 struct drm_device *dev = encoder->dev; 268 struct radeon_device *rdev = dev->dev_private; 269 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 270 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 271 uint32_t offset = dig->afmt->offset; 272 273 return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0; 274} 275 276/* 277 * have buffer status changed since last call? 278 */ 279int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder) 280{ 281 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 282 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 283 int status, result; 284 285 if (!dig->afmt || !dig->afmt->enabled) 286 return 0; 287 288 status = r600_hdmi_is_audio_buffer_filled(encoder); 289 result = dig->afmt->last_buffer_filled_status != status; 290 dig->afmt->last_buffer_filled_status = status; 291 292 return result; 293} 294 295/* 296 * write the audio workaround status to the hardware 297 */ 298static void r600_hdmi_audio_workaround(struct drm_encoder *encoder) 299{ 300 struct drm_device *dev = encoder->dev; 301 struct radeon_device *rdev = dev->dev_private; 302 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 303 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 304 uint32_t offset = dig->afmt->offset; 305 bool hdmi_audio_workaround = false; /* FIXME */ 306 u32 value; 307 308 if (!hdmi_audio_workaround || 309 r600_hdmi_is_audio_buffer_filled(encoder)) 310 value = 0; /* disable workaround */ 311 else 312 value = HDMI0_AUDIO_TEST_EN; /* enable workaround */ 313 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, 314 value, ~HDMI0_AUDIO_TEST_EN); 315} 316 317 318/* 319 * update the info frames with the data from the current display mode 320 */ 321void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) 322{ 323 struct drm_device *dev = encoder->dev; 324 struct radeon_device *rdev = dev->dev_private; 325 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 326 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 327 uint32_t offset; 328 329 /* Silent, r600_hdmi_enable will raise WARN for us */ 330 if (!dig->afmt->enabled) 331 return; 332 offset = dig->afmt->offset; 333 334 r600_audio_set_clock(encoder, mode->clock); 335 336 WREG32(HDMI0_VBI_PACKET_CONTROL + offset, 337 HDMI0_NULL_SEND); /* send null packets when required */ 338 339 WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); 340 341 if (ASIC_IS_DCE32(rdev)) { 342 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, 343 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ 344 HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ 345 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, 346 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */ 347 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ 348 } else { 349 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, 350 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ 351 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ 352 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */ 353 HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ 354 } 355 356 WREG32(HDMI0_ACR_PACKET_CONTROL + offset, 357 HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ 358 HDMI0_ACR_SOURCE); /* select SW CTS value */ 359 360 WREG32(HDMI0_VBI_PACKET_CONTROL + offset, 361 HDMI0_NULL_SEND | /* send null packets when required */ 362 HDMI0_GC_SEND | /* send general control packets */ 363 HDMI0_GC_CONT); /* send general control packets every frame */ 364 365 /* TODO: HDMI0_AUDIO_INFO_UPDATE */ 366 WREG32(HDMI0_INFOFRAME_CONTROL0 + offset, 367 HDMI0_AVI_INFO_SEND | /* enable AVI info frames */ 368 HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */ 369 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ 370 HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */ 371 372 WREG32(HDMI0_INFOFRAME_CONTROL1 + offset, 373 HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */ 374 HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */ 375 376 WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */ 377 378 r600_hdmi_videoinfoframe(encoder, RGB, 0, 0, 0, 0, 379 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); 380 381 r600_hdmi_update_ACR(encoder, mode->clock); 382 383 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ 384 WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF); 385 WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF); 386 WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001); 387 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); 388 389 r600_hdmi_audio_workaround(encoder); 390} 391 392/* 393 * update settings with current parameters from audio engine 394 */ 395void r600_hdmi_update_audio_settings(struct drm_encoder *encoder) 396{ 397 struct drm_device *dev = encoder->dev; 398 struct radeon_device *rdev = dev->dev_private; 399 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 400 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 401 struct r600_audio audio = r600_audio_status(rdev); 402 uint32_t offset; 403 uint32_t iec; 404 405 if (!dig->afmt || !dig->afmt->enabled) 406 return; 407 offset = dig->afmt->offset; 408 409 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n", 410 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped", 411 audio.channels, audio.rate, audio.bits_per_sample); 412 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n", 413 (int)audio.status_bits, (int)audio.category_code); 414 415 iec = 0; 416 if (audio.status_bits & AUDIO_STATUS_PROFESSIONAL) 417 iec |= 1 << 0; 418 if (audio.status_bits & AUDIO_STATUS_NONAUDIO) 419 iec |= 1 << 1; 420 if (audio.status_bits & AUDIO_STATUS_COPYRIGHT) 421 iec |= 1 << 2; 422 if (audio.status_bits & AUDIO_STATUS_EMPHASIS) 423 iec |= 1 << 3; 424 425 iec |= HDMI0_60958_CS_CATEGORY_CODE(audio.category_code); 426 427 switch (audio.rate) { 428 case 32000: 429 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3); 430 break; 431 case 44100: 432 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0); 433 break; 434 case 48000: 435 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2); 436 break; 437 case 88200: 438 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8); 439 break; 440 case 96000: 441 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa); 442 break; 443 case 176400: 444 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc); 445 break; 446 case 192000: 447 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe); 448 break; 449 } 450 451 WREG32(HDMI0_60958_0 + offset, iec); 452 453 iec = 0; 454 switch (audio.bits_per_sample) { 455 case 16: 456 iec |= HDMI0_60958_CS_WORD_LENGTH(0x2); 457 break; 458 case 20: 459 iec |= HDMI0_60958_CS_WORD_LENGTH(0x3); 460 break; 461 case 24: 462 iec |= HDMI0_60958_CS_WORD_LENGTH(0xb); 463 break; 464 } 465 if (audio.status_bits & AUDIO_STATUS_V) 466 iec |= 0x5 << 16; 467 WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f); 468 469 r600_hdmi_audioinfoframe(encoder, audio.channels - 1, 0, 0, 0, 0, 0, 0, 470 0); 471 472 r600_hdmi_audio_workaround(encoder); 473} 474 475/* 476 * enable the HDMI engine 477 */ 478void r600_hdmi_enable(struct drm_encoder *encoder) 479{ 480 struct drm_device *dev = encoder->dev; 481 struct radeon_device *rdev = dev->dev_private; 482 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 483 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 484 uint32_t offset; 485 u32 hdmi; 486 487 if (ASIC_IS_DCE6(rdev)) 488 return; 489 490 /* Silent, r600_hdmi_enable will raise WARN for us */ 491 if (dig->afmt->enabled) 492 return; 493 offset = dig->afmt->offset; 494 495 /* Older chipsets require setting HDMI and routing manually */ 496 if (ASIC_IS_DCE2(rdev) && !ASIC_IS_DCE3(rdev)) { 497 hdmi = HDMI0_ERROR_ACK | HDMI0_ENABLE; 498 switch (radeon_encoder->encoder_id) { 499 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 500 WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN, 501 ~AVIVO_TMDSA_CNTL_HDMI_EN); 502 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA); 503 break; 504 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 505 WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN, 506 ~AVIVO_LVTMA_CNTL_HDMI_EN); 507 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA); 508 break; 509 case ENCODER_OBJECT_ID_INTERNAL_DDI: 510 WREG32_P(DDIA_CNTL, DDIA_HDMI_EN, ~DDIA_HDMI_EN); 511 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA); 512 break; 513 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 514 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA); 515 break; 516 default: 517 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n", 518 radeon_encoder->encoder_id); 519 break; 520 } 521 WREG32(HDMI0_CONTROL + offset, hdmi); 522 } 523 524 if (rdev->irq.installed) { 525 /* if irq is available use it */ 526 radeon_irq_kms_enable_afmt(rdev, dig->afmt->id); 527 } 528 529 dig->afmt->enabled = true; 530 531 DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n", 532 offset, radeon_encoder->encoder_id); 533} 534 535/* 536 * disable the HDMI engine 537 */ 538void r600_hdmi_disable(struct drm_encoder *encoder) 539{ 540 struct drm_device *dev = encoder->dev; 541 struct radeon_device *rdev = dev->dev_private; 542 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 543 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 544 uint32_t offset; 545 546 if (ASIC_IS_DCE6(rdev)) 547 return; 548 549 /* Called for ATOM_ENCODER_MODE_HDMI only */ 550 if (!dig || !dig->afmt) { 551 return; 552 } 553 if (!dig->afmt->enabled) 554 return; 555 offset = dig->afmt->offset; 556 557 DRM_DEBUG("Disabling HDMI interface @ 0x%04X for encoder 0x%x\n", 558 offset, radeon_encoder->encoder_id); 559 560 /* disable irq */ 561 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id); 562 563 /* Older chipsets not handled by AtomBIOS */ 564 if (ASIC_IS_DCE2(rdev) && !ASIC_IS_DCE3(rdev)) { 565 switch (radeon_encoder->encoder_id) { 566 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 567 WREG32_P(AVIVO_TMDSA_CNTL, 0, 568 ~AVIVO_TMDSA_CNTL_HDMI_EN); 569 break; 570 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 571 WREG32_P(AVIVO_LVTMA_CNTL, 0, 572 ~AVIVO_LVTMA_CNTL_HDMI_EN); 573 break; 574 case ENCODER_OBJECT_ID_INTERNAL_DDI: 575 WREG32_P(DDIA_CNTL, 0, ~DDIA_HDMI_EN); 576 break; 577 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 578 break; 579 default: 580 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n", 581 radeon_encoder->encoder_id); 582 break; 583 } 584 WREG32(HDMI0_CONTROL + offset, HDMI0_ERROR_ACK); 585 } 586 587 dig->afmt->enabled = false; 588} 589