1254885Sdumbbell/* 2254885Sdumbbell * Copyright 2010 Advanced Micro Devices, Inc. 3254885Sdumbbell * 4254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 5254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 6254885Sdumbbell * to deal in the Software without restriction, including without limitation 7254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 9254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 10254885Sdumbbell * 11254885Sdumbbell * The above copyright notice and this permission notice shall be included in 12254885Sdumbbell * all copies or substantial portions of the Software. 13254885Sdumbbell * 14254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17254885Sdumbbell * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20254885Sdumbbell * OTHER DEALINGS IN THE SOFTWARE. 21254885Sdumbbell * 22254885Sdumbbell * Authors: Alex Deucher 23254885Sdumbbell */ 24254885Sdumbbell 25254885Sdumbbell#include <sys/cdefs.h> 26254885Sdumbbell__FBSDID("$FreeBSD$"); 27254885Sdumbbell 28254885Sdumbbell#ifndef EVERGREEND_H 29254885Sdumbbell#define EVERGREEND_H 30254885Sdumbbell 31254885Sdumbbell#define EVERGREEN_MAX_SH_GPRS 256 32254885Sdumbbell#define EVERGREEN_MAX_TEMP_GPRS 16 33254885Sdumbbell#define EVERGREEN_MAX_SH_THREADS 256 34254885Sdumbbell#define EVERGREEN_MAX_SH_STACK_ENTRIES 4096 35254885Sdumbbell#define EVERGREEN_MAX_FRC_EOV_CNT 16384 36254885Sdumbbell#define EVERGREEN_MAX_BACKENDS 8 37254885Sdumbbell#define EVERGREEN_MAX_BACKENDS_MASK 0xFF 38254885Sdumbbell#define EVERGREEN_MAX_SIMDS 16 39254885Sdumbbell#define EVERGREEN_MAX_SIMDS_MASK 0xFFFF 40254885Sdumbbell#define EVERGREEN_MAX_PIPES 8 41254885Sdumbbell#define EVERGREEN_MAX_PIPES_MASK 0xFF 42254885Sdumbbell#define EVERGREEN_MAX_LDS_NUM 0xFFFF 43254885Sdumbbell 44254885Sdumbbell#define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003 45254885Sdumbbell#define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003 46254885Sdumbbell#define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 47254885Sdumbbell#define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002 48254885Sdumbbell#define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002 49254885Sdumbbell#define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002 50254885Sdumbbell#define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001 51254885Sdumbbell#define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001 52254885Sdumbbell#define SUMO_GB_ADDR_CONFIG_GOLDEN 0x02010002 53254885Sdumbbell#define SUMO2_GB_ADDR_CONFIG_GOLDEN 0x02010002 54254885Sdumbbell 55254885Sdumbbell/* Registers */ 56254885Sdumbbell 57254885Sdumbbell#define RCU_IND_INDEX 0x100 58254885Sdumbbell#define RCU_IND_DATA 0x104 59254885Sdumbbell 60254885Sdumbbell#define GRBM_GFX_INDEX 0x802C 61254885Sdumbbell#define INSTANCE_INDEX(x) ((x) << 0) 62254885Sdumbbell#define SE_INDEX(x) ((x) << 16) 63254885Sdumbbell#define INSTANCE_BROADCAST_WRITES (1 << 30) 64258780Seadler#define SE_BROADCAST_WRITES (1U << 31) 65254885Sdumbbell#define RLC_GFX_INDEX 0x3fC4 66254885Sdumbbell#define CC_GC_SHADER_PIPE_CONFIG 0x8950 67254885Sdumbbell#define WRITE_DIS (1 << 0) 68254885Sdumbbell#define CC_RB_BACKEND_DISABLE 0x98F4 69254885Sdumbbell#define BACKEND_DISABLE(x) ((x) << 16) 70254885Sdumbbell#define GB_ADDR_CONFIG 0x98F8 71254885Sdumbbell#define NUM_PIPES(x) ((x) << 0) 72254885Sdumbbell#define NUM_PIPES_MASK 0x0000000f 73254885Sdumbbell#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 74254885Sdumbbell#define BANK_INTERLEAVE_SIZE(x) ((x) << 8) 75254885Sdumbbell#define NUM_SHADER_ENGINES(x) ((x) << 12) 76254885Sdumbbell#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 77254885Sdumbbell#define NUM_GPUS(x) ((x) << 20) 78254885Sdumbbell#define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 79254885Sdumbbell#define ROW_SIZE(x) ((x) << 28) 80254885Sdumbbell#define GB_BACKEND_MAP 0x98FC 81254885Sdumbbell#define DMIF_ADDR_CONFIG 0xBD4 82254885Sdumbbell#define HDP_ADDR_CONFIG 0x2F48 83254885Sdumbbell#define HDP_MISC_CNTL 0x2F4C 84254885Sdumbbell#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 85254885Sdumbbell 86254885Sdumbbell#define CC_SYS_RB_BACKEND_DISABLE 0x3F88 87254885Sdumbbell#define GC_USER_RB_BACKEND_DISABLE 0x9B7C 88254885Sdumbbell 89254885Sdumbbell#define CGTS_SYS_TCC_DISABLE 0x3F90 90254885Sdumbbell#define CGTS_TCC_DISABLE 0x9148 91254885Sdumbbell#define CGTS_USER_SYS_TCC_DISABLE 0x3F94 92254885Sdumbbell#define CGTS_USER_TCC_DISABLE 0x914C 93254885Sdumbbell 94254885Sdumbbell#define CONFIG_MEMSIZE 0x5428 95254885Sdumbbell 96254885Sdumbbell#define BIF_FB_EN 0x5490 97254885Sdumbbell#define FB_READ_EN (1 << 0) 98254885Sdumbbell#define FB_WRITE_EN (1 << 1) 99254885Sdumbbell 100254885Sdumbbell#define CP_STRMOUT_CNTL 0x84FC 101254885Sdumbbell 102254885Sdumbbell#define CP_COHER_CNTL 0x85F0 103254885Sdumbbell#define CP_COHER_SIZE 0x85F4 104254885Sdumbbell#define CP_COHER_BASE 0x85F8 105254885Sdumbbell#define CP_STALLED_STAT1 0x8674 106254885Sdumbbell#define CP_STALLED_STAT2 0x8678 107254885Sdumbbell#define CP_BUSY_STAT 0x867C 108254885Sdumbbell#define CP_STAT 0x8680 109254885Sdumbbell#define CP_ME_CNTL 0x86D8 110254885Sdumbbell#define CP_ME_HALT (1 << 28) 111254885Sdumbbell#define CP_PFP_HALT (1 << 26) 112254885Sdumbbell#define CP_ME_RAM_DATA 0xC160 113254885Sdumbbell#define CP_ME_RAM_RADDR 0xC158 114254885Sdumbbell#define CP_ME_RAM_WADDR 0xC15C 115254885Sdumbbell#define CP_MEQ_THRESHOLDS 0x8764 116254885Sdumbbell#define STQ_SPLIT(x) ((x) << 0) 117254885Sdumbbell#define CP_PERFMON_CNTL 0x87FC 118254885Sdumbbell#define CP_PFP_UCODE_ADDR 0xC150 119254885Sdumbbell#define CP_PFP_UCODE_DATA 0xC154 120254885Sdumbbell#define CP_QUEUE_THRESHOLDS 0x8760 121254885Sdumbbell#define ROQ_IB1_START(x) ((x) << 0) 122254885Sdumbbell#define ROQ_IB2_START(x) ((x) << 8) 123254885Sdumbbell#define CP_RB_BASE 0xC100 124254885Sdumbbell#define CP_RB_CNTL 0xC104 125254885Sdumbbell#define RB_BUFSZ(x) ((x) << 0) 126254885Sdumbbell#define RB_BLKSZ(x) ((x) << 8) 127254885Sdumbbell#define RB_NO_UPDATE (1 << 27) 128258780Seadler#define RB_RPTR_WR_ENA (1U << 31) 129254885Sdumbbell#define BUF_SWAP_32BIT (2 << 16) 130254885Sdumbbell#define CP_RB_RPTR 0x8700 131254885Sdumbbell#define CP_RB_RPTR_ADDR 0xC10C 132254885Sdumbbell#define RB_RPTR_SWAP(x) ((x) << 0) 133254885Sdumbbell#define CP_RB_RPTR_ADDR_HI 0xC110 134254885Sdumbbell#define CP_RB_RPTR_WR 0xC108 135254885Sdumbbell#define CP_RB_WPTR 0xC114 136254885Sdumbbell#define CP_RB_WPTR_ADDR 0xC118 137254885Sdumbbell#define CP_RB_WPTR_ADDR_HI 0xC11C 138254885Sdumbbell#define CP_RB_WPTR_DELAY 0x8704 139254885Sdumbbell#define CP_SEM_WAIT_TIMER 0x85BC 140254885Sdumbbell#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 141254885Sdumbbell#define CP_DEBUG 0xC1FC 142254885Sdumbbell 143254885Sdumbbell/* Audio clocks */ 144254885Sdumbbell#define DCCG_AUDIO_DTO_SOURCE 0x05ac 145254885Sdumbbell# define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */ 146254885Sdumbbell# define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */ 147254885Sdumbbell 148254885Sdumbbell#define DCCG_AUDIO_DTO0_PHASE 0x05b0 149254885Sdumbbell#define DCCG_AUDIO_DTO0_MODULE 0x05b4 150254885Sdumbbell#define DCCG_AUDIO_DTO0_LOAD 0x05b8 151254885Sdumbbell#define DCCG_AUDIO_DTO0_CNTL 0x05bc 152254885Sdumbbell 153254885Sdumbbell#define DCCG_AUDIO_DTO1_PHASE 0x05c0 154254885Sdumbbell#define DCCG_AUDIO_DTO1_MODULE 0x05c4 155254885Sdumbbell#define DCCG_AUDIO_DTO1_LOAD 0x05c8 156254885Sdumbbell#define DCCG_AUDIO_DTO1_CNTL 0x05cc 157254885Sdumbbell 158254885Sdumbbell/* DCE 4.0 AFMT */ 159254885Sdumbbell#define HDMI_CONTROL 0x7030 160254885Sdumbbell# define HDMI_KEEPOUT_MODE (1 << 0) 161254885Sdumbbell# define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */ 162254885Sdumbbell# define HDMI_ERROR_ACK (1 << 8) 163254885Sdumbbell# define HDMI_ERROR_MASK (1 << 9) 164254885Sdumbbell# define HDMI_DEEP_COLOR_ENABLE (1 << 24) 165254885Sdumbbell# define HDMI_DEEP_COLOR_DEPTH (((x) & 3) << 28) 166254885Sdumbbell# define HDMI_24BIT_DEEP_COLOR 0 167254885Sdumbbell# define HDMI_30BIT_DEEP_COLOR 1 168254885Sdumbbell# define HDMI_36BIT_DEEP_COLOR 2 169254885Sdumbbell#define HDMI_STATUS 0x7034 170254885Sdumbbell# define HDMI_ACTIVE_AVMUTE (1 << 0) 171254885Sdumbbell# define HDMI_AUDIO_PACKET_ERROR (1 << 16) 172254885Sdumbbell# define HDMI_VBI_PACKET_ERROR (1 << 20) 173254885Sdumbbell#define HDMI_AUDIO_PACKET_CONTROL 0x7038 174254885Sdumbbell# define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4) 175254885Sdumbbell# define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) 176254885Sdumbbell#define HDMI_ACR_PACKET_CONTROL 0x703c 177254885Sdumbbell# define HDMI_ACR_SEND (1 << 0) 178254885Sdumbbell# define HDMI_ACR_CONT (1 << 1) 179254885Sdumbbell# define HDMI_ACR_SELECT(x) (((x) & 3) << 4) 180254885Sdumbbell# define HDMI_ACR_HW 0 181254885Sdumbbell# define HDMI_ACR_32 1 182254885Sdumbbell# define HDMI_ACR_44 2 183254885Sdumbbell# define HDMI_ACR_48 3 184254885Sdumbbell# define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ 185254885Sdumbbell# define HDMI_ACR_AUTO_SEND (1 << 12) 186254885Sdumbbell# define HDMI_ACR_N_MULTIPLE(x) (((x) & 7) << 16) 187254885Sdumbbell# define HDMI_ACR_X1 1 188254885Sdumbbell# define HDMI_ACR_X2 2 189254885Sdumbbell# define HDMI_ACR_X4 4 190258780Seadler# define HDMI_ACR_AUDIO_PRIORITY (1U << 31) 191254885Sdumbbell#define HDMI_VBI_PACKET_CONTROL 0x7040 192254885Sdumbbell# define HDMI_NULL_SEND (1 << 0) 193254885Sdumbbell# define HDMI_GC_SEND (1 << 4) 194254885Sdumbbell# define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ 195254885Sdumbbell#define HDMI_INFOFRAME_CONTROL0 0x7044 196254885Sdumbbell# define HDMI_AVI_INFO_SEND (1 << 0) 197254885Sdumbbell# define HDMI_AVI_INFO_CONT (1 << 1) 198254885Sdumbbell# define HDMI_AUDIO_INFO_SEND (1 << 4) 199254885Sdumbbell# define HDMI_AUDIO_INFO_CONT (1 << 5) 200254885Sdumbbell# define HDMI_MPEG_INFO_SEND (1 << 8) 201254885Sdumbbell# define HDMI_MPEG_INFO_CONT (1 << 9) 202254885Sdumbbell#define HDMI_INFOFRAME_CONTROL1 0x7048 203254885Sdumbbell# define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) 204254885Sdumbbell# define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) 205254885Sdumbbell# define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) 206254885Sdumbbell#define HDMI_GENERIC_PACKET_CONTROL 0x704c 207254885Sdumbbell# define HDMI_GENERIC0_SEND (1 << 0) 208254885Sdumbbell# define HDMI_GENERIC0_CONT (1 << 1) 209254885Sdumbbell# define HDMI_GENERIC1_SEND (1 << 4) 210254885Sdumbbell# define HDMI_GENERIC1_CONT (1 << 5) 211254885Sdumbbell# define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16) 212254885Sdumbbell# define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24) 213254885Sdumbbell#define HDMI_GC 0x7058 214254885Sdumbbell# define HDMI_GC_AVMUTE (1 << 0) 215254885Sdumbbell# define HDMI_GC_AVMUTE_CONT (1 << 2) 216254885Sdumbbell#define AFMT_AUDIO_PACKET_CONTROL2 0x705c 217254885Sdumbbell# define AFMT_AUDIO_LAYOUT_OVRD (1 << 0) 218254885Sdumbbell# define AFMT_AUDIO_LAYOUT_SELECT (1 << 1) 219254885Sdumbbell# define AFMT_60958_CS_SOURCE (1 << 4) 220254885Sdumbbell# define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8) 221254885Sdumbbell# define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16) 222254885Sdumbbell#define AFMT_AVI_INFO0 0x7084 223254885Sdumbbell# define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 224254885Sdumbbell# define AFMT_AVI_INFO_S(x) (((x) & 3) << 8) 225254885Sdumbbell# define AFMT_AVI_INFO_B(x) (((x) & 3) << 10) 226254885Sdumbbell# define AFMT_AVI_INFO_A(x) (((x) & 1) << 12) 227254885Sdumbbell# define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13) 228254885Sdumbbell# define AFMT_AVI_INFO_Y_RGB 0 229254885Sdumbbell# define AFMT_AVI_INFO_Y_YCBCR422 1 230254885Sdumbbell# define AFMT_AVI_INFO_Y_YCBCR444 2 231254885Sdumbbell# define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) 232254885Sdumbbell# define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16) 233254885Sdumbbell# define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20) 234254885Sdumbbell# define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22) 235254885Sdumbbell# define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) 236254885Sdumbbell# define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24) 237254885Sdumbbell# define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26) 238254885Sdumbbell# define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28) 239254885Sdumbbell# define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31) 240254885Sdumbbell# define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) 241254885Sdumbbell#define AFMT_AVI_INFO1 0x7088 242254885Sdumbbell# define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ 243254885Sdumbbell# define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ 244254885Sdumbbell# define AFMT_AVI_INFO_CN(x) (((x) & 0x3) << 12) 245254885Sdumbbell# define AFMT_AVI_INFO_YQ(x) (((x) & 0x3) << 14) 246254885Sdumbbell# define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) 247254885Sdumbbell#define AFMT_AVI_INFO2 0x708c 248254885Sdumbbell# define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) 249254885Sdumbbell# define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) 250254885Sdumbbell#define AFMT_AVI_INFO3 0x7090 251254885Sdumbbell# define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) 252254885Sdumbbell# define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24) 253254885Sdumbbell#define AFMT_MPEG_INFO0 0x7094 254254885Sdumbbell# define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 255254885Sdumbbell# define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) 256254885Sdumbbell# define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) 257254885Sdumbbell# define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) 258254885Sdumbbell#define AFMT_MPEG_INFO1 0x7098 259254885Sdumbbell# define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) 260254885Sdumbbell# define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8) 261254885Sdumbbell# define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12) 262254885Sdumbbell#define AFMT_GENERIC0_HDR 0x709c 263254885Sdumbbell#define AFMT_GENERIC0_0 0x70a0 264254885Sdumbbell#define AFMT_GENERIC0_1 0x70a4 265254885Sdumbbell#define AFMT_GENERIC0_2 0x70a8 266254885Sdumbbell#define AFMT_GENERIC0_3 0x70ac 267254885Sdumbbell#define AFMT_GENERIC0_4 0x70b0 268254885Sdumbbell#define AFMT_GENERIC0_5 0x70b4 269254885Sdumbbell#define AFMT_GENERIC0_6 0x70b8 270254885Sdumbbell#define AFMT_GENERIC1_HDR 0x70bc 271254885Sdumbbell#define AFMT_GENERIC1_0 0x70c0 272254885Sdumbbell#define AFMT_GENERIC1_1 0x70c4 273254885Sdumbbell#define AFMT_GENERIC1_2 0x70c8 274254885Sdumbbell#define AFMT_GENERIC1_3 0x70cc 275254885Sdumbbell#define AFMT_GENERIC1_4 0x70d0 276254885Sdumbbell#define AFMT_GENERIC1_5 0x70d4 277254885Sdumbbell#define AFMT_GENERIC1_6 0x70d8 278254885Sdumbbell#define HDMI_ACR_32_0 0x70dc 279254885Sdumbbell# define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12) 280254885Sdumbbell#define HDMI_ACR_32_1 0x70e0 281254885Sdumbbell# define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0) 282254885Sdumbbell#define HDMI_ACR_44_0 0x70e4 283254885Sdumbbell# define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12) 284254885Sdumbbell#define HDMI_ACR_44_1 0x70e8 285254885Sdumbbell# define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0) 286254885Sdumbbell#define HDMI_ACR_48_0 0x70ec 287254885Sdumbbell# define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) 288254885Sdumbbell#define HDMI_ACR_48_1 0x70f0 289254885Sdumbbell# define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0) 290254885Sdumbbell#define HDMI_ACR_STATUS_0 0x70f4 291254885Sdumbbell#define HDMI_ACR_STATUS_1 0x70f8 292254885Sdumbbell#define AFMT_AUDIO_INFO0 0x70fc 293254885Sdumbbell# define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 294254885Sdumbbell# define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8) 295254885Sdumbbell# define AFMT_AUDIO_INFO_CT(x) (((x) & 0xf) << 11) 296254885Sdumbbell# define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16) 297254885Sdumbbell# define AFMT_AUDIO_INFO_CXT(x) (((x) & 0x1f) << 24) 298254885Sdumbbell#define AFMT_AUDIO_INFO1 0x7100 299254885Sdumbbell# define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) 300254885Sdumbbell# define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) 301254885Sdumbbell# define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) 302254885Sdumbbell# define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) 303254885Sdumbbell# define AFMT_AUDIO_INFO_LFEBPL(x) (((x) & 3) << 16) 304254885Sdumbbell#define AFMT_60958_0 0x7104 305254885Sdumbbell# define AFMT_60958_CS_A(x) (((x) & 1) << 0) 306254885Sdumbbell# define AFMT_60958_CS_B(x) (((x) & 1) << 1) 307254885Sdumbbell# define AFMT_60958_CS_C(x) (((x) & 1) << 2) 308254885Sdumbbell# define AFMT_60958_CS_D(x) (((x) & 3) << 3) 309254885Sdumbbell# define AFMT_60958_CS_MODE(x) (((x) & 3) << 6) 310254885Sdumbbell# define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) 311254885Sdumbbell# define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) 312254885Sdumbbell# define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) 313254885Sdumbbell# define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) 314254885Sdumbbell# define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) 315254885Sdumbbell#define AFMT_60958_1 0x7108 316254885Sdumbbell# define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) 317254885Sdumbbell# define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) 318254885Sdumbbell# define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16) 319254885Sdumbbell# define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18) 320254885Sdumbbell# define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) 321254885Sdumbbell#define AFMT_AUDIO_CRC_CONTROL 0x710c 322254885Sdumbbell# define AFMT_AUDIO_CRC_EN (1 << 0) 323254885Sdumbbell#define AFMT_RAMP_CONTROL0 0x7110 324254885Sdumbbell# define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) 325258780Seadler# define AFMT_RAMP_DATA_SIGN (1U << 31) 326254885Sdumbbell#define AFMT_RAMP_CONTROL1 0x7114 327254885Sdumbbell# define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) 328254885Sdumbbell# define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24) 329254885Sdumbbell#define AFMT_RAMP_CONTROL2 0x7118 330254885Sdumbbell# define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) 331254885Sdumbbell#define AFMT_RAMP_CONTROL3 0x711c 332254885Sdumbbell# define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) 333254885Sdumbbell#define AFMT_60958_2 0x7120 334254885Sdumbbell# define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) 335254885Sdumbbell# define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) 336254885Sdumbbell# define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) 337254885Sdumbbell# define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) 338254885Sdumbbell# define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) 339254885Sdumbbell# define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) 340254885Sdumbbell#define AFMT_STATUS 0x7128 341254885Sdumbbell# define AFMT_AUDIO_ENABLE (1 << 4) 342254885Sdumbbell# define AFMT_AUDIO_HBR_ENABLE (1 << 8) 343254885Sdumbbell# define AFMT_AZ_FORMAT_WTRIG (1 << 28) 344254885Sdumbbell# define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) 345254885Sdumbbell# define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) 346254885Sdumbbell#define AFMT_AUDIO_PACKET_CONTROL 0x712c 347254885Sdumbbell# define AFMT_AUDIO_SAMPLE_SEND (1 << 0) 348254885Sdumbbell# define AFMT_RESET_FIFO_WHEN_AUDIO_DIS (1 << 11) /* set to 1 */ 349254885Sdumbbell# define AFMT_AUDIO_TEST_EN (1 << 12) 350254885Sdumbbell# define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) 351254885Sdumbbell# define AFMT_60958_CS_UPDATE (1 << 26) 352254885Sdumbbell# define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) 353254885Sdumbbell# define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) 354254885Sdumbbell# define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) 355254885Sdumbbell# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) 356254885Sdumbbell#define AFMT_VBI_PACKET_CONTROL 0x7130 357254885Sdumbbell# define AFMT_GENERIC0_UPDATE (1 << 2) 358254885Sdumbbell#define AFMT_INFOFRAME_CONTROL0 0x7134 359254885Sdumbbell# define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - afmt regs */ 360254885Sdumbbell# define AFMT_AUDIO_INFO_UPDATE (1 << 7) 361254885Sdumbbell# define AFMT_MPEG_INFO_UPDATE (1 << 10) 362254885Sdumbbell#define AFMT_GENERIC0_7 0x7138 363254885Sdumbbell 364254885Sdumbbell/* DCE4/5 ELD audio interface */ 365254885Sdumbbell#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x5f84 /* LPCM */ 366254885Sdumbbell#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x5f88 /* AC3 */ 367254885Sdumbbell#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x5f8c /* MPEG1 */ 368254885Sdumbbell#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x5f90 /* MP3 */ 369254885Sdumbbell#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x5f94 /* MPEG2 */ 370254885Sdumbbell#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x5f98 /* AAC */ 371254885Sdumbbell#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x5f9c /* DTS */ 372254885Sdumbbell#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x5fa0 /* ATRAC */ 373254885Sdumbbell#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x5fa4 /* one bit audio - leave at 0 (default) */ 374254885Sdumbbell#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x5fa8 /* Dolby Digital */ 375254885Sdumbbell#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x5fac /* DTS-HD */ 376254885Sdumbbell#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x5fb0 /* MAT-MLP */ 377254885Sdumbbell#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x5fb4 /* DTS */ 378254885Sdumbbell#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x5fb8 /* WMA Pro */ 379254885Sdumbbell# define MAX_CHANNELS(x) (((x) & 0x7) << 0) 380254885Sdumbbell/* max channels minus one. 7 = 8 channels */ 381254885Sdumbbell# define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) 382254885Sdumbbell# define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) 383254885Sdumbbell# define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ 384254885Sdumbbell/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO 385254885Sdumbbell * bit0 = 32 kHz 386254885Sdumbbell * bit1 = 44.1 kHz 387254885Sdumbbell * bit2 = 48 kHz 388254885Sdumbbell * bit3 = 88.2 kHz 389254885Sdumbbell * bit4 = 96 kHz 390254885Sdumbbell * bit5 = 176.4 kHz 391254885Sdumbbell * bit6 = 192 kHz 392254885Sdumbbell */ 393254885Sdumbbell 394254885Sdumbbell#define AZ_HOT_PLUG_CONTROL 0x5e78 395254885Sdumbbell# define AZ_FORCE_CODEC_WAKE (1 << 0) 396254885Sdumbbell# define PIN0_JACK_DETECTION_ENABLE (1 << 4) 397254885Sdumbbell# define PIN1_JACK_DETECTION_ENABLE (1 << 5) 398254885Sdumbbell# define PIN2_JACK_DETECTION_ENABLE (1 << 6) 399254885Sdumbbell# define PIN3_JACK_DETECTION_ENABLE (1 << 7) 400254885Sdumbbell# define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8) 401254885Sdumbbell# define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9) 402254885Sdumbbell# define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10) 403254885Sdumbbell# define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11) 404254885Sdumbbell# define CODEC_HOT_PLUG_ENABLE (1 << 12) 405254885Sdumbbell# define PIN0_AUDIO_ENABLED (1 << 24) 406254885Sdumbbell# define PIN1_AUDIO_ENABLED (1 << 25) 407254885Sdumbbell# define PIN2_AUDIO_ENABLED (1 << 26) 408254885Sdumbbell# define PIN3_AUDIO_ENABLED (1 << 27) 409258780Seadler# define AUDIO_ENABLED (1U << 31) 410254885Sdumbbell 411254885Sdumbbell 412254885Sdumbbell#define GC_USER_SHADER_PIPE_CONFIG 0x8954 413254885Sdumbbell#define INACTIVE_QD_PIPES(x) ((x) << 8) 414254885Sdumbbell#define INACTIVE_QD_PIPES_MASK 0x0000FF00 415254885Sdumbbell#define INACTIVE_SIMDS(x) ((x) << 16) 416254885Sdumbbell#define INACTIVE_SIMDS_MASK 0x00FF0000 417254885Sdumbbell 418254885Sdumbbell#define GRBM_CNTL 0x8000 419254885Sdumbbell#define GRBM_READ_TIMEOUT(x) ((x) << 0) 420254885Sdumbbell#define GRBM_SOFT_RESET 0x8020 421254885Sdumbbell#define SOFT_RESET_CP (1 << 0) 422254885Sdumbbell#define SOFT_RESET_CB (1 << 1) 423254885Sdumbbell#define SOFT_RESET_DB (1 << 3) 424254885Sdumbbell#define SOFT_RESET_PA (1 << 5) 425254885Sdumbbell#define SOFT_RESET_SC (1 << 6) 426254885Sdumbbell#define SOFT_RESET_SPI (1 << 8) 427254885Sdumbbell#define SOFT_RESET_SH (1 << 9) 428254885Sdumbbell#define SOFT_RESET_SX (1 << 10) 429254885Sdumbbell#define SOFT_RESET_TC (1 << 11) 430254885Sdumbbell#define SOFT_RESET_TA (1 << 12) 431254885Sdumbbell#define SOFT_RESET_VC (1 << 13) 432254885Sdumbbell#define SOFT_RESET_VGT (1 << 14) 433254885Sdumbbell 434254885Sdumbbell#define GRBM_STATUS 0x8010 435254885Sdumbbell#define CMDFIFO_AVAIL_MASK 0x0000000F 436254885Sdumbbell#define SRBM_RQ_PENDING (1 << 5) 437254885Sdumbbell#define CF_RQ_PENDING (1 << 7) 438254885Sdumbbell#define PF_RQ_PENDING (1 << 8) 439254885Sdumbbell#define GRBM_EE_BUSY (1 << 10) 440254885Sdumbbell#define SX_CLEAN (1 << 11) 441254885Sdumbbell#define DB_CLEAN (1 << 12) 442254885Sdumbbell#define CB_CLEAN (1 << 13) 443254885Sdumbbell#define TA_BUSY (1 << 14) 444254885Sdumbbell#define VGT_BUSY_NO_DMA (1 << 16) 445254885Sdumbbell#define VGT_BUSY (1 << 17) 446254885Sdumbbell#define SX_BUSY (1 << 20) 447254885Sdumbbell#define SH_BUSY (1 << 21) 448254885Sdumbbell#define SPI_BUSY (1 << 22) 449254885Sdumbbell#define SC_BUSY (1 << 24) 450254885Sdumbbell#define PA_BUSY (1 << 25) 451254885Sdumbbell#define DB_BUSY (1 << 26) 452254885Sdumbbell#define CP_COHERENCY_BUSY (1 << 28) 453254885Sdumbbell#define CP_BUSY (1 << 29) 454254885Sdumbbell#define CB_BUSY (1 << 30) 455258780Seadler#define GUI_ACTIVE (1U << 31) 456254885Sdumbbell#define GRBM_STATUS_SE0 0x8014 457254885Sdumbbell#define GRBM_STATUS_SE1 0x8018 458254885Sdumbbell#define SE_SX_CLEAN (1 << 0) 459254885Sdumbbell#define SE_DB_CLEAN (1 << 1) 460254885Sdumbbell#define SE_CB_CLEAN (1 << 2) 461254885Sdumbbell#define SE_TA_BUSY (1 << 25) 462254885Sdumbbell#define SE_SX_BUSY (1 << 26) 463254885Sdumbbell#define SE_SPI_BUSY (1 << 27) 464254885Sdumbbell#define SE_SH_BUSY (1 << 28) 465254885Sdumbbell#define SE_SC_BUSY (1 << 29) 466254885Sdumbbell#define SE_DB_BUSY (1 << 30) 467258780Seadler#define SE_CB_BUSY (1U << 31) 468254885Sdumbbell/* evergreen */ 469254885Sdumbbell#define CG_THERMAL_CTRL 0x72c 470254885Sdumbbell#define TOFFSET_MASK 0x00003FE0 471254885Sdumbbell#define TOFFSET_SHIFT 5 472254885Sdumbbell#define CG_MULT_THERMAL_STATUS 0x740 473254885Sdumbbell#define ASIC_T(x) ((x) << 16) 474254885Sdumbbell#define ASIC_T_MASK 0x07FF0000 475254885Sdumbbell#define ASIC_T_SHIFT 16 476254885Sdumbbell#define CG_TS0_STATUS 0x760 477254885Sdumbbell#define TS0_ADC_DOUT_MASK 0x000003FF 478254885Sdumbbell#define TS0_ADC_DOUT_SHIFT 0 479254885Sdumbbell/* APU */ 480254885Sdumbbell#define CG_THERMAL_STATUS 0x678 481254885Sdumbbell 482254885Sdumbbell#define HDP_HOST_PATH_CNTL 0x2C00 483254885Sdumbbell#define HDP_NONSURFACE_BASE 0x2C04 484254885Sdumbbell#define HDP_NONSURFACE_INFO 0x2C08 485254885Sdumbbell#define HDP_NONSURFACE_SIZE 0x2C0C 486254885Sdumbbell#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 487254885Sdumbbell#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 488254885Sdumbbell#define HDP_TILING_CONFIG 0x2F3C 489254885Sdumbbell 490254885Sdumbbell#define MC_SHARED_CHMAP 0x2004 491254885Sdumbbell#define NOOFCHAN_SHIFT 12 492254885Sdumbbell#define NOOFCHAN_MASK 0x00003000 493254885Sdumbbell#define MC_SHARED_CHREMAP 0x2008 494254885Sdumbbell 495254885Sdumbbell#define MC_SHARED_BLACKOUT_CNTL 0x20ac 496254885Sdumbbell#define BLACKOUT_MODE_MASK 0x00000007 497254885Sdumbbell 498254885Sdumbbell#define MC_ARB_RAMCFG 0x2760 499254885Sdumbbell#define NOOFBANK_SHIFT 0 500254885Sdumbbell#define NOOFBANK_MASK 0x00000003 501254885Sdumbbell#define NOOFRANK_SHIFT 2 502254885Sdumbbell#define NOOFRANK_MASK 0x00000004 503254885Sdumbbell#define NOOFROWS_SHIFT 3 504254885Sdumbbell#define NOOFROWS_MASK 0x00000038 505254885Sdumbbell#define NOOFCOLS_SHIFT 6 506254885Sdumbbell#define NOOFCOLS_MASK 0x000000C0 507254885Sdumbbell#define CHANSIZE_SHIFT 8 508254885Sdumbbell#define CHANSIZE_MASK 0x00000100 509254885Sdumbbell#define BURSTLENGTH_SHIFT 9 510254885Sdumbbell#define BURSTLENGTH_MASK 0x00000200 511254885Sdumbbell#define CHANSIZE_OVERRIDE (1 << 11) 512254885Sdumbbell#define FUS_MC_ARB_RAMCFG 0x2768 513254885Sdumbbell#define MC_VM_AGP_TOP 0x2028 514254885Sdumbbell#define MC_VM_AGP_BOT 0x202C 515254885Sdumbbell#define MC_VM_AGP_BASE 0x2030 516254885Sdumbbell#define MC_VM_FB_LOCATION 0x2024 517254885Sdumbbell#define MC_FUS_VM_FB_OFFSET 0x2898 518254885Sdumbbell#define MC_VM_MB_L1_TLB0_CNTL 0x2234 519254885Sdumbbell#define MC_VM_MB_L1_TLB1_CNTL 0x2238 520254885Sdumbbell#define MC_VM_MB_L1_TLB2_CNTL 0x223C 521254885Sdumbbell#define MC_VM_MB_L1_TLB3_CNTL 0x2240 522254885Sdumbbell#define ENABLE_L1_TLB (1 << 0) 523254885Sdumbbell#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 524254885Sdumbbell#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 525254885Sdumbbell#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 526254885Sdumbbell#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 527254885Sdumbbell#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 528254885Sdumbbell#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 529254885Sdumbbell#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) 530254885Sdumbbell#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) 531254885Sdumbbell#define MC_VM_MD_L1_TLB0_CNTL 0x2654 532254885Sdumbbell#define MC_VM_MD_L1_TLB1_CNTL 0x2658 533254885Sdumbbell#define MC_VM_MD_L1_TLB2_CNTL 0x265C 534254885Sdumbbell#define MC_VM_MD_L1_TLB3_CNTL 0x2698 535254885Sdumbbell 536254885Sdumbbell#define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C 537254885Sdumbbell#define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660 538254885Sdumbbell#define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664 539254885Sdumbbell 540254885Sdumbbell#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 541254885Sdumbbell#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 542254885Sdumbbell#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 543254885Sdumbbell 544254885Sdumbbell#define PA_CL_ENHANCE 0x8A14 545254885Sdumbbell#define CLIP_VTX_REORDER_ENA (1 << 0) 546254885Sdumbbell#define NUM_CLIP_SEQ(x) ((x) << 1) 547254885Sdumbbell#define PA_SC_ENHANCE 0x8BF0 548254885Sdumbbell#define PA_SC_AA_CONFIG 0x28C04 549254885Sdumbbell#define MSAA_NUM_SAMPLES_SHIFT 0 550254885Sdumbbell#define MSAA_NUM_SAMPLES_MASK 0x3 551254885Sdumbbell#define PA_SC_CLIPRECT_RULE 0x2820C 552254885Sdumbbell#define PA_SC_EDGERULE 0x28230 553254885Sdumbbell#define PA_SC_FIFO_SIZE 0x8BCC 554254885Sdumbbell#define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 555254885Sdumbbell#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 556254885Sdumbbell#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 557254885Sdumbbell#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 558254885Sdumbbell#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 559254885Sdumbbell#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 560254885Sdumbbell#define PA_SC_LINE_STIPPLE 0x28A0C 561254885Sdumbbell#define PA_SU_LINE_STIPPLE_VALUE 0x8A60 562254885Sdumbbell#define PA_SC_LINE_STIPPLE_STATE 0x8B10 563254885Sdumbbell 564254885Sdumbbell#define SCRATCH_REG0 0x8500 565254885Sdumbbell#define SCRATCH_REG1 0x8504 566254885Sdumbbell#define SCRATCH_REG2 0x8508 567254885Sdumbbell#define SCRATCH_REG3 0x850C 568254885Sdumbbell#define SCRATCH_REG4 0x8510 569254885Sdumbbell#define SCRATCH_REG5 0x8514 570254885Sdumbbell#define SCRATCH_REG6 0x8518 571254885Sdumbbell#define SCRATCH_REG7 0x851C 572254885Sdumbbell#define SCRATCH_UMSK 0x8540 573254885Sdumbbell#define SCRATCH_ADDR 0x8544 574254885Sdumbbell 575254885Sdumbbell#define SMX_SAR_CTL0 0xA008 576254885Sdumbbell#define SMX_DC_CTL0 0xA020 577254885Sdumbbell#define USE_HASH_FUNCTION (1 << 0) 578254885Sdumbbell#define NUMBER_OF_SETS(x) ((x) << 1) 579254885Sdumbbell#define FLUSH_ALL_ON_EVENT (1 << 10) 580254885Sdumbbell#define STALL_ON_EVENT (1 << 11) 581254885Sdumbbell#define SMX_EVENT_CTL 0xA02C 582254885Sdumbbell#define ES_FLUSH_CTL(x) ((x) << 0) 583254885Sdumbbell#define GS_FLUSH_CTL(x) ((x) << 3) 584254885Sdumbbell#define ACK_FLUSH_CTL(x) ((x) << 6) 585254885Sdumbbell#define SYNC_FLUSH_CTL (1 << 8) 586254885Sdumbbell 587254885Sdumbbell#define SPI_CONFIG_CNTL 0x9100 588254885Sdumbbell#define GPR_WRITE_PRIORITY(x) ((x) << 0) 589254885Sdumbbell#define SPI_CONFIG_CNTL_1 0x913C 590254885Sdumbbell#define VTX_DONE_DELAY(x) ((x) << 0) 591254885Sdumbbell#define INTERP_ONE_PRIM_PER_ROW (1 << 4) 592254885Sdumbbell#define SPI_INPUT_Z 0x286D8 593254885Sdumbbell#define SPI_PS_IN_CONTROL_0 0x286CC 594254885Sdumbbell#define NUM_INTERP(x) ((x)<<0) 595254885Sdumbbell#define POSITION_ENA (1<<8) 596254885Sdumbbell#define POSITION_CENTROID (1<<9) 597254885Sdumbbell#define POSITION_ADDR(x) ((x)<<10) 598254885Sdumbbell#define PARAM_GEN(x) ((x)<<15) 599254885Sdumbbell#define PARAM_GEN_ADDR(x) ((x)<<19) 600254885Sdumbbell#define BARYC_SAMPLE_CNTL(x) ((x)<<26) 601254885Sdumbbell#define PERSP_GRADIENT_ENA (1<<28) 602254885Sdumbbell#define LINEAR_GRADIENT_ENA (1<<29) 603254885Sdumbbell#define POSITION_SAMPLE (1<<30) 604254885Sdumbbell#define BARYC_AT_SAMPLE_ENA (1<<31) 605254885Sdumbbell 606254885Sdumbbell#define SQ_CONFIG 0x8C00 607254885Sdumbbell#define VC_ENABLE (1 << 0) 608254885Sdumbbell#define EXPORT_SRC_C (1 << 1) 609254885Sdumbbell#define CS_PRIO(x) ((x) << 18) 610254885Sdumbbell#define LS_PRIO(x) ((x) << 20) 611254885Sdumbbell#define HS_PRIO(x) ((x) << 22) 612254885Sdumbbell#define PS_PRIO(x) ((x) << 24) 613254885Sdumbbell#define VS_PRIO(x) ((x) << 26) 614254885Sdumbbell#define GS_PRIO(x) ((x) << 28) 615254885Sdumbbell#define ES_PRIO(x) ((x) << 30) 616254885Sdumbbell#define SQ_GPR_RESOURCE_MGMT_1 0x8C04 617254885Sdumbbell#define NUM_PS_GPRS(x) ((x) << 0) 618254885Sdumbbell#define NUM_VS_GPRS(x) ((x) << 16) 619254885Sdumbbell#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 620254885Sdumbbell#define SQ_GPR_RESOURCE_MGMT_2 0x8C08 621254885Sdumbbell#define NUM_GS_GPRS(x) ((x) << 0) 622254885Sdumbbell#define NUM_ES_GPRS(x) ((x) << 16) 623254885Sdumbbell#define SQ_GPR_RESOURCE_MGMT_3 0x8C0C 624254885Sdumbbell#define NUM_HS_GPRS(x) ((x) << 0) 625254885Sdumbbell#define NUM_LS_GPRS(x) ((x) << 16) 626254885Sdumbbell#define SQ_GLOBAL_GPR_RESOURCE_MGMT_1 0x8C10 627254885Sdumbbell#define SQ_GLOBAL_GPR_RESOURCE_MGMT_2 0x8C14 628254885Sdumbbell#define SQ_THREAD_RESOURCE_MGMT 0x8C18 629254885Sdumbbell#define NUM_PS_THREADS(x) ((x) << 0) 630254885Sdumbbell#define NUM_VS_THREADS(x) ((x) << 8) 631254885Sdumbbell#define NUM_GS_THREADS(x) ((x) << 16) 632254885Sdumbbell#define NUM_ES_THREADS(x) ((x) << 24) 633254885Sdumbbell#define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C 634254885Sdumbbell#define NUM_HS_THREADS(x) ((x) << 0) 635254885Sdumbbell#define NUM_LS_THREADS(x) ((x) << 8) 636254885Sdumbbell#define SQ_STACK_RESOURCE_MGMT_1 0x8C20 637254885Sdumbbell#define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 638254885Sdumbbell#define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 639254885Sdumbbell#define SQ_STACK_RESOURCE_MGMT_2 0x8C24 640254885Sdumbbell#define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 641254885Sdumbbell#define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 642254885Sdumbbell#define SQ_STACK_RESOURCE_MGMT_3 0x8C28 643254885Sdumbbell#define NUM_HS_STACK_ENTRIES(x) ((x) << 0) 644254885Sdumbbell#define NUM_LS_STACK_ENTRIES(x) ((x) << 16) 645254885Sdumbbell#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C 646254885Sdumbbell#define SQ_DYN_GPR_SIMD_LOCK_EN 0x8D94 647254885Sdumbbell#define SQ_STATIC_THREAD_MGMT_1 0x8E20 648254885Sdumbbell#define SQ_STATIC_THREAD_MGMT_2 0x8E24 649254885Sdumbbell#define SQ_STATIC_THREAD_MGMT_3 0x8E28 650254885Sdumbbell#define SQ_LDS_RESOURCE_MGMT 0x8E2C 651254885Sdumbbell 652254885Sdumbbell#define SQ_MS_FIFO_SIZES 0x8CF0 653254885Sdumbbell#define CACHE_FIFO_SIZE(x) ((x) << 0) 654254885Sdumbbell#define FETCH_FIFO_HIWATER(x) ((x) << 8) 655254885Sdumbbell#define DONE_FIFO_HIWATER(x) ((x) << 16) 656254885Sdumbbell#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 657254885Sdumbbell 658254885Sdumbbell#define SX_DEBUG_1 0x9058 659254885Sdumbbell#define ENABLE_NEW_SMX_ADDRESS (1 << 16) 660254885Sdumbbell#define SX_EXPORT_BUFFER_SIZES 0x900C 661254885Sdumbbell#define COLOR_BUFFER_SIZE(x) ((x) << 0) 662254885Sdumbbell#define POSITION_BUFFER_SIZE(x) ((x) << 8) 663254885Sdumbbell#define SMX_BUFFER_SIZE(x) ((x) << 16) 664254885Sdumbbell#define SX_MEMORY_EXPORT_BASE 0x9010 665254885Sdumbbell#define SX_MISC 0x28350 666254885Sdumbbell 667254885Sdumbbell#define CB_PERF_CTR0_SEL_0 0x9A20 668254885Sdumbbell#define CB_PERF_CTR0_SEL_1 0x9A24 669254885Sdumbbell#define CB_PERF_CTR1_SEL_0 0x9A28 670254885Sdumbbell#define CB_PERF_CTR1_SEL_1 0x9A2C 671254885Sdumbbell#define CB_PERF_CTR2_SEL_0 0x9A30 672254885Sdumbbell#define CB_PERF_CTR2_SEL_1 0x9A34 673254885Sdumbbell#define CB_PERF_CTR3_SEL_0 0x9A38 674254885Sdumbbell#define CB_PERF_CTR3_SEL_1 0x9A3C 675254885Sdumbbell 676254885Sdumbbell#define TA_CNTL_AUX 0x9508 677254885Sdumbbell#define DISABLE_CUBE_WRAP (1 << 0) 678254885Sdumbbell#define DISABLE_CUBE_ANISO (1 << 1) 679254885Sdumbbell#define SYNC_GRADIENT (1 << 24) 680254885Sdumbbell#define SYNC_WALKER (1 << 25) 681254885Sdumbbell#define SYNC_ALIGNER (1 << 26) 682254885Sdumbbell 683254885Sdumbbell#define TCP_CHAN_STEER_LO 0x960c 684254885Sdumbbell#define TCP_CHAN_STEER_HI 0x9610 685254885Sdumbbell 686254885Sdumbbell#define VGT_CACHE_INVALIDATION 0x88C4 687254885Sdumbbell#define CACHE_INVALIDATION(x) ((x) << 0) 688254885Sdumbbell#define VC_ONLY 0 689254885Sdumbbell#define TC_ONLY 1 690254885Sdumbbell#define VC_AND_TC 2 691254885Sdumbbell#define AUTO_INVLD_EN(x) ((x) << 6) 692254885Sdumbbell#define NO_AUTO 0 693254885Sdumbbell#define ES_AUTO 1 694254885Sdumbbell#define GS_AUTO 2 695254885Sdumbbell#define ES_AND_GS_AUTO 3 696254885Sdumbbell#define VGT_GS_VERTEX_REUSE 0x88D4 697254885Sdumbbell#define VGT_NUM_INSTANCES 0x8974 698254885Sdumbbell#define VGT_OUT_DEALLOC_CNTL 0x28C5C 699254885Sdumbbell#define DEALLOC_DIST_MASK 0x0000007F 700254885Sdumbbell#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 701254885Sdumbbell#define VTX_REUSE_DEPTH_MASK 0x000000FF 702254885Sdumbbell 703254885Sdumbbell#define VM_CONTEXT0_CNTL 0x1410 704254885Sdumbbell#define ENABLE_CONTEXT (1 << 0) 705254885Sdumbbell#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 706254885Sdumbbell#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 707254885Sdumbbell#define VM_CONTEXT1_CNTL 0x1414 708254885Sdumbbell#define VM_CONTEXT1_CNTL2 0x1434 709254885Sdumbbell#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 710254885Sdumbbell#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 711254885Sdumbbell#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 712254885Sdumbbell#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 713254885Sdumbbell#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 714254885Sdumbbell#define REQUEST_TYPE(x) (((x) & 0xf) << 0) 715254885Sdumbbell#define RESPONSE_TYPE_MASK 0x000000F0 716254885Sdumbbell#define RESPONSE_TYPE_SHIFT 4 717254885Sdumbbell#define VM_L2_CNTL 0x1400 718254885Sdumbbell#define ENABLE_L2_CACHE (1 << 0) 719254885Sdumbbell#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 720254885Sdumbbell#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 721254885Sdumbbell#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 722254885Sdumbbell#define VM_L2_CNTL2 0x1404 723254885Sdumbbell#define INVALIDATE_ALL_L1_TLBS (1 << 0) 724254885Sdumbbell#define INVALIDATE_L2_CACHE (1 << 1) 725254885Sdumbbell#define VM_L2_CNTL3 0x1408 726254885Sdumbbell#define BANK_SELECT(x) ((x) << 0) 727254885Sdumbbell#define CACHE_UPDATE_MODE(x) ((x) << 6) 728254885Sdumbbell#define VM_L2_STATUS 0x140C 729254885Sdumbbell#define L2_BUSY (1 << 0) 730254885Sdumbbell#define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 731254885Sdumbbell#define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 732254885Sdumbbell 733254885Sdumbbell#define WAIT_UNTIL 0x8040 734254885Sdumbbell 735254885Sdumbbell#define SRBM_STATUS 0x0E50 736254885Sdumbbell#define SRBM_SOFT_RESET 0x0E60 737254885Sdumbbell#define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6 738254885Sdumbbell#define SOFT_RESET_BIF (1 << 1) 739254885Sdumbbell#define SOFT_RESET_CG (1 << 2) 740254885Sdumbbell#define SOFT_RESET_DC (1 << 5) 741254885Sdumbbell#define SOFT_RESET_GRBM (1 << 8) 742254885Sdumbbell#define SOFT_RESET_HDP (1 << 9) 743254885Sdumbbell#define SOFT_RESET_IH (1 << 10) 744254885Sdumbbell#define SOFT_RESET_MC (1 << 11) 745254885Sdumbbell#define SOFT_RESET_RLC (1 << 13) 746254885Sdumbbell#define SOFT_RESET_ROM (1 << 14) 747254885Sdumbbell#define SOFT_RESET_SEM (1 << 15) 748254885Sdumbbell#define SOFT_RESET_VMC (1 << 17) 749254885Sdumbbell#define SOFT_RESET_DMA (1 << 20) 750254885Sdumbbell#define SOFT_RESET_TST (1 << 21) 751254885Sdumbbell#define SOFT_RESET_REGBB (1 << 22) 752254885Sdumbbell#define SOFT_RESET_ORB (1 << 23) 753254885Sdumbbell 754254885Sdumbbell/* display watermarks */ 755254885Sdumbbell#define DC_LB_MEMORY_SPLIT 0x6b0c 756254885Sdumbbell#define PRIORITY_A_CNT 0x6b18 757254885Sdumbbell#define PRIORITY_MARK_MASK 0x7fff 758254885Sdumbbell#define PRIORITY_OFF (1 << 16) 759254885Sdumbbell#define PRIORITY_ALWAYS_ON (1 << 20) 760254885Sdumbbell#define PRIORITY_B_CNT 0x6b1c 761254885Sdumbbell#define PIPE0_ARBITRATION_CONTROL3 0x0bf0 762254885Sdumbbell# define LATENCY_WATERMARK_MASK(x) ((x) << 16) 763254885Sdumbbell#define PIPE0_LATENCY_CONTROL 0x0bf4 764254885Sdumbbell# define LATENCY_LOW_WATERMARK(x) ((x) << 0) 765254885Sdumbbell# define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 766254885Sdumbbell 767254885Sdumbbell#define IH_RB_CNTL 0x3e00 768254885Sdumbbell# define IH_RB_ENABLE (1 << 0) 769254885Sdumbbell# define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 770254885Sdumbbell# define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 771254885Sdumbbell# define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 772254885Sdumbbell# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 773254885Sdumbbell# define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 774258780Seadler# define IH_WPTR_OVERFLOW_CLEAR (1U << 31) 775254885Sdumbbell#define IH_RB_BASE 0x3e04 776254885Sdumbbell#define IH_RB_RPTR 0x3e08 777254885Sdumbbell#define IH_RB_WPTR 0x3e0c 778254885Sdumbbell# define RB_OVERFLOW (1 << 0) 779254885Sdumbbell# define WPTR_OFFSET_MASK 0x3fffc 780254885Sdumbbell#define IH_RB_WPTR_ADDR_HI 0x3e10 781254885Sdumbbell#define IH_RB_WPTR_ADDR_LO 0x3e14 782254885Sdumbbell#define IH_CNTL 0x3e18 783254885Sdumbbell# define ENABLE_INTR (1 << 0) 784254885Sdumbbell# define IH_MC_SWAP(x) ((x) << 1) 785254885Sdumbbell# define IH_MC_SWAP_NONE 0 786254885Sdumbbell# define IH_MC_SWAP_16BIT 1 787254885Sdumbbell# define IH_MC_SWAP_32BIT 2 788254885Sdumbbell# define IH_MC_SWAP_64BIT 3 789254885Sdumbbell# define RPTR_REARM (1 << 4) 790254885Sdumbbell# define MC_WRREQ_CREDIT(x) ((x) << 15) 791254885Sdumbbell# define MC_WR_CLEAN_CNT(x) ((x) << 20) 792254885Sdumbbell 793254885Sdumbbell#define CP_INT_CNTL 0xc124 794254885Sdumbbell# define CNTX_BUSY_INT_ENABLE (1 << 19) 795254885Sdumbbell# define CNTX_EMPTY_INT_ENABLE (1 << 20) 796254885Sdumbbell# define SCRATCH_INT_ENABLE (1 << 25) 797254885Sdumbbell# define TIME_STAMP_INT_ENABLE (1 << 26) 798254885Sdumbbell# define IB2_INT_ENABLE (1 << 29) 799254885Sdumbbell# define IB1_INT_ENABLE (1 << 30) 800258780Seadler# define RB_INT_ENABLE (1U << 31) 801254885Sdumbbell#define CP_INT_STATUS 0xc128 802254885Sdumbbell# define SCRATCH_INT_STAT (1 << 25) 803254885Sdumbbell# define TIME_STAMP_INT_STAT (1 << 26) 804254885Sdumbbell# define IB2_INT_STAT (1 << 29) 805254885Sdumbbell# define IB1_INT_STAT (1 << 30) 806258780Seadler# define RB_INT_STAT (1U << 31) 807254885Sdumbbell 808254885Sdumbbell#define GRBM_INT_CNTL 0x8060 809254885Sdumbbell# define RDERR_INT_ENABLE (1 << 0) 810254885Sdumbbell# define GUI_IDLE_INT_ENABLE (1 << 19) 811254885Sdumbbell 812254885Sdumbbell/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 813254885Sdumbbell#define CRTC_STATUS_FRAME_COUNT 0x6e98 814254885Sdumbbell 815254885Sdumbbell/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ 816254885Sdumbbell#define VLINE_STATUS 0x6bb8 817254885Sdumbbell# define VLINE_OCCURRED (1 << 0) 818254885Sdumbbell# define VLINE_ACK (1 << 4) 819254885Sdumbbell# define VLINE_STAT (1 << 12) 820254885Sdumbbell# define VLINE_INTERRUPT (1 << 16) 821254885Sdumbbell# define VLINE_INTERRUPT_TYPE (1 << 17) 822254885Sdumbbell/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ 823254885Sdumbbell#define VBLANK_STATUS 0x6bbc 824254885Sdumbbell# define VBLANK_OCCURRED (1 << 0) 825254885Sdumbbell# define VBLANK_ACK (1 << 4) 826254885Sdumbbell# define VBLANK_STAT (1 << 12) 827254885Sdumbbell# define VBLANK_INTERRUPT (1 << 16) 828254885Sdumbbell# define VBLANK_INTERRUPT_TYPE (1 << 17) 829254885Sdumbbell 830254885Sdumbbell/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ 831254885Sdumbbell#define INT_MASK 0x6b40 832254885Sdumbbell# define VBLANK_INT_MASK (1 << 0) 833254885Sdumbbell# define VLINE_INT_MASK (1 << 4) 834254885Sdumbbell 835254885Sdumbbell#define DISP_INTERRUPT_STATUS 0x60f4 836254885Sdumbbell# define LB_D1_VLINE_INTERRUPT (1 << 2) 837254885Sdumbbell# define LB_D1_VBLANK_INTERRUPT (1 << 3) 838254885Sdumbbell# define DC_HPD1_INTERRUPT (1 << 17) 839254885Sdumbbell# define DC_HPD1_RX_INTERRUPT (1 << 18) 840254885Sdumbbell# define DACA_AUTODETECT_INTERRUPT (1 << 22) 841254885Sdumbbell# define DACB_AUTODETECT_INTERRUPT (1 << 23) 842254885Sdumbbell# define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 843254885Sdumbbell# define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 844254885Sdumbbell#define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 845254885Sdumbbell# define LB_D2_VLINE_INTERRUPT (1 << 2) 846254885Sdumbbell# define LB_D2_VBLANK_INTERRUPT (1 << 3) 847254885Sdumbbell# define DC_HPD2_INTERRUPT (1 << 17) 848254885Sdumbbell# define DC_HPD2_RX_INTERRUPT (1 << 18) 849254885Sdumbbell# define DISP_TIMER_INTERRUPT (1 << 24) 850254885Sdumbbell#define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 851254885Sdumbbell# define LB_D3_VLINE_INTERRUPT (1 << 2) 852254885Sdumbbell# define LB_D3_VBLANK_INTERRUPT (1 << 3) 853254885Sdumbbell# define DC_HPD3_INTERRUPT (1 << 17) 854254885Sdumbbell# define DC_HPD3_RX_INTERRUPT (1 << 18) 855254885Sdumbbell#define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 856254885Sdumbbell# define LB_D4_VLINE_INTERRUPT (1 << 2) 857254885Sdumbbell# define LB_D4_VBLANK_INTERRUPT (1 << 3) 858254885Sdumbbell# define DC_HPD4_INTERRUPT (1 << 17) 859254885Sdumbbell# define DC_HPD4_RX_INTERRUPT (1 << 18) 860254885Sdumbbell#define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 861254885Sdumbbell# define LB_D5_VLINE_INTERRUPT (1 << 2) 862254885Sdumbbell# define LB_D5_VBLANK_INTERRUPT (1 << 3) 863254885Sdumbbell# define DC_HPD5_INTERRUPT (1 << 17) 864254885Sdumbbell# define DC_HPD5_RX_INTERRUPT (1 << 18) 865254885Sdumbbell#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 866254885Sdumbbell# define LB_D6_VLINE_INTERRUPT (1 << 2) 867254885Sdumbbell# define LB_D6_VBLANK_INTERRUPT (1 << 3) 868254885Sdumbbell# define DC_HPD6_INTERRUPT (1 << 17) 869254885Sdumbbell# define DC_HPD6_RX_INTERRUPT (1 << 18) 870254885Sdumbbell 871254885Sdumbbell/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 872254885Sdumbbell#define GRPH_INT_STATUS 0x6858 873254885Sdumbbell# define GRPH_PFLIP_INT_OCCURRED (1 << 0) 874254885Sdumbbell# define GRPH_PFLIP_INT_CLEAR (1 << 8) 875254885Sdumbbell/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 876254885Sdumbbell#define GRPH_INT_CONTROL 0x685c 877254885Sdumbbell# define GRPH_PFLIP_INT_MASK (1 << 0) 878254885Sdumbbell# define GRPH_PFLIP_INT_TYPE (1 << 8) 879254885Sdumbbell 880254885Sdumbbell#define DACA_AUTODETECT_INT_CONTROL 0x66c8 881254885Sdumbbell#define DACB_AUTODETECT_INT_CONTROL 0x67c8 882254885Sdumbbell 883254885Sdumbbell#define DC_HPD1_INT_STATUS 0x601c 884254885Sdumbbell#define DC_HPD2_INT_STATUS 0x6028 885254885Sdumbbell#define DC_HPD3_INT_STATUS 0x6034 886254885Sdumbbell#define DC_HPD4_INT_STATUS 0x6040 887254885Sdumbbell#define DC_HPD5_INT_STATUS 0x604c 888254885Sdumbbell#define DC_HPD6_INT_STATUS 0x6058 889254885Sdumbbell# define DC_HPDx_INT_STATUS (1 << 0) 890254885Sdumbbell# define DC_HPDx_SENSE (1 << 1) 891254885Sdumbbell# define DC_HPDx_RX_INT_STATUS (1 << 8) 892254885Sdumbbell 893254885Sdumbbell#define DC_HPD1_INT_CONTROL 0x6020 894254885Sdumbbell#define DC_HPD2_INT_CONTROL 0x602c 895254885Sdumbbell#define DC_HPD3_INT_CONTROL 0x6038 896254885Sdumbbell#define DC_HPD4_INT_CONTROL 0x6044 897254885Sdumbbell#define DC_HPD5_INT_CONTROL 0x6050 898254885Sdumbbell#define DC_HPD6_INT_CONTROL 0x605c 899254885Sdumbbell# define DC_HPDx_INT_ACK (1 << 0) 900254885Sdumbbell# define DC_HPDx_INT_POLARITY (1 << 8) 901254885Sdumbbell# define DC_HPDx_INT_EN (1 << 16) 902254885Sdumbbell# define DC_HPDx_RX_INT_ACK (1 << 20) 903254885Sdumbbell# define DC_HPDx_RX_INT_EN (1 << 24) 904254885Sdumbbell 905254885Sdumbbell#define DC_HPD1_CONTROL 0x6024 906254885Sdumbbell#define DC_HPD2_CONTROL 0x6030 907254885Sdumbbell#define DC_HPD3_CONTROL 0x603c 908254885Sdumbbell#define DC_HPD4_CONTROL 0x6048 909254885Sdumbbell#define DC_HPD5_CONTROL 0x6054 910254885Sdumbbell#define DC_HPD6_CONTROL 0x6060 911254885Sdumbbell# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 912254885Sdumbbell# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 913254885Sdumbbell# define DC_HPDx_EN (1 << 28) 914254885Sdumbbell 915254885Sdumbbell/* ASYNC DMA */ 916254885Sdumbbell#define DMA_RB_RPTR 0xd008 917254885Sdumbbell#define DMA_RB_WPTR 0xd00c 918254885Sdumbbell 919254885Sdumbbell#define DMA_CNTL 0xd02c 920254885Sdumbbell# define TRAP_ENABLE (1 << 0) 921254885Sdumbbell# define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 922254885Sdumbbell# define SEM_WAIT_INT_ENABLE (1 << 2) 923254885Sdumbbell# define DATA_SWAP_ENABLE (1 << 3) 924254885Sdumbbell# define FENCE_SWAP_ENABLE (1 << 4) 925254885Sdumbbell# define CTXEMPTY_INT_ENABLE (1 << 28) 926254885Sdumbbell#define DMA_TILING_CONFIG 0xD0B8 927254885Sdumbbell 928254885Sdumbbell#define CAYMAN_DMA1_CNTL 0xd82c 929254885Sdumbbell 930254885Sdumbbell/* async DMA packets */ 931254885Sdumbbell#define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ 932254885Sdumbbell (((t) & 0x1) << 23) | \ 933254885Sdumbbell (((s) & 0x1) << 22) | \ 934254885Sdumbbell (((n) & 0xFFFFF) << 0)) 935254885Sdumbbell/* async DMA Packet types */ 936254885Sdumbbell#define DMA_PACKET_WRITE 0x2 937254885Sdumbbell#define DMA_PACKET_COPY 0x3 938254885Sdumbbell#define DMA_PACKET_INDIRECT_BUFFER 0x4 939254885Sdumbbell#define DMA_PACKET_SEMAPHORE 0x5 940254885Sdumbbell#define DMA_PACKET_FENCE 0x6 941254885Sdumbbell#define DMA_PACKET_TRAP 0x7 942254885Sdumbbell#define DMA_PACKET_SRBM_WRITE 0x9 943254885Sdumbbell#define DMA_PACKET_CONSTANT_FILL 0xd 944254885Sdumbbell#define DMA_PACKET_NOP 0xf 945254885Sdumbbell 946254885Sdumbbell/* PCIE link stuff */ 947254885Sdumbbell#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 948254885Sdumbbell#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 949254885Sdumbbell# define LC_LINK_WIDTH_SHIFT 0 950254885Sdumbbell# define LC_LINK_WIDTH_MASK 0x7 951254885Sdumbbell# define LC_LINK_WIDTH_X0 0 952254885Sdumbbell# define LC_LINK_WIDTH_X1 1 953254885Sdumbbell# define LC_LINK_WIDTH_X2 2 954254885Sdumbbell# define LC_LINK_WIDTH_X4 3 955254885Sdumbbell# define LC_LINK_WIDTH_X8 4 956254885Sdumbbell# define LC_LINK_WIDTH_X16 6 957254885Sdumbbell# define LC_LINK_WIDTH_RD_SHIFT 4 958254885Sdumbbell# define LC_LINK_WIDTH_RD_MASK 0x70 959254885Sdumbbell# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 960254885Sdumbbell# define LC_RECONFIG_NOW (1 << 8) 961254885Sdumbbell# define LC_RENEGOTIATION_SUPPORT (1 << 9) 962254885Sdumbbell# define LC_RENEGOTIATE_EN (1 << 10) 963254885Sdumbbell# define LC_SHORT_RECONFIG_EN (1 << 11) 964254885Sdumbbell# define LC_UPCONFIGURE_SUPPORT (1 << 12) 965254885Sdumbbell# define LC_UPCONFIGURE_DIS (1 << 13) 966254885Sdumbbell#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 967254885Sdumbbell# define LC_GEN2_EN_STRAP (1 << 0) 968254885Sdumbbell# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 969254885Sdumbbell# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 970254885Sdumbbell# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 971254885Sdumbbell# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 972254885Sdumbbell# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 973254885Sdumbbell# define LC_CURRENT_DATA_RATE (1 << 11) 974254885Sdumbbell# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 975254885Sdumbbell# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 976254885Sdumbbell# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 977254885Sdumbbell# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 978254885Sdumbbell#define MM_CFGREGS_CNTL 0x544c 979254885Sdumbbell# define MM_WR_TO_CFG_EN (1 << 3) 980254885Sdumbbell#define LINK_CNTL2 0x88 /* F0 */ 981254885Sdumbbell# define TARGET_LINK_SPEED_MASK (0xf << 0) 982254885Sdumbbell# define SELECTABLE_DEEMPHASIS (1 << 6) 983254885Sdumbbell 984254885Sdumbbell/* 985254885Sdumbbell * PM4 986254885Sdumbbell */ 987254885Sdumbbell#define PACKET_TYPE0 0 988254885Sdumbbell#define PACKET_TYPE1 1 989254885Sdumbbell#define PACKET_TYPE2 2 990254885Sdumbbell#define PACKET_TYPE3 3 991254885Sdumbbell 992254885Sdumbbell#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 993254885Sdumbbell#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 994254885Sdumbbell#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 995254885Sdumbbell#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 996254885Sdumbbell#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 997254885Sdumbbell (((reg) >> 2) & 0xFFFF) | \ 998254885Sdumbbell ((n) & 0x3FFF) << 16) 999254885Sdumbbell#define CP_PACKET2 0x80000000 1000254885Sdumbbell#define PACKET2_PAD_SHIFT 0 1001254885Sdumbbell#define PACKET2_PAD_MASK (0x3fffffff << 0) 1002254885Sdumbbell 1003254885Sdumbbell#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 1004254885Sdumbbell 1005254885Sdumbbell#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 1006254885Sdumbbell (((op) & 0xFF) << 8) | \ 1007254885Sdumbbell ((n) & 0x3FFF) << 16) 1008254885Sdumbbell 1009254885Sdumbbell/* Packet 3 types */ 1010254885Sdumbbell#define PACKET3_NOP 0x10 1011254885Sdumbbell#define PACKET3_SET_BASE 0x11 1012254885Sdumbbell#define PACKET3_CLEAR_STATE 0x12 1013254885Sdumbbell#define PACKET3_INDEX_BUFFER_SIZE 0x13 1014254885Sdumbbell#define PACKET3_DISPATCH_DIRECT 0x15 1015254885Sdumbbell#define PACKET3_DISPATCH_INDIRECT 0x16 1016254885Sdumbbell#define PACKET3_INDIRECT_BUFFER_END 0x17 1017254885Sdumbbell#define PACKET3_MODE_CONTROL 0x18 1018254885Sdumbbell#define PACKET3_SET_PREDICATION 0x20 1019254885Sdumbbell#define PACKET3_REG_RMW 0x21 1020254885Sdumbbell#define PACKET3_COND_EXEC 0x22 1021254885Sdumbbell#define PACKET3_PRED_EXEC 0x23 1022254885Sdumbbell#define PACKET3_DRAW_INDIRECT 0x24 1023254885Sdumbbell#define PACKET3_DRAW_INDEX_INDIRECT 0x25 1024254885Sdumbbell#define PACKET3_INDEX_BASE 0x26 1025254885Sdumbbell#define PACKET3_DRAW_INDEX_2 0x27 1026254885Sdumbbell#define PACKET3_CONTEXT_CONTROL 0x28 1027254885Sdumbbell#define PACKET3_DRAW_INDEX_OFFSET 0x29 1028254885Sdumbbell#define PACKET3_INDEX_TYPE 0x2A 1029254885Sdumbbell#define PACKET3_DRAW_INDEX 0x2B 1030254885Sdumbbell#define PACKET3_DRAW_INDEX_AUTO 0x2D 1031254885Sdumbbell#define PACKET3_DRAW_INDEX_IMMD 0x2E 1032254885Sdumbbell#define PACKET3_NUM_INSTANCES 0x2F 1033254885Sdumbbell#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 1034254885Sdumbbell#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1035254885Sdumbbell#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 1036254885Sdumbbell#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 1037254885Sdumbbell#define PACKET3_MEM_SEMAPHORE 0x39 1038254885Sdumbbell#define PACKET3_MPEG_INDEX 0x3A 1039254885Sdumbbell#define PACKET3_COPY_DW 0x3B 1040254885Sdumbbell#define PACKET3_WAIT_REG_MEM 0x3C 1041254885Sdumbbell#define PACKET3_MEM_WRITE 0x3D 1042254885Sdumbbell#define PACKET3_INDIRECT_BUFFER 0x32 1043254885Sdumbbell#define PACKET3_CP_DMA 0x41 1044254885Sdumbbell/* 1. header 1045254885Sdumbbell * 2. SRC_ADDR_LO or DATA [31:0] 1046254885Sdumbbell * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | 1047254885Sdumbbell * SRC_ADDR_HI [7:0] 1048254885Sdumbbell * 4. DST_ADDR_LO [31:0] 1049254885Sdumbbell * 5. DST_ADDR_HI [7:0] 1050254885Sdumbbell * 6. COMMAND [29:22] | BYTE_COUNT [20:0] 1051254885Sdumbbell */ 1052254885Sdumbbell# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 1053254885Sdumbbell /* 0 - SRC_ADDR 1054254885Sdumbbell * 1 - GDS 1055254885Sdumbbell */ 1056254885Sdumbbell# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) 1057254885Sdumbbell /* 0 - ME 1058254885Sdumbbell * 1 - PFP 1059254885Sdumbbell */ 1060254885Sdumbbell# define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) 1061254885Sdumbbell /* 0 - SRC_ADDR 1062254885Sdumbbell * 1 - GDS 1063254885Sdumbbell * 2 - DATA 1064254885Sdumbbell */ 1065258780Seadler# define PACKET3_CP_DMA_CP_SYNC (1U << 31) 1066254885Sdumbbell/* COMMAND */ 1067254885Sdumbbell# define PACKET3_CP_DMA_DIS_WC (1 << 21) 1068254885Sdumbbell# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) 1069254885Sdumbbell /* 0 - none 1070254885Sdumbbell * 1 - 8 in 16 1071254885Sdumbbell * 2 - 8 in 32 1072254885Sdumbbell * 3 - 8 in 64 1073254885Sdumbbell */ 1074254885Sdumbbell# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 1075254885Sdumbbell /* 0 - none 1076254885Sdumbbell * 1 - 8 in 16 1077254885Sdumbbell * 2 - 8 in 32 1078254885Sdumbbell * 3 - 8 in 64 1079254885Sdumbbell */ 1080254885Sdumbbell# define PACKET3_CP_DMA_CMD_SAS (1 << 26) 1081254885Sdumbbell /* 0 - memory 1082254885Sdumbbell * 1 - register 1083254885Sdumbbell */ 1084254885Sdumbbell# define PACKET3_CP_DMA_CMD_DAS (1 << 27) 1085254885Sdumbbell /* 0 - memory 1086254885Sdumbbell * 1 - register 1087254885Sdumbbell */ 1088254885Sdumbbell# define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 1089254885Sdumbbell# define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 1090254885Sdumbbell#define PACKET3_SURFACE_SYNC 0x43 1091254885Sdumbbell# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1092254885Sdumbbell# define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 1093254885Sdumbbell# define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 1094254885Sdumbbell# define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 1095254885Sdumbbell# define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 1096254885Sdumbbell# define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 1097254885Sdumbbell# define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 1098254885Sdumbbell# define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 1099254885Sdumbbell# define PACKET3_DB_DEST_BASE_ENA (1 << 14) 1100254885Sdumbbell# define PACKET3_CB8_DEST_BASE_ENA (1 << 15) 1101254885Sdumbbell# define PACKET3_CB9_DEST_BASE_ENA (1 << 16) 1102254885Sdumbbell# define PACKET3_CB10_DEST_BASE_ENA (1 << 17) 1103254885Sdumbbell# define PACKET3_CB11_DEST_BASE_ENA (1 << 18) 1104254885Sdumbbell# define PACKET3_FULL_CACHE_ENA (1 << 20) 1105254885Sdumbbell# define PACKET3_TC_ACTION_ENA (1 << 23) 1106254885Sdumbbell# define PACKET3_VC_ACTION_ENA (1 << 24) 1107254885Sdumbbell# define PACKET3_CB_ACTION_ENA (1 << 25) 1108254885Sdumbbell# define PACKET3_DB_ACTION_ENA (1 << 26) 1109254885Sdumbbell# define PACKET3_SH_ACTION_ENA (1 << 27) 1110254885Sdumbbell# define PACKET3_SX_ACTION_ENA (1 << 28) 1111254885Sdumbbell#define PACKET3_ME_INITIALIZE 0x44 1112254885Sdumbbell#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1113254885Sdumbbell#define PACKET3_COND_WRITE 0x45 1114254885Sdumbbell#define PACKET3_EVENT_WRITE 0x46 1115254885Sdumbbell#define PACKET3_EVENT_WRITE_EOP 0x47 1116254885Sdumbbell#define PACKET3_EVENT_WRITE_EOS 0x48 1117254885Sdumbbell#define PACKET3_PREAMBLE_CNTL 0x4A 1118254885Sdumbbell# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 1119254885Sdumbbell# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 1120254885Sdumbbell#define PACKET3_RB_OFFSET 0x4B 1121254885Sdumbbell#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C 1122254885Sdumbbell#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D 1123254885Sdumbbell#define PACKET3_ALU_PS_CONST_UPDATE 0x4E 1124254885Sdumbbell#define PACKET3_ALU_VS_CONST_UPDATE 0x4F 1125254885Sdumbbell#define PACKET3_ONE_REG_WRITE 0x57 1126254885Sdumbbell#define PACKET3_SET_CONFIG_REG 0x68 1127254885Sdumbbell#define PACKET3_SET_CONFIG_REG_START 0x00008000 1128254885Sdumbbell#define PACKET3_SET_CONFIG_REG_END 0x0000ac00 1129254885Sdumbbell#define PACKET3_SET_CONTEXT_REG 0x69 1130254885Sdumbbell#define PACKET3_SET_CONTEXT_REG_START 0x00028000 1131254885Sdumbbell#define PACKET3_SET_CONTEXT_REG_END 0x00029000 1132254885Sdumbbell#define PACKET3_SET_ALU_CONST 0x6A 1133254885Sdumbbell/* alu const buffers only; no reg file */ 1134254885Sdumbbell#define PACKET3_SET_BOOL_CONST 0x6B 1135254885Sdumbbell#define PACKET3_SET_BOOL_CONST_START 0x0003a500 1136254885Sdumbbell#define PACKET3_SET_BOOL_CONST_END 0x0003a518 1137254885Sdumbbell#define PACKET3_SET_LOOP_CONST 0x6C 1138254885Sdumbbell#define PACKET3_SET_LOOP_CONST_START 0x0003a200 1139254885Sdumbbell#define PACKET3_SET_LOOP_CONST_END 0x0003a500 1140254885Sdumbbell#define PACKET3_SET_RESOURCE 0x6D 1141254885Sdumbbell#define PACKET3_SET_RESOURCE_START 0x00030000 1142254885Sdumbbell#define PACKET3_SET_RESOURCE_END 0x00038000 1143254885Sdumbbell#define PACKET3_SET_SAMPLER 0x6E 1144254885Sdumbbell#define PACKET3_SET_SAMPLER_START 0x0003c000 1145254885Sdumbbell#define PACKET3_SET_SAMPLER_END 0x0003c600 1146254885Sdumbbell#define PACKET3_SET_CTL_CONST 0x6F 1147254885Sdumbbell#define PACKET3_SET_CTL_CONST_START 0x0003cff0 1148254885Sdumbbell#define PACKET3_SET_CTL_CONST_END 0x0003ff0c 1149254885Sdumbbell#define PACKET3_SET_RESOURCE_OFFSET 0x70 1150254885Sdumbbell#define PACKET3_SET_ALU_CONST_VS 0x71 1151254885Sdumbbell#define PACKET3_SET_ALU_CONST_DI 0x72 1152254885Sdumbbell#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 1153254885Sdumbbell#define PACKET3_SET_RESOURCE_INDIRECT 0x74 1154254885Sdumbbell#define PACKET3_SET_APPEND_CNT 0x75 1155254885Sdumbbell 1156254885Sdumbbell#define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c 1157254885Sdumbbell#define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30) 1158254885Sdumbbell#define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3) 1159254885Sdumbbell#define SQ_TEX_VTX_INVALID_TEXTURE 0x0 1160254885Sdumbbell#define SQ_TEX_VTX_INVALID_BUFFER 0x1 1161254885Sdumbbell#define SQ_TEX_VTX_VALID_TEXTURE 0x2 1162254885Sdumbbell#define SQ_TEX_VTX_VALID_BUFFER 0x3 1163254885Sdumbbell 1164254885Sdumbbell#define VGT_VTX_VECT_EJECT_REG 0x88b0 1165254885Sdumbbell 1166254885Sdumbbell#define SQ_CONST_MEM_BASE 0x8df8 1167254885Sdumbbell 1168254885Sdumbbell#define SQ_ESGS_RING_BASE 0x8c40 1169254885Sdumbbell#define SQ_ESGS_RING_SIZE 0x8c44 1170254885Sdumbbell#define SQ_GSVS_RING_BASE 0x8c48 1171254885Sdumbbell#define SQ_GSVS_RING_SIZE 0x8c4c 1172254885Sdumbbell#define SQ_ESTMP_RING_BASE 0x8c50 1173254885Sdumbbell#define SQ_ESTMP_RING_SIZE 0x8c54 1174254885Sdumbbell#define SQ_GSTMP_RING_BASE 0x8c58 1175254885Sdumbbell#define SQ_GSTMP_RING_SIZE 0x8c5c 1176254885Sdumbbell#define SQ_VSTMP_RING_BASE 0x8c60 1177254885Sdumbbell#define SQ_VSTMP_RING_SIZE 0x8c64 1178254885Sdumbbell#define SQ_PSTMP_RING_BASE 0x8c68 1179254885Sdumbbell#define SQ_PSTMP_RING_SIZE 0x8c6c 1180254885Sdumbbell#define SQ_LSTMP_RING_BASE 0x8e10 1181254885Sdumbbell#define SQ_LSTMP_RING_SIZE 0x8e14 1182254885Sdumbbell#define SQ_HSTMP_RING_BASE 0x8e18 1183254885Sdumbbell#define SQ_HSTMP_RING_SIZE 0x8e1c 1184254885Sdumbbell#define VGT_TF_RING_SIZE 0x8988 1185254885Sdumbbell 1186254885Sdumbbell#define SQ_ESGS_RING_ITEMSIZE 0x28900 1187254885Sdumbbell#define SQ_GSVS_RING_ITEMSIZE 0x28904 1188254885Sdumbbell#define SQ_ESTMP_RING_ITEMSIZE 0x28908 1189254885Sdumbbell#define SQ_GSTMP_RING_ITEMSIZE 0x2890c 1190254885Sdumbbell#define SQ_VSTMP_RING_ITEMSIZE 0x28910 1191254885Sdumbbell#define SQ_PSTMP_RING_ITEMSIZE 0x28914 1192254885Sdumbbell#define SQ_LSTMP_RING_ITEMSIZE 0x28830 1193254885Sdumbbell#define SQ_HSTMP_RING_ITEMSIZE 0x28834 1194254885Sdumbbell 1195254885Sdumbbell#define SQ_GS_VERT_ITEMSIZE 0x2891c 1196254885Sdumbbell#define SQ_GS_VERT_ITEMSIZE_1 0x28920 1197254885Sdumbbell#define SQ_GS_VERT_ITEMSIZE_2 0x28924 1198254885Sdumbbell#define SQ_GS_VERT_ITEMSIZE_3 0x28928 1199254885Sdumbbell#define SQ_GSVS_RING_OFFSET_1 0x2892c 1200254885Sdumbbell#define SQ_GSVS_RING_OFFSET_2 0x28930 1201254885Sdumbbell#define SQ_GSVS_RING_OFFSET_3 0x28934 1202254885Sdumbbell 1203254885Sdumbbell#define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140 1204254885Sdumbbell#define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80 1205254885Sdumbbell 1206254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_0 0x28940 1207254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_1 0x28944 1208254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_2 0x28948 1209254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_3 0x2894c 1210254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_4 0x28950 1211254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_5 0x28954 1212254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_6 0x28958 1213254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_7 0x2895c 1214254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_8 0x28960 1215254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_9 0x28964 1216254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_10 0x28968 1217254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_11 0x2896c 1218254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_12 0x28970 1219254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_13 0x28974 1220254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_14 0x28978 1221254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_15 0x2897c 1222254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_0 0x28980 1223254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_1 0x28984 1224254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_2 0x28988 1225254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_3 0x2898c 1226254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_4 0x28990 1227254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_5 0x28994 1228254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_6 0x28998 1229254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_7 0x2899c 1230254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_8 0x289a0 1231254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_9 0x289a4 1232254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_10 0x289a8 1233254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_11 0x289ac 1234254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_12 0x289b0 1235254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_13 0x289b4 1236254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_14 0x289b8 1237254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_15 0x289bc 1238254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_0 0x289c0 1239254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_1 0x289c4 1240254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_2 0x289c8 1241254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_3 0x289cc 1242254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_4 0x289d0 1243254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_5 0x289d4 1244254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_6 0x289d8 1245254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_7 0x289dc 1246254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_8 0x289e0 1247254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_9 0x289e4 1248254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_10 0x289e8 1249254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_11 0x289ec 1250254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_12 0x289f0 1251254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_13 0x289f4 1252254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_14 0x289f8 1253254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_15 0x289fc 1254254885Sdumbbell#define SQ_ALU_CONST_CACHE_HS_0 0x28f00 1255254885Sdumbbell#define SQ_ALU_CONST_CACHE_HS_1 0x28f04 1256254885Sdumbbell#define SQ_ALU_CONST_CACHE_HS_2 0x28f08 1257254885Sdumbbell#define SQ_ALU_CONST_CACHE_HS_3 0x28f0c 1258254885Sdumbbell#define SQ_ALU_CONST_CACHE_HS_4 0x28f10 1259254885Sdumbbell#define SQ_ALU_CONST_CACHE_HS_5 0x28f14 1260254885Sdumbbell#define SQ_ALU_CONST_CACHE_HS_6 0x28f18 1261254885Sdumbbell#define SQ_ALU_CONST_CACHE_HS_7 0x28f1c 1262254885Sdumbbell#define SQ_ALU_CONST_CACHE_HS_8 0x28f20 1263254885Sdumbbell#define SQ_ALU_CONST_CACHE_HS_9 0x28f24 1264254885Sdumbbell#define SQ_ALU_CONST_CACHE_HS_10 0x28f28 1265254885Sdumbbell#define SQ_ALU_CONST_CACHE_HS_11 0x28f2c 1266254885Sdumbbell#define SQ_ALU_CONST_CACHE_HS_12 0x28f30 1267254885Sdumbbell#define SQ_ALU_CONST_CACHE_HS_13 0x28f34 1268254885Sdumbbell#define SQ_ALU_CONST_CACHE_HS_14 0x28f38 1269254885Sdumbbell#define SQ_ALU_CONST_CACHE_HS_15 0x28f3c 1270254885Sdumbbell#define SQ_ALU_CONST_CACHE_LS_0 0x28f40 1271254885Sdumbbell#define SQ_ALU_CONST_CACHE_LS_1 0x28f44 1272254885Sdumbbell#define SQ_ALU_CONST_CACHE_LS_2 0x28f48 1273254885Sdumbbell#define SQ_ALU_CONST_CACHE_LS_3 0x28f4c 1274254885Sdumbbell#define SQ_ALU_CONST_CACHE_LS_4 0x28f50 1275254885Sdumbbell#define SQ_ALU_CONST_CACHE_LS_5 0x28f54 1276254885Sdumbbell#define SQ_ALU_CONST_CACHE_LS_6 0x28f58 1277254885Sdumbbell#define SQ_ALU_CONST_CACHE_LS_7 0x28f5c 1278254885Sdumbbell#define SQ_ALU_CONST_CACHE_LS_8 0x28f60 1279254885Sdumbbell#define SQ_ALU_CONST_CACHE_LS_9 0x28f64 1280254885Sdumbbell#define SQ_ALU_CONST_CACHE_LS_10 0x28f68 1281254885Sdumbbell#define SQ_ALU_CONST_CACHE_LS_11 0x28f6c 1282254885Sdumbbell#define SQ_ALU_CONST_CACHE_LS_12 0x28f70 1283254885Sdumbbell#define SQ_ALU_CONST_CACHE_LS_13 0x28f74 1284254885Sdumbbell#define SQ_ALU_CONST_CACHE_LS_14 0x28f78 1285254885Sdumbbell#define SQ_ALU_CONST_CACHE_LS_15 0x28f7c 1286254885Sdumbbell 1287254885Sdumbbell#define PA_SC_SCREEN_SCISSOR_TL 0x28030 1288254885Sdumbbell#define PA_SC_GENERIC_SCISSOR_TL 0x28240 1289254885Sdumbbell#define PA_SC_WINDOW_SCISSOR_TL 0x28204 1290254885Sdumbbell 1291254885Sdumbbell#define VGT_PRIMITIVE_TYPE 0x8958 1292254885Sdumbbell#define VGT_INDEX_TYPE 0x895C 1293254885Sdumbbell 1294254885Sdumbbell#define VGT_NUM_INDICES 0x8970 1295254885Sdumbbell 1296254885Sdumbbell#define VGT_COMPUTE_DIM_X 0x8990 1297254885Sdumbbell#define VGT_COMPUTE_DIM_Y 0x8994 1298254885Sdumbbell#define VGT_COMPUTE_DIM_Z 0x8998 1299254885Sdumbbell#define VGT_COMPUTE_START_X 0x899C 1300254885Sdumbbell#define VGT_COMPUTE_START_Y 0x89A0 1301254885Sdumbbell#define VGT_COMPUTE_START_Z 0x89A4 1302254885Sdumbbell#define VGT_COMPUTE_INDEX 0x89A8 1303254885Sdumbbell#define VGT_COMPUTE_THREAD_GROUP_SIZE 0x89AC 1304254885Sdumbbell#define VGT_HS_OFFCHIP_PARAM 0x89B0 1305254885Sdumbbell 1306254885Sdumbbell#define DB_DEBUG 0x9830 1307254885Sdumbbell#define DB_DEBUG2 0x9834 1308254885Sdumbbell#define DB_DEBUG3 0x9838 1309254885Sdumbbell#define DB_DEBUG4 0x983C 1310254885Sdumbbell#define DB_WATERMARKS 0x9854 1311254885Sdumbbell#define DB_DEPTH_CONTROL 0x28800 1312254885Sdumbbell#define R_028800_DB_DEPTH_CONTROL 0x028800 1313254885Sdumbbell#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) 1314254885Sdumbbell#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) 1315254885Sdumbbell#define C_028800_STENCIL_ENABLE 0xFFFFFFFE 1316254885Sdumbbell#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) 1317254885Sdumbbell#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) 1318254885Sdumbbell#define C_028800_Z_ENABLE 0xFFFFFFFD 1319254885Sdumbbell#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) 1320254885Sdumbbell#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) 1321254885Sdumbbell#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB 1322254885Sdumbbell#define S_028800_ZFUNC(x) (((x) & 0x7) << 4) 1323254885Sdumbbell#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) 1324254885Sdumbbell#define C_028800_ZFUNC 0xFFFFFF8F 1325254885Sdumbbell#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) 1326254885Sdumbbell#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) 1327254885Sdumbbell#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F 1328254885Sdumbbell#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) 1329254885Sdumbbell#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) 1330254885Sdumbbell#define C_028800_STENCILFUNC 0xFFFFF8FF 1331254885Sdumbbell#define V_028800_STENCILFUNC_NEVER 0x00000000 1332254885Sdumbbell#define V_028800_STENCILFUNC_LESS 0x00000001 1333254885Sdumbbell#define V_028800_STENCILFUNC_EQUAL 0x00000002 1334254885Sdumbbell#define V_028800_STENCILFUNC_LEQUAL 0x00000003 1335254885Sdumbbell#define V_028800_STENCILFUNC_GREATER 0x00000004 1336254885Sdumbbell#define V_028800_STENCILFUNC_NOTEQUAL 0x00000005 1337254885Sdumbbell#define V_028800_STENCILFUNC_GEQUAL 0x00000006 1338254885Sdumbbell#define V_028800_STENCILFUNC_ALWAYS 0x00000007 1339254885Sdumbbell#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) 1340254885Sdumbbell#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) 1341254885Sdumbbell#define C_028800_STENCILFAIL 0xFFFFC7FF 1342254885Sdumbbell#define V_028800_STENCIL_KEEP 0x00000000 1343254885Sdumbbell#define V_028800_STENCIL_ZERO 0x00000001 1344254885Sdumbbell#define V_028800_STENCIL_REPLACE 0x00000002 1345254885Sdumbbell#define V_028800_STENCIL_INCR 0x00000003 1346254885Sdumbbell#define V_028800_STENCIL_DECR 0x00000004 1347254885Sdumbbell#define V_028800_STENCIL_INVERT 0x00000005 1348254885Sdumbbell#define V_028800_STENCIL_INCR_WRAP 0x00000006 1349254885Sdumbbell#define V_028800_STENCIL_DECR_WRAP 0x00000007 1350254885Sdumbbell#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) 1351254885Sdumbbell#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) 1352254885Sdumbbell#define C_028800_STENCILZPASS 0xFFFE3FFF 1353254885Sdumbbell#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) 1354254885Sdumbbell#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) 1355254885Sdumbbell#define C_028800_STENCILZFAIL 0xFFF1FFFF 1356254885Sdumbbell#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) 1357254885Sdumbbell#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) 1358254885Sdumbbell#define C_028800_STENCILFUNC_BF 0xFF8FFFFF 1359254885Sdumbbell#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) 1360254885Sdumbbell#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) 1361254885Sdumbbell#define C_028800_STENCILFAIL_BF 0xFC7FFFFF 1362254885Sdumbbell#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) 1363254885Sdumbbell#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) 1364254885Sdumbbell#define C_028800_STENCILZPASS_BF 0xE3FFFFFF 1365254885Sdumbbell#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) 1366254885Sdumbbell#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) 1367254885Sdumbbell#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF 1368254885Sdumbbell#define DB_DEPTH_VIEW 0x28008 1369254885Sdumbbell#define R_028008_DB_DEPTH_VIEW 0x00028008 1370254885Sdumbbell#define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0) 1371254885Sdumbbell#define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF) 1372254885Sdumbbell#define C_028008_SLICE_START 0xFFFFF800 1373254885Sdumbbell#define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13) 1374254885Sdumbbell#define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 1375254885Sdumbbell#define C_028008_SLICE_MAX 0xFF001FFF 1376254885Sdumbbell#define DB_HTILE_DATA_BASE 0x28014 1377254885Sdumbbell#define DB_HTILE_SURFACE 0x28abc 1378254885Sdumbbell#define S_028ABC_HTILE_WIDTH(x) (((x) & 0x1) << 0) 1379254885Sdumbbell#define G_028ABC_HTILE_WIDTH(x) (((x) >> 0) & 0x1) 1380254885Sdumbbell#define C_028ABC_HTILE_WIDTH 0xFFFFFFFE 1381254885Sdumbbell#define S_028ABC_HTILE_HEIGHT(x) (((x) & 0x1) << 1) 1382254885Sdumbbell#define G_028ABC_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) 1383254885Sdumbbell#define C_028ABC_HTILE_HEIGHT 0xFFFFFFFD 1384254885Sdumbbell#define G_028ABC_LINEAR(x) (((x) >> 2) & 0x1) 1385254885Sdumbbell#define DB_Z_INFO 0x28040 1386254885Sdumbbell# define Z_ARRAY_MODE(x) ((x) << 4) 1387254885Sdumbbell# define DB_TILE_SPLIT(x) (((x) & 0x7) << 8) 1388254885Sdumbbell# define DB_NUM_BANKS(x) (((x) & 0x3) << 12) 1389254885Sdumbbell# define DB_BANK_WIDTH(x) (((x) & 0x3) << 16) 1390254885Sdumbbell# define DB_BANK_HEIGHT(x) (((x) & 0x3) << 20) 1391254885Sdumbbell# define DB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24) 1392254885Sdumbbell#define R_028040_DB_Z_INFO 0x028040 1393254885Sdumbbell#define S_028040_FORMAT(x) (((x) & 0x3) << 0) 1394254885Sdumbbell#define G_028040_FORMAT(x) (((x) >> 0) & 0x3) 1395254885Sdumbbell#define C_028040_FORMAT 0xFFFFFFFC 1396254885Sdumbbell#define V_028040_Z_INVALID 0x00000000 1397254885Sdumbbell#define V_028040_Z_16 0x00000001 1398254885Sdumbbell#define V_028040_Z_24 0x00000002 1399254885Sdumbbell#define V_028040_Z_32_FLOAT 0x00000003 1400254885Sdumbbell#define S_028040_ARRAY_MODE(x) (((x) & 0xF) << 4) 1401254885Sdumbbell#define G_028040_ARRAY_MODE(x) (((x) >> 4) & 0xF) 1402254885Sdumbbell#define C_028040_ARRAY_MODE 0xFFFFFF0F 1403254885Sdumbbell#define S_028040_READ_SIZE(x) (((x) & 0x1) << 28) 1404254885Sdumbbell#define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1) 1405254885Sdumbbell#define C_028040_READ_SIZE 0xEFFFFFFF 1406254885Sdumbbell#define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29) 1407254885Sdumbbell#define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1) 1408254885Sdumbbell#define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF 1409254885Sdumbbell#define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) 1410254885Sdumbbell#define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) 1411254885Sdumbbell#define C_028040_ZRANGE_PRECISION 0x7FFFFFFF 1412254885Sdumbbell#define S_028040_TILE_SPLIT(x) (((x) & 0x7) << 8) 1413254885Sdumbbell#define G_028040_TILE_SPLIT(x) (((x) >> 8) & 0x7) 1414254885Sdumbbell#define S_028040_NUM_BANKS(x) (((x) & 0x3) << 12) 1415254885Sdumbbell#define G_028040_NUM_BANKS(x) (((x) >> 12) & 0x3) 1416254885Sdumbbell#define S_028040_BANK_WIDTH(x) (((x) & 0x3) << 16) 1417254885Sdumbbell#define G_028040_BANK_WIDTH(x) (((x) >> 16) & 0x3) 1418254885Sdumbbell#define S_028040_BANK_HEIGHT(x) (((x) & 0x3) << 20) 1419254885Sdumbbell#define G_028040_BANK_HEIGHT(x) (((x) >> 20) & 0x3) 1420254885Sdumbbell#define S_028040_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24) 1421254885Sdumbbell#define G_028040_MACRO_TILE_ASPECT(x) (((x) >> 24) & 0x3) 1422254885Sdumbbell#define DB_STENCIL_INFO 0x28044 1423254885Sdumbbell#define R_028044_DB_STENCIL_INFO 0x028044 1424254885Sdumbbell#define S_028044_FORMAT(x) (((x) & 0x1) << 0) 1425254885Sdumbbell#define G_028044_FORMAT(x) (((x) >> 0) & 0x1) 1426254885Sdumbbell#define C_028044_FORMAT 0xFFFFFFFE 1427254885Sdumbbell#define V_028044_STENCIL_INVALID 0 1428254885Sdumbbell#define V_028044_STENCIL_8 1 1429254885Sdumbbell#define G_028044_TILE_SPLIT(x) (((x) >> 8) & 0x7) 1430254885Sdumbbell#define DB_Z_READ_BASE 0x28048 1431254885Sdumbbell#define DB_STENCIL_READ_BASE 0x2804c 1432254885Sdumbbell#define DB_Z_WRITE_BASE 0x28050 1433254885Sdumbbell#define DB_STENCIL_WRITE_BASE 0x28054 1434254885Sdumbbell#define DB_DEPTH_SIZE 0x28058 1435254885Sdumbbell#define R_028058_DB_DEPTH_SIZE 0x028058 1436254885Sdumbbell#define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0) 1437254885Sdumbbell#define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF) 1438254885Sdumbbell#define C_028058_PITCH_TILE_MAX 0xFFFFF800 1439254885Sdumbbell#define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11) 1440254885Sdumbbell#define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF) 1441254885Sdumbbell#define C_028058_HEIGHT_TILE_MAX 0xFFC007FF 1442254885Sdumbbell#define R_02805C_DB_DEPTH_SLICE 0x02805C 1443254885Sdumbbell#define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) 1444254885Sdumbbell#define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) 1445254885Sdumbbell#define C_02805C_SLICE_TILE_MAX 0xFFC00000 1446254885Sdumbbell 1447254885Sdumbbell#define SQ_PGM_START_PS 0x28840 1448254885Sdumbbell#define SQ_PGM_START_VS 0x2885c 1449254885Sdumbbell#define SQ_PGM_START_GS 0x28874 1450254885Sdumbbell#define SQ_PGM_START_ES 0x2888c 1451254885Sdumbbell#define SQ_PGM_START_FS 0x288a4 1452254885Sdumbbell#define SQ_PGM_START_HS 0x288b8 1453254885Sdumbbell#define SQ_PGM_START_LS 0x288d0 1454254885Sdumbbell 1455254885Sdumbbell#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 1456254885Sdumbbell#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 1457254885Sdumbbell#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 1458254885Sdumbbell#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 1459254885Sdumbbell#define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0 1460254885Sdumbbell#define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0 1461254885Sdumbbell#define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0 1462254885Sdumbbell#define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00 1463254885Sdumbbell#define VGT_STRMOUT_CONFIG 0x28b94 1464254885Sdumbbell#define VGT_STRMOUT_BUFFER_CONFIG 0x28b98 1465254885Sdumbbell 1466254885Sdumbbell#define CB_TARGET_MASK 0x28238 1467254885Sdumbbell#define CB_SHADER_MASK 0x2823c 1468254885Sdumbbell 1469254885Sdumbbell#define GDS_ADDR_BASE 0x28720 1470254885Sdumbbell 1471254885Sdumbbell#define CB_IMMED0_BASE 0x28b9c 1472254885Sdumbbell#define CB_IMMED1_BASE 0x28ba0 1473254885Sdumbbell#define CB_IMMED2_BASE 0x28ba4 1474254885Sdumbbell#define CB_IMMED3_BASE 0x28ba8 1475254885Sdumbbell#define CB_IMMED4_BASE 0x28bac 1476254885Sdumbbell#define CB_IMMED5_BASE 0x28bb0 1477254885Sdumbbell#define CB_IMMED6_BASE 0x28bb4 1478254885Sdumbbell#define CB_IMMED7_BASE 0x28bb8 1479254885Sdumbbell#define CB_IMMED8_BASE 0x28bbc 1480254885Sdumbbell#define CB_IMMED9_BASE 0x28bc0 1481254885Sdumbbell#define CB_IMMED10_BASE 0x28bc4 1482254885Sdumbbell#define CB_IMMED11_BASE 0x28bc8 1483254885Sdumbbell 1484254885Sdumbbell/* all 12 CB blocks have these regs */ 1485254885Sdumbbell#define CB_COLOR0_BASE 0x28c60 1486254885Sdumbbell#define CB_COLOR0_PITCH 0x28c64 1487254885Sdumbbell#define CB_COLOR0_SLICE 0x28c68 1488254885Sdumbbell#define CB_COLOR0_VIEW 0x28c6c 1489254885Sdumbbell#define R_028C6C_CB_COLOR0_VIEW 0x00028C6C 1490254885Sdumbbell#define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0) 1491254885Sdumbbell#define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF) 1492254885Sdumbbell#define C_028C6C_SLICE_START 0xFFFFF800 1493254885Sdumbbell#define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13) 1494254885Sdumbbell#define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 1495254885Sdumbbell#define C_028C6C_SLICE_MAX 0xFF001FFF 1496254885Sdumbbell#define R_028C70_CB_COLOR0_INFO 0x028C70 1497254885Sdumbbell#define S_028C70_ENDIAN(x) (((x) & 0x3) << 0) 1498254885Sdumbbell#define G_028C70_ENDIAN(x) (((x) >> 0) & 0x3) 1499254885Sdumbbell#define C_028C70_ENDIAN 0xFFFFFFFC 1500254885Sdumbbell#define S_028C70_FORMAT(x) (((x) & 0x3F) << 2) 1501254885Sdumbbell#define G_028C70_FORMAT(x) (((x) >> 2) & 0x3F) 1502254885Sdumbbell#define C_028C70_FORMAT 0xFFFFFF03 1503254885Sdumbbell#define V_028C70_COLOR_INVALID 0x00000000 1504254885Sdumbbell#define V_028C70_COLOR_8 0x00000001 1505254885Sdumbbell#define V_028C70_COLOR_4_4 0x00000002 1506254885Sdumbbell#define V_028C70_COLOR_3_3_2 0x00000003 1507254885Sdumbbell#define V_028C70_COLOR_16 0x00000005 1508254885Sdumbbell#define V_028C70_COLOR_16_FLOAT 0x00000006 1509254885Sdumbbell#define V_028C70_COLOR_8_8 0x00000007 1510254885Sdumbbell#define V_028C70_COLOR_5_6_5 0x00000008 1511254885Sdumbbell#define V_028C70_COLOR_6_5_5 0x00000009 1512254885Sdumbbell#define V_028C70_COLOR_1_5_5_5 0x0000000A 1513254885Sdumbbell#define V_028C70_COLOR_4_4_4_4 0x0000000B 1514254885Sdumbbell#define V_028C70_COLOR_5_5_5_1 0x0000000C 1515254885Sdumbbell#define V_028C70_COLOR_32 0x0000000D 1516254885Sdumbbell#define V_028C70_COLOR_32_FLOAT 0x0000000E 1517254885Sdumbbell#define V_028C70_COLOR_16_16 0x0000000F 1518254885Sdumbbell#define V_028C70_COLOR_16_16_FLOAT 0x00000010 1519254885Sdumbbell#define V_028C70_COLOR_8_24 0x00000011 1520254885Sdumbbell#define V_028C70_COLOR_8_24_FLOAT 0x00000012 1521254885Sdumbbell#define V_028C70_COLOR_24_8 0x00000013 1522254885Sdumbbell#define V_028C70_COLOR_24_8_FLOAT 0x00000014 1523254885Sdumbbell#define V_028C70_COLOR_10_11_11 0x00000015 1524254885Sdumbbell#define V_028C70_COLOR_10_11_11_FLOAT 0x00000016 1525254885Sdumbbell#define V_028C70_COLOR_11_11_10 0x00000017 1526254885Sdumbbell#define V_028C70_COLOR_11_11_10_FLOAT 0x00000018 1527254885Sdumbbell#define V_028C70_COLOR_2_10_10_10 0x00000019 1528254885Sdumbbell#define V_028C70_COLOR_8_8_8_8 0x0000001A 1529254885Sdumbbell#define V_028C70_COLOR_10_10_10_2 0x0000001B 1530254885Sdumbbell#define V_028C70_COLOR_X24_8_32_FLOAT 0x0000001C 1531254885Sdumbbell#define V_028C70_COLOR_32_32 0x0000001D 1532254885Sdumbbell#define V_028C70_COLOR_32_32_FLOAT 0x0000001E 1533254885Sdumbbell#define V_028C70_COLOR_16_16_16_16 0x0000001F 1534254885Sdumbbell#define V_028C70_COLOR_16_16_16_16_FLOAT 0x00000020 1535254885Sdumbbell#define V_028C70_COLOR_32_32_32_32 0x00000022 1536254885Sdumbbell#define V_028C70_COLOR_32_32_32_32_FLOAT 0x00000023 1537254885Sdumbbell#define V_028C70_COLOR_32_32_32_FLOAT 0x00000030 1538254885Sdumbbell#define S_028C70_ARRAY_MODE(x) (((x) & 0xF) << 8) 1539254885Sdumbbell#define G_028C70_ARRAY_MODE(x) (((x) >> 8) & 0xF) 1540254885Sdumbbell#define C_028C70_ARRAY_MODE 0xFFFFF0FF 1541254885Sdumbbell#define V_028C70_ARRAY_LINEAR_GENERAL 0x00000000 1542254885Sdumbbell#define V_028C70_ARRAY_LINEAR_ALIGNED 0x00000001 1543254885Sdumbbell#define V_028C70_ARRAY_1D_TILED_THIN1 0x00000002 1544254885Sdumbbell#define V_028C70_ARRAY_2D_TILED_THIN1 0x00000004 1545254885Sdumbbell#define S_028C70_NUMBER_TYPE(x) (((x) & 0x7) << 12) 1546254885Sdumbbell#define G_028C70_NUMBER_TYPE(x) (((x) >> 12) & 0x7) 1547254885Sdumbbell#define C_028C70_NUMBER_TYPE 0xFFFF8FFF 1548254885Sdumbbell#define V_028C70_NUMBER_UNORM 0x00000000 1549254885Sdumbbell#define V_028C70_NUMBER_SNORM 0x00000001 1550254885Sdumbbell#define V_028C70_NUMBER_USCALED 0x00000002 1551254885Sdumbbell#define V_028C70_NUMBER_SSCALED 0x00000003 1552254885Sdumbbell#define V_028C70_NUMBER_UINT 0x00000004 1553254885Sdumbbell#define V_028C70_NUMBER_SINT 0x00000005 1554254885Sdumbbell#define V_028C70_NUMBER_SRGB 0x00000006 1555254885Sdumbbell#define V_028C70_NUMBER_FLOAT 0x00000007 1556254885Sdumbbell#define S_028C70_COMP_SWAP(x) (((x) & 0x3) << 15) 1557254885Sdumbbell#define G_028C70_COMP_SWAP(x) (((x) >> 15) & 0x3) 1558254885Sdumbbell#define C_028C70_COMP_SWAP 0xFFFE7FFF 1559254885Sdumbbell#define V_028C70_SWAP_STD 0x00000000 1560254885Sdumbbell#define V_028C70_SWAP_ALT 0x00000001 1561254885Sdumbbell#define V_028C70_SWAP_STD_REV 0x00000002 1562254885Sdumbbell#define V_028C70_SWAP_ALT_REV 0x00000003 1563254885Sdumbbell#define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 17) 1564254885Sdumbbell#define G_028C70_FAST_CLEAR(x) (((x) >> 17) & 0x1) 1565254885Sdumbbell#define C_028C70_FAST_CLEAR 0xFFFDFFFF 1566254885Sdumbbell#define S_028C70_COMPRESSION(x) (((x) & 0x3) << 18) 1567254885Sdumbbell#define G_028C70_COMPRESSION(x) (((x) >> 18) & 0x3) 1568254885Sdumbbell#define C_028C70_COMPRESSION 0xFFF3FFFF 1569254885Sdumbbell#define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 19) 1570254885Sdumbbell#define G_028C70_BLEND_CLAMP(x) (((x) >> 19) & 0x1) 1571254885Sdumbbell#define C_028C70_BLEND_CLAMP 0xFFF7FFFF 1572254885Sdumbbell#define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 20) 1573254885Sdumbbell#define G_028C70_BLEND_BYPASS(x) (((x) >> 20) & 0x1) 1574254885Sdumbbell#define C_028C70_BLEND_BYPASS 0xFFEFFFFF 1575254885Sdumbbell#define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 21) 1576254885Sdumbbell#define G_028C70_SIMPLE_FLOAT(x) (((x) >> 21) & 0x1) 1577254885Sdumbbell#define C_028C70_SIMPLE_FLOAT 0xFFDFFFFF 1578254885Sdumbbell#define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 22) 1579254885Sdumbbell#define G_028C70_ROUND_MODE(x) (((x) >> 22) & 0x1) 1580254885Sdumbbell#define C_028C70_ROUND_MODE 0xFFBFFFFF 1581254885Sdumbbell#define S_028C70_TILE_COMPACT(x) (((x) & 0x1) << 23) 1582254885Sdumbbell#define G_028C70_TILE_COMPACT(x) (((x) >> 23) & 0x1) 1583254885Sdumbbell#define C_028C70_TILE_COMPACT 0xFF7FFFFF 1584254885Sdumbbell#define S_028C70_SOURCE_FORMAT(x) (((x) & 0x3) << 24) 1585254885Sdumbbell#define G_028C70_SOURCE_FORMAT(x) (((x) >> 24) & 0x3) 1586254885Sdumbbell#define C_028C70_SOURCE_FORMAT 0xFCFFFFFF 1587254885Sdumbbell#define V_028C70_EXPORT_4C_32BPC 0x0 1588254885Sdumbbell#define V_028C70_EXPORT_4C_16BPC 0x1 1589254885Sdumbbell#define V_028C70_EXPORT_2C_32BPC 0x2 /* Do not use */ 1590254885Sdumbbell#define S_028C70_RAT(x) (((x) & 0x1) << 26) 1591254885Sdumbbell#define G_028C70_RAT(x) (((x) >> 26) & 0x1) 1592254885Sdumbbell#define C_028C70_RAT 0xFBFFFFFF 1593254885Sdumbbell#define S_028C70_RESOURCE_TYPE(x) (((x) & 0x7) << 27) 1594254885Sdumbbell#define G_028C70_RESOURCE_TYPE(x) (((x) >> 27) & 0x7) 1595254885Sdumbbell#define C_028C70_RESOURCE_TYPE 0xC7FFFFFF 1596254885Sdumbbell 1597254885Sdumbbell#define CB_COLOR0_INFO 0x28c70 1598254885Sdumbbell# define CB_FORMAT(x) ((x) << 2) 1599254885Sdumbbell# define CB_ARRAY_MODE(x) ((x) << 8) 1600254885Sdumbbell# define ARRAY_LINEAR_GENERAL 0 1601254885Sdumbbell# define ARRAY_LINEAR_ALIGNED 1 1602254885Sdumbbell# define ARRAY_1D_TILED_THIN1 2 1603254885Sdumbbell# define ARRAY_2D_TILED_THIN1 4 1604254885Sdumbbell# define CB_SOURCE_FORMAT(x) ((x) << 24) 1605254885Sdumbbell# define CB_SF_EXPORT_FULL 0 1606254885Sdumbbell# define CB_SF_EXPORT_NORM 1 1607254885Sdumbbell#define R_028C74_CB_COLOR0_ATTRIB 0x028C74 1608254885Sdumbbell#define S_028C74_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 4) 1609254885Sdumbbell#define G_028C74_NON_DISP_TILING_ORDER(x) (((x) >> 4) & 0x1) 1610254885Sdumbbell#define C_028C74_NON_DISP_TILING_ORDER 0xFFFFFFEF 1611254885Sdumbbell#define S_028C74_TILE_SPLIT(x) (((x) & 0xf) << 5) 1612254885Sdumbbell#define G_028C74_TILE_SPLIT(x) (((x) >> 5) & 0xf) 1613254885Sdumbbell#define S_028C74_NUM_BANKS(x) (((x) & 0x3) << 10) 1614254885Sdumbbell#define G_028C74_NUM_BANKS(x) (((x) >> 10) & 0x3) 1615254885Sdumbbell#define S_028C74_BANK_WIDTH(x) (((x) & 0x3) << 13) 1616254885Sdumbbell#define G_028C74_BANK_WIDTH(x) (((x) >> 13) & 0x3) 1617254885Sdumbbell#define S_028C74_BANK_HEIGHT(x) (((x) & 0x3) << 16) 1618254885Sdumbbell#define G_028C74_BANK_HEIGHT(x) (((x) >> 16) & 0x3) 1619254885Sdumbbell#define S_028C74_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19) 1620254885Sdumbbell#define G_028C74_MACRO_TILE_ASPECT(x) (((x) >> 19) & 0x3) 1621254885Sdumbbell#define CB_COLOR0_ATTRIB 0x28c74 1622254885Sdumbbell# define CB_TILE_SPLIT(x) (((x) & 0x7) << 5) 1623254885Sdumbbell# define ADDR_SURF_TILE_SPLIT_64B 0 1624254885Sdumbbell# define ADDR_SURF_TILE_SPLIT_128B 1 1625254885Sdumbbell# define ADDR_SURF_TILE_SPLIT_256B 2 1626254885Sdumbbell# define ADDR_SURF_TILE_SPLIT_512B 3 1627254885Sdumbbell# define ADDR_SURF_TILE_SPLIT_1KB 4 1628254885Sdumbbell# define ADDR_SURF_TILE_SPLIT_2KB 5 1629254885Sdumbbell# define ADDR_SURF_TILE_SPLIT_4KB 6 1630254885Sdumbbell# define CB_NUM_BANKS(x) (((x) & 0x3) << 10) 1631254885Sdumbbell# define ADDR_SURF_2_BANK 0 1632254885Sdumbbell# define ADDR_SURF_4_BANK 1 1633254885Sdumbbell# define ADDR_SURF_8_BANK 2 1634254885Sdumbbell# define ADDR_SURF_16_BANK 3 1635254885Sdumbbell# define CB_BANK_WIDTH(x) (((x) & 0x3) << 13) 1636254885Sdumbbell# define ADDR_SURF_BANK_WIDTH_1 0 1637254885Sdumbbell# define ADDR_SURF_BANK_WIDTH_2 1 1638254885Sdumbbell# define ADDR_SURF_BANK_WIDTH_4 2 1639254885Sdumbbell# define ADDR_SURF_BANK_WIDTH_8 3 1640254885Sdumbbell# define CB_BANK_HEIGHT(x) (((x) & 0x3) << 16) 1641254885Sdumbbell# define ADDR_SURF_BANK_HEIGHT_1 0 1642254885Sdumbbell# define ADDR_SURF_BANK_HEIGHT_2 1 1643254885Sdumbbell# define ADDR_SURF_BANK_HEIGHT_4 2 1644254885Sdumbbell# define ADDR_SURF_BANK_HEIGHT_8 3 1645254885Sdumbbell# define CB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19) 1646254885Sdumbbell#define CB_COLOR0_DIM 0x28c78 1647254885Sdumbbell/* only CB0-7 blocks have these regs */ 1648254885Sdumbbell#define CB_COLOR0_CMASK 0x28c7c 1649254885Sdumbbell#define CB_COLOR0_CMASK_SLICE 0x28c80 1650254885Sdumbbell#define CB_COLOR0_FMASK 0x28c84 1651254885Sdumbbell#define CB_COLOR0_FMASK_SLICE 0x28c88 1652254885Sdumbbell#define CB_COLOR0_CLEAR_WORD0 0x28c8c 1653254885Sdumbbell#define CB_COLOR0_CLEAR_WORD1 0x28c90 1654254885Sdumbbell#define CB_COLOR0_CLEAR_WORD2 0x28c94 1655254885Sdumbbell#define CB_COLOR0_CLEAR_WORD3 0x28c98 1656254885Sdumbbell 1657254885Sdumbbell#define CB_COLOR1_BASE 0x28c9c 1658254885Sdumbbell#define CB_COLOR2_BASE 0x28cd8 1659254885Sdumbbell#define CB_COLOR3_BASE 0x28d14 1660254885Sdumbbell#define CB_COLOR4_BASE 0x28d50 1661254885Sdumbbell#define CB_COLOR5_BASE 0x28d8c 1662254885Sdumbbell#define CB_COLOR6_BASE 0x28dc8 1663254885Sdumbbell#define CB_COLOR7_BASE 0x28e04 1664254885Sdumbbell#define CB_COLOR8_BASE 0x28e40 1665254885Sdumbbell#define CB_COLOR9_BASE 0x28e5c 1666254885Sdumbbell#define CB_COLOR10_BASE 0x28e78 1667254885Sdumbbell#define CB_COLOR11_BASE 0x28e94 1668254885Sdumbbell 1669254885Sdumbbell#define CB_COLOR1_PITCH 0x28ca0 1670254885Sdumbbell#define CB_COLOR2_PITCH 0x28cdc 1671254885Sdumbbell#define CB_COLOR3_PITCH 0x28d18 1672254885Sdumbbell#define CB_COLOR4_PITCH 0x28d54 1673254885Sdumbbell#define CB_COLOR5_PITCH 0x28d90 1674254885Sdumbbell#define CB_COLOR6_PITCH 0x28dcc 1675254885Sdumbbell#define CB_COLOR7_PITCH 0x28e08 1676254885Sdumbbell#define CB_COLOR8_PITCH 0x28e44 1677254885Sdumbbell#define CB_COLOR9_PITCH 0x28e60 1678254885Sdumbbell#define CB_COLOR10_PITCH 0x28e7c 1679254885Sdumbbell#define CB_COLOR11_PITCH 0x28e98 1680254885Sdumbbell 1681254885Sdumbbell#define CB_COLOR1_SLICE 0x28ca4 1682254885Sdumbbell#define CB_COLOR2_SLICE 0x28ce0 1683254885Sdumbbell#define CB_COLOR3_SLICE 0x28d1c 1684254885Sdumbbell#define CB_COLOR4_SLICE 0x28d58 1685254885Sdumbbell#define CB_COLOR5_SLICE 0x28d94 1686254885Sdumbbell#define CB_COLOR6_SLICE 0x28dd0 1687254885Sdumbbell#define CB_COLOR7_SLICE 0x28e0c 1688254885Sdumbbell#define CB_COLOR8_SLICE 0x28e48 1689254885Sdumbbell#define CB_COLOR9_SLICE 0x28e64 1690254885Sdumbbell#define CB_COLOR10_SLICE 0x28e80 1691254885Sdumbbell#define CB_COLOR11_SLICE 0x28e9c 1692254885Sdumbbell 1693254885Sdumbbell#define CB_COLOR1_VIEW 0x28ca8 1694254885Sdumbbell#define CB_COLOR2_VIEW 0x28ce4 1695254885Sdumbbell#define CB_COLOR3_VIEW 0x28d20 1696254885Sdumbbell#define CB_COLOR4_VIEW 0x28d5c 1697254885Sdumbbell#define CB_COLOR5_VIEW 0x28d98 1698254885Sdumbbell#define CB_COLOR6_VIEW 0x28dd4 1699254885Sdumbbell#define CB_COLOR7_VIEW 0x28e10 1700254885Sdumbbell#define CB_COLOR8_VIEW 0x28e4c 1701254885Sdumbbell#define CB_COLOR9_VIEW 0x28e68 1702254885Sdumbbell#define CB_COLOR10_VIEW 0x28e84 1703254885Sdumbbell#define CB_COLOR11_VIEW 0x28ea0 1704254885Sdumbbell 1705254885Sdumbbell#define CB_COLOR1_INFO 0x28cac 1706254885Sdumbbell#define CB_COLOR2_INFO 0x28ce8 1707254885Sdumbbell#define CB_COLOR3_INFO 0x28d24 1708254885Sdumbbell#define CB_COLOR4_INFO 0x28d60 1709254885Sdumbbell#define CB_COLOR5_INFO 0x28d9c 1710254885Sdumbbell#define CB_COLOR6_INFO 0x28dd8 1711254885Sdumbbell#define CB_COLOR7_INFO 0x28e14 1712254885Sdumbbell#define CB_COLOR8_INFO 0x28e50 1713254885Sdumbbell#define CB_COLOR9_INFO 0x28e6c 1714254885Sdumbbell#define CB_COLOR10_INFO 0x28e88 1715254885Sdumbbell#define CB_COLOR11_INFO 0x28ea4 1716254885Sdumbbell 1717254885Sdumbbell#define CB_COLOR1_ATTRIB 0x28cb0 1718254885Sdumbbell#define CB_COLOR2_ATTRIB 0x28cec 1719254885Sdumbbell#define CB_COLOR3_ATTRIB 0x28d28 1720254885Sdumbbell#define CB_COLOR4_ATTRIB 0x28d64 1721254885Sdumbbell#define CB_COLOR5_ATTRIB 0x28da0 1722254885Sdumbbell#define CB_COLOR6_ATTRIB 0x28ddc 1723254885Sdumbbell#define CB_COLOR7_ATTRIB 0x28e18 1724254885Sdumbbell#define CB_COLOR8_ATTRIB 0x28e54 1725254885Sdumbbell#define CB_COLOR9_ATTRIB 0x28e70 1726254885Sdumbbell#define CB_COLOR10_ATTRIB 0x28e8c 1727254885Sdumbbell#define CB_COLOR11_ATTRIB 0x28ea8 1728254885Sdumbbell 1729254885Sdumbbell#define CB_COLOR1_DIM 0x28cb4 1730254885Sdumbbell#define CB_COLOR2_DIM 0x28cf0 1731254885Sdumbbell#define CB_COLOR3_DIM 0x28d2c 1732254885Sdumbbell#define CB_COLOR4_DIM 0x28d68 1733254885Sdumbbell#define CB_COLOR5_DIM 0x28da4 1734254885Sdumbbell#define CB_COLOR6_DIM 0x28de0 1735254885Sdumbbell#define CB_COLOR7_DIM 0x28e1c 1736254885Sdumbbell#define CB_COLOR8_DIM 0x28e58 1737254885Sdumbbell#define CB_COLOR9_DIM 0x28e74 1738254885Sdumbbell#define CB_COLOR10_DIM 0x28e90 1739254885Sdumbbell#define CB_COLOR11_DIM 0x28eac 1740254885Sdumbbell 1741254885Sdumbbell#define CB_COLOR1_CMASK 0x28cb8 1742254885Sdumbbell#define CB_COLOR2_CMASK 0x28cf4 1743254885Sdumbbell#define CB_COLOR3_CMASK 0x28d30 1744254885Sdumbbell#define CB_COLOR4_CMASK 0x28d6c 1745254885Sdumbbell#define CB_COLOR5_CMASK 0x28da8 1746254885Sdumbbell#define CB_COLOR6_CMASK 0x28de4 1747254885Sdumbbell#define CB_COLOR7_CMASK 0x28e20 1748254885Sdumbbell 1749254885Sdumbbell#define CB_COLOR1_CMASK_SLICE 0x28cbc 1750254885Sdumbbell#define CB_COLOR2_CMASK_SLICE 0x28cf8 1751254885Sdumbbell#define CB_COLOR3_CMASK_SLICE 0x28d34 1752254885Sdumbbell#define CB_COLOR4_CMASK_SLICE 0x28d70 1753254885Sdumbbell#define CB_COLOR5_CMASK_SLICE 0x28dac 1754254885Sdumbbell#define CB_COLOR6_CMASK_SLICE 0x28de8 1755254885Sdumbbell#define CB_COLOR7_CMASK_SLICE 0x28e24 1756254885Sdumbbell 1757254885Sdumbbell#define CB_COLOR1_FMASK 0x28cc0 1758254885Sdumbbell#define CB_COLOR2_FMASK 0x28cfc 1759254885Sdumbbell#define CB_COLOR3_FMASK 0x28d38 1760254885Sdumbbell#define CB_COLOR4_FMASK 0x28d74 1761254885Sdumbbell#define CB_COLOR5_FMASK 0x28db0 1762254885Sdumbbell#define CB_COLOR6_FMASK 0x28dec 1763254885Sdumbbell#define CB_COLOR7_FMASK 0x28e28 1764254885Sdumbbell 1765254885Sdumbbell#define CB_COLOR1_FMASK_SLICE 0x28cc4 1766254885Sdumbbell#define CB_COLOR2_FMASK_SLICE 0x28d00 1767254885Sdumbbell#define CB_COLOR3_FMASK_SLICE 0x28d3c 1768254885Sdumbbell#define CB_COLOR4_FMASK_SLICE 0x28d78 1769254885Sdumbbell#define CB_COLOR5_FMASK_SLICE 0x28db4 1770254885Sdumbbell#define CB_COLOR6_FMASK_SLICE 0x28df0 1771254885Sdumbbell#define CB_COLOR7_FMASK_SLICE 0x28e2c 1772254885Sdumbbell 1773254885Sdumbbell#define CB_COLOR1_CLEAR_WORD0 0x28cc8 1774254885Sdumbbell#define CB_COLOR2_CLEAR_WORD0 0x28d04 1775254885Sdumbbell#define CB_COLOR3_CLEAR_WORD0 0x28d40 1776254885Sdumbbell#define CB_COLOR4_CLEAR_WORD0 0x28d7c 1777254885Sdumbbell#define CB_COLOR5_CLEAR_WORD0 0x28db8 1778254885Sdumbbell#define CB_COLOR6_CLEAR_WORD0 0x28df4 1779254885Sdumbbell#define CB_COLOR7_CLEAR_WORD0 0x28e30 1780254885Sdumbbell 1781254885Sdumbbell#define CB_COLOR1_CLEAR_WORD1 0x28ccc 1782254885Sdumbbell#define CB_COLOR2_CLEAR_WORD1 0x28d08 1783254885Sdumbbell#define CB_COLOR3_CLEAR_WORD1 0x28d44 1784254885Sdumbbell#define CB_COLOR4_CLEAR_WORD1 0x28d80 1785254885Sdumbbell#define CB_COLOR5_CLEAR_WORD1 0x28dbc 1786254885Sdumbbell#define CB_COLOR6_CLEAR_WORD1 0x28df8 1787254885Sdumbbell#define CB_COLOR7_CLEAR_WORD1 0x28e34 1788254885Sdumbbell 1789254885Sdumbbell#define CB_COLOR1_CLEAR_WORD2 0x28cd0 1790254885Sdumbbell#define CB_COLOR2_CLEAR_WORD2 0x28d0c 1791254885Sdumbbell#define CB_COLOR3_CLEAR_WORD2 0x28d48 1792254885Sdumbbell#define CB_COLOR4_CLEAR_WORD2 0x28d84 1793254885Sdumbbell#define CB_COLOR5_CLEAR_WORD2 0x28dc0 1794254885Sdumbbell#define CB_COLOR6_CLEAR_WORD2 0x28dfc 1795254885Sdumbbell#define CB_COLOR7_CLEAR_WORD2 0x28e38 1796254885Sdumbbell 1797254885Sdumbbell#define CB_COLOR1_CLEAR_WORD3 0x28cd4 1798254885Sdumbbell#define CB_COLOR2_CLEAR_WORD3 0x28d10 1799254885Sdumbbell#define CB_COLOR3_CLEAR_WORD3 0x28d4c 1800254885Sdumbbell#define CB_COLOR4_CLEAR_WORD3 0x28d88 1801254885Sdumbbell#define CB_COLOR5_CLEAR_WORD3 0x28dc4 1802254885Sdumbbell#define CB_COLOR6_CLEAR_WORD3 0x28e00 1803254885Sdumbbell#define CB_COLOR7_CLEAR_WORD3 0x28e3c 1804254885Sdumbbell 1805254885Sdumbbell#define SQ_TEX_RESOURCE_WORD0_0 0x30000 1806254885Sdumbbell# define TEX_DIM(x) ((x) << 0) 1807254885Sdumbbell# define SQ_TEX_DIM_1D 0 1808254885Sdumbbell# define SQ_TEX_DIM_2D 1 1809254885Sdumbbell# define SQ_TEX_DIM_3D 2 1810254885Sdumbbell# define SQ_TEX_DIM_CUBEMAP 3 1811254885Sdumbbell# define SQ_TEX_DIM_1D_ARRAY 4 1812254885Sdumbbell# define SQ_TEX_DIM_2D_ARRAY 5 1813254885Sdumbbell# define SQ_TEX_DIM_2D_MSAA 6 1814254885Sdumbbell# define SQ_TEX_DIM_2D_ARRAY_MSAA 7 1815254885Sdumbbell#define SQ_TEX_RESOURCE_WORD1_0 0x30004 1816254885Sdumbbell# define TEX_ARRAY_MODE(x) ((x) << 28) 1817254885Sdumbbell#define SQ_TEX_RESOURCE_WORD2_0 0x30008 1818254885Sdumbbell#define SQ_TEX_RESOURCE_WORD3_0 0x3000C 1819254885Sdumbbell#define SQ_TEX_RESOURCE_WORD4_0 0x30010 1820254885Sdumbbell# define TEX_DST_SEL_X(x) ((x) << 16) 1821254885Sdumbbell# define TEX_DST_SEL_Y(x) ((x) << 19) 1822254885Sdumbbell# define TEX_DST_SEL_Z(x) ((x) << 22) 1823254885Sdumbbell# define TEX_DST_SEL_W(x) ((x) << 25) 1824254885Sdumbbell# define SQ_SEL_X 0 1825254885Sdumbbell# define SQ_SEL_Y 1 1826254885Sdumbbell# define SQ_SEL_Z 2 1827254885Sdumbbell# define SQ_SEL_W 3 1828254885Sdumbbell# define SQ_SEL_0 4 1829254885Sdumbbell# define SQ_SEL_1 5 1830254885Sdumbbell#define SQ_TEX_RESOURCE_WORD5_0 0x30014 1831254885Sdumbbell#define SQ_TEX_RESOURCE_WORD6_0 0x30018 1832254885Sdumbbell# define TEX_TILE_SPLIT(x) (((x) & 0x7) << 29) 1833254885Sdumbbell#define SQ_TEX_RESOURCE_WORD7_0 0x3001c 1834254885Sdumbbell# define MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) 1835254885Sdumbbell# define TEX_BANK_WIDTH(x) (((x) & 0x3) << 8) 1836254885Sdumbbell# define TEX_BANK_HEIGHT(x) (((x) & 0x3) << 10) 1837254885Sdumbbell# define TEX_NUM_BANKS(x) (((x) & 0x3) << 16) 1838254885Sdumbbell#define R_030000_SQ_TEX_RESOURCE_WORD0_0 0x030000 1839254885Sdumbbell#define S_030000_DIM(x) (((x) & 0x7) << 0) 1840254885Sdumbbell#define G_030000_DIM(x) (((x) >> 0) & 0x7) 1841254885Sdumbbell#define C_030000_DIM 0xFFFFFFF8 1842254885Sdumbbell#define V_030000_SQ_TEX_DIM_1D 0x00000000 1843254885Sdumbbell#define V_030000_SQ_TEX_DIM_2D 0x00000001 1844254885Sdumbbell#define V_030000_SQ_TEX_DIM_3D 0x00000002 1845254885Sdumbbell#define V_030000_SQ_TEX_DIM_CUBEMAP 0x00000003 1846254885Sdumbbell#define V_030000_SQ_TEX_DIM_1D_ARRAY 0x00000004 1847254885Sdumbbell#define V_030000_SQ_TEX_DIM_2D_ARRAY 0x00000005 1848254885Sdumbbell#define V_030000_SQ_TEX_DIM_2D_MSAA 0x00000006 1849254885Sdumbbell#define V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 1850254885Sdumbbell#define S_030000_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 5) 1851254885Sdumbbell#define G_030000_NON_DISP_TILING_ORDER(x) (((x) >> 5) & 0x1) 1852254885Sdumbbell#define C_030000_NON_DISP_TILING_ORDER 0xFFFFFFDF 1853254885Sdumbbell#define S_030000_PITCH(x) (((x) & 0xFFF) << 6) 1854254885Sdumbbell#define G_030000_PITCH(x) (((x) >> 6) & 0xFFF) 1855254885Sdumbbell#define C_030000_PITCH 0xFFFC003F 1856254885Sdumbbell#define S_030000_TEX_WIDTH(x) (((x) & 0x3FFF) << 18) 1857254885Sdumbbell#define G_030000_TEX_WIDTH(x) (((x) >> 18) & 0x3FFF) 1858254885Sdumbbell#define C_030000_TEX_WIDTH 0x0003FFFF 1859254885Sdumbbell#define R_030004_SQ_TEX_RESOURCE_WORD1_0 0x030004 1860254885Sdumbbell#define S_030004_TEX_HEIGHT(x) (((x) & 0x3FFF) << 0) 1861254885Sdumbbell#define G_030004_TEX_HEIGHT(x) (((x) >> 0) & 0x3FFF) 1862254885Sdumbbell#define C_030004_TEX_HEIGHT 0xFFFFC000 1863254885Sdumbbell#define S_030004_TEX_DEPTH(x) (((x) & 0x1FFF) << 14) 1864254885Sdumbbell#define G_030004_TEX_DEPTH(x) (((x) >> 14) & 0x1FFF) 1865254885Sdumbbell#define C_030004_TEX_DEPTH 0xF8003FFF 1866254885Sdumbbell#define S_030004_ARRAY_MODE(x) (((x) & 0xF) << 28) 1867254885Sdumbbell#define G_030004_ARRAY_MODE(x) (((x) >> 28) & 0xF) 1868254885Sdumbbell#define C_030004_ARRAY_MODE 0x0FFFFFFF 1869254885Sdumbbell#define R_030008_SQ_TEX_RESOURCE_WORD2_0 0x030008 1870254885Sdumbbell#define S_030008_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 1871254885Sdumbbell#define G_030008_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 1872254885Sdumbbell#define C_030008_BASE_ADDRESS 0x00000000 1873254885Sdumbbell#define R_03000C_SQ_TEX_RESOURCE_WORD3_0 0x03000C 1874254885Sdumbbell#define S_03000C_MIP_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 1875254885Sdumbbell#define G_03000C_MIP_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 1876254885Sdumbbell#define C_03000C_MIP_ADDRESS 0x00000000 1877254885Sdumbbell#define R_030010_SQ_TEX_RESOURCE_WORD4_0 0x030010 1878254885Sdumbbell#define S_030010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) 1879254885Sdumbbell#define G_030010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) 1880254885Sdumbbell#define C_030010_FORMAT_COMP_X 0xFFFFFFFC 1881254885Sdumbbell#define V_030010_SQ_FORMAT_COMP_UNSIGNED 0x00000000 1882254885Sdumbbell#define V_030010_SQ_FORMAT_COMP_SIGNED 0x00000001 1883254885Sdumbbell#define V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED 0x00000002 1884254885Sdumbbell#define S_030010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) 1885254885Sdumbbell#define G_030010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) 1886254885Sdumbbell#define C_030010_FORMAT_COMP_Y 0xFFFFFFF3 1887254885Sdumbbell#define S_030010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) 1888254885Sdumbbell#define G_030010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) 1889254885Sdumbbell#define C_030010_FORMAT_COMP_Z 0xFFFFFFCF 1890254885Sdumbbell#define S_030010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) 1891254885Sdumbbell#define G_030010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) 1892254885Sdumbbell#define C_030010_FORMAT_COMP_W 0xFFFFFF3F 1893254885Sdumbbell#define S_030010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) 1894254885Sdumbbell#define G_030010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) 1895254885Sdumbbell#define C_030010_NUM_FORMAT_ALL 0xFFFFFCFF 1896254885Sdumbbell#define V_030010_SQ_NUM_FORMAT_NORM 0x00000000 1897254885Sdumbbell#define V_030010_SQ_NUM_FORMAT_INT 0x00000001 1898254885Sdumbbell#define V_030010_SQ_NUM_FORMAT_SCALED 0x00000002 1899254885Sdumbbell#define S_030010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) 1900254885Sdumbbell#define G_030010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) 1901254885Sdumbbell#define C_030010_SRF_MODE_ALL 0xFFFFFBFF 1902254885Sdumbbell#define V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE 0x00000000 1903254885Sdumbbell#define V_030010_SRF_MODE_NO_ZERO 0x00000001 1904254885Sdumbbell#define S_030010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) 1905254885Sdumbbell#define G_030010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) 1906254885Sdumbbell#define C_030010_FORCE_DEGAMMA 0xFFFFF7FF 1907254885Sdumbbell#define S_030010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) 1908254885Sdumbbell#define G_030010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) 1909254885Sdumbbell#define C_030010_ENDIAN_SWAP 0xFFFFCFFF 1910254885Sdumbbell#define S_030010_DST_SEL_X(x) (((x) & 0x7) << 16) 1911254885Sdumbbell#define G_030010_DST_SEL_X(x) (((x) >> 16) & 0x7) 1912254885Sdumbbell#define C_030010_DST_SEL_X 0xFFF8FFFF 1913254885Sdumbbell#define V_030010_SQ_SEL_X 0x00000000 1914254885Sdumbbell#define V_030010_SQ_SEL_Y 0x00000001 1915254885Sdumbbell#define V_030010_SQ_SEL_Z 0x00000002 1916254885Sdumbbell#define V_030010_SQ_SEL_W 0x00000003 1917254885Sdumbbell#define V_030010_SQ_SEL_0 0x00000004 1918254885Sdumbbell#define V_030010_SQ_SEL_1 0x00000005 1919254885Sdumbbell#define S_030010_DST_SEL_Y(x) (((x) & 0x7) << 19) 1920254885Sdumbbell#define G_030010_DST_SEL_Y(x) (((x) >> 19) & 0x7) 1921254885Sdumbbell#define C_030010_DST_SEL_Y 0xFFC7FFFF 1922254885Sdumbbell#define S_030010_DST_SEL_Z(x) (((x) & 0x7) << 22) 1923254885Sdumbbell#define G_030010_DST_SEL_Z(x) (((x) >> 22) & 0x7) 1924254885Sdumbbell#define C_030010_DST_SEL_Z 0xFE3FFFFF 1925254885Sdumbbell#define S_030010_DST_SEL_W(x) (((x) & 0x7) << 25) 1926254885Sdumbbell#define G_030010_DST_SEL_W(x) (((x) >> 25) & 0x7) 1927254885Sdumbbell#define C_030010_DST_SEL_W 0xF1FFFFFF 1928254885Sdumbbell#define S_030010_BASE_LEVEL(x) (((x) & 0xF) << 28) 1929254885Sdumbbell#define G_030010_BASE_LEVEL(x) (((x) >> 28) & 0xF) 1930254885Sdumbbell#define C_030010_BASE_LEVEL 0x0FFFFFFF 1931254885Sdumbbell#define R_030014_SQ_TEX_RESOURCE_WORD5_0 0x030014 1932254885Sdumbbell#define S_030014_LAST_LEVEL(x) (((x) & 0xF) << 0) 1933254885Sdumbbell#define G_030014_LAST_LEVEL(x) (((x) >> 0) & 0xF) 1934254885Sdumbbell#define C_030014_LAST_LEVEL 0xFFFFFFF0 1935254885Sdumbbell#define S_030014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) 1936254885Sdumbbell#define G_030014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) 1937254885Sdumbbell#define C_030014_BASE_ARRAY 0xFFFE000F 1938254885Sdumbbell#define S_030014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) 1939254885Sdumbbell#define G_030014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) 1940254885Sdumbbell#define C_030014_LAST_ARRAY 0xC001FFFF 1941254885Sdumbbell#define R_030018_SQ_TEX_RESOURCE_WORD6_0 0x030018 1942254885Sdumbbell#define S_030018_MAX_ANISO(x) (((x) & 0x7) << 0) 1943254885Sdumbbell#define G_030018_MAX_ANISO(x) (((x) >> 0) & 0x7) 1944254885Sdumbbell#define C_030018_MAX_ANISO 0xFFFFFFF8 1945254885Sdumbbell#define S_030018_PERF_MODULATION(x) (((x) & 0x7) << 3) 1946254885Sdumbbell#define G_030018_PERF_MODULATION(x) (((x) >> 3) & 0x7) 1947254885Sdumbbell#define C_030018_PERF_MODULATION 0xFFFFFFC7 1948254885Sdumbbell#define S_030018_INTERLACED(x) (((x) & 0x1) << 6) 1949254885Sdumbbell#define G_030018_INTERLACED(x) (((x) >> 6) & 0x1) 1950254885Sdumbbell#define C_030018_INTERLACED 0xFFFFFFBF 1951254885Sdumbbell#define S_030018_TILE_SPLIT(x) (((x) & 0x7) << 29) 1952254885Sdumbbell#define G_030018_TILE_SPLIT(x) (((x) >> 29) & 0x7) 1953254885Sdumbbell#define R_03001C_SQ_TEX_RESOURCE_WORD7_0 0x03001C 1954254885Sdumbbell#define S_03001C_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) 1955254885Sdumbbell#define G_03001C_MACRO_TILE_ASPECT(x) (((x) >> 6) & 0x3) 1956254885Sdumbbell#define S_03001C_BANK_WIDTH(x) (((x) & 0x3) << 8) 1957254885Sdumbbell#define G_03001C_BANK_WIDTH(x) (((x) >> 8) & 0x3) 1958254885Sdumbbell#define S_03001C_BANK_HEIGHT(x) (((x) & 0x3) << 10) 1959254885Sdumbbell#define G_03001C_BANK_HEIGHT(x) (((x) >> 10) & 0x3) 1960254885Sdumbbell#define S_03001C_NUM_BANKS(x) (((x) & 0x3) << 16) 1961254885Sdumbbell#define G_03001C_NUM_BANKS(x) (((x) >> 16) & 0x3) 1962254885Sdumbbell#define S_03001C_TYPE(x) (((x) & 0x3) << 30) 1963254885Sdumbbell#define G_03001C_TYPE(x) (((x) >> 30) & 0x3) 1964254885Sdumbbell#define C_03001C_TYPE 0x3FFFFFFF 1965254885Sdumbbell#define V_03001C_SQ_TEX_VTX_INVALID_TEXTURE 0x00000000 1966254885Sdumbbell#define V_03001C_SQ_TEX_VTX_INVALID_BUFFER 0x00000001 1967254885Sdumbbell#define V_03001C_SQ_TEX_VTX_VALID_TEXTURE 0x00000002 1968254885Sdumbbell#define V_03001C_SQ_TEX_VTX_VALID_BUFFER 0x00000003 1969254885Sdumbbell#define S_03001C_DATA_FORMAT(x) (((x) & 0x3F) << 0) 1970254885Sdumbbell#define G_03001C_DATA_FORMAT(x) (((x) >> 0) & 0x3F) 1971254885Sdumbbell#define C_03001C_DATA_FORMAT 0xFFFFFFC0 1972254885Sdumbbell 1973254885Sdumbbell#define SQ_VTX_CONSTANT_WORD0_0 0x30000 1974254885Sdumbbell#define SQ_VTX_CONSTANT_WORD1_0 0x30004 1975254885Sdumbbell#define SQ_VTX_CONSTANT_WORD2_0 0x30008 1976254885Sdumbbell# define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0) 1977254885Sdumbbell# define SQ_VTXC_STRIDE(x) ((x) << 8) 1978254885Sdumbbell# define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30) 1979254885Sdumbbell# define SQ_ENDIAN_NONE 0 1980254885Sdumbbell# define SQ_ENDIAN_8IN16 1 1981254885Sdumbbell# define SQ_ENDIAN_8IN32 2 1982254885Sdumbbell#define SQ_VTX_CONSTANT_WORD3_0 0x3000C 1983254885Sdumbbell# define SQ_VTCX_SEL_X(x) ((x) << 3) 1984254885Sdumbbell# define SQ_VTCX_SEL_Y(x) ((x) << 6) 1985254885Sdumbbell# define SQ_VTCX_SEL_Z(x) ((x) << 9) 1986254885Sdumbbell# define SQ_VTCX_SEL_W(x) ((x) << 12) 1987254885Sdumbbell#define SQ_VTX_CONSTANT_WORD4_0 0x30010 1988254885Sdumbbell#define SQ_VTX_CONSTANT_WORD5_0 0x30014 1989254885Sdumbbell#define SQ_VTX_CONSTANT_WORD6_0 0x30018 1990254885Sdumbbell#define SQ_VTX_CONSTANT_WORD7_0 0x3001c 1991254885Sdumbbell 1992254885Sdumbbell#define TD_PS_BORDER_COLOR_INDEX 0xA400 1993254885Sdumbbell#define TD_PS_BORDER_COLOR_RED 0xA404 1994254885Sdumbbell#define TD_PS_BORDER_COLOR_GREEN 0xA408 1995254885Sdumbbell#define TD_PS_BORDER_COLOR_BLUE 0xA40C 1996254885Sdumbbell#define TD_PS_BORDER_COLOR_ALPHA 0xA410 1997254885Sdumbbell#define TD_VS_BORDER_COLOR_INDEX 0xA414 1998254885Sdumbbell#define TD_VS_BORDER_COLOR_RED 0xA418 1999254885Sdumbbell#define TD_VS_BORDER_COLOR_GREEN 0xA41C 2000254885Sdumbbell#define TD_VS_BORDER_COLOR_BLUE 0xA420 2001254885Sdumbbell#define TD_VS_BORDER_COLOR_ALPHA 0xA424 2002254885Sdumbbell#define TD_GS_BORDER_COLOR_INDEX 0xA428 2003254885Sdumbbell#define TD_GS_BORDER_COLOR_RED 0xA42C 2004254885Sdumbbell#define TD_GS_BORDER_COLOR_GREEN 0xA430 2005254885Sdumbbell#define TD_GS_BORDER_COLOR_BLUE 0xA434 2006254885Sdumbbell#define TD_GS_BORDER_COLOR_ALPHA 0xA438 2007254885Sdumbbell#define TD_HS_BORDER_COLOR_INDEX 0xA43C 2008254885Sdumbbell#define TD_HS_BORDER_COLOR_RED 0xA440 2009254885Sdumbbell#define TD_HS_BORDER_COLOR_GREEN 0xA444 2010254885Sdumbbell#define TD_HS_BORDER_COLOR_BLUE 0xA448 2011254885Sdumbbell#define TD_HS_BORDER_COLOR_ALPHA 0xA44C 2012254885Sdumbbell#define TD_LS_BORDER_COLOR_INDEX 0xA450 2013254885Sdumbbell#define TD_LS_BORDER_COLOR_RED 0xA454 2014254885Sdumbbell#define TD_LS_BORDER_COLOR_GREEN 0xA458 2015254885Sdumbbell#define TD_LS_BORDER_COLOR_BLUE 0xA45C 2016254885Sdumbbell#define TD_LS_BORDER_COLOR_ALPHA 0xA460 2017254885Sdumbbell#define TD_CS_BORDER_COLOR_INDEX 0xA464 2018254885Sdumbbell#define TD_CS_BORDER_COLOR_RED 0xA468 2019254885Sdumbbell#define TD_CS_BORDER_COLOR_GREEN 0xA46C 2020254885Sdumbbell#define TD_CS_BORDER_COLOR_BLUE 0xA470 2021254885Sdumbbell#define TD_CS_BORDER_COLOR_ALPHA 0xA474 2022254885Sdumbbell 2023254885Sdumbbell/* cayman 3D regs */ 2024254885Sdumbbell#define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B4 2025254885Sdumbbell#define CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS 0x8E48 2026254885Sdumbbell#define CAYMAN_DB_EQAA 0x28804 2027254885Sdumbbell#define CAYMAN_DB_DEPTH_INFO 0x2803C 2028254885Sdumbbell#define CAYMAN_PA_SC_AA_CONFIG 0x28BE0 2029254885Sdumbbell#define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0 2030254885Sdumbbell#define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7 2031254885Sdumbbell#define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358 2032254885Sdumbbell/* cayman packet3 addition */ 2033254885Sdumbbell#define CAYMAN_PACKET3_DEALLOC_STATE 0x14 2034254885Sdumbbell 2035254885Sdumbbell/* DMA regs common on r6xx/r7xx/evergreen/ni */ 2036254885Sdumbbell#define DMA_RB_CNTL 0xd000 2037254885Sdumbbell# define DMA_RB_ENABLE (1 << 0) 2038254885Sdumbbell# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 2039254885Sdumbbell# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 2040254885Sdumbbell# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 2041254885Sdumbbell# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 2042254885Sdumbbell# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 2043254885Sdumbbell#define DMA_STATUS_REG 0xd034 2044254885Sdumbbell# define DMA_IDLE (1 << 0) 2045254885Sdumbbell 2046254885Sdumbbell#endif 2047