1/* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 25#include <sys/cdefs.h> 26__FBSDID("$FreeBSD$"); 27 28#ifndef EVERGREEND_H 29#define EVERGREEND_H 30 31#define EVERGREEN_MAX_SH_GPRS 256 32#define EVERGREEN_MAX_TEMP_GPRS 16 33#define EVERGREEN_MAX_SH_THREADS 256 34#define EVERGREEN_MAX_SH_STACK_ENTRIES 4096 35#define EVERGREEN_MAX_FRC_EOV_CNT 16384 36#define EVERGREEN_MAX_BACKENDS 8 37#define EVERGREEN_MAX_BACKENDS_MASK 0xFF 38#define EVERGREEN_MAX_SIMDS 16 39#define EVERGREEN_MAX_SIMDS_MASK 0xFFFF 40#define EVERGREEN_MAX_PIPES 8 41#define EVERGREEN_MAX_PIPES_MASK 0xFF 42#define EVERGREEN_MAX_LDS_NUM 0xFFFF 43 44#define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003 45#define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003 46#define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 47#define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002 48#define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002 49#define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002 50#define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001 51#define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001 52#define SUMO_GB_ADDR_CONFIG_GOLDEN 0x02010002 53#define SUMO2_GB_ADDR_CONFIG_GOLDEN 0x02010002 54 55/* Registers */ 56 57#define RCU_IND_INDEX 0x100 58#define RCU_IND_DATA 0x104 59 60#define GRBM_GFX_INDEX 0x802C 61#define INSTANCE_INDEX(x) ((x) << 0) 62#define SE_INDEX(x) ((x) << 16) 63#define INSTANCE_BROADCAST_WRITES (1 << 30) 64#define SE_BROADCAST_WRITES (1U << 31) 65#define RLC_GFX_INDEX 0x3fC4 66#define CC_GC_SHADER_PIPE_CONFIG 0x8950 67#define WRITE_DIS (1 << 0) 68#define CC_RB_BACKEND_DISABLE 0x98F4 69#define BACKEND_DISABLE(x) ((x) << 16) 70#define GB_ADDR_CONFIG 0x98F8 71#define NUM_PIPES(x) ((x) << 0) 72#define NUM_PIPES_MASK 0x0000000f 73#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 74#define BANK_INTERLEAVE_SIZE(x) ((x) << 8) 75#define NUM_SHADER_ENGINES(x) ((x) << 12) 76#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 77#define NUM_GPUS(x) ((x) << 20) 78#define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 79#define ROW_SIZE(x) ((x) << 28) 80#define GB_BACKEND_MAP 0x98FC 81#define DMIF_ADDR_CONFIG 0xBD4 82#define HDP_ADDR_CONFIG 0x2F48 83#define HDP_MISC_CNTL 0x2F4C 84#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 85 86#define CC_SYS_RB_BACKEND_DISABLE 0x3F88 87#define GC_USER_RB_BACKEND_DISABLE 0x9B7C 88 89#define CGTS_SYS_TCC_DISABLE 0x3F90 90#define CGTS_TCC_DISABLE 0x9148 91#define CGTS_USER_SYS_TCC_DISABLE 0x3F94 92#define CGTS_USER_TCC_DISABLE 0x914C 93 94#define CONFIG_MEMSIZE 0x5428 95 96#define BIF_FB_EN 0x5490 97#define FB_READ_EN (1 << 0) 98#define FB_WRITE_EN (1 << 1) 99 100#define CP_STRMOUT_CNTL 0x84FC 101 102#define CP_COHER_CNTL 0x85F0 103#define CP_COHER_SIZE 0x85F4 104#define CP_COHER_BASE 0x85F8 105#define CP_STALLED_STAT1 0x8674 106#define CP_STALLED_STAT2 0x8678 107#define CP_BUSY_STAT 0x867C 108#define CP_STAT 0x8680 109#define CP_ME_CNTL 0x86D8 110#define CP_ME_HALT (1 << 28) 111#define CP_PFP_HALT (1 << 26) 112#define CP_ME_RAM_DATA 0xC160 113#define CP_ME_RAM_RADDR 0xC158 114#define CP_ME_RAM_WADDR 0xC15C 115#define CP_MEQ_THRESHOLDS 0x8764 116#define STQ_SPLIT(x) ((x) << 0) 117#define CP_PERFMON_CNTL 0x87FC 118#define CP_PFP_UCODE_ADDR 0xC150 119#define CP_PFP_UCODE_DATA 0xC154 120#define CP_QUEUE_THRESHOLDS 0x8760 121#define ROQ_IB1_START(x) ((x) << 0) 122#define ROQ_IB2_START(x) ((x) << 8) 123#define CP_RB_BASE 0xC100 124#define CP_RB_CNTL 0xC104 125#define RB_BUFSZ(x) ((x) << 0) 126#define RB_BLKSZ(x) ((x) << 8) 127#define RB_NO_UPDATE (1 << 27) 128#define RB_RPTR_WR_ENA (1U << 31) 129#define BUF_SWAP_32BIT (2 << 16) 130#define CP_RB_RPTR 0x8700 131#define CP_RB_RPTR_ADDR 0xC10C 132#define RB_RPTR_SWAP(x) ((x) << 0) 133#define CP_RB_RPTR_ADDR_HI 0xC110 134#define CP_RB_RPTR_WR 0xC108 135#define CP_RB_WPTR 0xC114 136#define CP_RB_WPTR_ADDR 0xC118 137#define CP_RB_WPTR_ADDR_HI 0xC11C 138#define CP_RB_WPTR_DELAY 0x8704 139#define CP_SEM_WAIT_TIMER 0x85BC 140#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 141#define CP_DEBUG 0xC1FC 142 143/* Audio clocks */ 144#define DCCG_AUDIO_DTO_SOURCE 0x05ac 145# define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */ 146# define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */ 147 148#define DCCG_AUDIO_DTO0_PHASE 0x05b0 149#define DCCG_AUDIO_DTO0_MODULE 0x05b4 150#define DCCG_AUDIO_DTO0_LOAD 0x05b8 151#define DCCG_AUDIO_DTO0_CNTL 0x05bc 152 153#define DCCG_AUDIO_DTO1_PHASE 0x05c0 154#define DCCG_AUDIO_DTO1_MODULE 0x05c4 155#define DCCG_AUDIO_DTO1_LOAD 0x05c8 156#define DCCG_AUDIO_DTO1_CNTL 0x05cc 157 158/* DCE 4.0 AFMT */ 159#define HDMI_CONTROL 0x7030 160# define HDMI_KEEPOUT_MODE (1 << 0) 161# define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */ 162# define HDMI_ERROR_ACK (1 << 8) 163# define HDMI_ERROR_MASK (1 << 9) 164# define HDMI_DEEP_COLOR_ENABLE (1 << 24) 165# define HDMI_DEEP_COLOR_DEPTH (((x) & 3) << 28) 166# define HDMI_24BIT_DEEP_COLOR 0 167# define HDMI_30BIT_DEEP_COLOR 1 168# define HDMI_36BIT_DEEP_COLOR 2 169#define HDMI_STATUS 0x7034 170# define HDMI_ACTIVE_AVMUTE (1 << 0) 171# define HDMI_AUDIO_PACKET_ERROR (1 << 16) 172# define HDMI_VBI_PACKET_ERROR (1 << 20) 173#define HDMI_AUDIO_PACKET_CONTROL 0x7038 174# define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4) 175# define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) 176#define HDMI_ACR_PACKET_CONTROL 0x703c 177# define HDMI_ACR_SEND (1 << 0) 178# define HDMI_ACR_CONT (1 << 1) 179# define HDMI_ACR_SELECT(x) (((x) & 3) << 4) 180# define HDMI_ACR_HW 0 181# define HDMI_ACR_32 1 182# define HDMI_ACR_44 2 183# define HDMI_ACR_48 3 184# define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ 185# define HDMI_ACR_AUTO_SEND (1 << 12) 186# define HDMI_ACR_N_MULTIPLE(x) (((x) & 7) << 16) 187# define HDMI_ACR_X1 1 188# define HDMI_ACR_X2 2 189# define HDMI_ACR_X4 4 190# define HDMI_ACR_AUDIO_PRIORITY (1U << 31) 191#define HDMI_VBI_PACKET_CONTROL 0x7040 192# define HDMI_NULL_SEND (1 << 0) 193# define HDMI_GC_SEND (1 << 4) 194# define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ 195#define HDMI_INFOFRAME_CONTROL0 0x7044 196# define HDMI_AVI_INFO_SEND (1 << 0) 197# define HDMI_AVI_INFO_CONT (1 << 1) 198# define HDMI_AUDIO_INFO_SEND (1 << 4) 199# define HDMI_AUDIO_INFO_CONT (1 << 5) 200# define HDMI_MPEG_INFO_SEND (1 << 8) 201# define HDMI_MPEG_INFO_CONT (1 << 9) 202#define HDMI_INFOFRAME_CONTROL1 0x7048 203# define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) 204# define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) 205# define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) 206#define HDMI_GENERIC_PACKET_CONTROL 0x704c 207# define HDMI_GENERIC0_SEND (1 << 0) 208# define HDMI_GENERIC0_CONT (1 << 1) 209# define HDMI_GENERIC1_SEND (1 << 4) 210# define HDMI_GENERIC1_CONT (1 << 5) 211# define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16) 212# define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24) 213#define HDMI_GC 0x7058 214# define HDMI_GC_AVMUTE (1 << 0) 215# define HDMI_GC_AVMUTE_CONT (1 << 2) 216#define AFMT_AUDIO_PACKET_CONTROL2 0x705c 217# define AFMT_AUDIO_LAYOUT_OVRD (1 << 0) 218# define AFMT_AUDIO_LAYOUT_SELECT (1 << 1) 219# define AFMT_60958_CS_SOURCE (1 << 4) 220# define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8) 221# define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16) 222#define AFMT_AVI_INFO0 0x7084 223# define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 224# define AFMT_AVI_INFO_S(x) (((x) & 3) << 8) 225# define AFMT_AVI_INFO_B(x) (((x) & 3) << 10) 226# define AFMT_AVI_INFO_A(x) (((x) & 1) << 12) 227# define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13) 228# define AFMT_AVI_INFO_Y_RGB 0 229# define AFMT_AVI_INFO_Y_YCBCR422 1 230# define AFMT_AVI_INFO_Y_YCBCR444 2 231# define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) 232# define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16) 233# define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20) 234# define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22) 235# define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) 236# define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24) 237# define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26) 238# define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28) 239# define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31) 240# define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) 241#define AFMT_AVI_INFO1 0x7088 242# define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ 243# define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ 244# define AFMT_AVI_INFO_CN(x) (((x) & 0x3) << 12) 245# define AFMT_AVI_INFO_YQ(x) (((x) & 0x3) << 14) 246# define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) 247#define AFMT_AVI_INFO2 0x708c 248# define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) 249# define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) 250#define AFMT_AVI_INFO3 0x7090 251# define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) 252# define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24) 253#define AFMT_MPEG_INFO0 0x7094 254# define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 255# define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) 256# define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) 257# define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) 258#define AFMT_MPEG_INFO1 0x7098 259# define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) 260# define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8) 261# define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12) 262#define AFMT_GENERIC0_HDR 0x709c 263#define AFMT_GENERIC0_0 0x70a0 264#define AFMT_GENERIC0_1 0x70a4 265#define AFMT_GENERIC0_2 0x70a8 266#define AFMT_GENERIC0_3 0x70ac 267#define AFMT_GENERIC0_4 0x70b0 268#define AFMT_GENERIC0_5 0x70b4 269#define AFMT_GENERIC0_6 0x70b8 270#define AFMT_GENERIC1_HDR 0x70bc 271#define AFMT_GENERIC1_0 0x70c0 272#define AFMT_GENERIC1_1 0x70c4 273#define AFMT_GENERIC1_2 0x70c8 274#define AFMT_GENERIC1_3 0x70cc 275#define AFMT_GENERIC1_4 0x70d0 276#define AFMT_GENERIC1_5 0x70d4 277#define AFMT_GENERIC1_6 0x70d8 278#define HDMI_ACR_32_0 0x70dc 279# define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12) 280#define HDMI_ACR_32_1 0x70e0 281# define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0) 282#define HDMI_ACR_44_0 0x70e4 283# define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12) 284#define HDMI_ACR_44_1 0x70e8 285# define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0) 286#define HDMI_ACR_48_0 0x70ec 287# define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) 288#define HDMI_ACR_48_1 0x70f0 289# define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0) 290#define HDMI_ACR_STATUS_0 0x70f4 291#define HDMI_ACR_STATUS_1 0x70f8 292#define AFMT_AUDIO_INFO0 0x70fc 293# define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 294# define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8) 295# define AFMT_AUDIO_INFO_CT(x) (((x) & 0xf) << 11) 296# define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16) 297# define AFMT_AUDIO_INFO_CXT(x) (((x) & 0x1f) << 24) 298#define AFMT_AUDIO_INFO1 0x7100 299# define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) 300# define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) 301# define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) 302# define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) 303# define AFMT_AUDIO_INFO_LFEBPL(x) (((x) & 3) << 16) 304#define AFMT_60958_0 0x7104 305# define AFMT_60958_CS_A(x) (((x) & 1) << 0) 306# define AFMT_60958_CS_B(x) (((x) & 1) << 1) 307# define AFMT_60958_CS_C(x) (((x) & 1) << 2) 308# define AFMT_60958_CS_D(x) (((x) & 3) << 3) 309# define AFMT_60958_CS_MODE(x) (((x) & 3) << 6) 310# define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) 311# define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) 312# define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) 313# define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) 314# define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) 315#define AFMT_60958_1 0x7108 316# define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) 317# define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) 318# define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16) 319# define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18) 320# define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) 321#define AFMT_AUDIO_CRC_CONTROL 0x710c 322# define AFMT_AUDIO_CRC_EN (1 << 0) 323#define AFMT_RAMP_CONTROL0 0x7110 324# define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) 325# define AFMT_RAMP_DATA_SIGN (1U << 31) 326#define AFMT_RAMP_CONTROL1 0x7114 327# define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) 328# define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24) 329#define AFMT_RAMP_CONTROL2 0x7118 330# define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) 331#define AFMT_RAMP_CONTROL3 0x711c 332# define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) 333#define AFMT_60958_2 0x7120 334# define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) 335# define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) 336# define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) 337# define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) 338# define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) 339# define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) 340#define AFMT_STATUS 0x7128 341# define AFMT_AUDIO_ENABLE (1 << 4) 342# define AFMT_AUDIO_HBR_ENABLE (1 << 8) 343# define AFMT_AZ_FORMAT_WTRIG (1 << 28) 344# define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) 345# define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) 346#define AFMT_AUDIO_PACKET_CONTROL 0x712c 347# define AFMT_AUDIO_SAMPLE_SEND (1 << 0) 348# define AFMT_RESET_FIFO_WHEN_AUDIO_DIS (1 << 11) /* set to 1 */ 349# define AFMT_AUDIO_TEST_EN (1 << 12) 350# define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) 351# define AFMT_60958_CS_UPDATE (1 << 26) 352# define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) 353# define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) 354# define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) 355# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) 356#define AFMT_VBI_PACKET_CONTROL 0x7130 357# define AFMT_GENERIC0_UPDATE (1 << 2) 358#define AFMT_INFOFRAME_CONTROL0 0x7134 359# define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - afmt regs */ 360# define AFMT_AUDIO_INFO_UPDATE (1 << 7) 361# define AFMT_MPEG_INFO_UPDATE (1 << 10) 362#define AFMT_GENERIC0_7 0x7138 363 364/* DCE4/5 ELD audio interface */ 365#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x5f84 /* LPCM */ 366#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x5f88 /* AC3 */ 367#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x5f8c /* MPEG1 */ 368#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x5f90 /* MP3 */ 369#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x5f94 /* MPEG2 */ 370#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x5f98 /* AAC */ 371#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x5f9c /* DTS */ 372#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x5fa0 /* ATRAC */ 373#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x5fa4 /* one bit audio - leave at 0 (default) */ 374#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x5fa8 /* Dolby Digital */ 375#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x5fac /* DTS-HD */ 376#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x5fb0 /* MAT-MLP */ 377#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x5fb4 /* DTS */ 378#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x5fb8 /* WMA Pro */ 379# define MAX_CHANNELS(x) (((x) & 0x7) << 0) 380/* max channels minus one. 7 = 8 channels */ 381# define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) 382# define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) 383# define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ 384/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO 385 * bit0 = 32 kHz 386 * bit1 = 44.1 kHz 387 * bit2 = 48 kHz 388 * bit3 = 88.2 kHz 389 * bit4 = 96 kHz 390 * bit5 = 176.4 kHz 391 * bit6 = 192 kHz 392 */ 393 394#define AZ_HOT_PLUG_CONTROL 0x5e78 395# define AZ_FORCE_CODEC_WAKE (1 << 0) 396# define PIN0_JACK_DETECTION_ENABLE (1 << 4) 397# define PIN1_JACK_DETECTION_ENABLE (1 << 5) 398# define PIN2_JACK_DETECTION_ENABLE (1 << 6) 399# define PIN3_JACK_DETECTION_ENABLE (1 << 7) 400# define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8) 401# define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9) 402# define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10) 403# define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11) 404# define CODEC_HOT_PLUG_ENABLE (1 << 12) 405# define PIN0_AUDIO_ENABLED (1 << 24) 406# define PIN1_AUDIO_ENABLED (1 << 25) 407# define PIN2_AUDIO_ENABLED (1 << 26) 408# define PIN3_AUDIO_ENABLED (1 << 27) 409# define AUDIO_ENABLED (1U << 31) 410 411 412#define GC_USER_SHADER_PIPE_CONFIG 0x8954 413#define INACTIVE_QD_PIPES(x) ((x) << 8) 414#define INACTIVE_QD_PIPES_MASK 0x0000FF00 415#define INACTIVE_SIMDS(x) ((x) << 16) 416#define INACTIVE_SIMDS_MASK 0x00FF0000 417 418#define GRBM_CNTL 0x8000 419#define GRBM_READ_TIMEOUT(x) ((x) << 0) 420#define GRBM_SOFT_RESET 0x8020 421#define SOFT_RESET_CP (1 << 0) 422#define SOFT_RESET_CB (1 << 1) 423#define SOFT_RESET_DB (1 << 3) 424#define SOFT_RESET_PA (1 << 5) 425#define SOFT_RESET_SC (1 << 6) 426#define SOFT_RESET_SPI (1 << 8) 427#define SOFT_RESET_SH (1 << 9) 428#define SOFT_RESET_SX (1 << 10) 429#define SOFT_RESET_TC (1 << 11) 430#define SOFT_RESET_TA (1 << 12) 431#define SOFT_RESET_VC (1 << 13) 432#define SOFT_RESET_VGT (1 << 14) 433 434#define GRBM_STATUS 0x8010 435#define CMDFIFO_AVAIL_MASK 0x0000000F 436#define SRBM_RQ_PENDING (1 << 5) 437#define CF_RQ_PENDING (1 << 7) 438#define PF_RQ_PENDING (1 << 8) 439#define GRBM_EE_BUSY (1 << 10) 440#define SX_CLEAN (1 << 11) 441#define DB_CLEAN (1 << 12) 442#define CB_CLEAN (1 << 13) 443#define TA_BUSY (1 << 14) 444#define VGT_BUSY_NO_DMA (1 << 16) 445#define VGT_BUSY (1 << 17) 446#define SX_BUSY (1 << 20) 447#define SH_BUSY (1 << 21) 448#define SPI_BUSY (1 << 22) 449#define SC_BUSY (1 << 24) 450#define PA_BUSY (1 << 25) 451#define DB_BUSY (1 << 26) 452#define CP_COHERENCY_BUSY (1 << 28) 453#define CP_BUSY (1 << 29) 454#define CB_BUSY (1 << 30) 455#define GUI_ACTIVE (1U << 31) 456#define GRBM_STATUS_SE0 0x8014 457#define GRBM_STATUS_SE1 0x8018 458#define SE_SX_CLEAN (1 << 0) 459#define SE_DB_CLEAN (1 << 1) 460#define SE_CB_CLEAN (1 << 2) 461#define SE_TA_BUSY (1 << 25) 462#define SE_SX_BUSY (1 << 26) 463#define SE_SPI_BUSY (1 << 27) 464#define SE_SH_BUSY (1 << 28) 465#define SE_SC_BUSY (1 << 29) 466#define SE_DB_BUSY (1 << 30) 467#define SE_CB_BUSY (1U << 31) 468/* evergreen */ 469#define CG_THERMAL_CTRL 0x72c 470#define TOFFSET_MASK 0x00003FE0 471#define TOFFSET_SHIFT 5 472#define CG_MULT_THERMAL_STATUS 0x740 473#define ASIC_T(x) ((x) << 16) 474#define ASIC_T_MASK 0x07FF0000 475#define ASIC_T_SHIFT 16 476#define CG_TS0_STATUS 0x760 477#define TS0_ADC_DOUT_MASK 0x000003FF 478#define TS0_ADC_DOUT_SHIFT 0 479/* APU */ 480#define CG_THERMAL_STATUS 0x678 481 482#define HDP_HOST_PATH_CNTL 0x2C00 483#define HDP_NONSURFACE_BASE 0x2C04 484#define HDP_NONSURFACE_INFO 0x2C08 485#define HDP_NONSURFACE_SIZE 0x2C0C 486#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 487#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 488#define HDP_TILING_CONFIG 0x2F3C 489 490#define MC_SHARED_CHMAP 0x2004 491#define NOOFCHAN_SHIFT 12 492#define NOOFCHAN_MASK 0x00003000 493#define MC_SHARED_CHREMAP 0x2008 494 495#define MC_SHARED_BLACKOUT_CNTL 0x20ac 496#define BLACKOUT_MODE_MASK 0x00000007 497 498#define MC_ARB_RAMCFG 0x2760 499#define NOOFBANK_SHIFT 0 500#define NOOFBANK_MASK 0x00000003 501#define NOOFRANK_SHIFT 2 502#define NOOFRANK_MASK 0x00000004 503#define NOOFROWS_SHIFT 3 504#define NOOFROWS_MASK 0x00000038 505#define NOOFCOLS_SHIFT 6 506#define NOOFCOLS_MASK 0x000000C0 507#define CHANSIZE_SHIFT 8 508#define CHANSIZE_MASK 0x00000100 509#define BURSTLENGTH_SHIFT 9 510#define BURSTLENGTH_MASK 0x00000200 511#define CHANSIZE_OVERRIDE (1 << 11) 512#define FUS_MC_ARB_RAMCFG 0x2768 513#define MC_VM_AGP_TOP 0x2028 514#define MC_VM_AGP_BOT 0x202C 515#define MC_VM_AGP_BASE 0x2030 516#define MC_VM_FB_LOCATION 0x2024 517#define MC_FUS_VM_FB_OFFSET 0x2898 518#define MC_VM_MB_L1_TLB0_CNTL 0x2234 519#define MC_VM_MB_L1_TLB1_CNTL 0x2238 520#define MC_VM_MB_L1_TLB2_CNTL 0x223C 521#define MC_VM_MB_L1_TLB3_CNTL 0x2240 522#define ENABLE_L1_TLB (1 << 0) 523#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 524#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 525#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 526#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 527#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 528#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 529#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) 530#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) 531#define MC_VM_MD_L1_TLB0_CNTL 0x2654 532#define MC_VM_MD_L1_TLB1_CNTL 0x2658 533#define MC_VM_MD_L1_TLB2_CNTL 0x265C 534#define MC_VM_MD_L1_TLB3_CNTL 0x2698 535 536#define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C 537#define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660 538#define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664 539 540#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 541#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 542#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 543 544#define PA_CL_ENHANCE 0x8A14 545#define CLIP_VTX_REORDER_ENA (1 << 0) 546#define NUM_CLIP_SEQ(x) ((x) << 1) 547#define PA_SC_ENHANCE 0x8BF0 548#define PA_SC_AA_CONFIG 0x28C04 549#define MSAA_NUM_SAMPLES_SHIFT 0 550#define MSAA_NUM_SAMPLES_MASK 0x3 551#define PA_SC_CLIPRECT_RULE 0x2820C 552#define PA_SC_EDGERULE 0x28230 553#define PA_SC_FIFO_SIZE 0x8BCC 554#define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 555#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 556#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 557#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 558#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 559#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 560#define PA_SC_LINE_STIPPLE 0x28A0C 561#define PA_SU_LINE_STIPPLE_VALUE 0x8A60 562#define PA_SC_LINE_STIPPLE_STATE 0x8B10 563 564#define SCRATCH_REG0 0x8500 565#define SCRATCH_REG1 0x8504 566#define SCRATCH_REG2 0x8508 567#define SCRATCH_REG3 0x850C 568#define SCRATCH_REG4 0x8510 569#define SCRATCH_REG5 0x8514 570#define SCRATCH_REG6 0x8518 571#define SCRATCH_REG7 0x851C 572#define SCRATCH_UMSK 0x8540 573#define SCRATCH_ADDR 0x8544 574 575#define SMX_SAR_CTL0 0xA008 576#define SMX_DC_CTL0 0xA020 577#define USE_HASH_FUNCTION (1 << 0) 578#define NUMBER_OF_SETS(x) ((x) << 1) 579#define FLUSH_ALL_ON_EVENT (1 << 10) 580#define STALL_ON_EVENT (1 << 11) 581#define SMX_EVENT_CTL 0xA02C 582#define ES_FLUSH_CTL(x) ((x) << 0) 583#define GS_FLUSH_CTL(x) ((x) << 3) 584#define ACK_FLUSH_CTL(x) ((x) << 6) 585#define SYNC_FLUSH_CTL (1 << 8) 586 587#define SPI_CONFIG_CNTL 0x9100 588#define GPR_WRITE_PRIORITY(x) ((x) << 0) 589#define SPI_CONFIG_CNTL_1 0x913C 590#define VTX_DONE_DELAY(x) ((x) << 0) 591#define INTERP_ONE_PRIM_PER_ROW (1 << 4) 592#define SPI_INPUT_Z 0x286D8 593#define SPI_PS_IN_CONTROL_0 0x286CC 594#define NUM_INTERP(x) ((x)<<0) 595#define POSITION_ENA (1<<8) 596#define POSITION_CENTROID (1<<9) 597#define POSITION_ADDR(x) ((x)<<10) 598#define PARAM_GEN(x) ((x)<<15) 599#define PARAM_GEN_ADDR(x) ((x)<<19) 600#define BARYC_SAMPLE_CNTL(x) ((x)<<26) 601#define PERSP_GRADIENT_ENA (1<<28) 602#define LINEAR_GRADIENT_ENA (1<<29) 603#define POSITION_SAMPLE (1<<30) 604#define BARYC_AT_SAMPLE_ENA (1<<31) 605 606#define SQ_CONFIG 0x8C00 607#define VC_ENABLE (1 << 0) 608#define EXPORT_SRC_C (1 << 1) 609#define CS_PRIO(x) ((x) << 18) 610#define LS_PRIO(x) ((x) << 20) 611#define HS_PRIO(x) ((x) << 22) 612#define PS_PRIO(x) ((x) << 24) 613#define VS_PRIO(x) ((x) << 26) 614#define GS_PRIO(x) ((x) << 28) 615#define ES_PRIO(x) ((x) << 30) 616#define SQ_GPR_RESOURCE_MGMT_1 0x8C04 617#define NUM_PS_GPRS(x) ((x) << 0) 618#define NUM_VS_GPRS(x) ((x) << 16) 619#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 620#define SQ_GPR_RESOURCE_MGMT_2 0x8C08 621#define NUM_GS_GPRS(x) ((x) << 0) 622#define NUM_ES_GPRS(x) ((x) << 16) 623#define SQ_GPR_RESOURCE_MGMT_3 0x8C0C 624#define NUM_HS_GPRS(x) ((x) << 0) 625#define NUM_LS_GPRS(x) ((x) << 16) 626#define SQ_GLOBAL_GPR_RESOURCE_MGMT_1 0x8C10 627#define SQ_GLOBAL_GPR_RESOURCE_MGMT_2 0x8C14 628#define SQ_THREAD_RESOURCE_MGMT 0x8C18 629#define NUM_PS_THREADS(x) ((x) << 0) 630#define NUM_VS_THREADS(x) ((x) << 8) 631#define NUM_GS_THREADS(x) ((x) << 16) 632#define NUM_ES_THREADS(x) ((x) << 24) 633#define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C 634#define NUM_HS_THREADS(x) ((x) << 0) 635#define NUM_LS_THREADS(x) ((x) << 8) 636#define SQ_STACK_RESOURCE_MGMT_1 0x8C20 637#define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 638#define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 639#define SQ_STACK_RESOURCE_MGMT_2 0x8C24 640#define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 641#define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 642#define SQ_STACK_RESOURCE_MGMT_3 0x8C28 643#define NUM_HS_STACK_ENTRIES(x) ((x) << 0) 644#define NUM_LS_STACK_ENTRIES(x) ((x) << 16) 645#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C 646#define SQ_DYN_GPR_SIMD_LOCK_EN 0x8D94 647#define SQ_STATIC_THREAD_MGMT_1 0x8E20 648#define SQ_STATIC_THREAD_MGMT_2 0x8E24 649#define SQ_STATIC_THREAD_MGMT_3 0x8E28 650#define SQ_LDS_RESOURCE_MGMT 0x8E2C 651 652#define SQ_MS_FIFO_SIZES 0x8CF0 653#define CACHE_FIFO_SIZE(x) ((x) << 0) 654#define FETCH_FIFO_HIWATER(x) ((x) << 8) 655#define DONE_FIFO_HIWATER(x) ((x) << 16) 656#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 657 658#define SX_DEBUG_1 0x9058 659#define ENABLE_NEW_SMX_ADDRESS (1 << 16) 660#define SX_EXPORT_BUFFER_SIZES 0x900C 661#define COLOR_BUFFER_SIZE(x) ((x) << 0) 662#define POSITION_BUFFER_SIZE(x) ((x) << 8) 663#define SMX_BUFFER_SIZE(x) ((x) << 16) 664#define SX_MEMORY_EXPORT_BASE 0x9010 665#define SX_MISC 0x28350 666 667#define CB_PERF_CTR0_SEL_0 0x9A20 668#define CB_PERF_CTR0_SEL_1 0x9A24 669#define CB_PERF_CTR1_SEL_0 0x9A28 670#define CB_PERF_CTR1_SEL_1 0x9A2C 671#define CB_PERF_CTR2_SEL_0 0x9A30 672#define CB_PERF_CTR2_SEL_1 0x9A34 673#define CB_PERF_CTR3_SEL_0 0x9A38 674#define CB_PERF_CTR3_SEL_1 0x9A3C 675 676#define TA_CNTL_AUX 0x9508 677#define DISABLE_CUBE_WRAP (1 << 0) 678#define DISABLE_CUBE_ANISO (1 << 1) 679#define SYNC_GRADIENT (1 << 24) 680#define SYNC_WALKER (1 << 25) 681#define SYNC_ALIGNER (1 << 26) 682 683#define TCP_CHAN_STEER_LO 0x960c 684#define TCP_CHAN_STEER_HI 0x9610 685 686#define VGT_CACHE_INVALIDATION 0x88C4 687#define CACHE_INVALIDATION(x) ((x) << 0) 688#define VC_ONLY 0 689#define TC_ONLY 1 690#define VC_AND_TC 2 691#define AUTO_INVLD_EN(x) ((x) << 6) 692#define NO_AUTO 0 693#define ES_AUTO 1 694#define GS_AUTO 2 695#define ES_AND_GS_AUTO 3 696#define VGT_GS_VERTEX_REUSE 0x88D4 697#define VGT_NUM_INSTANCES 0x8974 698#define VGT_OUT_DEALLOC_CNTL 0x28C5C 699#define DEALLOC_DIST_MASK 0x0000007F 700#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 701#define VTX_REUSE_DEPTH_MASK 0x000000FF 702 703#define VM_CONTEXT0_CNTL 0x1410 704#define ENABLE_CONTEXT (1 << 0) 705#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 706#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 707#define VM_CONTEXT1_CNTL 0x1414 708#define VM_CONTEXT1_CNTL2 0x1434 709#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 710#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 711#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 712#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 713#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 714#define REQUEST_TYPE(x) (((x) & 0xf) << 0) 715#define RESPONSE_TYPE_MASK 0x000000F0 716#define RESPONSE_TYPE_SHIFT 4 717#define VM_L2_CNTL 0x1400 718#define ENABLE_L2_CACHE (1 << 0) 719#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 720#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 721#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 722#define VM_L2_CNTL2 0x1404 723#define INVALIDATE_ALL_L1_TLBS (1 << 0) 724#define INVALIDATE_L2_CACHE (1 << 1) 725#define VM_L2_CNTL3 0x1408 726#define BANK_SELECT(x) ((x) << 0) 727#define CACHE_UPDATE_MODE(x) ((x) << 6) 728#define VM_L2_STATUS 0x140C 729#define L2_BUSY (1 << 0) 730#define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 731#define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 732 733#define WAIT_UNTIL 0x8040 734 735#define SRBM_STATUS 0x0E50 736#define SRBM_SOFT_RESET 0x0E60 737#define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6 738#define SOFT_RESET_BIF (1 << 1) 739#define SOFT_RESET_CG (1 << 2) 740#define SOFT_RESET_DC (1 << 5) 741#define SOFT_RESET_GRBM (1 << 8) 742#define SOFT_RESET_HDP (1 << 9) 743#define SOFT_RESET_IH (1 << 10) 744#define SOFT_RESET_MC (1 << 11) 745#define SOFT_RESET_RLC (1 << 13) 746#define SOFT_RESET_ROM (1 << 14) 747#define SOFT_RESET_SEM (1 << 15) 748#define SOFT_RESET_VMC (1 << 17) 749#define SOFT_RESET_DMA (1 << 20) 750#define SOFT_RESET_TST (1 << 21) 751#define SOFT_RESET_REGBB (1 << 22) 752#define SOFT_RESET_ORB (1 << 23) 753 754/* display watermarks */ 755#define DC_LB_MEMORY_SPLIT 0x6b0c 756#define PRIORITY_A_CNT 0x6b18 757#define PRIORITY_MARK_MASK 0x7fff 758#define PRIORITY_OFF (1 << 16) 759#define PRIORITY_ALWAYS_ON (1 << 20) 760#define PRIORITY_B_CNT 0x6b1c 761#define PIPE0_ARBITRATION_CONTROL3 0x0bf0 762# define LATENCY_WATERMARK_MASK(x) ((x) << 16) 763#define PIPE0_LATENCY_CONTROL 0x0bf4 764# define LATENCY_LOW_WATERMARK(x) ((x) << 0) 765# define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 766 767#define IH_RB_CNTL 0x3e00 768# define IH_RB_ENABLE (1 << 0) 769# define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 770# define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 771# define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 772# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 773# define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 774# define IH_WPTR_OVERFLOW_CLEAR (1U << 31) 775#define IH_RB_BASE 0x3e04 776#define IH_RB_RPTR 0x3e08 777#define IH_RB_WPTR 0x3e0c 778# define RB_OVERFLOW (1 << 0) 779# define WPTR_OFFSET_MASK 0x3fffc 780#define IH_RB_WPTR_ADDR_HI 0x3e10 781#define IH_RB_WPTR_ADDR_LO 0x3e14 782#define IH_CNTL 0x3e18 783# define ENABLE_INTR (1 << 0) 784# define IH_MC_SWAP(x) ((x) << 1) 785# define IH_MC_SWAP_NONE 0 786# define IH_MC_SWAP_16BIT 1 787# define IH_MC_SWAP_32BIT 2 788# define IH_MC_SWAP_64BIT 3 789# define RPTR_REARM (1 << 4) 790# define MC_WRREQ_CREDIT(x) ((x) << 15) 791# define MC_WR_CLEAN_CNT(x) ((x) << 20) 792 793#define CP_INT_CNTL 0xc124 794# define CNTX_BUSY_INT_ENABLE (1 << 19) 795# define CNTX_EMPTY_INT_ENABLE (1 << 20) 796# define SCRATCH_INT_ENABLE (1 << 25) 797# define TIME_STAMP_INT_ENABLE (1 << 26) 798# define IB2_INT_ENABLE (1 << 29) 799# define IB1_INT_ENABLE (1 << 30) 800# define RB_INT_ENABLE (1U << 31) 801#define CP_INT_STATUS 0xc128 802# define SCRATCH_INT_STAT (1 << 25) 803# define TIME_STAMP_INT_STAT (1 << 26) 804# define IB2_INT_STAT (1 << 29) 805# define IB1_INT_STAT (1 << 30) 806# define RB_INT_STAT (1U << 31) 807 808#define GRBM_INT_CNTL 0x8060 809# define RDERR_INT_ENABLE (1 << 0) 810# define GUI_IDLE_INT_ENABLE (1 << 19) 811 812/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 813#define CRTC_STATUS_FRAME_COUNT 0x6e98 814 815/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ 816#define VLINE_STATUS 0x6bb8 817# define VLINE_OCCURRED (1 << 0) 818# define VLINE_ACK (1 << 4) 819# define VLINE_STAT (1 << 12) 820# define VLINE_INTERRUPT (1 << 16) 821# define VLINE_INTERRUPT_TYPE (1 << 17) 822/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ 823#define VBLANK_STATUS 0x6bbc 824# define VBLANK_OCCURRED (1 << 0) 825# define VBLANK_ACK (1 << 4) 826# define VBLANK_STAT (1 << 12) 827# define VBLANK_INTERRUPT (1 << 16) 828# define VBLANK_INTERRUPT_TYPE (1 << 17) 829 830/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ 831#define INT_MASK 0x6b40 832# define VBLANK_INT_MASK (1 << 0) 833# define VLINE_INT_MASK (1 << 4) 834 835#define DISP_INTERRUPT_STATUS 0x60f4 836# define LB_D1_VLINE_INTERRUPT (1 << 2) 837# define LB_D1_VBLANK_INTERRUPT (1 << 3) 838# define DC_HPD1_INTERRUPT (1 << 17) 839# define DC_HPD1_RX_INTERRUPT (1 << 18) 840# define DACA_AUTODETECT_INTERRUPT (1 << 22) 841# define DACB_AUTODETECT_INTERRUPT (1 << 23) 842# define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 843# define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 844#define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 845# define LB_D2_VLINE_INTERRUPT (1 << 2) 846# define LB_D2_VBLANK_INTERRUPT (1 << 3) 847# define DC_HPD2_INTERRUPT (1 << 17) 848# define DC_HPD2_RX_INTERRUPT (1 << 18) 849# define DISP_TIMER_INTERRUPT (1 << 24) 850#define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 851# define LB_D3_VLINE_INTERRUPT (1 << 2) 852# define LB_D3_VBLANK_INTERRUPT (1 << 3) 853# define DC_HPD3_INTERRUPT (1 << 17) 854# define DC_HPD3_RX_INTERRUPT (1 << 18) 855#define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 856# define LB_D4_VLINE_INTERRUPT (1 << 2) 857# define LB_D4_VBLANK_INTERRUPT (1 << 3) 858# define DC_HPD4_INTERRUPT (1 << 17) 859# define DC_HPD4_RX_INTERRUPT (1 << 18) 860#define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 861# define LB_D5_VLINE_INTERRUPT (1 << 2) 862# define LB_D5_VBLANK_INTERRUPT (1 << 3) 863# define DC_HPD5_INTERRUPT (1 << 17) 864# define DC_HPD5_RX_INTERRUPT (1 << 18) 865#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 866# define LB_D6_VLINE_INTERRUPT (1 << 2) 867# define LB_D6_VBLANK_INTERRUPT (1 << 3) 868# define DC_HPD6_INTERRUPT (1 << 17) 869# define DC_HPD6_RX_INTERRUPT (1 << 18) 870 871/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 872#define GRPH_INT_STATUS 0x6858 873# define GRPH_PFLIP_INT_OCCURRED (1 << 0) 874# define GRPH_PFLIP_INT_CLEAR (1 << 8) 875/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 876#define GRPH_INT_CONTROL 0x685c 877# define GRPH_PFLIP_INT_MASK (1 << 0) 878# define GRPH_PFLIP_INT_TYPE (1 << 8) 879 880#define DACA_AUTODETECT_INT_CONTROL 0x66c8 881#define DACB_AUTODETECT_INT_CONTROL 0x67c8 882 883#define DC_HPD1_INT_STATUS 0x601c 884#define DC_HPD2_INT_STATUS 0x6028 885#define DC_HPD3_INT_STATUS 0x6034 886#define DC_HPD4_INT_STATUS 0x6040 887#define DC_HPD5_INT_STATUS 0x604c 888#define DC_HPD6_INT_STATUS 0x6058 889# define DC_HPDx_INT_STATUS (1 << 0) 890# define DC_HPDx_SENSE (1 << 1) 891# define DC_HPDx_RX_INT_STATUS (1 << 8) 892 893#define DC_HPD1_INT_CONTROL 0x6020 894#define DC_HPD2_INT_CONTROL 0x602c 895#define DC_HPD3_INT_CONTROL 0x6038 896#define DC_HPD4_INT_CONTROL 0x6044 897#define DC_HPD5_INT_CONTROL 0x6050 898#define DC_HPD6_INT_CONTROL 0x605c 899# define DC_HPDx_INT_ACK (1 << 0) 900# define DC_HPDx_INT_POLARITY (1 << 8) 901# define DC_HPDx_INT_EN (1 << 16) 902# define DC_HPDx_RX_INT_ACK (1 << 20) 903# define DC_HPDx_RX_INT_EN (1 << 24) 904 905#define DC_HPD1_CONTROL 0x6024 906#define DC_HPD2_CONTROL 0x6030 907#define DC_HPD3_CONTROL 0x603c 908#define DC_HPD4_CONTROL 0x6048 909#define DC_HPD5_CONTROL 0x6054 910#define DC_HPD6_CONTROL 0x6060 911# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 912# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 913# define DC_HPDx_EN (1 << 28) 914 915/* ASYNC DMA */ 916#define DMA_RB_RPTR 0xd008 917#define DMA_RB_WPTR 0xd00c 918 919#define DMA_CNTL 0xd02c 920# define TRAP_ENABLE (1 << 0) 921# define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 922# define SEM_WAIT_INT_ENABLE (1 << 2) 923# define DATA_SWAP_ENABLE (1 << 3) 924# define FENCE_SWAP_ENABLE (1 << 4) 925# define CTXEMPTY_INT_ENABLE (1 << 28) 926#define DMA_TILING_CONFIG 0xD0B8 927 928#define CAYMAN_DMA1_CNTL 0xd82c 929 930/* async DMA packets */ 931#define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ 932 (((t) & 0x1) << 23) | \ 933 (((s) & 0x1) << 22) | \ 934 (((n) & 0xFFFFF) << 0)) 935/* async DMA Packet types */ 936#define DMA_PACKET_WRITE 0x2 937#define DMA_PACKET_COPY 0x3 938#define DMA_PACKET_INDIRECT_BUFFER 0x4 939#define DMA_PACKET_SEMAPHORE 0x5 940#define DMA_PACKET_FENCE 0x6 941#define DMA_PACKET_TRAP 0x7 942#define DMA_PACKET_SRBM_WRITE 0x9 943#define DMA_PACKET_CONSTANT_FILL 0xd 944#define DMA_PACKET_NOP 0xf 945 946/* PCIE link stuff */ 947#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 948#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 949# define LC_LINK_WIDTH_SHIFT 0 950# define LC_LINK_WIDTH_MASK 0x7 951# define LC_LINK_WIDTH_X0 0 952# define LC_LINK_WIDTH_X1 1 953# define LC_LINK_WIDTH_X2 2 954# define LC_LINK_WIDTH_X4 3 955# define LC_LINK_WIDTH_X8 4 956# define LC_LINK_WIDTH_X16 6 957# define LC_LINK_WIDTH_RD_SHIFT 4 958# define LC_LINK_WIDTH_RD_MASK 0x70 959# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 960# define LC_RECONFIG_NOW (1 << 8) 961# define LC_RENEGOTIATION_SUPPORT (1 << 9) 962# define LC_RENEGOTIATE_EN (1 << 10) 963# define LC_SHORT_RECONFIG_EN (1 << 11) 964# define LC_UPCONFIGURE_SUPPORT (1 << 12) 965# define LC_UPCONFIGURE_DIS (1 << 13) 966#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 967# define LC_GEN2_EN_STRAP (1 << 0) 968# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 969# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 970# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 971# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 972# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 973# define LC_CURRENT_DATA_RATE (1 << 11) 974# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 975# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 976# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 977# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 978#define MM_CFGREGS_CNTL 0x544c 979# define MM_WR_TO_CFG_EN (1 << 3) 980#define LINK_CNTL2 0x88 /* F0 */ 981# define TARGET_LINK_SPEED_MASK (0xf << 0) 982# define SELECTABLE_DEEMPHASIS (1 << 6) 983 984/* 985 * PM4 986 */ 987#define PACKET_TYPE0 0 988#define PACKET_TYPE1 1 989#define PACKET_TYPE2 2 990#define PACKET_TYPE3 3 991 992#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 993#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 994#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 995#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 996#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 997 (((reg) >> 2) & 0xFFFF) | \ 998 ((n) & 0x3FFF) << 16) 999#define CP_PACKET2 0x80000000 1000#define PACKET2_PAD_SHIFT 0 1001#define PACKET2_PAD_MASK (0x3fffffff << 0) 1002 1003#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 1004 1005#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 1006 (((op) & 0xFF) << 8) | \ 1007 ((n) & 0x3FFF) << 16) 1008 1009/* Packet 3 types */ 1010#define PACKET3_NOP 0x10 1011#define PACKET3_SET_BASE 0x11 1012#define PACKET3_CLEAR_STATE 0x12 1013#define PACKET3_INDEX_BUFFER_SIZE 0x13 1014#define PACKET3_DISPATCH_DIRECT 0x15 1015#define PACKET3_DISPATCH_INDIRECT 0x16 1016#define PACKET3_INDIRECT_BUFFER_END 0x17 1017#define PACKET3_MODE_CONTROL 0x18 1018#define PACKET3_SET_PREDICATION 0x20 1019#define PACKET3_REG_RMW 0x21 1020#define PACKET3_COND_EXEC 0x22 1021#define PACKET3_PRED_EXEC 0x23 1022#define PACKET3_DRAW_INDIRECT 0x24 1023#define PACKET3_DRAW_INDEX_INDIRECT 0x25 1024#define PACKET3_INDEX_BASE 0x26 1025#define PACKET3_DRAW_INDEX_2 0x27 1026#define PACKET3_CONTEXT_CONTROL 0x28 1027#define PACKET3_DRAW_INDEX_OFFSET 0x29 1028#define PACKET3_INDEX_TYPE 0x2A 1029#define PACKET3_DRAW_INDEX 0x2B 1030#define PACKET3_DRAW_INDEX_AUTO 0x2D 1031#define PACKET3_DRAW_INDEX_IMMD 0x2E 1032#define PACKET3_NUM_INSTANCES 0x2F 1033#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 1034#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1035#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 1036#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 1037#define PACKET3_MEM_SEMAPHORE 0x39 1038#define PACKET3_MPEG_INDEX 0x3A 1039#define PACKET3_COPY_DW 0x3B 1040#define PACKET3_WAIT_REG_MEM 0x3C 1041#define PACKET3_MEM_WRITE 0x3D 1042#define PACKET3_INDIRECT_BUFFER 0x32 1043#define PACKET3_CP_DMA 0x41 1044/* 1. header 1045 * 2. SRC_ADDR_LO or DATA [31:0] 1046 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | 1047 * SRC_ADDR_HI [7:0] 1048 * 4. DST_ADDR_LO [31:0] 1049 * 5. DST_ADDR_HI [7:0] 1050 * 6. COMMAND [29:22] | BYTE_COUNT [20:0] 1051 */ 1052# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 1053 /* 0 - SRC_ADDR 1054 * 1 - GDS 1055 */ 1056# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) 1057 /* 0 - ME 1058 * 1 - PFP 1059 */ 1060# define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) 1061 /* 0 - SRC_ADDR 1062 * 1 - GDS 1063 * 2 - DATA 1064 */ 1065# define PACKET3_CP_DMA_CP_SYNC (1U << 31) 1066/* COMMAND */ 1067# define PACKET3_CP_DMA_DIS_WC (1 << 21) 1068# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) 1069 /* 0 - none 1070 * 1 - 8 in 16 1071 * 2 - 8 in 32 1072 * 3 - 8 in 64 1073 */ 1074# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 1075 /* 0 - none 1076 * 1 - 8 in 16 1077 * 2 - 8 in 32 1078 * 3 - 8 in 64 1079 */ 1080# define PACKET3_CP_DMA_CMD_SAS (1 << 26) 1081 /* 0 - memory 1082 * 1 - register 1083 */ 1084# define PACKET3_CP_DMA_CMD_DAS (1 << 27) 1085 /* 0 - memory 1086 * 1 - register 1087 */ 1088# define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 1089# define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 1090#define PACKET3_SURFACE_SYNC 0x43 1091# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1092# define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 1093# define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 1094# define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 1095# define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 1096# define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 1097# define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 1098# define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 1099# define PACKET3_DB_DEST_BASE_ENA (1 << 14) 1100# define PACKET3_CB8_DEST_BASE_ENA (1 << 15) 1101# define PACKET3_CB9_DEST_BASE_ENA (1 << 16) 1102# define PACKET3_CB10_DEST_BASE_ENA (1 << 17) 1103# define PACKET3_CB11_DEST_BASE_ENA (1 << 18) 1104# define PACKET3_FULL_CACHE_ENA (1 << 20) 1105# define PACKET3_TC_ACTION_ENA (1 << 23) 1106# define PACKET3_VC_ACTION_ENA (1 << 24) 1107# define PACKET3_CB_ACTION_ENA (1 << 25) 1108# define PACKET3_DB_ACTION_ENA (1 << 26) 1109# define PACKET3_SH_ACTION_ENA (1 << 27) 1110# define PACKET3_SX_ACTION_ENA (1 << 28) 1111#define PACKET3_ME_INITIALIZE 0x44 1112#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1113#define PACKET3_COND_WRITE 0x45 1114#define PACKET3_EVENT_WRITE 0x46 1115#define PACKET3_EVENT_WRITE_EOP 0x47 1116#define PACKET3_EVENT_WRITE_EOS 0x48 1117#define PACKET3_PREAMBLE_CNTL 0x4A 1118# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 1119# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 1120#define PACKET3_RB_OFFSET 0x4B 1121#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C 1122#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D 1123#define PACKET3_ALU_PS_CONST_UPDATE 0x4E 1124#define PACKET3_ALU_VS_CONST_UPDATE 0x4F 1125#define PACKET3_ONE_REG_WRITE 0x57 1126#define PACKET3_SET_CONFIG_REG 0x68 1127#define PACKET3_SET_CONFIG_REG_START 0x00008000 1128#define PACKET3_SET_CONFIG_REG_END 0x0000ac00 1129#define PACKET3_SET_CONTEXT_REG 0x69 1130#define PACKET3_SET_CONTEXT_REG_START 0x00028000 1131#define PACKET3_SET_CONTEXT_REG_END 0x00029000 1132#define PACKET3_SET_ALU_CONST 0x6A 1133/* alu const buffers only; no reg file */ 1134#define PACKET3_SET_BOOL_CONST 0x6B 1135#define PACKET3_SET_BOOL_CONST_START 0x0003a500 1136#define PACKET3_SET_BOOL_CONST_END 0x0003a518 1137#define PACKET3_SET_LOOP_CONST 0x6C 1138#define PACKET3_SET_LOOP_CONST_START 0x0003a200 1139#define PACKET3_SET_LOOP_CONST_END 0x0003a500 1140#define PACKET3_SET_RESOURCE 0x6D 1141#define PACKET3_SET_RESOURCE_START 0x00030000 1142#define PACKET3_SET_RESOURCE_END 0x00038000 1143#define PACKET3_SET_SAMPLER 0x6E 1144#define PACKET3_SET_SAMPLER_START 0x0003c000 1145#define PACKET3_SET_SAMPLER_END 0x0003c600 1146#define PACKET3_SET_CTL_CONST 0x6F 1147#define PACKET3_SET_CTL_CONST_START 0x0003cff0 1148#define PACKET3_SET_CTL_CONST_END 0x0003ff0c 1149#define PACKET3_SET_RESOURCE_OFFSET 0x70 1150#define PACKET3_SET_ALU_CONST_VS 0x71 1151#define PACKET3_SET_ALU_CONST_DI 0x72 1152#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 1153#define PACKET3_SET_RESOURCE_INDIRECT 0x74 1154#define PACKET3_SET_APPEND_CNT 0x75 1155 1156#define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c 1157#define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30) 1158#define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3) 1159#define SQ_TEX_VTX_INVALID_TEXTURE 0x0 1160#define SQ_TEX_VTX_INVALID_BUFFER 0x1 1161#define SQ_TEX_VTX_VALID_TEXTURE 0x2 1162#define SQ_TEX_VTX_VALID_BUFFER 0x3 1163 1164#define VGT_VTX_VECT_EJECT_REG 0x88b0 1165 1166#define SQ_CONST_MEM_BASE 0x8df8 1167 1168#define SQ_ESGS_RING_BASE 0x8c40 1169#define SQ_ESGS_RING_SIZE 0x8c44 1170#define SQ_GSVS_RING_BASE 0x8c48 1171#define SQ_GSVS_RING_SIZE 0x8c4c 1172#define SQ_ESTMP_RING_BASE 0x8c50 1173#define SQ_ESTMP_RING_SIZE 0x8c54 1174#define SQ_GSTMP_RING_BASE 0x8c58 1175#define SQ_GSTMP_RING_SIZE 0x8c5c 1176#define SQ_VSTMP_RING_BASE 0x8c60 1177#define SQ_VSTMP_RING_SIZE 0x8c64 1178#define SQ_PSTMP_RING_BASE 0x8c68 1179#define SQ_PSTMP_RING_SIZE 0x8c6c 1180#define SQ_LSTMP_RING_BASE 0x8e10 1181#define SQ_LSTMP_RING_SIZE 0x8e14 1182#define SQ_HSTMP_RING_BASE 0x8e18 1183#define SQ_HSTMP_RING_SIZE 0x8e1c 1184#define VGT_TF_RING_SIZE 0x8988 1185 1186#define SQ_ESGS_RING_ITEMSIZE 0x28900 1187#define SQ_GSVS_RING_ITEMSIZE 0x28904 1188#define SQ_ESTMP_RING_ITEMSIZE 0x28908 1189#define SQ_GSTMP_RING_ITEMSIZE 0x2890c 1190#define SQ_VSTMP_RING_ITEMSIZE 0x28910 1191#define SQ_PSTMP_RING_ITEMSIZE 0x28914 1192#define SQ_LSTMP_RING_ITEMSIZE 0x28830 1193#define SQ_HSTMP_RING_ITEMSIZE 0x28834 1194 1195#define SQ_GS_VERT_ITEMSIZE 0x2891c 1196#define SQ_GS_VERT_ITEMSIZE_1 0x28920 1197#define SQ_GS_VERT_ITEMSIZE_2 0x28924 1198#define SQ_GS_VERT_ITEMSIZE_3 0x28928 1199#define SQ_GSVS_RING_OFFSET_1 0x2892c 1200#define SQ_GSVS_RING_OFFSET_2 0x28930 1201#define SQ_GSVS_RING_OFFSET_3 0x28934 1202 1203#define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140 1204#define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80 1205 1206#define SQ_ALU_CONST_CACHE_PS_0 0x28940 1207#define SQ_ALU_CONST_CACHE_PS_1 0x28944 1208#define SQ_ALU_CONST_CACHE_PS_2 0x28948 1209#define SQ_ALU_CONST_CACHE_PS_3 0x2894c 1210#define SQ_ALU_CONST_CACHE_PS_4 0x28950 1211#define SQ_ALU_CONST_CACHE_PS_5 0x28954 1212#define SQ_ALU_CONST_CACHE_PS_6 0x28958 1213#define SQ_ALU_CONST_CACHE_PS_7 0x2895c 1214#define SQ_ALU_CONST_CACHE_PS_8 0x28960 1215#define SQ_ALU_CONST_CACHE_PS_9 0x28964 1216#define SQ_ALU_CONST_CACHE_PS_10 0x28968 1217#define SQ_ALU_CONST_CACHE_PS_11 0x2896c 1218#define SQ_ALU_CONST_CACHE_PS_12 0x28970 1219#define SQ_ALU_CONST_CACHE_PS_13 0x28974 1220#define SQ_ALU_CONST_CACHE_PS_14 0x28978 1221#define SQ_ALU_CONST_CACHE_PS_15 0x2897c 1222#define SQ_ALU_CONST_CACHE_VS_0 0x28980 1223#define SQ_ALU_CONST_CACHE_VS_1 0x28984 1224#define SQ_ALU_CONST_CACHE_VS_2 0x28988 1225#define SQ_ALU_CONST_CACHE_VS_3 0x2898c 1226#define SQ_ALU_CONST_CACHE_VS_4 0x28990 1227#define SQ_ALU_CONST_CACHE_VS_5 0x28994 1228#define SQ_ALU_CONST_CACHE_VS_6 0x28998 1229#define SQ_ALU_CONST_CACHE_VS_7 0x2899c 1230#define SQ_ALU_CONST_CACHE_VS_8 0x289a0 1231#define SQ_ALU_CONST_CACHE_VS_9 0x289a4 1232#define SQ_ALU_CONST_CACHE_VS_10 0x289a8 1233#define SQ_ALU_CONST_CACHE_VS_11 0x289ac 1234#define SQ_ALU_CONST_CACHE_VS_12 0x289b0 1235#define SQ_ALU_CONST_CACHE_VS_13 0x289b4 1236#define SQ_ALU_CONST_CACHE_VS_14 0x289b8 1237#define SQ_ALU_CONST_CACHE_VS_15 0x289bc 1238#define SQ_ALU_CONST_CACHE_GS_0 0x289c0 1239#define SQ_ALU_CONST_CACHE_GS_1 0x289c4 1240#define SQ_ALU_CONST_CACHE_GS_2 0x289c8 1241#define SQ_ALU_CONST_CACHE_GS_3 0x289cc 1242#define SQ_ALU_CONST_CACHE_GS_4 0x289d0 1243#define SQ_ALU_CONST_CACHE_GS_5 0x289d4 1244#define SQ_ALU_CONST_CACHE_GS_6 0x289d8 1245#define SQ_ALU_CONST_CACHE_GS_7 0x289dc 1246#define SQ_ALU_CONST_CACHE_GS_8 0x289e0 1247#define SQ_ALU_CONST_CACHE_GS_9 0x289e4 1248#define SQ_ALU_CONST_CACHE_GS_10 0x289e8 1249#define SQ_ALU_CONST_CACHE_GS_11 0x289ec 1250#define SQ_ALU_CONST_CACHE_GS_12 0x289f0 1251#define SQ_ALU_CONST_CACHE_GS_13 0x289f4 1252#define SQ_ALU_CONST_CACHE_GS_14 0x289f8 1253#define SQ_ALU_CONST_CACHE_GS_15 0x289fc 1254#define SQ_ALU_CONST_CACHE_HS_0 0x28f00 1255#define SQ_ALU_CONST_CACHE_HS_1 0x28f04 1256#define SQ_ALU_CONST_CACHE_HS_2 0x28f08 1257#define SQ_ALU_CONST_CACHE_HS_3 0x28f0c 1258#define SQ_ALU_CONST_CACHE_HS_4 0x28f10 1259#define SQ_ALU_CONST_CACHE_HS_5 0x28f14 1260#define SQ_ALU_CONST_CACHE_HS_6 0x28f18 1261#define SQ_ALU_CONST_CACHE_HS_7 0x28f1c 1262#define SQ_ALU_CONST_CACHE_HS_8 0x28f20 1263#define SQ_ALU_CONST_CACHE_HS_9 0x28f24 1264#define SQ_ALU_CONST_CACHE_HS_10 0x28f28 1265#define SQ_ALU_CONST_CACHE_HS_11 0x28f2c 1266#define SQ_ALU_CONST_CACHE_HS_12 0x28f30 1267#define SQ_ALU_CONST_CACHE_HS_13 0x28f34 1268#define SQ_ALU_CONST_CACHE_HS_14 0x28f38 1269#define SQ_ALU_CONST_CACHE_HS_15 0x28f3c 1270#define SQ_ALU_CONST_CACHE_LS_0 0x28f40 1271#define SQ_ALU_CONST_CACHE_LS_1 0x28f44 1272#define SQ_ALU_CONST_CACHE_LS_2 0x28f48 1273#define SQ_ALU_CONST_CACHE_LS_3 0x28f4c 1274#define SQ_ALU_CONST_CACHE_LS_4 0x28f50 1275#define SQ_ALU_CONST_CACHE_LS_5 0x28f54 1276#define SQ_ALU_CONST_CACHE_LS_6 0x28f58 1277#define SQ_ALU_CONST_CACHE_LS_7 0x28f5c 1278#define SQ_ALU_CONST_CACHE_LS_8 0x28f60 1279#define SQ_ALU_CONST_CACHE_LS_9 0x28f64 1280#define SQ_ALU_CONST_CACHE_LS_10 0x28f68 1281#define SQ_ALU_CONST_CACHE_LS_11 0x28f6c 1282#define SQ_ALU_CONST_CACHE_LS_12 0x28f70 1283#define SQ_ALU_CONST_CACHE_LS_13 0x28f74 1284#define SQ_ALU_CONST_CACHE_LS_14 0x28f78 1285#define SQ_ALU_CONST_CACHE_LS_15 0x28f7c 1286 1287#define PA_SC_SCREEN_SCISSOR_TL 0x28030 1288#define PA_SC_GENERIC_SCISSOR_TL 0x28240 1289#define PA_SC_WINDOW_SCISSOR_TL 0x28204 1290 1291#define VGT_PRIMITIVE_TYPE 0x8958 1292#define VGT_INDEX_TYPE 0x895C 1293 1294#define VGT_NUM_INDICES 0x8970 1295 1296#define VGT_COMPUTE_DIM_X 0x8990 1297#define VGT_COMPUTE_DIM_Y 0x8994 1298#define VGT_COMPUTE_DIM_Z 0x8998 1299#define VGT_COMPUTE_START_X 0x899C 1300#define VGT_COMPUTE_START_Y 0x89A0 1301#define VGT_COMPUTE_START_Z 0x89A4 1302#define VGT_COMPUTE_INDEX 0x89A8 1303#define VGT_COMPUTE_THREAD_GROUP_SIZE 0x89AC 1304#define VGT_HS_OFFCHIP_PARAM 0x89B0 1305 1306#define DB_DEBUG 0x9830 1307#define DB_DEBUG2 0x9834 1308#define DB_DEBUG3 0x9838 1309#define DB_DEBUG4 0x983C 1310#define DB_WATERMARKS 0x9854 1311#define DB_DEPTH_CONTROL 0x28800 1312#define R_028800_DB_DEPTH_CONTROL 0x028800 1313#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) 1314#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) 1315#define C_028800_STENCIL_ENABLE 0xFFFFFFFE 1316#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) 1317#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) 1318#define C_028800_Z_ENABLE 0xFFFFFFFD 1319#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) 1320#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) 1321#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB 1322#define S_028800_ZFUNC(x) (((x) & 0x7) << 4) 1323#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) 1324#define C_028800_ZFUNC 0xFFFFFF8F 1325#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) 1326#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) 1327#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F 1328#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) 1329#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) 1330#define C_028800_STENCILFUNC 0xFFFFF8FF 1331#define V_028800_STENCILFUNC_NEVER 0x00000000 1332#define V_028800_STENCILFUNC_LESS 0x00000001 1333#define V_028800_STENCILFUNC_EQUAL 0x00000002 1334#define V_028800_STENCILFUNC_LEQUAL 0x00000003 1335#define V_028800_STENCILFUNC_GREATER 0x00000004 1336#define V_028800_STENCILFUNC_NOTEQUAL 0x00000005 1337#define V_028800_STENCILFUNC_GEQUAL 0x00000006 1338#define V_028800_STENCILFUNC_ALWAYS 0x00000007 1339#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) 1340#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) 1341#define C_028800_STENCILFAIL 0xFFFFC7FF 1342#define V_028800_STENCIL_KEEP 0x00000000 1343#define V_028800_STENCIL_ZERO 0x00000001 1344#define V_028800_STENCIL_REPLACE 0x00000002 1345#define V_028800_STENCIL_INCR 0x00000003 1346#define V_028800_STENCIL_DECR 0x00000004 1347#define V_028800_STENCIL_INVERT 0x00000005 1348#define V_028800_STENCIL_INCR_WRAP 0x00000006 1349#define V_028800_STENCIL_DECR_WRAP 0x00000007 1350#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) 1351#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) 1352#define C_028800_STENCILZPASS 0xFFFE3FFF 1353#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) 1354#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) 1355#define C_028800_STENCILZFAIL 0xFFF1FFFF 1356#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) 1357#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) 1358#define C_028800_STENCILFUNC_BF 0xFF8FFFFF 1359#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) 1360#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) 1361#define C_028800_STENCILFAIL_BF 0xFC7FFFFF 1362#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) 1363#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) 1364#define C_028800_STENCILZPASS_BF 0xE3FFFFFF 1365#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) 1366#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) 1367#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF 1368#define DB_DEPTH_VIEW 0x28008 1369#define R_028008_DB_DEPTH_VIEW 0x00028008 1370#define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0) 1371#define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF) 1372#define C_028008_SLICE_START 0xFFFFF800 1373#define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13) 1374#define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 1375#define C_028008_SLICE_MAX 0xFF001FFF 1376#define DB_HTILE_DATA_BASE 0x28014 1377#define DB_HTILE_SURFACE 0x28abc 1378#define S_028ABC_HTILE_WIDTH(x) (((x) & 0x1) << 0) 1379#define G_028ABC_HTILE_WIDTH(x) (((x) >> 0) & 0x1) 1380#define C_028ABC_HTILE_WIDTH 0xFFFFFFFE 1381#define S_028ABC_HTILE_HEIGHT(x) (((x) & 0x1) << 1) 1382#define G_028ABC_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) 1383#define C_028ABC_HTILE_HEIGHT 0xFFFFFFFD 1384#define G_028ABC_LINEAR(x) (((x) >> 2) & 0x1) 1385#define DB_Z_INFO 0x28040 1386# define Z_ARRAY_MODE(x) ((x) << 4) 1387# define DB_TILE_SPLIT(x) (((x) & 0x7) << 8) 1388# define DB_NUM_BANKS(x) (((x) & 0x3) << 12) 1389# define DB_BANK_WIDTH(x) (((x) & 0x3) << 16) 1390# define DB_BANK_HEIGHT(x) (((x) & 0x3) << 20) 1391# define DB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24) 1392#define R_028040_DB_Z_INFO 0x028040 1393#define S_028040_FORMAT(x) (((x) & 0x3) << 0) 1394#define G_028040_FORMAT(x) (((x) >> 0) & 0x3) 1395#define C_028040_FORMAT 0xFFFFFFFC 1396#define V_028040_Z_INVALID 0x00000000 1397#define V_028040_Z_16 0x00000001 1398#define V_028040_Z_24 0x00000002 1399#define V_028040_Z_32_FLOAT 0x00000003 1400#define S_028040_ARRAY_MODE(x) (((x) & 0xF) << 4) 1401#define G_028040_ARRAY_MODE(x) (((x) >> 4) & 0xF) 1402#define C_028040_ARRAY_MODE 0xFFFFFF0F 1403#define S_028040_READ_SIZE(x) (((x) & 0x1) << 28) 1404#define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1) 1405#define C_028040_READ_SIZE 0xEFFFFFFF 1406#define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29) 1407#define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1) 1408#define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF 1409#define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) 1410#define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) 1411#define C_028040_ZRANGE_PRECISION 0x7FFFFFFF 1412#define S_028040_TILE_SPLIT(x) (((x) & 0x7) << 8) 1413#define G_028040_TILE_SPLIT(x) (((x) >> 8) & 0x7) 1414#define S_028040_NUM_BANKS(x) (((x) & 0x3) << 12) 1415#define G_028040_NUM_BANKS(x) (((x) >> 12) & 0x3) 1416#define S_028040_BANK_WIDTH(x) (((x) & 0x3) << 16) 1417#define G_028040_BANK_WIDTH(x) (((x) >> 16) & 0x3) 1418#define S_028040_BANK_HEIGHT(x) (((x) & 0x3) << 20) 1419#define G_028040_BANK_HEIGHT(x) (((x) >> 20) & 0x3) 1420#define S_028040_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24) 1421#define G_028040_MACRO_TILE_ASPECT(x) (((x) >> 24) & 0x3) 1422#define DB_STENCIL_INFO 0x28044 1423#define R_028044_DB_STENCIL_INFO 0x028044 1424#define S_028044_FORMAT(x) (((x) & 0x1) << 0) 1425#define G_028044_FORMAT(x) (((x) >> 0) & 0x1) 1426#define C_028044_FORMAT 0xFFFFFFFE 1427#define V_028044_STENCIL_INVALID 0 1428#define V_028044_STENCIL_8 1 1429#define G_028044_TILE_SPLIT(x) (((x) >> 8) & 0x7) 1430#define DB_Z_READ_BASE 0x28048 1431#define DB_STENCIL_READ_BASE 0x2804c 1432#define DB_Z_WRITE_BASE 0x28050 1433#define DB_STENCIL_WRITE_BASE 0x28054 1434#define DB_DEPTH_SIZE 0x28058 1435#define R_028058_DB_DEPTH_SIZE 0x028058 1436#define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0) 1437#define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF) 1438#define C_028058_PITCH_TILE_MAX 0xFFFFF800 1439#define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11) 1440#define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF) 1441#define C_028058_HEIGHT_TILE_MAX 0xFFC007FF 1442#define R_02805C_DB_DEPTH_SLICE 0x02805C 1443#define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) 1444#define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) 1445#define C_02805C_SLICE_TILE_MAX 0xFFC00000 1446 1447#define SQ_PGM_START_PS 0x28840 1448#define SQ_PGM_START_VS 0x2885c 1449#define SQ_PGM_START_GS 0x28874 1450#define SQ_PGM_START_ES 0x2888c 1451#define SQ_PGM_START_FS 0x288a4 1452#define SQ_PGM_START_HS 0x288b8 1453#define SQ_PGM_START_LS 0x288d0 1454 1455#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 1456#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 1457#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 1458#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 1459#define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0 1460#define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0 1461#define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0 1462#define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00 1463#define VGT_STRMOUT_CONFIG 0x28b94 1464#define VGT_STRMOUT_BUFFER_CONFIG 0x28b98 1465 1466#define CB_TARGET_MASK 0x28238 1467#define CB_SHADER_MASK 0x2823c 1468 1469#define GDS_ADDR_BASE 0x28720 1470 1471#define CB_IMMED0_BASE 0x28b9c 1472#define CB_IMMED1_BASE 0x28ba0 1473#define CB_IMMED2_BASE 0x28ba4 1474#define CB_IMMED3_BASE 0x28ba8 1475#define CB_IMMED4_BASE 0x28bac 1476#define CB_IMMED5_BASE 0x28bb0 1477#define CB_IMMED6_BASE 0x28bb4 1478#define CB_IMMED7_BASE 0x28bb8 1479#define CB_IMMED8_BASE 0x28bbc 1480#define CB_IMMED9_BASE 0x28bc0 1481#define CB_IMMED10_BASE 0x28bc4 1482#define CB_IMMED11_BASE 0x28bc8 1483 1484/* all 12 CB blocks have these regs */ 1485#define CB_COLOR0_BASE 0x28c60 1486#define CB_COLOR0_PITCH 0x28c64 1487#define CB_COLOR0_SLICE 0x28c68 1488#define CB_COLOR0_VIEW 0x28c6c 1489#define R_028C6C_CB_COLOR0_VIEW 0x00028C6C 1490#define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0) 1491#define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF) 1492#define C_028C6C_SLICE_START 0xFFFFF800 1493#define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13) 1494#define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 1495#define C_028C6C_SLICE_MAX 0xFF001FFF 1496#define R_028C70_CB_COLOR0_INFO 0x028C70 1497#define S_028C70_ENDIAN(x) (((x) & 0x3) << 0) 1498#define G_028C70_ENDIAN(x) (((x) >> 0) & 0x3) 1499#define C_028C70_ENDIAN 0xFFFFFFFC 1500#define S_028C70_FORMAT(x) (((x) & 0x3F) << 2) 1501#define G_028C70_FORMAT(x) (((x) >> 2) & 0x3F) 1502#define C_028C70_FORMAT 0xFFFFFF03 1503#define V_028C70_COLOR_INVALID 0x00000000 1504#define V_028C70_COLOR_8 0x00000001 1505#define V_028C70_COLOR_4_4 0x00000002 1506#define V_028C70_COLOR_3_3_2 0x00000003 1507#define V_028C70_COLOR_16 0x00000005 1508#define V_028C70_COLOR_16_FLOAT 0x00000006 1509#define V_028C70_COLOR_8_8 0x00000007 1510#define V_028C70_COLOR_5_6_5 0x00000008 1511#define V_028C70_COLOR_6_5_5 0x00000009 1512#define V_028C70_COLOR_1_5_5_5 0x0000000A 1513#define V_028C70_COLOR_4_4_4_4 0x0000000B 1514#define V_028C70_COLOR_5_5_5_1 0x0000000C 1515#define V_028C70_COLOR_32 0x0000000D 1516#define V_028C70_COLOR_32_FLOAT 0x0000000E 1517#define V_028C70_COLOR_16_16 0x0000000F 1518#define V_028C70_COLOR_16_16_FLOAT 0x00000010 1519#define V_028C70_COLOR_8_24 0x00000011 1520#define V_028C70_COLOR_8_24_FLOAT 0x00000012 1521#define V_028C70_COLOR_24_8 0x00000013 1522#define V_028C70_COLOR_24_8_FLOAT 0x00000014 1523#define V_028C70_COLOR_10_11_11 0x00000015 1524#define V_028C70_COLOR_10_11_11_FLOAT 0x00000016 1525#define V_028C70_COLOR_11_11_10 0x00000017 1526#define V_028C70_COLOR_11_11_10_FLOAT 0x00000018 1527#define V_028C70_COLOR_2_10_10_10 0x00000019 1528#define V_028C70_COLOR_8_8_8_8 0x0000001A 1529#define V_028C70_COLOR_10_10_10_2 0x0000001B 1530#define V_028C70_COLOR_X24_8_32_FLOAT 0x0000001C 1531#define V_028C70_COLOR_32_32 0x0000001D 1532#define V_028C70_COLOR_32_32_FLOAT 0x0000001E 1533#define V_028C70_COLOR_16_16_16_16 0x0000001F 1534#define V_028C70_COLOR_16_16_16_16_FLOAT 0x00000020 1535#define V_028C70_COLOR_32_32_32_32 0x00000022 1536#define V_028C70_COLOR_32_32_32_32_FLOAT 0x00000023 1537#define V_028C70_COLOR_32_32_32_FLOAT 0x00000030 1538#define S_028C70_ARRAY_MODE(x) (((x) & 0xF) << 8) 1539#define G_028C70_ARRAY_MODE(x) (((x) >> 8) & 0xF) 1540#define C_028C70_ARRAY_MODE 0xFFFFF0FF 1541#define V_028C70_ARRAY_LINEAR_GENERAL 0x00000000 1542#define V_028C70_ARRAY_LINEAR_ALIGNED 0x00000001 1543#define V_028C70_ARRAY_1D_TILED_THIN1 0x00000002 1544#define V_028C70_ARRAY_2D_TILED_THIN1 0x00000004 1545#define S_028C70_NUMBER_TYPE(x) (((x) & 0x7) << 12) 1546#define G_028C70_NUMBER_TYPE(x) (((x) >> 12) & 0x7) 1547#define C_028C70_NUMBER_TYPE 0xFFFF8FFF 1548#define V_028C70_NUMBER_UNORM 0x00000000 1549#define V_028C70_NUMBER_SNORM 0x00000001 1550#define V_028C70_NUMBER_USCALED 0x00000002 1551#define V_028C70_NUMBER_SSCALED 0x00000003 1552#define V_028C70_NUMBER_UINT 0x00000004 1553#define V_028C70_NUMBER_SINT 0x00000005 1554#define V_028C70_NUMBER_SRGB 0x00000006 1555#define V_028C70_NUMBER_FLOAT 0x00000007 1556#define S_028C70_COMP_SWAP(x) (((x) & 0x3) << 15) 1557#define G_028C70_COMP_SWAP(x) (((x) >> 15) & 0x3) 1558#define C_028C70_COMP_SWAP 0xFFFE7FFF 1559#define V_028C70_SWAP_STD 0x00000000 1560#define V_028C70_SWAP_ALT 0x00000001 1561#define V_028C70_SWAP_STD_REV 0x00000002 1562#define V_028C70_SWAP_ALT_REV 0x00000003 1563#define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 17) 1564#define G_028C70_FAST_CLEAR(x) (((x) >> 17) & 0x1) 1565#define C_028C70_FAST_CLEAR 0xFFFDFFFF 1566#define S_028C70_COMPRESSION(x) (((x) & 0x3) << 18) 1567#define G_028C70_COMPRESSION(x) (((x) >> 18) & 0x3) 1568#define C_028C70_COMPRESSION 0xFFF3FFFF 1569#define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 19) 1570#define G_028C70_BLEND_CLAMP(x) (((x) >> 19) & 0x1) 1571#define C_028C70_BLEND_CLAMP 0xFFF7FFFF 1572#define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 20) 1573#define G_028C70_BLEND_BYPASS(x) (((x) >> 20) & 0x1) 1574#define C_028C70_BLEND_BYPASS 0xFFEFFFFF 1575#define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 21) 1576#define G_028C70_SIMPLE_FLOAT(x) (((x) >> 21) & 0x1) 1577#define C_028C70_SIMPLE_FLOAT 0xFFDFFFFF 1578#define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 22) 1579#define G_028C70_ROUND_MODE(x) (((x) >> 22) & 0x1) 1580#define C_028C70_ROUND_MODE 0xFFBFFFFF 1581#define S_028C70_TILE_COMPACT(x) (((x) & 0x1) << 23) 1582#define G_028C70_TILE_COMPACT(x) (((x) >> 23) & 0x1) 1583#define C_028C70_TILE_COMPACT 0xFF7FFFFF 1584#define S_028C70_SOURCE_FORMAT(x) (((x) & 0x3) << 24) 1585#define G_028C70_SOURCE_FORMAT(x) (((x) >> 24) & 0x3) 1586#define C_028C70_SOURCE_FORMAT 0xFCFFFFFF 1587#define V_028C70_EXPORT_4C_32BPC 0x0 1588#define V_028C70_EXPORT_4C_16BPC 0x1 1589#define V_028C70_EXPORT_2C_32BPC 0x2 /* Do not use */ 1590#define S_028C70_RAT(x) (((x) & 0x1) << 26) 1591#define G_028C70_RAT(x) (((x) >> 26) & 0x1) 1592#define C_028C70_RAT 0xFBFFFFFF 1593#define S_028C70_RESOURCE_TYPE(x) (((x) & 0x7) << 27) 1594#define G_028C70_RESOURCE_TYPE(x) (((x) >> 27) & 0x7) 1595#define C_028C70_RESOURCE_TYPE 0xC7FFFFFF 1596 1597#define CB_COLOR0_INFO 0x28c70 1598# define CB_FORMAT(x) ((x) << 2) 1599# define CB_ARRAY_MODE(x) ((x) << 8) 1600# define ARRAY_LINEAR_GENERAL 0 1601# define ARRAY_LINEAR_ALIGNED 1 1602# define ARRAY_1D_TILED_THIN1 2 1603# define ARRAY_2D_TILED_THIN1 4 1604# define CB_SOURCE_FORMAT(x) ((x) << 24) 1605# define CB_SF_EXPORT_FULL 0 1606# define CB_SF_EXPORT_NORM 1 1607#define R_028C74_CB_COLOR0_ATTRIB 0x028C74 1608#define S_028C74_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 4) 1609#define G_028C74_NON_DISP_TILING_ORDER(x) (((x) >> 4) & 0x1) 1610#define C_028C74_NON_DISP_TILING_ORDER 0xFFFFFFEF 1611#define S_028C74_TILE_SPLIT(x) (((x) & 0xf) << 5) 1612#define G_028C74_TILE_SPLIT(x) (((x) >> 5) & 0xf) 1613#define S_028C74_NUM_BANKS(x) (((x) & 0x3) << 10) 1614#define G_028C74_NUM_BANKS(x) (((x) >> 10) & 0x3) 1615#define S_028C74_BANK_WIDTH(x) (((x) & 0x3) << 13) 1616#define G_028C74_BANK_WIDTH(x) (((x) >> 13) & 0x3) 1617#define S_028C74_BANK_HEIGHT(x) (((x) & 0x3) << 16) 1618#define G_028C74_BANK_HEIGHT(x) (((x) >> 16) & 0x3) 1619#define S_028C74_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19) 1620#define G_028C74_MACRO_TILE_ASPECT(x) (((x) >> 19) & 0x3) 1621#define CB_COLOR0_ATTRIB 0x28c74 1622# define CB_TILE_SPLIT(x) (((x) & 0x7) << 5) 1623# define ADDR_SURF_TILE_SPLIT_64B 0 1624# define ADDR_SURF_TILE_SPLIT_128B 1 1625# define ADDR_SURF_TILE_SPLIT_256B 2 1626# define ADDR_SURF_TILE_SPLIT_512B 3 1627# define ADDR_SURF_TILE_SPLIT_1KB 4 1628# define ADDR_SURF_TILE_SPLIT_2KB 5 1629# define ADDR_SURF_TILE_SPLIT_4KB 6 1630# define CB_NUM_BANKS(x) (((x) & 0x3) << 10) 1631# define ADDR_SURF_2_BANK 0 1632# define ADDR_SURF_4_BANK 1 1633# define ADDR_SURF_8_BANK 2 1634# define ADDR_SURF_16_BANK 3 1635# define CB_BANK_WIDTH(x) (((x) & 0x3) << 13) 1636# define ADDR_SURF_BANK_WIDTH_1 0 1637# define ADDR_SURF_BANK_WIDTH_2 1 1638# define ADDR_SURF_BANK_WIDTH_4 2 1639# define ADDR_SURF_BANK_WIDTH_8 3 1640# define CB_BANK_HEIGHT(x) (((x) & 0x3) << 16) 1641# define ADDR_SURF_BANK_HEIGHT_1 0 1642# define ADDR_SURF_BANK_HEIGHT_2 1 1643# define ADDR_SURF_BANK_HEIGHT_4 2 1644# define ADDR_SURF_BANK_HEIGHT_8 3 1645# define CB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19) 1646#define CB_COLOR0_DIM 0x28c78 1647/* only CB0-7 blocks have these regs */ 1648#define CB_COLOR0_CMASK 0x28c7c 1649#define CB_COLOR0_CMASK_SLICE 0x28c80 1650#define CB_COLOR0_FMASK 0x28c84 1651#define CB_COLOR0_FMASK_SLICE 0x28c88 1652#define CB_COLOR0_CLEAR_WORD0 0x28c8c 1653#define CB_COLOR0_CLEAR_WORD1 0x28c90 1654#define CB_COLOR0_CLEAR_WORD2 0x28c94 1655#define CB_COLOR0_CLEAR_WORD3 0x28c98 1656 1657#define CB_COLOR1_BASE 0x28c9c 1658#define CB_COLOR2_BASE 0x28cd8 1659#define CB_COLOR3_BASE 0x28d14 1660#define CB_COLOR4_BASE 0x28d50 1661#define CB_COLOR5_BASE 0x28d8c 1662#define CB_COLOR6_BASE 0x28dc8 1663#define CB_COLOR7_BASE 0x28e04 1664#define CB_COLOR8_BASE 0x28e40 1665#define CB_COLOR9_BASE 0x28e5c 1666#define CB_COLOR10_BASE 0x28e78 1667#define CB_COLOR11_BASE 0x28e94 1668 1669#define CB_COLOR1_PITCH 0x28ca0 1670#define CB_COLOR2_PITCH 0x28cdc 1671#define CB_COLOR3_PITCH 0x28d18 1672#define CB_COLOR4_PITCH 0x28d54 1673#define CB_COLOR5_PITCH 0x28d90 1674#define CB_COLOR6_PITCH 0x28dcc 1675#define CB_COLOR7_PITCH 0x28e08 1676#define CB_COLOR8_PITCH 0x28e44 1677#define CB_COLOR9_PITCH 0x28e60 1678#define CB_COLOR10_PITCH 0x28e7c 1679#define CB_COLOR11_PITCH 0x28e98 1680 1681#define CB_COLOR1_SLICE 0x28ca4 1682#define CB_COLOR2_SLICE 0x28ce0 1683#define CB_COLOR3_SLICE 0x28d1c 1684#define CB_COLOR4_SLICE 0x28d58 1685#define CB_COLOR5_SLICE 0x28d94 1686#define CB_COLOR6_SLICE 0x28dd0 1687#define CB_COLOR7_SLICE 0x28e0c 1688#define CB_COLOR8_SLICE 0x28e48 1689#define CB_COLOR9_SLICE 0x28e64 1690#define CB_COLOR10_SLICE 0x28e80 1691#define CB_COLOR11_SLICE 0x28e9c 1692 1693#define CB_COLOR1_VIEW 0x28ca8 1694#define CB_COLOR2_VIEW 0x28ce4 1695#define CB_COLOR3_VIEW 0x28d20 1696#define CB_COLOR4_VIEW 0x28d5c 1697#define CB_COLOR5_VIEW 0x28d98 1698#define CB_COLOR6_VIEW 0x28dd4 1699#define CB_COLOR7_VIEW 0x28e10 1700#define CB_COLOR8_VIEW 0x28e4c 1701#define CB_COLOR9_VIEW 0x28e68 1702#define CB_COLOR10_VIEW 0x28e84 1703#define CB_COLOR11_VIEW 0x28ea0 1704 1705#define CB_COLOR1_INFO 0x28cac 1706#define CB_COLOR2_INFO 0x28ce8 1707#define CB_COLOR3_INFO 0x28d24 1708#define CB_COLOR4_INFO 0x28d60 1709#define CB_COLOR5_INFO 0x28d9c 1710#define CB_COLOR6_INFO 0x28dd8 1711#define CB_COLOR7_INFO 0x28e14 1712#define CB_COLOR8_INFO 0x28e50 1713#define CB_COLOR9_INFO 0x28e6c 1714#define CB_COLOR10_INFO 0x28e88 1715#define CB_COLOR11_INFO 0x28ea4 1716 1717#define CB_COLOR1_ATTRIB 0x28cb0 1718#define CB_COLOR2_ATTRIB 0x28cec 1719#define CB_COLOR3_ATTRIB 0x28d28 1720#define CB_COLOR4_ATTRIB 0x28d64 1721#define CB_COLOR5_ATTRIB 0x28da0 1722#define CB_COLOR6_ATTRIB 0x28ddc 1723#define CB_COLOR7_ATTRIB 0x28e18 1724#define CB_COLOR8_ATTRIB 0x28e54 1725#define CB_COLOR9_ATTRIB 0x28e70 1726#define CB_COLOR10_ATTRIB 0x28e8c 1727#define CB_COLOR11_ATTRIB 0x28ea8 1728 1729#define CB_COLOR1_DIM 0x28cb4 1730#define CB_COLOR2_DIM 0x28cf0 1731#define CB_COLOR3_DIM 0x28d2c 1732#define CB_COLOR4_DIM 0x28d68 1733#define CB_COLOR5_DIM 0x28da4 1734#define CB_COLOR6_DIM 0x28de0 1735#define CB_COLOR7_DIM 0x28e1c 1736#define CB_COLOR8_DIM 0x28e58 1737#define CB_COLOR9_DIM 0x28e74 1738#define CB_COLOR10_DIM 0x28e90 1739#define CB_COLOR11_DIM 0x28eac 1740 1741#define CB_COLOR1_CMASK 0x28cb8 1742#define CB_COLOR2_CMASK 0x28cf4 1743#define CB_COLOR3_CMASK 0x28d30 1744#define CB_COLOR4_CMASK 0x28d6c 1745#define CB_COLOR5_CMASK 0x28da8 1746#define CB_COLOR6_CMASK 0x28de4 1747#define CB_COLOR7_CMASK 0x28e20 1748 1749#define CB_COLOR1_CMASK_SLICE 0x28cbc 1750#define CB_COLOR2_CMASK_SLICE 0x28cf8 1751#define CB_COLOR3_CMASK_SLICE 0x28d34 1752#define CB_COLOR4_CMASK_SLICE 0x28d70 1753#define CB_COLOR5_CMASK_SLICE 0x28dac 1754#define CB_COLOR6_CMASK_SLICE 0x28de8 1755#define CB_COLOR7_CMASK_SLICE 0x28e24 1756 1757#define CB_COLOR1_FMASK 0x28cc0 1758#define CB_COLOR2_FMASK 0x28cfc 1759#define CB_COLOR3_FMASK 0x28d38 1760#define CB_COLOR4_FMASK 0x28d74 1761#define CB_COLOR5_FMASK 0x28db0 1762#define CB_COLOR6_FMASK 0x28dec 1763#define CB_COLOR7_FMASK 0x28e28 1764 1765#define CB_COLOR1_FMASK_SLICE 0x28cc4 1766#define CB_COLOR2_FMASK_SLICE 0x28d00 1767#define CB_COLOR3_FMASK_SLICE 0x28d3c 1768#define CB_COLOR4_FMASK_SLICE 0x28d78 1769#define CB_COLOR5_FMASK_SLICE 0x28db4 1770#define CB_COLOR6_FMASK_SLICE 0x28df0 1771#define CB_COLOR7_FMASK_SLICE 0x28e2c 1772 1773#define CB_COLOR1_CLEAR_WORD0 0x28cc8 1774#define CB_COLOR2_CLEAR_WORD0 0x28d04 1775#define CB_COLOR3_CLEAR_WORD0 0x28d40 1776#define CB_COLOR4_CLEAR_WORD0 0x28d7c 1777#define CB_COLOR5_CLEAR_WORD0 0x28db8 1778#define CB_COLOR6_CLEAR_WORD0 0x28df4 1779#define CB_COLOR7_CLEAR_WORD0 0x28e30 1780 1781#define CB_COLOR1_CLEAR_WORD1 0x28ccc 1782#define CB_COLOR2_CLEAR_WORD1 0x28d08 1783#define CB_COLOR3_CLEAR_WORD1 0x28d44 1784#define CB_COLOR4_CLEAR_WORD1 0x28d80 1785#define CB_COLOR5_CLEAR_WORD1 0x28dbc 1786#define CB_COLOR6_CLEAR_WORD1 0x28df8 1787#define CB_COLOR7_CLEAR_WORD1 0x28e34 1788 1789#define CB_COLOR1_CLEAR_WORD2 0x28cd0 1790#define CB_COLOR2_CLEAR_WORD2 0x28d0c 1791#define CB_COLOR3_CLEAR_WORD2 0x28d48 1792#define CB_COLOR4_CLEAR_WORD2 0x28d84 1793#define CB_COLOR5_CLEAR_WORD2 0x28dc0 1794#define CB_COLOR6_CLEAR_WORD2 0x28dfc 1795#define CB_COLOR7_CLEAR_WORD2 0x28e38 1796 1797#define CB_COLOR1_CLEAR_WORD3 0x28cd4 1798#define CB_COLOR2_CLEAR_WORD3 0x28d10 1799#define CB_COLOR3_CLEAR_WORD3 0x28d4c 1800#define CB_COLOR4_CLEAR_WORD3 0x28d88 1801#define CB_COLOR5_CLEAR_WORD3 0x28dc4 1802#define CB_COLOR6_CLEAR_WORD3 0x28e00 1803#define CB_COLOR7_CLEAR_WORD3 0x28e3c 1804 1805#define SQ_TEX_RESOURCE_WORD0_0 0x30000 1806# define TEX_DIM(x) ((x) << 0) 1807# define SQ_TEX_DIM_1D 0 1808# define SQ_TEX_DIM_2D 1 1809# define SQ_TEX_DIM_3D 2 1810# define SQ_TEX_DIM_CUBEMAP 3 1811# define SQ_TEX_DIM_1D_ARRAY 4 1812# define SQ_TEX_DIM_2D_ARRAY 5 1813# define SQ_TEX_DIM_2D_MSAA 6 1814# define SQ_TEX_DIM_2D_ARRAY_MSAA 7 1815#define SQ_TEX_RESOURCE_WORD1_0 0x30004 1816# define TEX_ARRAY_MODE(x) ((x) << 28) 1817#define SQ_TEX_RESOURCE_WORD2_0 0x30008 1818#define SQ_TEX_RESOURCE_WORD3_0 0x3000C 1819#define SQ_TEX_RESOURCE_WORD4_0 0x30010 1820# define TEX_DST_SEL_X(x) ((x) << 16) 1821# define TEX_DST_SEL_Y(x) ((x) << 19) 1822# define TEX_DST_SEL_Z(x) ((x) << 22) 1823# define TEX_DST_SEL_W(x) ((x) << 25) 1824# define SQ_SEL_X 0 1825# define SQ_SEL_Y 1 1826# define SQ_SEL_Z 2 1827# define SQ_SEL_W 3 1828# define SQ_SEL_0 4 1829# define SQ_SEL_1 5 1830#define SQ_TEX_RESOURCE_WORD5_0 0x30014 1831#define SQ_TEX_RESOURCE_WORD6_0 0x30018 1832# define TEX_TILE_SPLIT(x) (((x) & 0x7) << 29) 1833#define SQ_TEX_RESOURCE_WORD7_0 0x3001c 1834# define MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) 1835# define TEX_BANK_WIDTH(x) (((x) & 0x3) << 8) 1836# define TEX_BANK_HEIGHT(x) (((x) & 0x3) << 10) 1837# define TEX_NUM_BANKS(x) (((x) & 0x3) << 16) 1838#define R_030000_SQ_TEX_RESOURCE_WORD0_0 0x030000 1839#define S_030000_DIM(x) (((x) & 0x7) << 0) 1840#define G_030000_DIM(x) (((x) >> 0) & 0x7) 1841#define C_030000_DIM 0xFFFFFFF8 1842#define V_030000_SQ_TEX_DIM_1D 0x00000000 1843#define V_030000_SQ_TEX_DIM_2D 0x00000001 1844#define V_030000_SQ_TEX_DIM_3D 0x00000002 1845#define V_030000_SQ_TEX_DIM_CUBEMAP 0x00000003 1846#define V_030000_SQ_TEX_DIM_1D_ARRAY 0x00000004 1847#define V_030000_SQ_TEX_DIM_2D_ARRAY 0x00000005 1848#define V_030000_SQ_TEX_DIM_2D_MSAA 0x00000006 1849#define V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 1850#define S_030000_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 5) 1851#define G_030000_NON_DISP_TILING_ORDER(x) (((x) >> 5) & 0x1) 1852#define C_030000_NON_DISP_TILING_ORDER 0xFFFFFFDF 1853#define S_030000_PITCH(x) (((x) & 0xFFF) << 6) 1854#define G_030000_PITCH(x) (((x) >> 6) & 0xFFF) 1855#define C_030000_PITCH 0xFFFC003F 1856#define S_030000_TEX_WIDTH(x) (((x) & 0x3FFF) << 18) 1857#define G_030000_TEX_WIDTH(x) (((x) >> 18) & 0x3FFF) 1858#define C_030000_TEX_WIDTH 0x0003FFFF 1859#define R_030004_SQ_TEX_RESOURCE_WORD1_0 0x030004 1860#define S_030004_TEX_HEIGHT(x) (((x) & 0x3FFF) << 0) 1861#define G_030004_TEX_HEIGHT(x) (((x) >> 0) & 0x3FFF) 1862#define C_030004_TEX_HEIGHT 0xFFFFC000 1863#define S_030004_TEX_DEPTH(x) (((x) & 0x1FFF) << 14) 1864#define G_030004_TEX_DEPTH(x) (((x) >> 14) & 0x1FFF) 1865#define C_030004_TEX_DEPTH 0xF8003FFF 1866#define S_030004_ARRAY_MODE(x) (((x) & 0xF) << 28) 1867#define G_030004_ARRAY_MODE(x) (((x) >> 28) & 0xF) 1868#define C_030004_ARRAY_MODE 0x0FFFFFFF 1869#define R_030008_SQ_TEX_RESOURCE_WORD2_0 0x030008 1870#define S_030008_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 1871#define G_030008_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 1872#define C_030008_BASE_ADDRESS 0x00000000 1873#define R_03000C_SQ_TEX_RESOURCE_WORD3_0 0x03000C 1874#define S_03000C_MIP_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 1875#define G_03000C_MIP_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 1876#define C_03000C_MIP_ADDRESS 0x00000000 1877#define R_030010_SQ_TEX_RESOURCE_WORD4_0 0x030010 1878#define S_030010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) 1879#define G_030010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) 1880#define C_030010_FORMAT_COMP_X 0xFFFFFFFC 1881#define V_030010_SQ_FORMAT_COMP_UNSIGNED 0x00000000 1882#define V_030010_SQ_FORMAT_COMP_SIGNED 0x00000001 1883#define V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED 0x00000002 1884#define S_030010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) 1885#define G_030010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) 1886#define C_030010_FORMAT_COMP_Y 0xFFFFFFF3 1887#define S_030010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) 1888#define G_030010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) 1889#define C_030010_FORMAT_COMP_Z 0xFFFFFFCF 1890#define S_030010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) 1891#define G_030010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) 1892#define C_030010_FORMAT_COMP_W 0xFFFFFF3F 1893#define S_030010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) 1894#define G_030010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) 1895#define C_030010_NUM_FORMAT_ALL 0xFFFFFCFF 1896#define V_030010_SQ_NUM_FORMAT_NORM 0x00000000 1897#define V_030010_SQ_NUM_FORMAT_INT 0x00000001 1898#define V_030010_SQ_NUM_FORMAT_SCALED 0x00000002 1899#define S_030010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) 1900#define G_030010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) 1901#define C_030010_SRF_MODE_ALL 0xFFFFFBFF 1902#define V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE 0x00000000 1903#define V_030010_SRF_MODE_NO_ZERO 0x00000001 1904#define S_030010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) 1905#define G_030010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) 1906#define C_030010_FORCE_DEGAMMA 0xFFFFF7FF 1907#define S_030010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) 1908#define G_030010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) 1909#define C_030010_ENDIAN_SWAP 0xFFFFCFFF 1910#define S_030010_DST_SEL_X(x) (((x) & 0x7) << 16) 1911#define G_030010_DST_SEL_X(x) (((x) >> 16) & 0x7) 1912#define C_030010_DST_SEL_X 0xFFF8FFFF 1913#define V_030010_SQ_SEL_X 0x00000000 1914#define V_030010_SQ_SEL_Y 0x00000001 1915#define V_030010_SQ_SEL_Z 0x00000002 1916#define V_030010_SQ_SEL_W 0x00000003 1917#define V_030010_SQ_SEL_0 0x00000004 1918#define V_030010_SQ_SEL_1 0x00000005 1919#define S_030010_DST_SEL_Y(x) (((x) & 0x7) << 19) 1920#define G_030010_DST_SEL_Y(x) (((x) >> 19) & 0x7) 1921#define C_030010_DST_SEL_Y 0xFFC7FFFF 1922#define S_030010_DST_SEL_Z(x) (((x) & 0x7) << 22) 1923#define G_030010_DST_SEL_Z(x) (((x) >> 22) & 0x7) 1924#define C_030010_DST_SEL_Z 0xFE3FFFFF 1925#define S_030010_DST_SEL_W(x) (((x) & 0x7) << 25) 1926#define G_030010_DST_SEL_W(x) (((x) >> 25) & 0x7) 1927#define C_030010_DST_SEL_W 0xF1FFFFFF 1928#define S_030010_BASE_LEVEL(x) (((x) & 0xF) << 28) 1929#define G_030010_BASE_LEVEL(x) (((x) >> 28) & 0xF) 1930#define C_030010_BASE_LEVEL 0x0FFFFFFF 1931#define R_030014_SQ_TEX_RESOURCE_WORD5_0 0x030014 1932#define S_030014_LAST_LEVEL(x) (((x) & 0xF) << 0) 1933#define G_030014_LAST_LEVEL(x) (((x) >> 0) & 0xF) 1934#define C_030014_LAST_LEVEL 0xFFFFFFF0 1935#define S_030014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) 1936#define G_030014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) 1937#define C_030014_BASE_ARRAY 0xFFFE000F 1938#define S_030014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) 1939#define G_030014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) 1940#define C_030014_LAST_ARRAY 0xC001FFFF 1941#define R_030018_SQ_TEX_RESOURCE_WORD6_0 0x030018 1942#define S_030018_MAX_ANISO(x) (((x) & 0x7) << 0) 1943#define G_030018_MAX_ANISO(x) (((x) >> 0) & 0x7) 1944#define C_030018_MAX_ANISO 0xFFFFFFF8 1945#define S_030018_PERF_MODULATION(x) (((x) & 0x7) << 3) 1946#define G_030018_PERF_MODULATION(x) (((x) >> 3) & 0x7) 1947#define C_030018_PERF_MODULATION 0xFFFFFFC7 1948#define S_030018_INTERLACED(x) (((x) & 0x1) << 6) 1949#define G_030018_INTERLACED(x) (((x) >> 6) & 0x1) 1950#define C_030018_INTERLACED 0xFFFFFFBF 1951#define S_030018_TILE_SPLIT(x) (((x) & 0x7) << 29) 1952#define G_030018_TILE_SPLIT(x) (((x) >> 29) & 0x7) 1953#define R_03001C_SQ_TEX_RESOURCE_WORD7_0 0x03001C 1954#define S_03001C_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) 1955#define G_03001C_MACRO_TILE_ASPECT(x) (((x) >> 6) & 0x3) 1956#define S_03001C_BANK_WIDTH(x) (((x) & 0x3) << 8) 1957#define G_03001C_BANK_WIDTH(x) (((x) >> 8) & 0x3) 1958#define S_03001C_BANK_HEIGHT(x) (((x) & 0x3) << 10) 1959#define G_03001C_BANK_HEIGHT(x) (((x) >> 10) & 0x3) 1960#define S_03001C_NUM_BANKS(x) (((x) & 0x3) << 16) 1961#define G_03001C_NUM_BANKS(x) (((x) >> 16) & 0x3) 1962#define S_03001C_TYPE(x) (((x) & 0x3) << 30) 1963#define G_03001C_TYPE(x) (((x) >> 30) & 0x3) 1964#define C_03001C_TYPE 0x3FFFFFFF 1965#define V_03001C_SQ_TEX_VTX_INVALID_TEXTURE 0x00000000 1966#define V_03001C_SQ_TEX_VTX_INVALID_BUFFER 0x00000001 1967#define V_03001C_SQ_TEX_VTX_VALID_TEXTURE 0x00000002 1968#define V_03001C_SQ_TEX_VTX_VALID_BUFFER 0x00000003 1969#define S_03001C_DATA_FORMAT(x) (((x) & 0x3F) << 0) 1970#define G_03001C_DATA_FORMAT(x) (((x) >> 0) & 0x3F) 1971#define C_03001C_DATA_FORMAT 0xFFFFFFC0 1972 1973#define SQ_VTX_CONSTANT_WORD0_0 0x30000 1974#define SQ_VTX_CONSTANT_WORD1_0 0x30004 1975#define SQ_VTX_CONSTANT_WORD2_0 0x30008 1976# define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0) 1977# define SQ_VTXC_STRIDE(x) ((x) << 8) 1978# define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30) 1979# define SQ_ENDIAN_NONE 0 1980# define SQ_ENDIAN_8IN16 1 1981# define SQ_ENDIAN_8IN32 2 1982#define SQ_VTX_CONSTANT_WORD3_0 0x3000C 1983# define SQ_VTCX_SEL_X(x) ((x) << 3) 1984# define SQ_VTCX_SEL_Y(x) ((x) << 6) 1985# define SQ_VTCX_SEL_Z(x) ((x) << 9) 1986# define SQ_VTCX_SEL_W(x) ((x) << 12) 1987#define SQ_VTX_CONSTANT_WORD4_0 0x30010 1988#define SQ_VTX_CONSTANT_WORD5_0 0x30014 1989#define SQ_VTX_CONSTANT_WORD6_0 0x30018 1990#define SQ_VTX_CONSTANT_WORD7_0 0x3001c 1991 1992#define TD_PS_BORDER_COLOR_INDEX 0xA400 1993#define TD_PS_BORDER_COLOR_RED 0xA404 1994#define TD_PS_BORDER_COLOR_GREEN 0xA408 1995#define TD_PS_BORDER_COLOR_BLUE 0xA40C 1996#define TD_PS_BORDER_COLOR_ALPHA 0xA410 1997#define TD_VS_BORDER_COLOR_INDEX 0xA414 1998#define TD_VS_BORDER_COLOR_RED 0xA418 1999#define TD_VS_BORDER_COLOR_GREEN 0xA41C 2000#define TD_VS_BORDER_COLOR_BLUE 0xA420 2001#define TD_VS_BORDER_COLOR_ALPHA 0xA424 2002#define TD_GS_BORDER_COLOR_INDEX 0xA428 2003#define TD_GS_BORDER_COLOR_RED 0xA42C 2004#define TD_GS_BORDER_COLOR_GREEN 0xA430 2005#define TD_GS_BORDER_COLOR_BLUE 0xA434 2006#define TD_GS_BORDER_COLOR_ALPHA 0xA438 2007#define TD_HS_BORDER_COLOR_INDEX 0xA43C 2008#define TD_HS_BORDER_COLOR_RED 0xA440 2009#define TD_HS_BORDER_COLOR_GREEN 0xA444 2010#define TD_HS_BORDER_COLOR_BLUE 0xA448 2011#define TD_HS_BORDER_COLOR_ALPHA 0xA44C 2012#define TD_LS_BORDER_COLOR_INDEX 0xA450 2013#define TD_LS_BORDER_COLOR_RED 0xA454 2014#define TD_LS_BORDER_COLOR_GREEN 0xA458 2015#define TD_LS_BORDER_COLOR_BLUE 0xA45C 2016#define TD_LS_BORDER_COLOR_ALPHA 0xA460 2017#define TD_CS_BORDER_COLOR_INDEX 0xA464 2018#define TD_CS_BORDER_COLOR_RED 0xA468 2019#define TD_CS_BORDER_COLOR_GREEN 0xA46C 2020#define TD_CS_BORDER_COLOR_BLUE 0xA470 2021#define TD_CS_BORDER_COLOR_ALPHA 0xA474 2022 2023/* cayman 3D regs */ 2024#define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B4 2025#define CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS 0x8E48 2026#define CAYMAN_DB_EQAA 0x28804 2027#define CAYMAN_DB_DEPTH_INFO 0x2803C 2028#define CAYMAN_PA_SC_AA_CONFIG 0x28BE0 2029#define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0 2030#define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7 2031#define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358 2032/* cayman packet3 addition */ 2033#define CAYMAN_PACKET3_DEALLOC_STATE 0x14 2034 2035/* DMA regs common on r6xx/r7xx/evergreen/ni */ 2036#define DMA_RB_CNTL 0xd000 2037# define DMA_RB_ENABLE (1 << 0) 2038# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 2039# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 2040# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 2041# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 2042# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 2043#define DMA_STATUS_REG 0xd034 2044# define DMA_IDLE (1 << 0) 2045 2046#endif 2047