1/* 2 * Copyright © 2011-2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Ben Widawsky <ben@bwidawsk.net> 25 * 26 */ 27 28/* 29 * This file implements HW context support. On gen5+ a HW context consists of an 30 * opaque GPU object which is referenced at times of context saves and restores. 31 * With RC6 enabled, the context is also referenced as the GPU enters and exists 32 * from RC6 (GPU has it's own internal power context, except on gen5). Though 33 * something like a context does exist for the media ring, the code only 34 * supports contexts for the render ring. 35 * 36 * In software, there is a distinction between contexts created by the user, 37 * and the default HW context. The default HW context is used by GPU clients 38 * that do not request setup of their own hardware context. The default 39 * context's state is never restored to help prevent programming errors. This 40 * would happen if a client ran and piggy-backed off another clients GPU state. 41 * The default context only exists to give the GPU some offset to load as the 42 * current to invoke a save of the context we actually care about. In fact, the 43 * code could likely be constructed, albeit in a more complicated fashion, to 44 * never use the default context, though that limits the driver's ability to 45 * swap out, and/or destroy other contexts. 46 * 47 * All other contexts are created as a request by the GPU client. These contexts 48 * store GPU state, and thus allow GPU clients to not re-emit state (and 49 * potentially query certain state) at any time. The kernel driver makes 50 * certain that the appropriate commands are inserted. 51 * 52 * The context life cycle is semi-complicated in that context BOs may live 53 * longer than the context itself because of the way the hardware, and object 54 * tracking works. Below is a very crude representation of the state machine 55 * describing the context life. 56 * refcount pincount active 57 * S0: initial state 0 0 0 58 * S1: context created 1 0 0 59 * S2: context is currently running 2 1 X 60 * S3: GPU referenced, but not current 2 0 1 61 * S4: context is current, but destroyed 1 1 0 62 * S5: like S3, but destroyed 1 0 1 63 * 64 * The most common (but not all) transitions: 65 * S0->S1: client creates a context 66 * S1->S2: client submits execbuf with context 67 * S2->S3: other clients submits execbuf with context 68 * S3->S1: context object was retired 69 * S3->S2: clients submits another execbuf 70 * S2->S4: context destroy called with current context 71 * S3->S5->S0: destroy path 72 * S4->S5->S0: destroy path on current context 73 * 74 * There are two confusing terms used above: 75 * The "current context" means the context which is currently running on the 76 * GPU. The GPU has loaded it's state already and has stored away the gtt 77 * offset of the BO. The GPU is not actively referencing the data at this 78 * offset, but it will on the next context switch. The only way to avoid this 79 * is to do a GPU reset. 80 * 81 * An "active context' is one which was previously the "current context" and is 82 * on the active list waiting for the next context switch to occur. Until this 83 * happens, the object must remain at the same gtt offset. It is therefore 84 * possible to destroy a context, but it is still active. 85 * 86 */ 87 88#include <sys/cdefs.h> 89__FBSDID("$FreeBSD$"); 90 91#include <dev/drm2/drmP.h> 92#include <dev/drm2/i915/i915_drm.h> 93#include "i915_drv.h" 94 95/* This is a HW constraint. The value below is the largest known requirement 96 * I've seen in a spec to date, and that was a workaround for a non-shipping 97 * part. It should be safe to decrease this, but it's more future proof as is. 98 */ 99#define CONTEXT_ALIGN (64<<10) 100 101static struct i915_hw_context * 102i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); 103static int do_switch(struct i915_hw_context *to); 104 105static int get_context_size(struct drm_device *dev) 106{ 107 struct drm_i915_private *dev_priv = dev->dev_private; 108 int ret; 109 u32 reg; 110 111 switch (INTEL_INFO(dev)->gen) { 112 case 6: 113 reg = I915_READ(CXT_SIZE); 114 ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; 115 break; 116 case 7: 117 reg = I915_READ(GEN7_CXT_SIZE); 118 if (IS_HASWELL(dev)) 119 ret = HSW_CXT_TOTAL_SIZE(reg) * 64; 120 else 121 ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; 122 break; 123 default: 124 panic("i915_gem_context: Unsupported Intel GPU generation %d", 125 INTEL_INFO(dev)->gen); 126 } 127 128 return ret; 129} 130 131static void do_destroy(struct i915_hw_context *ctx) 132{ 133#if defined(INVARIANTS) 134 struct drm_device *dev = ctx->obj->base.dev; 135 struct drm_i915_private *dev_priv = dev->dev_private; 136#endif 137 138 if (ctx->file_priv) 139 drm_gem_names_remove(&ctx->file_priv->context_idr, ctx->id); 140 else 141 KASSERT(ctx == dev_priv->ring[RCS].default_context, 142 ("i915_gem_context: ctx != default_context")); 143 144 drm_gem_object_unreference(&ctx->obj->base); 145 free(ctx, DRM_I915_GEM); 146} 147 148static int 149create_hw_context(struct drm_device *dev, 150 struct drm_i915_file_private *file_priv, 151 struct i915_hw_context **ret_ctx) 152{ 153 struct drm_i915_private *dev_priv = dev->dev_private; 154 struct i915_hw_context *ctx; 155 int ret, id; 156 157 ctx = malloc(sizeof(*ctx), DRM_I915_GEM, M_NOWAIT | M_ZERO); 158 if (ctx == NULL) 159 return (-ENOMEM); 160 161 ctx->obj = i915_gem_alloc_object(dev, dev_priv->hw_context_size); 162 if (ctx->obj == NULL) { 163 free(ctx, DRM_I915_GEM); 164 DRM_DEBUG_DRIVER("Context object allocated failed\n"); 165 return (-ENOMEM); 166 } 167 168 if (INTEL_INFO(dev)->gen >= 7) { 169 ret = i915_gem_object_set_cache_level(ctx->obj, 170 I915_CACHE_LLC_MLC); 171 if (ret) 172 goto err_out; 173 } 174 175 /* The ring associated with the context object is handled by the normal 176 * object tracking code. We give an initial ring value simple to pass an 177 * assertion in the context switch code. 178 */ 179 ctx->ring = &dev_priv->ring[RCS]; 180 181 /* Default context will never have a file_priv */ 182 if (file_priv == NULL) { 183 *ret_ctx = ctx; 184 return (0); 185 } 186 187 ctx->file_priv = file_priv; 188 189again: 190 id = 0; 191 ret = drm_gem_name_create(&file_priv->context_idr, ctx, &id); 192 if (ret == 0) 193 ctx->id = id; 194 195 if (ret == -EAGAIN) 196 goto again; 197 else if (ret) 198 goto err_out; 199 200 *ret_ctx = ctx; 201 return (0); 202 203err_out: 204 do_destroy(ctx); 205 return (ret); 206} 207 208static inline bool is_default_context(struct i915_hw_context *ctx) 209{ 210 return (ctx == ctx->ring->default_context); 211} 212 213/** 214 * The default context needs to exist per ring that uses contexts. It stores the 215 * context state of the GPU for applications that don't utilize HW contexts, as 216 * well as an idle case. 217 */ 218static int create_default_context(struct drm_i915_private *dev_priv) 219{ 220 struct i915_hw_context *ctx; 221 int ret; 222 223 DRM_LOCK_ASSERT(dev_priv->dev); 224 225 ret = create_hw_context(dev_priv->dev, NULL, &ctx); 226 if (ret != 0) 227 return (ret); 228 229 /* We may need to do things with the shrinker which require us to 230 * immediately switch back to the default context. This can cause a 231 * problem as pinning the default context also requires GTT space which 232 * may not be available. To avoid this we always pin the 233 * default context. 234 */ 235 dev_priv->ring[RCS].default_context = ctx; 236 ret = i915_gem_object_pin(ctx->obj, CONTEXT_ALIGN, false, false); 237 if (ret) 238 goto err_destroy; 239 240 ret = do_switch(ctx); 241 if (ret) 242 goto err_unpin; 243 244 DRM_DEBUG_DRIVER("Default HW context loaded\n"); 245 return 0; 246 247err_unpin: 248 i915_gem_object_unpin(ctx->obj); 249err_destroy: 250 do_destroy(ctx); 251 return ret; 252} 253 254void i915_gem_context_init(struct drm_device *dev) 255{ 256 struct drm_i915_private *dev_priv = dev->dev_private; 257 uint32_t ctx_size; 258 259 if (!HAS_HW_CONTEXTS(dev)) { 260 dev_priv->hw_contexts_disabled = true; 261 return; 262 } 263 264 /* If called from reset, or thaw... we've been here already */ 265 if (dev_priv->hw_contexts_disabled || 266 dev_priv->ring[RCS].default_context) 267 return; 268 269 ctx_size = get_context_size(dev); 270 dev_priv->hw_context_size = get_context_size(dev); 271 dev_priv->hw_context_size = round_up(dev_priv->hw_context_size, 4096); 272 273 if (ctx_size <= 0 || ctx_size > (1<<20)) { 274 dev_priv->hw_contexts_disabled = true; 275 return; 276 } 277 278 if (create_default_context(dev_priv)) { 279 dev_priv->hw_contexts_disabled = true; 280 return; 281 } 282 283 DRM_DEBUG_DRIVER("HW context support initialized\n"); 284} 285 286void i915_gem_context_fini(struct drm_device *dev) 287{ 288 struct drm_i915_private *dev_priv = dev->dev_private; 289 290 if (dev_priv->hw_contexts_disabled) 291 return; 292 293 /* The only known way to stop the gpu from accessing the hw context is 294 * to reset it. Do this as the very last operation to avoid confusing 295 * other code, leading to spurious errors. */ 296 intel_gpu_reset(dev); 297 298 i915_gem_object_unpin(dev_priv->ring[RCS].default_context->obj); 299 300 /* When default context is created and switched to, base object refcount 301 * will be 2 (+1 from object creation and +1 from do_switch()). 302 * i915_gem_context_fini() will be called after gpu_idle() has switched 303 * to default context. So we need to unreference the base object once 304 * to offset the do_switch part, so that i915_gem_context_unreference() 305 * can then free the base object correctly. */ 306 drm_gem_object_unreference(&dev_priv->ring[RCS].default_context->obj->base); 307 308 do_destroy(dev_priv->ring[RCS].default_context); 309} 310 311static int context_idr_cleanup(uint32_t id, void *p, void *data) 312{ 313 struct i915_hw_context *ctx = p; 314 315 KASSERT(id != DEFAULT_CONTEXT_ID, ("i915_gem_context: id == DEFAULT_CONTEXT_ID in cleanup")); 316 317 do_destroy(ctx); 318 319 return 0; 320} 321 322void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) 323{ 324 struct drm_i915_file_private *file_priv = file->driver_priv; 325 326 DRM_LOCK(dev); 327 drm_gem_names_foreach(&file_priv->context_idr, context_idr_cleanup, NULL); 328 drm_gem_names_fini(&file_priv->context_idr); 329 DRM_UNLOCK(dev); 330} 331 332static struct i915_hw_context * 333i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) 334{ 335 return (struct i915_hw_context *)drm_gem_find_ptr(&file_priv->context_idr, id); 336} 337 338static inline int 339mi_set_context(struct intel_ring_buffer *ring, 340 struct i915_hw_context *new_context, 341 u32 hw_flags) 342{ 343 int ret; 344 345 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB 346 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value 347 * explicitly, so we rely on the value at ring init, stored in 348 * itlb_before_ctx_switch. 349 */ 350 if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) { 351 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0); 352 if (ret) 353 return ret; 354 } 355 356 ret = intel_ring_begin(ring, 6); 357 if (ret) 358 return ret; 359 360 if (IS_GEN7(ring->dev)) 361 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); 362 else 363 intel_ring_emit(ring, MI_NOOP); 364 365 intel_ring_emit(ring, MI_NOOP); 366 intel_ring_emit(ring, MI_SET_CONTEXT); 367 intel_ring_emit(ring, new_context->obj->gtt_offset | 368 MI_MM_SPACE_GTT | 369 MI_SAVE_EXT_STATE_EN | 370 MI_RESTORE_EXT_STATE_EN | 371 hw_flags); 372 /* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP */ 373 intel_ring_emit(ring, MI_NOOP); 374 375 if (IS_GEN7(ring->dev)) 376 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); 377 else 378 intel_ring_emit(ring, MI_NOOP); 379 380 intel_ring_advance(ring); 381 382 return ret; 383} 384 385static int do_switch(struct i915_hw_context *to) 386{ 387 struct intel_ring_buffer *ring = to->ring; 388 struct drm_i915_gem_object *from_obj = ring->last_context_obj; 389 u32 hw_flags = 0; 390 int ret; 391 392 KASSERT(!(from_obj != NULL && from_obj->pin_count == 0), 393 ("i915_gem_context: invalid \"from\" context")); 394 395 if (from_obj == to->obj) 396 return 0; 397 398 ret = i915_gem_object_pin(to->obj, CONTEXT_ALIGN, false, false); 399 if (ret) 400 return ret; 401 402 /* Clear this page out of any CPU caches for coherent swap-in/out. Note 403 * that thanks to write = false in this call and us not setting any gpu 404 * write domains when putting a context object onto the active list 405 * (when switching away from it), this won't block. 406 * XXX: We need a real interface to do this instead of trickery. */ 407 ret = i915_gem_object_set_to_gtt_domain(to->obj, false); 408 if (ret) { 409 i915_gem_object_unpin(to->obj); 410 return ret; 411 } 412 413 if (!to->obj->has_global_gtt_mapping) 414 i915_gem_gtt_bind_object(to->obj, to->obj->cache_level); 415 416 if (!to->is_initialized || is_default_context(to)) 417 hw_flags |= MI_RESTORE_INHIBIT; 418 else if (from_obj == to->obj) /* not yet expected */ 419 hw_flags |= MI_FORCE_RESTORE; 420 421 ret = mi_set_context(ring, to, hw_flags); 422 if (ret) { 423 i915_gem_object_unpin(to->obj); 424 return ret; 425 } 426 427 /* The backing object for the context is done after switching to the 428 * *next* context. Therefore we cannot retire the previous context until 429 * the next context has already started running. In fact, the below code 430 * is a bit suboptimal because the retiring can occur simply after the 431 * MI_SET_CONTEXT instead of when the next seqno has completed. 432 */ 433 if (from_obj != NULL) { 434 from_obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; 435 i915_gem_object_move_to_active(from_obj, ring); 436 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the 437 * whole damn pipeline, we don't need to explicitly mark the 438 * object dirty. The only exception is that the context must be 439 * correct in case the object gets swapped out. Ideally we'd be 440 * able to defer doing this until we know the object would be 441 * swapped, but there is no way to do that yet. 442 */ 443 from_obj->dirty = 1; 444 KASSERT(from_obj->ring == ring, ("i915_gem_context: from_ring != ring")); 445 i915_gem_object_unpin(from_obj); 446 447 drm_gem_object_unreference(&from_obj->base); 448 } 449 450 drm_gem_object_reference(&to->obj->base); 451 ring->last_context_obj = to->obj; 452 to->is_initialized = true; 453 454 return 0; 455} 456 457/** 458 * i915_switch_context() - perform a GPU context switch. 459 * @ring: ring for which we'll execute the context switch 460 * @file_priv: file_priv associated with the context, may be NULL 461 * @id: context id number 462 * @seqno: sequence number by which the new context will be switched to 463 * @flags: 464 * 465 * The context life cycle is simple. The context refcount is incremented and 466 * decremented by 1 and create and destroy. If the context is in use by the GPU, 467 * it will have a refoucnt > 1. This allows us to destroy the context abstract 468 * object while letting the normal object tracking destroy the backing BO. 469 */ 470int i915_switch_context(struct intel_ring_buffer *ring, 471 struct drm_file *file, 472 int to_id) 473{ 474 struct drm_i915_private *dev_priv = ring->dev->dev_private; 475 struct i915_hw_context *to; 476 477 if (dev_priv->hw_contexts_disabled) 478 return 0; 479 480 if (ring != &dev_priv->ring[RCS]) 481 return 0; 482 483 if (to_id == DEFAULT_CONTEXT_ID) { 484 to = ring->default_context; 485 } else { 486 if (file == NULL) 487 return -EINVAL; 488 489 to = i915_gem_context_get(file->driver_priv, to_id); 490 if (to == NULL) 491 return -ENOENT; 492 } 493 494 return do_switch(to); 495} 496 497int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 498 struct drm_file *file) 499{ 500 struct drm_i915_private *dev_priv = dev->dev_private; 501 struct drm_i915_gem_context_create *args = data; 502 struct drm_i915_file_private *file_priv = file->driver_priv; 503 struct i915_hw_context *ctx; 504 int ret; 505 506 if (!(dev->driver->driver_features & DRIVER_GEM)) 507 return -ENODEV; 508 509 if (dev_priv->hw_contexts_disabled) 510 return -ENODEV; 511 512 ret = i915_mutex_lock_interruptible(dev); 513 if (ret) 514 return ret; 515 516 ret = create_hw_context(dev, file_priv, &ctx); 517 DRM_UNLOCK(dev); 518 if (ret != 0) 519 return (ret); 520 521 args->ctx_id = ctx->id; 522 DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); 523 524 return 0; 525} 526 527int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 528 struct drm_file *file) 529{ 530 struct drm_i915_gem_context_destroy *args = data; 531 struct drm_i915_file_private *file_priv = file->driver_priv; 532 struct i915_hw_context *ctx; 533 int ret; 534 535 if (!(dev->driver->driver_features & DRIVER_GEM)) 536 return -ENODEV; 537 538 ret = i915_mutex_lock_interruptible(dev); 539 if (ret) 540 return ret; 541 542 ctx = i915_gem_context_get(file_priv, args->ctx_id); 543 if (!ctx) { 544 DRM_UNLOCK(dev); 545 return -ENOENT; 546 } 547 548 do_destroy(ctx); 549 550 DRM_UNLOCK(dev); 551 552 DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); 553 return 0; 554} 555