savage_bci.c revision 145132
1145132Sanholt/* savage_bci.c -- BCI support for Savage 2145132Sanholt * 3145132Sanholt * Copyright 2004 Felix Kuehling 4145132Sanholt * All Rights Reserved. 5145132Sanholt * 6145132Sanholt * Permission is hereby granted, free of charge, to any person obtaining a 7145132Sanholt * copy of this software and associated documentation files (the "Software"), 8145132Sanholt * to deal in the Software without restriction, including without limitation 9145132Sanholt * the rights to use, copy, modify, merge, publish, distribute, sub license, 10145132Sanholt * and/or sell copies of the Software, and to permit persons to whom the 11145132Sanholt * Software is furnished to do so, subject to the following conditions: 12145132Sanholt * 13145132Sanholt * The above copyright notice and this permission notice (including the 14145132Sanholt * next paragraph) shall be included in all copies or substantial portions 15145132Sanholt * of the Software. 16145132Sanholt * 17145132Sanholt * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18145132Sanholt * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19145132Sanholt * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 20145132Sanholt * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR 21145132Sanholt * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 22145132Sanholt * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23145132Sanholt * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24145132Sanholt * 25145132Sanholt * $FreeBSD: head/sys/dev/drm/savage_bci.c 145132 2005-04-16 03:44:47Z anholt $ 26145132Sanholt */ 27145132Sanholt 28145132Sanholt#include "drmP.h" 29145132Sanholt#include "savage_drm.h" 30145132Sanholt#include "savage_drv.h" 31145132Sanholt 32145132Sanholt/* Need a long timeout for shadow status updates can take a while 33145132Sanholt * and so can waiting for events when the queue is full. */ 34145132Sanholt#define SAVAGE_DEFAULT_USEC_TIMEOUT 1000000 /* 1s */ 35145132Sanholt#define SAVAGE_EVENT_USEC_TIMEOUT 5000000 /* 5s */ 36145132Sanholt#define SAVAGE_FREELIST_DEBUG 0 37145132Sanholt 38145132Sanholtstatic int 39145132Sanholtsavage_bci_wait_fifo_shadow(drm_savage_private_t *dev_priv, unsigned int n) 40145132Sanholt{ 41145132Sanholt uint32_t mask = dev_priv->status_used_mask; 42145132Sanholt uint32_t threshold = dev_priv->bci_threshold_hi; 43145132Sanholt uint32_t status; 44145132Sanholt int i; 45145132Sanholt 46145132Sanholt#if SAVAGE_BCI_DEBUG 47145132Sanholt if (n > dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - threshold) 48145132Sanholt DRM_ERROR("Trying to emit %d words " 49145132Sanholt "(more than guaranteed space in COB)\n", n); 50145132Sanholt#endif 51145132Sanholt 52145132Sanholt for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) { 53145132Sanholt DRM_MEMORYBARRIER(); 54145132Sanholt status = dev_priv->status_ptr[0]; 55145132Sanholt if ((status & mask) < threshold) 56145132Sanholt return 0; 57145132Sanholt DRM_UDELAY(1); 58145132Sanholt } 59145132Sanholt 60145132Sanholt#if SAVAGE_BCI_DEBUG 61145132Sanholt DRM_ERROR("failed!\n"); 62145132Sanholt DRM_INFO(" status=0x%08x, threshold=0x%08x\n", status, threshold); 63145132Sanholt#endif 64145132Sanholt return DRM_ERR(EBUSY); 65145132Sanholt} 66145132Sanholt 67145132Sanholtstatic int 68145132Sanholtsavage_bci_wait_fifo_s3d(drm_savage_private_t *dev_priv, unsigned int n) 69145132Sanholt{ 70145132Sanholt uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; 71145132Sanholt uint32_t status; 72145132Sanholt int i; 73145132Sanholt 74145132Sanholt for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) { 75145132Sanholt status = SAVAGE_READ(SAVAGE_STATUS_WORD0); 76145132Sanholt if ((status & SAVAGE_FIFO_USED_MASK_S3D) <= maxUsed) 77145132Sanholt return 0; 78145132Sanholt DRM_UDELAY(1); 79145132Sanholt } 80145132Sanholt 81145132Sanholt#if SAVAGE_BCI_DEBUG 82145132Sanholt DRM_ERROR("failed!\n"); 83145132Sanholt DRM_INFO(" status=0x%08x\n", status); 84145132Sanholt#endif 85145132Sanholt return DRM_ERR(EBUSY); 86145132Sanholt} 87145132Sanholt 88145132Sanholtstatic int 89145132Sanholtsavage_bci_wait_fifo_s4(drm_savage_private_t *dev_priv, unsigned int n) 90145132Sanholt{ 91145132Sanholt uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; 92145132Sanholt uint32_t status; 93145132Sanholt int i; 94145132Sanholt 95145132Sanholt for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) { 96145132Sanholt status = SAVAGE_READ(SAVAGE_ALT_STATUS_WORD0); 97145132Sanholt if ((status & SAVAGE_FIFO_USED_MASK_S4) <= maxUsed) 98145132Sanholt return 0; 99145132Sanholt DRM_UDELAY(1); 100145132Sanholt } 101145132Sanholt 102145132Sanholt#if SAVAGE_BCI_DEBUG 103145132Sanholt DRM_ERROR("failed!\n"); 104145132Sanholt DRM_INFO(" status=0x%08x\n", status); 105145132Sanholt#endif 106145132Sanholt return DRM_ERR(EBUSY); 107145132Sanholt} 108145132Sanholt 109145132Sanholt/* 110145132Sanholt * Waiting for events. 111145132Sanholt * 112145132Sanholt * The BIOSresets the event tag to 0 on mode changes. Therefore we 113145132Sanholt * never emit 0 to the event tag. If we find a 0 event tag we know the 114145132Sanholt * BIOS stomped on it and return success assuming that the BIOS waited 115145132Sanholt * for engine idle. 116145132Sanholt * 117145132Sanholt * Note: if the Xserver uses the event tag it has to follow the same 118145132Sanholt * rule. Otherwise there may be glitches every 2^16 events. 119145132Sanholt */ 120145132Sanholtstatic int 121145132Sanholtsavage_bci_wait_event_shadow(drm_savage_private_t *dev_priv, uint16_t e) 122145132Sanholt{ 123145132Sanholt uint32_t status; 124145132Sanholt int i; 125145132Sanholt 126145132Sanholt for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) { 127145132Sanholt DRM_MEMORYBARRIER(); 128145132Sanholt status = dev_priv->status_ptr[1]; 129145132Sanholt if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff || 130145132Sanholt (status & 0xffff) == 0) 131145132Sanholt return 0; 132145132Sanholt DRM_UDELAY(1); 133145132Sanholt } 134145132Sanholt 135145132Sanholt#if SAVAGE_BCI_DEBUG 136145132Sanholt DRM_ERROR("failed!\n"); 137145132Sanholt DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e); 138145132Sanholt#endif 139145132Sanholt 140145132Sanholt return DRM_ERR(EBUSY); 141145132Sanholt} 142145132Sanholt 143145132Sanholtstatic int 144145132Sanholtsavage_bci_wait_event_reg(drm_savage_private_t *dev_priv, uint16_t e) 145145132Sanholt{ 146145132Sanholt uint32_t status; 147145132Sanholt int i; 148145132Sanholt 149145132Sanholt for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) { 150145132Sanholt status = SAVAGE_READ(SAVAGE_STATUS_WORD1); 151145132Sanholt if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff || 152145132Sanholt (status & 0xffff) == 0) 153145132Sanholt return 0; 154145132Sanholt DRM_UDELAY(1); 155145132Sanholt } 156145132Sanholt 157145132Sanholt#if SAVAGE_BCI_DEBUG 158145132Sanholt DRM_ERROR("failed!\n"); 159145132Sanholt DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e); 160145132Sanholt#endif 161145132Sanholt 162145132Sanholt return DRM_ERR(EBUSY); 163145132Sanholt} 164145132Sanholt 165145132Sanholtuint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv, 166145132Sanholt unsigned int flags) 167145132Sanholt{ 168145132Sanholt BCI_LOCALS; 169145132Sanholt uint16_t count; 170145132Sanholt 171145132Sanholt if (dev_priv->status_ptr) { 172145132Sanholt /* coordinate with Xserver */ 173145132Sanholt count = dev_priv->status_ptr[1023]; 174145132Sanholt if (count < dev_priv->event_counter) 175145132Sanholt dev_priv->event_wrap++; 176145132Sanholt } else { 177145132Sanholt count = dev_priv->event_counter; 178145132Sanholt } 179145132Sanholt count = (count + 1) & 0xffff; 180145132Sanholt if (count == 0) { 181145132Sanholt count++; /* See the comment above savage_wait_event_*. */ 182145132Sanholt dev_priv->event_wrap++; 183145132Sanholt } 184145132Sanholt dev_priv->event_counter = count; 185145132Sanholt if (dev_priv->status_ptr) 186145132Sanholt dev_priv->status_ptr[1023] = (uint32_t)count; 187145132Sanholt 188145132Sanholt if ((flags & (SAVAGE_WAIT_2D | SAVAGE_WAIT_3D))) { 189145132Sanholt unsigned int wait_cmd = BCI_CMD_WAIT; 190145132Sanholt if ((flags & SAVAGE_WAIT_2D)) 191145132Sanholt wait_cmd |= BCI_CMD_WAIT_2D; 192145132Sanholt if ((flags & SAVAGE_WAIT_3D)) 193145132Sanholt wait_cmd |= BCI_CMD_WAIT_3D; 194145132Sanholt BEGIN_BCI(2); 195145132Sanholt BCI_WRITE(wait_cmd); 196145132Sanholt } else { 197145132Sanholt BEGIN_BCI(1); 198145132Sanholt } 199145132Sanholt BCI_WRITE(BCI_CMD_UPDATE_EVENT_TAG | (uint32_t)count); 200145132Sanholt 201145132Sanholt return count; 202145132Sanholt} 203145132Sanholt 204145132Sanholt/* 205145132Sanholt * Freelist management 206145132Sanholt */ 207145132Sanholtstatic int savage_freelist_init(drm_device_t *dev) 208145132Sanholt{ 209145132Sanholt drm_savage_private_t *dev_priv = dev->dev_private; 210145132Sanholt drm_device_dma_t *dma = dev->dma; 211145132Sanholt drm_buf_t *buf; 212145132Sanholt drm_savage_buf_priv_t *entry; 213145132Sanholt int i; 214145132Sanholt DRM_DEBUG("count=%d\n", dma->buf_count); 215145132Sanholt 216145132Sanholt dev_priv->head.next = &dev_priv->tail; 217145132Sanholt dev_priv->head.prev = NULL; 218145132Sanholt dev_priv->head.buf = NULL; 219145132Sanholt 220145132Sanholt dev_priv->tail.next = NULL; 221145132Sanholt dev_priv->tail.prev = &dev_priv->head; 222145132Sanholt dev_priv->tail.buf = NULL; 223145132Sanholt 224145132Sanholt for (i = 0; i < dma->buf_count; i++) { 225145132Sanholt buf = dma->buflist[i]; 226145132Sanholt entry = buf->dev_private; 227145132Sanholt 228145132Sanholt SET_AGE(&entry->age, 0, 0); 229145132Sanholt entry->buf = buf; 230145132Sanholt 231145132Sanholt entry->next = dev_priv->head.next; 232145132Sanholt entry->prev = &dev_priv->head; 233145132Sanholt dev_priv->head.next->prev = entry; 234145132Sanholt dev_priv->head.next = entry; 235145132Sanholt } 236145132Sanholt 237145132Sanholt return 0; 238145132Sanholt} 239145132Sanholt 240145132Sanholtstatic drm_buf_t *savage_freelist_get(drm_device_t *dev) 241145132Sanholt{ 242145132Sanholt drm_savage_private_t *dev_priv = dev->dev_private; 243145132Sanholt drm_savage_buf_priv_t *tail = dev_priv->tail.prev; 244145132Sanholt uint16_t event; 245145132Sanholt unsigned int wrap; 246145132Sanholt DRM_DEBUG("\n"); 247145132Sanholt 248145132Sanholt UPDATE_EVENT_COUNTER(); 249145132Sanholt if (dev_priv->status_ptr) 250145132Sanholt event = dev_priv->status_ptr[1] & 0xffff; 251145132Sanholt else 252145132Sanholt event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff; 253145132Sanholt wrap = dev_priv->event_wrap; 254145132Sanholt if (event > dev_priv->event_counter) 255145132Sanholt wrap--; /* hardware hasn't passed the last wrap yet */ 256145132Sanholt 257145132Sanholt DRM_DEBUG(" tail=0x%04x %d\n", tail->age.event, tail->age.wrap); 258145132Sanholt DRM_DEBUG(" head=0x%04x %d\n", event, wrap); 259145132Sanholt 260145132Sanholt if (tail->buf && (TEST_AGE(&tail->age, event, wrap) || event == 0)) { 261145132Sanholt drm_savage_buf_priv_t *next = tail->next; 262145132Sanholt drm_savage_buf_priv_t *prev = tail->prev; 263145132Sanholt prev->next = next; 264145132Sanholt next->prev = prev; 265145132Sanholt tail->next = tail->prev = NULL; 266145132Sanholt return tail->buf; 267145132Sanholt } 268145132Sanholt 269145132Sanholt DRM_DEBUG("returning NULL, tail->buf=%p!\n", tail->buf); 270145132Sanholt return NULL; 271145132Sanholt} 272145132Sanholt 273145132Sanholtvoid savage_freelist_put(drm_device_t *dev, drm_buf_t *buf) 274145132Sanholt{ 275145132Sanholt drm_savage_private_t *dev_priv = dev->dev_private; 276145132Sanholt drm_savage_buf_priv_t *entry = buf->dev_private, *prev, *next; 277145132Sanholt 278145132Sanholt DRM_DEBUG("age=0x%04x wrap=%d\n", entry->age.event, entry->age.wrap); 279145132Sanholt 280145132Sanholt if (entry->next != NULL || entry->prev != NULL) { 281145132Sanholt DRM_ERROR("entry already on freelist.\n"); 282145132Sanholt return; 283145132Sanholt } 284145132Sanholt 285145132Sanholt prev = &dev_priv->head; 286145132Sanholt next = prev->next; 287145132Sanholt prev->next = entry; 288145132Sanholt next->prev = entry; 289145132Sanholt entry->prev = prev; 290145132Sanholt entry->next = next; 291145132Sanholt} 292145132Sanholt 293145132Sanholt/* 294145132Sanholt * Command DMA 295145132Sanholt */ 296145132Sanholtstatic int savage_dma_init(drm_savage_private_t *dev_priv) 297145132Sanholt{ 298145132Sanholt unsigned int i; 299145132Sanholt 300145132Sanholt dev_priv->nr_dma_pages = dev_priv->cmd_dma->size / 301145132Sanholt (SAVAGE_DMA_PAGE_SIZE*4); 302145132Sanholt dev_priv->dma_pages = drm_alloc(sizeof(drm_savage_dma_page_t) * 303145132Sanholt dev_priv->nr_dma_pages, 304145132Sanholt DRM_MEM_DRIVER); 305145132Sanholt if (dev_priv->dma_pages == NULL) 306145132Sanholt return DRM_ERR(ENOMEM); 307145132Sanholt 308145132Sanholt for (i = 0; i < dev_priv->nr_dma_pages; ++i) { 309145132Sanholt SET_AGE(&dev_priv->dma_pages[i].age, 0, 0); 310145132Sanholt dev_priv->dma_pages[i].used = 0; 311145132Sanholt dev_priv->dma_pages[i].flushed = 0; 312145132Sanholt } 313145132Sanholt SET_AGE(&dev_priv->last_dma_age, 0, 0); 314145132Sanholt 315145132Sanholt dev_priv->first_dma_page = 0; 316145132Sanholt dev_priv->current_dma_page = 0; 317145132Sanholt 318145132Sanholt return 0; 319145132Sanholt} 320145132Sanholt 321145132Sanholtvoid savage_dma_reset(drm_savage_private_t *dev_priv) 322145132Sanholt{ 323145132Sanholt uint16_t event; 324145132Sanholt unsigned int wrap, i; 325145132Sanholt event = savage_bci_emit_event(dev_priv, 0); 326145132Sanholt wrap = dev_priv->event_wrap; 327145132Sanholt for (i = 0; i < dev_priv->nr_dma_pages; ++i) { 328145132Sanholt SET_AGE(&dev_priv->dma_pages[i].age, event, wrap); 329145132Sanholt dev_priv->dma_pages[i].used = 0; 330145132Sanholt dev_priv->dma_pages[i].flushed = 0; 331145132Sanholt } 332145132Sanholt SET_AGE(&dev_priv->last_dma_age, event, wrap); 333145132Sanholt dev_priv->first_dma_page = dev_priv->current_dma_page = 0; 334145132Sanholt} 335145132Sanholt 336145132Sanholtvoid savage_dma_wait(drm_savage_private_t *dev_priv, unsigned int page) 337145132Sanholt{ 338145132Sanholt uint16_t event; 339145132Sanholt unsigned int wrap; 340145132Sanholt 341145132Sanholt /* Faked DMA buffer pages don't age. */ 342145132Sanholt if (dev_priv->cmd_dma == &dev_priv->fake_dma) 343145132Sanholt return; 344145132Sanholt 345145132Sanholt UPDATE_EVENT_COUNTER(); 346145132Sanholt if (dev_priv->status_ptr) 347145132Sanholt event = dev_priv->status_ptr[1] & 0xffff; 348145132Sanholt else 349145132Sanholt event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff; 350145132Sanholt wrap = dev_priv->event_wrap; 351145132Sanholt if (event > dev_priv->event_counter) 352145132Sanholt wrap--; /* hardware hasn't passed the last wrap yet */ 353145132Sanholt 354145132Sanholt if (dev_priv->dma_pages[page].age.wrap > wrap || 355145132Sanholt (dev_priv->dma_pages[page].age.wrap == wrap && 356145132Sanholt dev_priv->dma_pages[page].age.event > event)) { 357145132Sanholt if (dev_priv->wait_evnt(dev_priv, 358145132Sanholt dev_priv->dma_pages[page].age.event) 359145132Sanholt < 0) 360145132Sanholt DRM_ERROR("wait_evnt failed!\n"); 361145132Sanholt } 362145132Sanholt} 363145132Sanholt 364145132Sanholtuint32_t *savage_dma_alloc(drm_savage_private_t *dev_priv, unsigned int n) 365145132Sanholt{ 366145132Sanholt unsigned int cur = dev_priv->current_dma_page; 367145132Sanholt unsigned int rest = SAVAGE_DMA_PAGE_SIZE - 368145132Sanholt dev_priv->dma_pages[cur].used; 369145132Sanholt unsigned int nr_pages = (n - rest + SAVAGE_DMA_PAGE_SIZE-1) / 370145132Sanholt SAVAGE_DMA_PAGE_SIZE; 371145132Sanholt uint32_t *dma_ptr; 372145132Sanholt unsigned int i; 373145132Sanholt 374145132Sanholt DRM_DEBUG("cur=%u, cur->used=%u, n=%u, rest=%u, nr_pages=%u\n", 375145132Sanholt cur, dev_priv->dma_pages[cur].used, n, rest, nr_pages); 376145132Sanholt 377145132Sanholt if (cur + nr_pages < dev_priv->nr_dma_pages) { 378145132Sanholt dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + 379145132Sanholt cur*SAVAGE_DMA_PAGE_SIZE + 380145132Sanholt dev_priv->dma_pages[cur].used; 381145132Sanholt if (n < rest) 382145132Sanholt rest = n; 383145132Sanholt dev_priv->dma_pages[cur].used += rest; 384145132Sanholt n -= rest; 385145132Sanholt cur++; 386145132Sanholt } else { 387145132Sanholt dev_priv->dma_flush(dev_priv); 388145132Sanholt nr_pages = (n + SAVAGE_DMA_PAGE_SIZE-1) / SAVAGE_DMA_PAGE_SIZE; 389145132Sanholt for (i = cur; i < dev_priv->nr_dma_pages; ++i) { 390145132Sanholt dev_priv->dma_pages[i].age = dev_priv->last_dma_age; 391145132Sanholt dev_priv->dma_pages[i].used = 0; 392145132Sanholt dev_priv->dma_pages[i].flushed = 0; 393145132Sanholt } 394145132Sanholt dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle; 395145132Sanholt dev_priv->first_dma_page = cur = 0; 396145132Sanholt } 397145132Sanholt for (i = cur; nr_pages > 0; ++i, --nr_pages) { 398145132Sanholt#if SAVAGE_DMA_DEBUG 399145132Sanholt if (dev_priv->dma_pages[i].used) { 400145132Sanholt DRM_ERROR("unflushed page %u: used=%u\n", 401145132Sanholt i, dev_priv->dma_pages[i].used); 402145132Sanholt } 403145132Sanholt#endif 404145132Sanholt if (n > SAVAGE_DMA_PAGE_SIZE) 405145132Sanholt dev_priv->dma_pages[i].used = SAVAGE_DMA_PAGE_SIZE; 406145132Sanholt else 407145132Sanholt dev_priv->dma_pages[i].used = n; 408145132Sanholt n -= SAVAGE_DMA_PAGE_SIZE; 409145132Sanholt } 410145132Sanholt dev_priv->current_dma_page = --i; 411145132Sanholt 412145132Sanholt DRM_DEBUG("cur=%u, cur->used=%u, n=%u\n", 413145132Sanholt i, dev_priv->dma_pages[i].used, n); 414145132Sanholt 415145132Sanholt savage_dma_wait(dev_priv, dev_priv->current_dma_page); 416145132Sanholt 417145132Sanholt return dma_ptr; 418145132Sanholt} 419145132Sanholt 420145132Sanholtstatic void savage_dma_flush(drm_savage_private_t *dev_priv) 421145132Sanholt{ 422145132Sanholt BCI_LOCALS; 423145132Sanholt unsigned int first = dev_priv->first_dma_page; 424145132Sanholt unsigned int cur = dev_priv->current_dma_page; 425145132Sanholt uint16_t event; 426145132Sanholt unsigned int wrap, pad, align, len, i; 427145132Sanholt unsigned long phys_addr; 428145132Sanholt 429145132Sanholt if (first == cur && 430145132Sanholt dev_priv->dma_pages[cur].used == dev_priv->dma_pages[cur].flushed) 431145132Sanholt return; 432145132Sanholt 433145132Sanholt /* pad length to multiples of 2 entries 434145132Sanholt * align start of next DMA block to multiles of 8 entries */ 435145132Sanholt pad = -dev_priv->dma_pages[cur].used & 1; 436145132Sanholt align = -(dev_priv->dma_pages[cur].used + pad) & 7; 437145132Sanholt 438145132Sanholt DRM_DEBUG("first=%u, cur=%u, first->flushed=%u, cur->used=%u, " 439145132Sanholt "pad=%u, align=%u\n", 440145132Sanholt first, cur, dev_priv->dma_pages[first].flushed, 441145132Sanholt dev_priv->dma_pages[cur].used, pad, align); 442145132Sanholt 443145132Sanholt /* pad with noops */ 444145132Sanholt if (pad) { 445145132Sanholt uint32_t *dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + 446145132Sanholt cur * SAVAGE_DMA_PAGE_SIZE + 447145132Sanholt dev_priv->dma_pages[cur].used; 448145132Sanholt dev_priv->dma_pages[cur].used += pad; 449145132Sanholt while(pad != 0) { 450145132Sanholt *dma_ptr++ = BCI_CMD_WAIT; 451145132Sanholt pad--; 452145132Sanholt } 453145132Sanholt } 454145132Sanholt 455145132Sanholt DRM_MEMORYBARRIER(); 456145132Sanholt 457145132Sanholt /* do flush ... */ 458145132Sanholt phys_addr = dev_priv->cmd_dma->offset + 459145132Sanholt (first * SAVAGE_DMA_PAGE_SIZE + 460145132Sanholt dev_priv->dma_pages[first].flushed) * 4; 461145132Sanholt len = (cur - first) * SAVAGE_DMA_PAGE_SIZE + 462145132Sanholt dev_priv->dma_pages[cur].used - 463145132Sanholt dev_priv->dma_pages[first].flushed; 464145132Sanholt 465145132Sanholt DRM_DEBUG("phys_addr=%lx, len=%u\n", 466145132Sanholt phys_addr | dev_priv->dma_type, len); 467145132Sanholt 468145132Sanholt BEGIN_BCI(3); 469145132Sanholt BCI_SET_REGISTERS(SAVAGE_DMABUFADDR, 1); 470145132Sanholt BCI_WRITE(phys_addr | dev_priv->dma_type); 471145132Sanholt BCI_DMA(len); 472145132Sanholt 473145132Sanholt /* fix alignment of the start of the next block */ 474145132Sanholt dev_priv->dma_pages[cur].used += align; 475145132Sanholt 476145132Sanholt /* age DMA pages */ 477145132Sanholt event = savage_bci_emit_event(dev_priv, 0); 478145132Sanholt wrap = dev_priv->event_wrap; 479145132Sanholt for (i = first; i < cur; ++i) { 480145132Sanholt SET_AGE(&dev_priv->dma_pages[i].age, event, wrap); 481145132Sanholt dev_priv->dma_pages[i].used = 0; 482145132Sanholt dev_priv->dma_pages[i].flushed = 0; 483145132Sanholt } 484145132Sanholt /* age the current page only when it's full */ 485145132Sanholt if (dev_priv->dma_pages[cur].used == SAVAGE_DMA_PAGE_SIZE) { 486145132Sanholt SET_AGE(&dev_priv->dma_pages[cur].age, event, wrap); 487145132Sanholt dev_priv->dma_pages[cur].used = 0; 488145132Sanholt dev_priv->dma_pages[cur].flushed = 0; 489145132Sanholt /* advance to next page */ 490145132Sanholt cur++; 491145132Sanholt if (cur == dev_priv->nr_dma_pages) 492145132Sanholt cur = 0; 493145132Sanholt dev_priv->first_dma_page = dev_priv->current_dma_page = cur; 494145132Sanholt } else { 495145132Sanholt dev_priv->first_dma_page = cur; 496145132Sanholt dev_priv->dma_pages[cur].flushed = dev_priv->dma_pages[i].used; 497145132Sanholt } 498145132Sanholt SET_AGE(&dev_priv->last_dma_age, event, wrap); 499145132Sanholt 500145132Sanholt DRM_DEBUG("first=cur=%u, cur->used=%u, cur->flushed=%u\n", cur, 501145132Sanholt dev_priv->dma_pages[cur].used, 502145132Sanholt dev_priv->dma_pages[cur].flushed); 503145132Sanholt} 504145132Sanholt 505145132Sanholtstatic void savage_fake_dma_flush(drm_savage_private_t *dev_priv) 506145132Sanholt{ 507145132Sanholt BCI_LOCALS; 508145132Sanholt unsigned int i, j; 509145132Sanholt if (dev_priv->first_dma_page == dev_priv->current_dma_page && 510145132Sanholt dev_priv->dma_pages[dev_priv->current_dma_page].used == 0) 511145132Sanholt return; 512145132Sanholt 513145132Sanholt DRM_DEBUG("first=%u, cur=%u, cur->used=%u\n", 514145132Sanholt dev_priv->first_dma_page, dev_priv->current_dma_page, 515145132Sanholt dev_priv->dma_pages[dev_priv->current_dma_page].used); 516145132Sanholt 517145132Sanholt for (i = dev_priv->first_dma_page; 518145132Sanholt i <= dev_priv->current_dma_page && dev_priv->dma_pages[i].used; 519145132Sanholt ++i) { 520145132Sanholt uint32_t *dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + 521145132Sanholt i * SAVAGE_DMA_PAGE_SIZE; 522145132Sanholt#if SAVAGE_DMA_DEBUG 523145132Sanholt /* Sanity check: all pages except the last one must be full. */ 524145132Sanholt if (i < dev_priv->current_dma_page && 525145132Sanholt dev_priv->dma_pages[i].used != SAVAGE_DMA_PAGE_SIZE) { 526145132Sanholt DRM_ERROR("partial DMA page %u: used=%u", 527145132Sanholt i, dev_priv->dma_pages[i].used); 528145132Sanholt } 529145132Sanholt#endif 530145132Sanholt BEGIN_BCI(dev_priv->dma_pages[i].used); 531145132Sanholt for (j = 0; j < dev_priv->dma_pages[i].used; ++j) { 532145132Sanholt BCI_WRITE(dma_ptr[j]); 533145132Sanholt } 534145132Sanholt dev_priv->dma_pages[i].used = 0; 535145132Sanholt } 536145132Sanholt 537145132Sanholt /* reset to first page */ 538145132Sanholt dev_priv->first_dma_page = dev_priv->current_dma_page = 0; 539145132Sanholt} 540145132Sanholt 541145132Sanholt/* 542145132Sanholt * Initalize permanent mappings. On Savage4 and SavageIX the alignment 543145132Sanholt * and size of the aperture is not suitable for automatic MTRR setup 544145132Sanholt * in drm_initmap. Therefore we do it manually before the maps are 545145132Sanholt * initialized. We also need to take care of deleting the MTRRs in 546145132Sanholt * postcleanup. 547145132Sanholt * 548145132Sanholt * FIXME: this is linux-specific 549145132Sanholt */ 550145132Sanholtint savage_preinit(drm_device_t *dev, unsigned long chipset) 551145132Sanholt{ 552145132Sanholt drm_savage_private_t *dev_priv; 553145132Sanholt unsigned long mmio_base, fb_base, fb_size, aperture_base; 554145132Sanholt unsigned int fb_rsrc, aper_rsrc; 555145132Sanholt int ret = 0; 556145132Sanholt 557145132Sanholt dev_priv = drm_alloc(sizeof(drm_savage_private_t), DRM_MEM_DRIVER); 558145132Sanholt if (dev_priv == NULL) 559145132Sanholt return DRM_ERR(ENOMEM); 560145132Sanholt 561145132Sanholt memset(dev_priv, 0, sizeof(drm_savage_private_t)); 562145132Sanholt dev->dev_private = (void *)dev_priv; 563145132Sanholt dev_priv->chipset = (enum savage_family)chipset; 564145132Sanholt 565145132Sanholt dev_priv->mtrr[0].handle = -1; 566145132Sanholt dev_priv->mtrr[1].handle = -1; 567145132Sanholt dev_priv->mtrr[2].handle = -1; 568145132Sanholt if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 569145132Sanholt fb_rsrc = 0; 570145132Sanholt fb_base = drm_get_resource_start(dev, 0); 571145132Sanholt fb_size = SAVAGE_FB_SIZE_S3; 572145132Sanholt mmio_base = fb_base + SAVAGE_FB_SIZE_S3; 573145132Sanholt aper_rsrc = 0; 574145132Sanholt aperture_base = fb_base + SAVAGE_APERTURE_OFFSET; 575145132Sanholt /* this should always be true */ 576145132Sanholt if (drm_get_resource_len(dev, 0) == 0x08000000) { 577145132Sanholt /* Don't make MMIO write-cobining! We need 3 578145132Sanholt * MTRRs. */ 579145132Sanholt dev_priv->mtrr[0].base = fb_base; 580145132Sanholt dev_priv->mtrr[0].size = 0x01000000; 581145132Sanholt dev_priv->mtrr[0].handle = mtrr_add( 582145132Sanholt dev_priv->mtrr[0].base, dev_priv->mtrr[0].size, 583145132Sanholt MTRR_TYPE_WRCOMB, 1); 584145132Sanholt dev_priv->mtrr[1].base = fb_base+0x02000000; 585145132Sanholt dev_priv->mtrr[1].size = 0x02000000; 586145132Sanholt dev_priv->mtrr[1].handle = mtrr_add( 587145132Sanholt dev_priv->mtrr[1].base, dev_priv->mtrr[1].size, 588145132Sanholt MTRR_TYPE_WRCOMB, 1); 589145132Sanholt dev_priv->mtrr[2].base = fb_base+0x04000000; 590145132Sanholt dev_priv->mtrr[2].size = 0x04000000; 591145132Sanholt dev_priv->mtrr[2].handle = mtrr_add( 592145132Sanholt dev_priv->mtrr[2].base, dev_priv->mtrr[2].size, 593145132Sanholt MTRR_TYPE_WRCOMB, 1); 594145132Sanholt } else { 595145132Sanholt DRM_ERROR("strange pci_resource_len %08lx\n", 596145132Sanholt drm_get_resource_len(dev, 0)); 597145132Sanholt } 598145132Sanholt } else if (chipset != S3_SUPERSAVAGE && chipset != S3_SAVAGE2000) { 599145132Sanholt mmio_base = drm_get_resource_start(dev, 0); 600145132Sanholt fb_rsrc = 1; 601145132Sanholt fb_base = drm_get_resource_start(dev, 1); 602145132Sanholt fb_size = SAVAGE_FB_SIZE_S4; 603145132Sanholt aper_rsrc = 1; 604145132Sanholt aperture_base = fb_base + SAVAGE_APERTURE_OFFSET; 605145132Sanholt /* this should always be true */ 606145132Sanholt if (drm_get_resource_len(dev, 1) == 0x08000000) { 607145132Sanholt /* Can use one MTRR to cover both fb and 608145132Sanholt * aperture. */ 609145132Sanholt dev_priv->mtrr[0].base = fb_base; 610145132Sanholt dev_priv->mtrr[0].size = 0x08000000; 611145132Sanholt dev_priv->mtrr[0].handle = mtrr_add( 612145132Sanholt dev_priv->mtrr[0].base, dev_priv->mtrr[0].size, 613145132Sanholt MTRR_TYPE_WRCOMB, 1); 614145132Sanholt } else { 615145132Sanholt DRM_ERROR("strange pci_resource_len %08lx\n", 616145132Sanholt drm_get_resource_len(dev, 1)); 617145132Sanholt } 618145132Sanholt } else { 619145132Sanholt mmio_base = drm_get_resource_start(dev, 0); 620145132Sanholt fb_rsrc = 1; 621145132Sanholt fb_base = drm_get_resource_start(dev, 1); 622145132Sanholt fb_size = drm_get_resource_len(dev, 1); 623145132Sanholt aper_rsrc = 2; 624145132Sanholt aperture_base = drm_get_resource_start(dev, 2); 625145132Sanholt /* Automatic MTRR setup will do the right thing. */ 626145132Sanholt } 627145132Sanholt 628145132Sanholt if ((ret = drm_initmap(dev, mmio_base, SAVAGE_MMIO_SIZE, 0, 629145132Sanholt _DRM_REGISTERS, 0))) 630145132Sanholt return ret; 631145132Sanholt if (!(dev_priv->mmio = drm_core_findmap (dev, mmio_base))) 632145132Sanholt return DRM_ERR(ENOMEM); 633145132Sanholt 634145132Sanholt if ((ret = drm_initmap(dev, fb_base, fb_size, fb_rsrc, 635145132Sanholt _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING))) 636145132Sanholt return ret; 637145132Sanholt if (!(dev_priv->fb = drm_core_findmap (dev, fb_base))) 638145132Sanholt return DRM_ERR(ENOMEM); 639145132Sanholt 640145132Sanholt if ((ret = drm_initmap(dev, aperture_base, SAVAGE_APERTURE_SIZE, 641145132Sanholt aper_rsrc, 642145132Sanholt _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING))) 643145132Sanholt return ret; 644145132Sanholt if (!(dev_priv->aperture = drm_core_findmap (dev, aperture_base))) 645145132Sanholt return DRM_ERR(ENOMEM); 646145132Sanholt 647145132Sanholt return ret; 648145132Sanholt} 649145132Sanholt 650145132Sanholt/* 651145132Sanholt * Delete MTRRs and free device-private data. 652145132Sanholt */ 653145132Sanholtint savage_postcleanup(drm_device_t *dev) 654145132Sanholt{ 655145132Sanholt drm_savage_private_t *dev_priv = dev->dev_private; 656145132Sanholt int i; 657145132Sanholt 658145132Sanholt for (i = 0; i < 3; ++i) 659145132Sanholt if (dev_priv->mtrr[i].handle >= 0) 660145132Sanholt mtrr_del(dev_priv->mtrr[i].handle, 661145132Sanholt dev_priv->mtrr[i].base, 662145132Sanholt dev_priv->mtrr[i].size); 663145132Sanholt 664145132Sanholt drm_free(dev_priv, sizeof(drm_savage_private_t), DRM_MEM_DRIVER); 665145132Sanholt 666145132Sanholt return 0; 667145132Sanholt} 668145132Sanholt 669145132Sanholtstatic int savage_do_init_bci(drm_device_t *dev, drm_savage_init_t *init) 670145132Sanholt{ 671145132Sanholt drm_savage_private_t *dev_priv = dev->dev_private; 672145132Sanholt 673145132Sanholt if (init->fb_bpp != 16 && init->fb_bpp != 32) { 674145132Sanholt DRM_ERROR("invalid frame buffer bpp %d!\n", init->fb_bpp); 675145132Sanholt return DRM_ERR(EINVAL); 676145132Sanholt } 677145132Sanholt if (init->depth_bpp != 16 && init->depth_bpp != 32) { 678145132Sanholt DRM_ERROR("invalid depth buffer bpp %d!\n", init->fb_bpp); 679145132Sanholt return DRM_ERR(EINVAL); 680145132Sanholt } 681145132Sanholt if (init->dma_type != SAVAGE_DMA_AGP && 682145132Sanholt init->dma_type != SAVAGE_DMA_PCI) { 683145132Sanholt DRM_ERROR("invalid dma memory type %d!\n", init->dma_type); 684145132Sanholt return DRM_ERR(EINVAL); 685145132Sanholt } 686145132Sanholt 687145132Sanholt dev_priv->cob_size = init->cob_size; 688145132Sanholt dev_priv->bci_threshold_lo = init->bci_threshold_lo; 689145132Sanholt dev_priv->bci_threshold_hi = init->bci_threshold_hi; 690145132Sanholt dev_priv->dma_type = init->dma_type; 691145132Sanholt 692145132Sanholt dev_priv->fb_bpp = init->fb_bpp; 693145132Sanholt dev_priv->front_offset = init->front_offset; 694145132Sanholt dev_priv->front_pitch = init->front_pitch; 695145132Sanholt dev_priv->back_offset = init->back_offset; 696145132Sanholt dev_priv->back_pitch = init->back_pitch; 697145132Sanholt dev_priv->depth_bpp = init->depth_bpp; 698145132Sanholt dev_priv->depth_offset = init->depth_offset; 699145132Sanholt dev_priv->depth_pitch = init->depth_pitch; 700145132Sanholt 701145132Sanholt dev_priv->texture_offset = init->texture_offset; 702145132Sanholt dev_priv->texture_size = init->texture_size; 703145132Sanholt 704145132Sanholt DRM_GETSAREA(); 705145132Sanholt if (!dev_priv->sarea) { 706145132Sanholt DRM_ERROR("could not find sarea!\n"); 707145132Sanholt savage_do_cleanup_bci(dev); 708145132Sanholt return DRM_ERR(EINVAL); 709145132Sanholt } 710145132Sanholt if (init->status_offset != 0) { 711145132Sanholt dev_priv->status = drm_core_findmap(dev, init->status_offset); 712145132Sanholt if (!dev_priv->status) { 713145132Sanholt DRM_ERROR("could not find shadow status region!\n"); 714145132Sanholt savage_do_cleanup_bci(dev); 715145132Sanholt return DRM_ERR(EINVAL); 716145132Sanholt } 717145132Sanholt } else { 718145132Sanholt dev_priv->status = NULL; 719145132Sanholt } 720145132Sanholt if (dev_priv->dma_type == SAVAGE_DMA_AGP && init->buffers_offset) { 721145132Sanholt dev->agp_buffer_map = drm_core_findmap(dev, 722145132Sanholt init->buffers_offset); 723145132Sanholt if (!dev->agp_buffer_map) { 724145132Sanholt DRM_ERROR("could not find DMA buffer region!\n"); 725145132Sanholt savage_do_cleanup_bci(dev); 726145132Sanholt return DRM_ERR(EINVAL); 727145132Sanholt } 728145132Sanholt drm_core_ioremap(dev->agp_buffer_map, dev); 729145132Sanholt if (!dev->agp_buffer_map) { 730145132Sanholt DRM_ERROR("failed to ioremap DMA buffer region!\n"); 731145132Sanholt savage_do_cleanup_bci(dev); 732145132Sanholt return DRM_ERR(ENOMEM); 733145132Sanholt } 734145132Sanholt } 735145132Sanholt if (init->agp_textures_offset) { 736145132Sanholt dev_priv->agp_textures = 737145132Sanholt drm_core_findmap(dev, init->agp_textures_offset); 738145132Sanholt if (!dev_priv->agp_textures) { 739145132Sanholt DRM_ERROR("could not find agp texture region!\n"); 740145132Sanholt savage_do_cleanup_bci(dev); 741145132Sanholt return DRM_ERR(EINVAL); 742145132Sanholt } 743145132Sanholt } else { 744145132Sanholt dev_priv->agp_textures = NULL; 745145132Sanholt } 746145132Sanholt 747145132Sanholt if (init->cmd_dma_offset) { 748145132Sanholt if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 749145132Sanholt DRM_ERROR("command DMA not supported on " 750145132Sanholt "Savage3D/MX/IX.\n"); 751145132Sanholt savage_do_cleanup_bci(dev); 752145132Sanholt return DRM_ERR(EINVAL); 753145132Sanholt } 754145132Sanholt if (dev->dma && dev->dma->buflist) { 755145132Sanholt DRM_ERROR("command and vertex DMA not supported " 756145132Sanholt "at the same time.\n"); 757145132Sanholt savage_do_cleanup_bci(dev); 758145132Sanholt return DRM_ERR(EINVAL); 759145132Sanholt } 760145132Sanholt dev_priv->cmd_dma = drm_core_findmap(dev, init->cmd_dma_offset); 761145132Sanholt if (!dev_priv->cmd_dma) { 762145132Sanholt DRM_ERROR("could not find command DMA region!\n"); 763145132Sanholt savage_do_cleanup_bci(dev); 764145132Sanholt return DRM_ERR(EINVAL); 765145132Sanholt } 766145132Sanholt if (dev_priv->dma_type == SAVAGE_DMA_AGP) { 767145132Sanholt if (dev_priv->cmd_dma->type != _DRM_AGP) { 768145132Sanholt DRM_ERROR("AGP command DMA region is not a " 769145132Sanholt "_DRM_AGP map!\n"); 770145132Sanholt savage_do_cleanup_bci(dev); 771145132Sanholt return DRM_ERR(EINVAL); 772145132Sanholt } 773145132Sanholt drm_core_ioremap(dev_priv->cmd_dma, dev); 774145132Sanholt if (!dev_priv->cmd_dma->handle) { 775145132Sanholt DRM_ERROR("failed to ioremap command " 776145132Sanholt "DMA region!\n"); 777145132Sanholt savage_do_cleanup_bci(dev); 778145132Sanholt return DRM_ERR(ENOMEM); 779145132Sanholt } 780145132Sanholt } else if (dev_priv->cmd_dma->type != _DRM_CONSISTENT) { 781145132Sanholt DRM_ERROR("PCI command DMA region is not a " 782145132Sanholt "_DRM_CONSISTENT map!\n"); 783145132Sanholt savage_do_cleanup_bci(dev); 784145132Sanholt return DRM_ERR(EINVAL); 785145132Sanholt } 786145132Sanholt } else { 787145132Sanholt dev_priv->cmd_dma = NULL; 788145132Sanholt } 789145132Sanholt 790145132Sanholt dev_priv->dma_flush = savage_dma_flush; 791145132Sanholt if (!dev_priv->cmd_dma) { 792145132Sanholt DRM_DEBUG("falling back to faked command DMA.\n"); 793145132Sanholt dev_priv->fake_dma.offset = 0; 794145132Sanholt dev_priv->fake_dma.size = SAVAGE_FAKE_DMA_SIZE; 795145132Sanholt dev_priv->fake_dma.type = _DRM_SHM; 796145132Sanholt dev_priv->fake_dma.handle = drm_alloc(SAVAGE_FAKE_DMA_SIZE, 797145132Sanholt DRM_MEM_DRIVER); 798145132Sanholt if (!dev_priv->fake_dma.handle) { 799145132Sanholt DRM_ERROR("could not allocate faked DMA buffer!\n"); 800145132Sanholt savage_do_cleanup_bci(dev); 801145132Sanholt return DRM_ERR(ENOMEM); 802145132Sanholt } 803145132Sanholt dev_priv->cmd_dma = &dev_priv->fake_dma; 804145132Sanholt dev_priv->dma_flush = savage_fake_dma_flush; 805145132Sanholt } 806145132Sanholt 807145132Sanholt dev_priv->sarea_priv = 808145132Sanholt (drm_savage_sarea_t *)((uint8_t *)dev_priv->sarea->handle + 809145132Sanholt init->sarea_priv_offset); 810145132Sanholt 811145132Sanholt /* setup bitmap descriptors */ 812145132Sanholt { 813145132Sanholt unsigned int color_tile_format; 814145132Sanholt unsigned int depth_tile_format; 815145132Sanholt unsigned int front_stride, back_stride, depth_stride; 816145132Sanholt if (dev_priv->chipset <= S3_SAVAGE4) { 817145132Sanholt color_tile_format = dev_priv->fb_bpp == 16 ? 818145132Sanholt SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP; 819145132Sanholt depth_tile_format = dev_priv->depth_bpp == 16 ? 820145132Sanholt SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP; 821145132Sanholt } else { 822145132Sanholt color_tile_format = SAVAGE_BD_TILE_DEST; 823145132Sanholt depth_tile_format = SAVAGE_BD_TILE_DEST; 824145132Sanholt } 825145132Sanholt front_stride = dev_priv->front_pitch / (dev_priv->fb_bpp/8); 826145132Sanholt back_stride = dev_priv-> back_pitch / (dev_priv->fb_bpp/8); 827145132Sanholt depth_stride = dev_priv->depth_pitch / (dev_priv->depth_bpp/8); 828145132Sanholt 829145132Sanholt dev_priv->front_bd = front_stride | SAVAGE_BD_BW_DISABLE | 830145132Sanholt (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) | 831145132Sanholt (color_tile_format << SAVAGE_BD_TILE_SHIFT); 832145132Sanholt 833145132Sanholt dev_priv-> back_bd = back_stride | SAVAGE_BD_BW_DISABLE | 834145132Sanholt (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) | 835145132Sanholt (color_tile_format << SAVAGE_BD_TILE_SHIFT); 836145132Sanholt 837145132Sanholt dev_priv->depth_bd = depth_stride | SAVAGE_BD_BW_DISABLE | 838145132Sanholt (dev_priv->depth_bpp << SAVAGE_BD_BPP_SHIFT) | 839145132Sanholt (depth_tile_format << SAVAGE_BD_TILE_SHIFT); 840145132Sanholt } 841145132Sanholt 842145132Sanholt /* setup status and bci ptr */ 843145132Sanholt dev_priv->event_counter = 0; 844145132Sanholt dev_priv->event_wrap = 0; 845145132Sanholt dev_priv->bci_ptr = (volatile uint32_t *) 846145132Sanholt ((uint8_t *)dev_priv->mmio->handle + SAVAGE_BCI_OFFSET); 847145132Sanholt if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 848145132Sanholt dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S3D; 849145132Sanholt } else { 850145132Sanholt dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S4; 851145132Sanholt } 852145132Sanholt if (dev_priv->status != NULL) { 853145132Sanholt dev_priv->status_ptr = 854145132Sanholt (volatile uint32_t *)dev_priv->status->handle; 855145132Sanholt dev_priv->wait_fifo = savage_bci_wait_fifo_shadow; 856145132Sanholt dev_priv->wait_evnt = savage_bci_wait_event_shadow; 857145132Sanholt dev_priv->status_ptr[1023] = dev_priv->event_counter; 858145132Sanholt } else { 859145132Sanholt dev_priv->status_ptr = NULL; 860145132Sanholt if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 861145132Sanholt dev_priv->wait_fifo = savage_bci_wait_fifo_s3d; 862145132Sanholt } else { 863145132Sanholt dev_priv->wait_fifo = savage_bci_wait_fifo_s4; 864145132Sanholt } 865145132Sanholt dev_priv->wait_evnt = savage_bci_wait_event_reg; 866145132Sanholt } 867145132Sanholt 868145132Sanholt /* cliprect functions */ 869145132Sanholt if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) 870145132Sanholt dev_priv->emit_clip_rect = savage_emit_clip_rect_s3d; 871145132Sanholt else 872145132Sanholt dev_priv->emit_clip_rect = savage_emit_clip_rect_s4; 873145132Sanholt 874145132Sanholt if (savage_freelist_init(dev) < 0) { 875145132Sanholt DRM_ERROR("could not initialize freelist\n"); 876145132Sanholt savage_do_cleanup_bci(dev); 877145132Sanholt return DRM_ERR(ENOMEM); 878145132Sanholt } 879145132Sanholt 880145132Sanholt if (savage_dma_init(dev_priv) < 0) { 881145132Sanholt DRM_ERROR("could not initialize command DMA\n"); 882145132Sanholt savage_do_cleanup_bci(dev); 883145132Sanholt return DRM_ERR(ENOMEM); 884145132Sanholt } 885145132Sanholt 886145132Sanholt return 0; 887145132Sanholt} 888145132Sanholt 889145132Sanholtint savage_do_cleanup_bci(drm_device_t *dev) 890145132Sanholt{ 891145132Sanholt drm_savage_private_t *dev_priv = dev->dev_private; 892145132Sanholt 893145132Sanholt if (dev_priv->cmd_dma == &dev_priv->fake_dma) { 894145132Sanholt if (dev_priv->fake_dma.handle) 895145132Sanholt drm_free(dev_priv->fake_dma.handle, 896145132Sanholt SAVAGE_FAKE_DMA_SIZE, DRM_MEM_DRIVER); 897145132Sanholt } else if (dev_priv->cmd_dma && dev_priv->cmd_dma->handle && 898145132Sanholt dev_priv->cmd_dma->type == _DRM_AGP && 899145132Sanholt dev_priv->dma_type == SAVAGE_DMA_AGP) 900145132Sanholt drm_core_ioremapfree(dev_priv->cmd_dma, dev); 901145132Sanholt 902145132Sanholt if (dev_priv->dma_type == SAVAGE_DMA_AGP && 903145132Sanholt dev->agp_buffer_map && dev->agp_buffer_map->handle) { 904145132Sanholt drm_core_ioremapfree(dev->agp_buffer_map, dev); 905145132Sanholt /* make sure the next instance (which may be running 906145132Sanholt * in PCI mode) doesn't try to use an old 907145132Sanholt * agp_buffer_map. */ 908145132Sanholt dev->agp_buffer_map = NULL; 909145132Sanholt } 910145132Sanholt 911145132Sanholt if (dev_priv->dma_pages) 912145132Sanholt drm_free(dev_priv->dma_pages, 913145132Sanholt sizeof(drm_savage_dma_page_t)*dev_priv->nr_dma_pages, 914145132Sanholt DRM_MEM_DRIVER); 915145132Sanholt 916145132Sanholt return 0; 917145132Sanholt} 918145132Sanholt 919145132Sanholtint savage_bci_init(DRM_IOCTL_ARGS) 920145132Sanholt{ 921145132Sanholt DRM_DEVICE; 922145132Sanholt drm_savage_init_t init; 923145132Sanholt 924145132Sanholt LOCK_TEST_WITH_RETURN(dev, filp); 925145132Sanholt 926145132Sanholt DRM_COPY_FROM_USER_IOCTL(init, (drm_savage_init_t __user *)data, 927145132Sanholt sizeof(init)); 928145132Sanholt 929145132Sanholt switch (init.func) { 930145132Sanholt case SAVAGE_INIT_BCI: 931145132Sanholt return savage_do_init_bci(dev, &init); 932145132Sanholt case SAVAGE_CLEANUP_BCI: 933145132Sanholt return savage_do_cleanup_bci(dev); 934145132Sanholt } 935145132Sanholt 936145132Sanholt return DRM_ERR(EINVAL); 937145132Sanholt} 938145132Sanholt 939145132Sanholtint savage_bci_event_emit(DRM_IOCTL_ARGS) 940145132Sanholt{ 941145132Sanholt DRM_DEVICE; 942145132Sanholt drm_savage_private_t *dev_priv = dev->dev_private; 943145132Sanholt drm_savage_event_emit_t event; 944145132Sanholt 945145132Sanholt DRM_DEBUG("\n"); 946145132Sanholt 947145132Sanholt LOCK_TEST_WITH_RETURN(dev, filp); 948145132Sanholt 949145132Sanholt DRM_COPY_FROM_USER_IOCTL(event, (drm_savage_event_emit_t __user *)data, 950145132Sanholt sizeof(event)); 951145132Sanholt 952145132Sanholt event.count = savage_bci_emit_event(dev_priv, event.flags); 953145132Sanholt event.count |= dev_priv->event_wrap << 16; 954145132Sanholt DRM_COPY_TO_USER_IOCTL(&((drm_savage_event_emit_t __user *)data)->count, 955145132Sanholt event.count, sizeof(event.count)); 956145132Sanholt return 0; 957145132Sanholt} 958145132Sanholt 959145132Sanholtint savage_bci_event_wait(DRM_IOCTL_ARGS) 960145132Sanholt{ 961145132Sanholt DRM_DEVICE; 962145132Sanholt drm_savage_private_t *dev_priv = dev->dev_private; 963145132Sanholt drm_savage_event_wait_t event; 964145132Sanholt unsigned int event_e, hw_e; 965145132Sanholt unsigned int event_w, hw_w; 966145132Sanholt 967145132Sanholt DRM_DEBUG("\n"); 968145132Sanholt 969145132Sanholt DRM_COPY_FROM_USER_IOCTL(event, (drm_savage_event_wait_t __user *)data, 970145132Sanholt sizeof(event)); 971145132Sanholt 972145132Sanholt UPDATE_EVENT_COUNTER(); 973145132Sanholt if (dev_priv->status_ptr) 974145132Sanholt hw_e = dev_priv->status_ptr[1] & 0xffff; 975145132Sanholt else 976145132Sanholt hw_e = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff; 977145132Sanholt hw_w = dev_priv->event_wrap; 978145132Sanholt if (hw_e > dev_priv->event_counter) 979145132Sanholt hw_w--; /* hardware hasn't passed the last wrap yet */ 980145132Sanholt 981145132Sanholt event_e = event.count & 0xffff; 982145132Sanholt event_w = event.count >> 16; 983145132Sanholt 984145132Sanholt /* Don't need to wait if 985145132Sanholt * - event counter wrapped since the event was emitted or 986145132Sanholt * - the hardware has advanced up to or over the event to wait for. 987145132Sanholt */ 988145132Sanholt if (event_w < hw_w || (event_w == hw_w && event_e <= hw_e) ) 989145132Sanholt return 0; 990145132Sanholt else 991145132Sanholt return dev_priv->wait_evnt(dev_priv, event_e); 992145132Sanholt} 993145132Sanholt 994145132Sanholt/* 995145132Sanholt * DMA buffer management 996145132Sanholt */ 997145132Sanholt 998145132Sanholtstatic int savage_bci_get_buffers(DRMFILE filp, drm_device_t *dev, drm_dma_t *d) 999145132Sanholt{ 1000145132Sanholt drm_buf_t *buf; 1001145132Sanholt int i; 1002145132Sanholt 1003145132Sanholt for (i = d->granted_count; i < d->request_count; i++) { 1004145132Sanholt buf = savage_freelist_get(dev); 1005145132Sanholt if (!buf) 1006145132Sanholt return DRM_ERR(EAGAIN); 1007145132Sanholt 1008145132Sanholt buf->filp = filp; 1009145132Sanholt 1010145132Sanholt if (DRM_COPY_TO_USER(&d->request_indices[i], 1011145132Sanholt &buf->idx, sizeof(buf->idx))) 1012145132Sanholt return DRM_ERR(EFAULT); 1013145132Sanholt if (DRM_COPY_TO_USER(&d->request_sizes[i], 1014145132Sanholt &buf->total, sizeof(buf->total))) 1015145132Sanholt return DRM_ERR(EFAULT); 1016145132Sanholt 1017145132Sanholt d->granted_count++; 1018145132Sanholt } 1019145132Sanholt return 0; 1020145132Sanholt} 1021145132Sanholt 1022145132Sanholtint savage_bci_buffers(DRM_IOCTL_ARGS) 1023145132Sanholt{ 1024145132Sanholt DRM_DEVICE; 1025145132Sanholt drm_device_dma_t *dma = dev->dma; 1026145132Sanholt drm_dma_t d; 1027145132Sanholt int ret = 0; 1028145132Sanholt 1029145132Sanholt LOCK_TEST_WITH_RETURN(dev, filp); 1030145132Sanholt 1031145132Sanholt DRM_COPY_FROM_USER_IOCTL(d, (drm_dma_t __user *)data, sizeof(d)); 1032145132Sanholt 1033145132Sanholt /* Please don't send us buffers. 1034145132Sanholt */ 1035145132Sanholt if (d.send_count != 0) { 1036145132Sanholt DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", 1037145132Sanholt DRM_CURRENTPID, d.send_count); 1038145132Sanholt return DRM_ERR(EINVAL); 1039145132Sanholt } 1040145132Sanholt 1041145132Sanholt /* We'll send you buffers. 1042145132Sanholt */ 1043145132Sanholt if (d.request_count < 0 || d.request_count > dma->buf_count) { 1044145132Sanholt DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", 1045145132Sanholt DRM_CURRENTPID, d.request_count, dma->buf_count); 1046145132Sanholt return DRM_ERR(EINVAL); 1047145132Sanholt } 1048145132Sanholt 1049145132Sanholt d.granted_count = 0; 1050145132Sanholt 1051145132Sanholt if (d.request_count) { 1052145132Sanholt ret = savage_bci_get_buffers(filp, dev, &d); 1053145132Sanholt } 1054145132Sanholt 1055145132Sanholt DRM_COPY_TO_USER_IOCTL((drm_dma_t __user *)data, d, sizeof(d)); 1056145132Sanholt 1057145132Sanholt return ret; 1058145132Sanholt} 1059145132Sanholt 1060145132Sanholtvoid savage_reclaim_buffers(drm_device_t *dev, DRMFILE filp) { 1061145132Sanholt drm_device_dma_t *dma = dev->dma; 1062145132Sanholt drm_savage_private_t *dev_priv = dev->dev_private; 1063145132Sanholt int i; 1064145132Sanholt 1065145132Sanholt if (!dma) 1066145132Sanholt return; 1067145132Sanholt if (!dev_priv) 1068145132Sanholt return; 1069145132Sanholt if (!dma->buflist) 1070145132Sanholt return; 1071145132Sanholt 1072145132Sanholt /*i830_flush_queue(dev);*/ 1073145132Sanholt 1074145132Sanholt for (i = 0; i < dma->buf_count; i++) { 1075145132Sanholt drm_buf_t *buf = dma->buflist[i]; 1076145132Sanholt drm_savage_buf_priv_t *buf_priv = buf->dev_private; 1077145132Sanholt 1078145132Sanholt if (buf->filp == filp && buf_priv && 1079145132Sanholt buf_priv->next == NULL && buf_priv->prev == NULL) { 1080145132Sanholt uint16_t event; 1081145132Sanholt DRM_DEBUG("reclaimed from client\n"); 1082145132Sanholt event = savage_bci_emit_event(dev_priv, SAVAGE_WAIT_3D); 1083145132Sanholt SET_AGE(&buf_priv->age, event, dev_priv->event_wrap); 1084145132Sanholt savage_freelist_put(dev, buf); 1085145132Sanholt } 1086145132Sanholt } 1087145132Sanholt 1088145132Sanholt drm_core_reclaim_buffers(dev, filp); 1089145132Sanholt} 1090