dpt_pci.c revision 73280
1193323Sed/*- 2193323Sed * Copyright (c) 2000 Matthew N. Dodd <winter@jurai.net> 3193323Sed * All rights reserved. 4193323Sed * 5193323Sed * Copyright (c) 1997 Simon Shapiro 6193323Sed * All Rights Reserved 7193323Sed * 8193323Sed * Redistribution and use in source and binary forms, with or without 9193323Sed * modification, are permitted provided that the following conditions 10193323Sed * are met: 11193323Sed * 1. Redistributions of source code must retain the above copyright 12203954Srdivacky * notice, this list of conditions and the following disclaimer. 13193323Sed * 2. Redistributions in binary form must reproduce the above copyright 14193323Sed * notice, this list of conditions and the following disclaimer in the 15193323Sed * documentation and/or other materials provided with the distribution. 16193323Sed * 17193323Sed * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18193323Sed * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19234353Sdim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20249423Sdim * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21239462Sdim * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22249423Sdim * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23249423Sdim * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24239462Sdim * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25243830Sdim * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26193323Sed * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27193323Sed * SUCH DAMAGE. 28193323Sed * 29193323Sed * $FreeBSD: head/sys/dev/dpt/dpt_pci.c 73280 2001-03-01 17:09:09Z markm $ 30239462Sdim */ 31263508Sdim 32193323Sed#include <sys/param.h> 33193323Sed#include <sys/systm.h> 34193323Sed#include <sys/kernel.h> 35198090Srdivacky#include <sys/module.h> 36249423Sdim#include <sys/bus.h> 37249423Sdim 38249423Sdim#include <machine/bus_memio.h> 39193323Sed#include <machine/bus_pio.h> 40193323Sed#include <machine/bus.h> 41193323Sed#include <machine/resource.h> 42226633Sdim#include <sys/rman.h> 43226633Sdim 44193323Sed#include <pci/pcireg.h> 45193323Sed#include <pci/pcivar.h> 46193323Sed 47193323Sed#include <cam/scsi/scsi_all.h> 48193323Sed 49193323Sed#include <dev/dpt/dpt.h> 50193323Sed 51218893Sdim#define DPT_VENDOR_ID 0x1044 52193323Sed#define DPT_DEVICE_ID 0xa400 53193323Sed 54194612Sed#define DPT_PCI_IOADDR PCIR_MAPS /* I/O Address */ 55193323Sed#define DPT_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 56193323Sed 57193323Sed#define ISA_PRIMARY_WD_ADDRESS 0x1f8 58198892Srdivacky 59193323Sedstatic int dpt_pci_probe (device_t); 60193323Sedstatic int dpt_pci_attach (device_t); 61193323Sed 62193323Sedstatic int 63193323Seddpt_pci_probe (device_t dev) 64193323Sed{ 65193323Sed if ((pci_get_vendor(dev) == DPT_VENDOR_ID) && 66193323Sed (pci_get_device(dev) == DPT_DEVICE_ID)) { 67193323Sed device_set_desc(dev, "DPT Caching SCSI RAID Controller"); 68218893Sdim return (0); 69218893Sdim } 70218893Sdim return (ENXIO); 71218893Sdim} 72193323Sed 73193323Sedstatic int 74218893Sdimdpt_pci_attach (device_t dev) 75218893Sdim{ 76218893Sdim dpt_softc_t * dpt; 77226633Sdim struct resource *io = 0; 78218893Sdim struct resource *irq = 0; 79218893Sdim int s; 80218893Sdim int rid; 81249423Sdim void * ih; 82249423Sdim int error = 0; 83249423Sdim 84249423Sdim int iotype = 0; 85249423Sdim u_int32_t command; 86249423Sdim 87249423Sdim command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1); 88194612Sed 89194612Sed#ifdef DPT_ALLOW_MMIO 90249423Sdim if ((command & PCIM_CMD_MEMEN) != 0) { 91249423Sdim rid = DPT_PCI_MEMADDR; 92249423Sdim iotype = SYS_RES_MEMORY; 93249423Sdim io = bus_alloc_resource(dev, iotype, &rid, 0, ~0, 1, RF_ACTIVE); 94249423Sdim } 95249423Sdim#endif 96249423Sdim if (io == NULL && (command & PCIM_CMD_PORTEN) != 0) { 97249423Sdim rid = DPT_PCI_IOADDR; 98249423Sdim iotype = SYS_RES_IOPORT; 99193323Sed io = bus_alloc_resource(dev, iotype, &rid, 0, ~0, 1, RF_ACTIVE); 100193323Sed } 101193323Sed 102193323Sed if (io == NULL) { 103193323Sed device_printf(dev, "can't allocate register resources\n"); 104218893Sdim error = ENOMEM; 105193323Sed goto bad; 106193323Sed } 107193323Sed 108193323Sed rid = 0; 109193323Sed irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 110193323Sed RF_ACTIVE | RF_SHAREABLE); 111193323Sed if (!irq) { 112193323Sed device_printf(dev, "No irq?!\n"); 113193323Sed error = ENOMEM; 114193323Sed goto bad; 115193323Sed } 116193323Sed 117239462Sdim /* Ensure busmastering is enabled */ 118239462Sdim command |= PCIM_CMD_BUSMASTEREN; 119239462Sdim pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1); 120239462Sdim 121239462Sdim if (rman_get_start(io) == (ISA_PRIMARY_WD_ADDRESS - 0x10)) { 122239462Sdim#ifdef DPT_DEBUG_WARN 123239462Sdim device_printf(dev, "Mapped as an IDE controller. " 124239462Sdim "Disabling SCSI setup\n"); 125239462Sdim#endif 126239462Sdim error = ENXIO; 127239462Sdim goto bad; 128239462Sdim } 129239462Sdim 130239462Sdim /* Device registers are offset 0x10 into the register window. FEH */ 131239462Sdim dpt = dpt_alloc(dev, rman_get_bustag(io), rman_get_bushandle(io) + 0x10); 132239462Sdim if (dpt == NULL) { 133239462Sdim error = ENXIO; 134239462Sdim goto bad; 135239462Sdim } 136239462Sdim 137239462Sdim /* Allocate a dmatag representing the capabilities of this attachment */ 138243830Sdim /* XXX Should be a child of the PCI bus dma tag */ 139239462Sdim if (bus_dma_tag_create( /* parent */ NULL, 140239462Sdim /* alignemnt */ 1, 141239462Sdim /* boundary */ 0, 142243830Sdim /* lowaddr */ BUS_SPACE_MAXADDR_32BIT, 143239462Sdim /* highaddr */ BUS_SPACE_MAXADDR, 144239462Sdim /* filter */ NULL, 145239462Sdim /* filterarg */ NULL, 146239462Sdim /* maxsize */ BUS_SPACE_MAXSIZE_32BIT, 147239462Sdim /* nsegments */ BUS_SPACE_UNRESTRICTED, 148239462Sdim /* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT, 149239462Sdim /* flags */ 0, 150239462Sdim &dpt->parent_dmat) != 0) { 151239462Sdim dpt_free(dpt); 152239462Sdim error = ENXIO; 153239462Sdim goto bad; 154239462Sdim } 155239462Sdim 156239462Sdim s = splcam(); 157239462Sdim 158239462Sdim if (dpt_init(dpt) != 0) { 159239462Sdim dpt_free(dpt); 160239462Sdim error = ENXIO; 161239462Sdim goto bad; 162239462Sdim } 163239462Sdim 164239462Sdim /* Register with the XPT */ 165239462Sdim dpt_attach(dpt); 166239462Sdim 167239462Sdim splx(s); 168239462Sdim 169239462Sdim if (bus_setup_intr(dev, irq, INTR_TYPE_CAM | INTR_ENTROPY, dpt_intr, 170239462Sdim dpt, &ih)) { 171239462Sdim device_printf(dev, "Unable to register interrupt handler\n"); 172239462Sdim error = ENXIO; 173239462Sdim goto bad; 174239462Sdim } 175239462Sdim 176239462Sdim return (error); 177239462Sdim 178239462Sdimbad: 179239462Sdim if (io) 180239462Sdim bus_release_resource(dev, iotype, 0, io); 181239462Sdim if (irq) 182239462Sdim bus_release_resource(dev, SYS_RES_IRQ, 0, irq); 183243830Sdim 184239462Sdim return (error); 185239462Sdim} 186239462Sdim 187239462Sdimstatic device_method_t dpt_pci_methods[] = { 188239462Sdim /* Device interface */ 189239462Sdim DEVMETHOD(device_probe, dpt_pci_probe), 190239462Sdim DEVMETHOD(device_attach, dpt_pci_attach), 191239462Sdim 192239462Sdim { 0, 0 } 193239462Sdim}; 194239462Sdim 195239462Sdimstatic driver_t dpt_pci_driver = { 196243830Sdim "dpt", 197243830Sdim dpt_pci_methods, 198239462Sdim sizeof(dpt_softc_t), 199239462Sdim}; 200239462Sdim 201239462Sdimstatic devclass_t dpt_devclass; 202239462Sdim 203239462SdimDRIVER_MODULE(dpt, pci, dpt_pci_driver, dpt_devclass, 0, 0); 204239462Sdim