1/*- 2 * Copyright (c) 2000 Matthew N. Dodd <winter@jurai.net> 3 * All rights reserved. 4 * 5 * Copyright (c) 1997 Simon Shapiro 6 * All Rights Reserved 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD$"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/kernel.h> 36#include <sys/module.h> 37#include <sys/lock.h> 38#include <sys/mutex.h> 39#include <sys/bus.h> 40 41#include <machine/bus.h> 42#include <machine/resource.h> 43#include <sys/rman.h> 44 45#include <dev/pci/pcireg.h> 46#include <dev/pci/pcivar.h> 47 48#include <cam/scsi/scsi_all.h> 49 50#include <dev/dpt/dpt.h> 51 52#define DPT_VENDOR_ID 0x1044 53#define DPT_DEVICE_ID 0xa400 54 55#define DPT_PCI_IOADDR PCIR_BAR(0) /* I/O Address */ 56#define DPT_PCI_MEMADDR PCIR_BAR(1) /* Mem I/O Address */ 57 58#define ISA_PRIMARY_WD_ADDRESS 0x1f8 59 60static int dpt_pci_probe (device_t); 61static int dpt_pci_attach (device_t); 62 63static int 64dpt_pci_probe (device_t dev) 65{ 66 if ((pci_get_vendor(dev) == DPT_VENDOR_ID) && 67 (pci_get_device(dev) == DPT_DEVICE_ID)) { 68 device_set_desc(dev, "DPT Caching SCSI RAID Controller"); 69 return (BUS_PROBE_DEFAULT); 70 } 71 return (ENXIO); 72} 73 74static int 75dpt_pci_attach (device_t dev) 76{ 77 dpt_softc_t * dpt; 78 int error = 0; 79 80 dpt = device_get_softc(dev); 81 dpt->dev = dev; 82 dpt_alloc(dev); 83 84#ifdef DPT_ALLOW_MMIO 85 dpt->io_rid = DPT_PCI_MEMADDR; 86 dpt->io_type = SYS_RES_MEMORY; 87 dpt->io_res = bus_alloc_resource_any(dev, dpt->io_type, 88 &dpt->io_rid, RF_ACTIVE); 89#endif 90 if (dpt->io_res == NULL) { 91 dpt->io_rid = DPT_PCI_IOADDR; 92 dpt->io_type = SYS_RES_IOPORT; 93 dpt->io_res = bus_alloc_resource_any(dev, dpt->io_type, 94 &dpt->io_rid, RF_ACTIVE); 95 } 96 97 if (dpt->io_res == NULL) { 98 device_printf(dev, "can't allocate register resources\n"); 99 error = ENOMEM; 100 goto bad; 101 } 102 dpt->io_offset = 0x10; 103 104 dpt->irq_rid = 0; 105 dpt->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &dpt->irq_rid, 106 RF_ACTIVE | RF_SHAREABLE); 107 if (dpt->irq_res == NULL) { 108 device_printf(dev, "No irq?!\n"); 109 error = ENOMEM; 110 goto bad; 111 } 112 113 /* Ensure busmastering is enabled */ 114 pci_enable_busmaster(dev); 115 116 if (rman_get_start(dpt->io_res) == (ISA_PRIMARY_WD_ADDRESS - 0x10)) { 117#ifdef DPT_DEBUG_WARN 118 device_printf(dev, "Mapped as an IDE controller. " 119 "Disabling SCSI setup\n"); 120#endif 121 error = ENXIO; 122 goto bad; 123 } 124 125 /* Allocate a dmatag representing the capabilities of this attachment */ 126 if (bus_dma_tag_create( /* PCI parent */ bus_get_dma_tag(dev), 127 /* alignemnt */ 1, 128 /* boundary */ 0, 129 /* lowaddr */ BUS_SPACE_MAXADDR_32BIT, 130 /* highaddr */ BUS_SPACE_MAXADDR, 131 /* filter */ NULL, 132 /* filterarg */ NULL, 133 /* maxsize */ BUS_SPACE_MAXSIZE_32BIT, 134 /* nsegments */ ~0, 135 /* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT, 136 /* flags */ 0, 137 /* lockfunc */ NULL, 138 /* lockarg */ NULL, 139 &dpt->parent_dmat) != 0) { 140 error = ENXIO; 141 goto bad; 142 } 143 144 if (dpt_init(dpt) != 0) { 145 error = ENXIO; 146 goto bad; 147 } 148 149 /* Register with the XPT */ 150 dpt_attach(dpt); 151 152 if (bus_setup_intr(dev, dpt->irq_res, INTR_TYPE_CAM | INTR_ENTROPY | 153 INTR_MPSAFE, NULL, dpt_intr, dpt, &dpt->ih)) { 154 device_printf(dev, "Unable to register interrupt handler\n"); 155 error = ENXIO; 156 goto bad; 157 } 158 159 return (error); 160 161bad: 162 dpt_release_resources(dev); 163 164 dpt_free(dpt); 165 166 return (error); 167} 168 169static device_method_t dpt_pci_methods[] = { 170 /* Device interface */ 171 DEVMETHOD(device_probe, dpt_pci_probe), 172 DEVMETHOD(device_attach, dpt_pci_attach), 173 DEVMETHOD(device_detach, dpt_detach), 174 175 { 0, 0 } 176}; 177 178static driver_t dpt_pci_driver = { 179 "dpt", 180 dpt_pci_methods, 181 sizeof(dpt_softc_t), 182}; 183 184DRIVER_MODULE(dpt, pci, dpt_pci_driver, dpt_devclass, 0, 0); 185MODULE_DEPEND(dpt, pci, 1, 1, 1); 186MODULE_DEPEND(dpt, cam, 1, 1, 1); 187